ChipFind - документация

Электронный компонент: PLL502-21

Скачать:  PDF   ZIP
Preliminary
PLL502-21
384MHz 768MHz Low Phase Noise PECL VCXO (12 24MHz Crystal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 08/10/01 Page 1
FEATURES
Low phase noise output for the 384MHz to
768MHz range (-130 dBc at 10kHz offset).
PECL output.
12 to 24MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Output Enable selector.
Wide pull range (+/-180 ppm)
3.3V operation.
Available in 16 Pin TSSOP or SOIC.
DESCRIPTION
The PLL502-21 is a monolithic low jitter and low
phase noise (-130dBc/Hz @ 10kHz offset) VCXO IC
with PECL output, for 384MHz to 768MHz output
range. It allows the control of the output frequency
with an input voltage (VIN), using a low cost crystal.
The chip provides a pullable output at a frequency of
F
XIN
x 32. This makes the PLL502-21 ideal for a wide
range of applications, including 622.08MHz for
SONET.
PIN CONFIGURATION
F
OUT
= F
XIN
x 32
OE (Pin 5)
Output State
0 (Default)
Output enabled
1
Tri-state
Pin 5: Logical states are defined at PECL levels.
BLOCK DIAGRAM
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
VCO
Divider
XTAL
OSC
CLKBAR
OE
XIN
XOUT
CLK
VIN
VARICAP
PLL 502-21
1
2
3
4
5
6
7
8
VDD
9
10
11
12
13
14
15
16
VDD
XIN
XOUT
OE
VIN
GND
GND
VDD
GND_BUF
CLKBAR
VDD_BUF
CLK
GND_BUF
GND
GND
Preliminary
PLL502-21
384MHz 768MHz Low Phase Noise PECL VCXO (12 24MHz Crystal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 08/10/01 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
VDD
1,2,16
P
+3.3V Power supply connectors.
XIN
3
I
Crystal input pin.
XOUT
4
I
Crystal output pin.
OE
5
I
Output enable input pin. Disables (tri-state) output when low. Internal
pull-up enables output by default if pin is not connected to low.
VIN
6
I
Frequency control voltage input pin.
GND
7,8,9,10
P
GND Power connectors.
GND_BUF
11,15
P
GND connector for output buffers.
CLK
12
O
True clock output pin.
VDD_BUF
13
P
+3.3V Power supply connector for output buffers.
CLKB
14
O
Complementary clock output pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
7
V
Input Voltage, dc
V
I
V
SS
-
0.5
V
DD
+
0.5
V
Output Voltage, dc
V
O
V
SS
-
0.5
V
DD
+
0.5
V
Storage Temperature
T
S
-65
150
C
Ambient Operating Temperature
T
A
0
70
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
Input Static Discharge Voltage Protection
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
Preliminary
PLL502-21
384MHz 768MHz Low Phase Noise PECL VCXO (12 24MHz Crystal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 08/10/01 Page 3
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator
Frequency
F
XIN
Parallel Fundamental
Mode
12
24
MHz
Crystal Loading Rating
C
L
(xtal)
TBD
pF
Crystal Pullability
C
0
/C
1
(xtal)
AT cut
250
-
Recommended ESR
R
E
AT cut
30
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
T
VCXOSTB
From power valid
10
ms
Output Frequency Synthesis
Error
(Unless otherwise noted in
Frequency Table)
30
ppm
VCXO Tuning Range
F
XIN
= 12 - 24MHz;
XTAL C
0
/C
1
< 250
380
ppm
CLK output pullability
0V
VCON
3.3V
190
ppm
Linearity
5
10
%
VCXO Tuning Characteristic
115
ppm/V
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current, Dynamic
(with Loaded Outputs)
I
DD
PECL
80
mA
Operating Voltage
V
DD
3.13
3.47
V
Output Clock Duty Cycle
@ Vdd 1.3V (PECL)
45
50
55
%
Short Circuit Current
50
mA
Preliminary
PLL502-21
384MHz 768MHz Low Phase Noise PECL VCXO (12 24MHz Crystal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 08/10/01 Page 4
5. Jitter and Phase Noise specification
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
With capacitive decoupling
between VDD and GND.
7
ps
Accumulated jitter RMS
With capacitive decoupling
between VDD and GND. Over
10,000 cycles.
11
ps
Phase Noise relative to carrier
622MHz @100Hz offset
-80
dBc/Hz
Phase Noise relative to carrier
622MHz @1kHz offset
-109
dBc/Hz
Phase Noise relative to carrier
622MHz @10kHz offset
-130
dBc/Hz
Phase Noise relative to carrier
622MHz @100kHz offset
-132
dBc/Hz
Preliminary
PLL502-21
384MHz 768MHz Low Phase Noise PECL VCXO (12 24MHz Crystal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 08/10/01 Page 5
6. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.620
V
7. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
t
r
@20/80% - PECL
0.6
1.5
ns
Clock Fall Time
t
f
@80/20% - PECL
0.5
1.5
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V