PLL502-25
Low Phase Noise VCXO (12MHz to 27MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 1
FEATURES
Low phase noise VCXO output for the 12MHz to
27MHz range (-135 dBc at 10kHz offset).
CMOS output.
12 to 27MHz crystal input.
Integrated variable capacitors.
Wide pull range (+/- 250 ppm).
Low jitter (RMS): 2.2ps period.
2.5V or 3.3V operation voltage.
Available in 8-Pin SOIC.
DESCRIPTION
The PLL502-25 is a low cost, high performance and
low phase noise VCXO, providing less than -135dBc
at 10kHz offset in the 12MHz to 27MHz operating
range. The very low jitter (2.2 ps RMS period jitter)
makes this chip ideal for applications requiring volt-
age controlled frequency sources. Input crystal can
range from 12 to 27MHz (fundamental resonant
mode).
PIN CONFIGURATION
OUTPUT RANGE
MULTIPLIER
FREQUENCY
RANGE
OUTPUT
BUFFER
No PLL
12 - 27MHz
CMOS
BLOCK DIAGRAM
PLL5
02-
2
5
1
2
3
4
5
6
7
8
XOUT
VDD
VCON
GND
XIN
N/C
CLK
N/C
XTAL
OSC
OE
XIN
XOUT
CLK
VCON
VARICAP
PLL502-25
Low Phase Noise VCXO (12MHz to 27MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 2
PIN DESCRIPTIONS
Name Number
Type
Description
XOUT
1
I
Crystal output. See Crystal Specification on page 3.
VDD 2
P
Power
supply.
VCON 3
I
Voltage
Control
input.
GND 4
P
Ground.
CLK 5
O
Output
clock.
N/C 6
-
No
connection.
N/C 7
-
No
connection.
XIN
8
I
Crystal input. See Crystal Specification on page 3.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5 V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature*
T
A
-40 85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. DC Electrical Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Supply Current, Dynamic, with
Loaded Outputs
I
DD
F
XIN
= 12 - 25MHz
Output load of 10pF
16
20 mA
Operating Voltage
V
DD
2.25
3.63
V
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 10 mA
Output drive current
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
10
mA
Short Circuit Current
50
mA
VCXO Control Voltage
VCON
0
V
DD
V
PLL502-25
Low Phase Noise VCXO (12MHz to 27MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 3
3. AC Electrical Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Input Crystal Frequency
12
27
MHz
Output Clock Rise/Fall Time
0.3V ~ 3.0V with 15 pF load
2.4
ns
Output Clock Duty Cycle
Measured @ 50% V
DD
45
50
55
%
4. Voltage Control Crystal Oscillator (3.3V)
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
T
VCXOSTB
From power valid
10
ms
VCXO Tuning Range
F
XIN
= 12 25MHz;
XTAL C
0
/C
1
< 250
0V
VCON 3.3V
500 ppm
CLK output pullability
VCON=1.65V,
1.65V
200
ppm
VCXO Tuning Characteristic
150
ppm/V
Pull range linearity
10
%
VCON pin input impedance
2000
k
VCON modulation BW
0V
VCON 3.3V, -3dB
25
kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
5. Jitter and Phase Noise specification
PARAMETERS CONDITIONS
MIN.
TYP.
MAX.
UNITS
RMS Period Jitter
(1 sigma 1000 samples)
with capacitive decoupling between
VDD and GND.
2.2 ps
Phase Noise relative to carrier
27MHz @100Hz offset
-95
dBc/Hz
Phase Noise relative to carrier
27MHz @1kHz offset
-120
dBc/Hz
Phase Noise relative to carrier
27MHz @10kHz offset
-142
dBc/Hz
Phase Noise relative to carrier
27MHz @100kHz offset
-150
dBc/Hz
Phase Noise relative to carrier
27MHz @1MHz offset
-150
dBc/Hz
6. Crystal Specifications
PARAMETERS SYMBOL
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
12
27
MHz
Crystal Loading Capacitance Rating
C
L (xtal)
9.5
pF
C0/C1
250
-
ESR R
S
30
Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at
nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
PLL502-25
Low Phase Noise VCXO (12MHz to 27MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/17/04 Page 4
PACKAGE INFORMATION
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
C
L
A
8 PIN ( dimensions in mm )
Narrow SOIC
Symbol
Min.
Max.
A
1.47
1.73
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
4.95
E
3.80
4.00
H
5.80
6.20
L
0.38
1.27
e
1.27 BSC
E
H
D
A
1
e
B
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL502-25 x x
Temperature
C=Commercial
Package
S=SOIC
Part Number
Order Number
Marking
Package Option
PLL502-25SC P502-25SC
8-Pin SOIC (Tube)
PLL502-25SC-R P502-25SC
8-Pin SOIC (Tape and Reel)
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