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Электронный компонент: PLL520-00D1

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Preliminary
PLL520-00D1
Low Phase Noise VCXO with multipliers (for 120-200MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/26/03 Page 1
FEATURES
120MHz to 200MHz Fundamental Mode Crystal.
Output range: 120 200MHz (no multiplication),
240 400MHz (2x multiplier) or 480 700MHz
(4x multiplier).
Available outputs: PECL, LVDS, or CMOS.
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DESCRIPTIONS
PLL520-00 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
BLOCK DIAGRAM
DIE CONFIGURATION
DIE SPECIFICATIONS
Name
Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
Pad #25
OUTSEL0
Selected Output
0
0
High Drive CMOS
0
1
Standard CMOS
1
0
LVDS
1
1
PECL (default)
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
State
0
Tri-state
0
1 (Default) Output enabled
0 (Default) Output enabled
1 (Default)
1
Tri-state
Pad #9, 18, 25: Bond to GND to set to "0", bond to VDD to set to "1"
No connection results to "default" setting through internal pull-up/-down.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is "1"
Logical states defined by CMOS levels if OE_SELECT is "0"
18
19
20
21
23
25
7
13
10
26
29
31
Y
X
(0,0)
(1550,1475)
62 mil
65 mil
24
22
17
16
15
14
12
11
9
8
6
1
2
3
4
5
27
28
30
X+
X-
OE
Q
PLL520-00
VCON
Q
PLL by-pass
SEL
PLL
(Phase
Locked
Loop)
Oscillator
Amplifier
w/
integrated
varicaps
Preliminary
PLL520-00D1
Low Phase Noise VCXO with multipliers (for 120-200MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/26/03 Page 2
FREQUENCY SELECTION TABLE
Pad #28
SEL3
Pad #29
SEL2
Pad #19
SEL1
Pad #20
SEL0
Selected Multiplier
1
0
1
1
Fin x 4
1
1
1
0
Fin x 2
1
1
1
1
No multiplication (no PLL)
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
7
V
Input Voltage, dc
V
I
V
SS
-0.5
V
DD
+0.5
V
Output Voltage, dc
V
O
V
SS
-0.5
V
DD
+0.5
V
Storage Temperature
T
S
-65
150
C
Ambient Operating Temperature*
T
A
-40
85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
Input Static Discharge Voltage Protection
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
Parallel Fundamental Mode
120
200
MHz
Crystal Loading Rating
C
L (xtal)
Die at VCON = 1.65V
4
pF
Interelectrode Capacitance
C
0
3.5
pF
Crystal Pullability
C
0
/C
1 (xtal)
AT cut
300
-
Recommended ESR
R
E
AT cut
30
Preliminary
PLL520-00D1
Low Phase Noise VCXO with multipliers (for 120-200MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/26/03 Page 3
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
T
VCXOSTB
From power valid
10
ms
VCXO Tuning Range
XTAL C
0
/C
1
< 300
200*
ppm
CLK output pullability
0V
VCON
3.3V
at room temperature
100*
ppm
On-chip Varicaps control range
VCON = 0 to 3.3V
4 18*
pF
Linearity
5*
10*
%
VCXO Tuning Characteristic
65
ppm/V
VCON input impedance
60
k
VCON modulation BW
0V
VCON
3.3V, -3dB
25
kHz
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded Outputs)
I
DD
PECL/LVDS/CMOS
100/80/40
mA
Operating Voltage
V
DD
3.13
3.47
V
Output Clock Duty Cycle
@ 1.4V (CMOS)
@ 1.25V (LVDS)
@ Vdd 1.3V (PECL)
45
45
45
50
50
50
55
55
55
%
Short Circuit Current
50
mA
Preliminary
PLL520-00D1
Low Phase Noise VCXO with multipliers (for 120-200MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/26/03 Page 4
5. Jitter specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
2.5
Period jitter peak-to-peak
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
18.5
20
ps
Accumulated jitter RMS
2.5
Accumulated jitter peak-to-peak
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000 cycles.
24
27
ps
Random Jitter
"RJ" measured on Wavecrest SIA 3000
2.5
ps
Integrated jitter RMS at 155MHz
Integrated 12 kHz to 20 MHz
0.3
0.4
ps
Period jitter RMS
11
Period jitter peak-to-peak
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
45
49
ps
Accumulated jitter RMS
11
Accumulated jitter peak-to-peak
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000 cycles.
24
27
ps
Random Jitter
"RJ" measured on Wavecrest SIA 3000
3
ps
Integrated jitter RMS at 622MHz
Integrated 12 kHz to 20 MHz
1.6
1.8
ps
Measured on Wavecrest SIA 3000
6. Phase noise specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz @1kHz @10kHz @100kHz UNITS
155.52MHz
-75
-95
-125
-140
-145
Phase Noise relative to
carrier
622.08MHz
-75
-95
-110
-125
-120
dBc/Hz
Note: Phase Noise measured at VCON = 0V
Preliminary
PLL520-00D1
Low Phase Noise VCXO with multipliers (for 120-200MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 06/26/03 Page 5
7. CMOS Output Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP. MAX. UNITS
Output High Voltage
V
OH
I
OH
= -12mA (Standard drive)
2.4
V
Output Low Voltage
V
OL
I
LO
= 12mA (Standard drive)
0.4
V
Output High Voltage at CMOS
level
V
OHC
I
OH
= -4mA (Standard drive)
V
DD
0.4
V
At TTL level (High drive)
36
51
mA
Output drive current
At TTL level (Standard drive)
12
17
mA
8. CMOS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP. MAX. UNITS
0.8V ~ 2.0V with 10 pF load
1.15
Output Clock Rise/Fall Time
(Standard Drive)
0.3V ~ 3.0V with 15 pF load
3.7
0.8V ~ 2.0V with 10 pF load
0.5
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
1.5
ns