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Электронный компонент: PLL520-39

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PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
FEATURES
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz 130MHz (no PLL).
Low Injection Power for crystal 50uW.
PECL (PLL520-38) or LVDS output (PLL520-39).
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in 16-Pin (TSSOP or 3x3 QFN).
DESCRIPTION
The PLL520-38/-39 is a family of VCXO IC's
specifically designed to pull high frequency
fundamental crystals from 65MHz to 130MHz, with
selectable PECL or LVDS outputs.. They achieve
very low current into the crystal resulting in better
overall stability. Their internal varicaps allow an on
chip frequency pulling, controlled by the VCON
input. Their very low jitter makes them ideal for the
most demanding timing requirements.
BLOCK DIAGRAM
PIN CONFIGURATION
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0
(Default)
Output enabled
PLL520-38
1 Tri-state
0 Tri-state
PLL520-39
1
(Default)
Output enabled
OE input: Logical states defined by PECL levels for PLL520-38
Logical states defined by CMOS levels for PLL520-39
PLL 520-3x
1
2
3
4
5
6
7
8
VDD
9
10
11
12
13
14
15
16
XIN
XOUT
N/C
N/C
OE
VCON
GND
N/C
N/C
GND
CLKC
VDD
CLKT
N/C
N/C
XIN
XOUT
OE
Q
PLL520-38/-39
VCON
Q
Oscillator
Amplifier
w/
integrated
varicaps
P520-3x
GND
VDD
CLKT
CLKC
VD
D
N/C
N/C
VD
D
XOUT
XIN
N/C
OE
GND
VCON
GND
GND
4
16
15
14
13
12
11
10
9
8
7
6
5
1
2
3
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2
PIN DESCRIPTIONS
Name Number
Type
Description
XIN
2
I
Crystal input. See Crystal Specifications on page 2.
XOUT
3
I
Crystal output. See Crystal Specifications on page 2.
OE
6
I
Output enable. See Output Enable Logic table on page 1.
VCON
7
I
Voltage control input.
GND 8,
14
P
Ground.
CLKT
11
O
True output PECL (PLL520-38) or LVDS (PLL520-39).
CLKC
13
O
Complementary output PECL (PLL520-38) or LVDS (PLL520-39).
N/C 4,5,9,10,15,16
-
Not
connected.
VDD 1,
12
P
Power
supply.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5 V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature*
T
A
-40 85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
CX+
2
Built-in Capacitance
CX-
2
Inter-electrode capacitance
C
0
65MHz to 130MHz
(VDD=3.3V)
2.6
pF
C0/C1 ratio (gamma)
300
-
Oscillation Frequency
OF
Fund.
65
130
MHz
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3
3. Voltage Control Crystal Oscillator (3.3V)
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
T
VCXOSTB
From power valid
10
ms
VCXO Tuning Range
F
XIN
= 100 200MHz;
XTAL C
0
/C
1
< 250
0V
VCON 3.3V
200* ppm
CLK output pullability
VCON=1.65V,
1.65V
100*
ppm
On-chip Varicaps control range
VCON = 0 to 3.3V
4 18*
pF
Linearity
10*
%
VCXO Tuning Characteristic
65
ppm/V
VCON input impedance
60
k
VCON modulation BW
0V
VCON 3.3V, -3dB
25 kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded
Outputs)
I
DD
PECL/LVDS
100/80
mA
Operating Voltage
V
DD
2.97
3.63
V
Output Clock Duty Cycle
@ 1.25V (LVDS)
@ V
DD
1.3V (PECL)
45
45
50
50
55
55
%
Short Circuit Current
50
mA
5. Jitter Specifications
PARAMETERS CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
77.76MHz
2.5
ps
Period jitter peak-to-peak
77.76MHz
18.5
ps
Integrated jitter RMS
Integrated 12 kHz to 20 MHz at 77.76MHz
0.5
ps
6. Phase Noise Specifications
PARAMETERS FREQUENCY @10Hz
@100Hz @1kHz @10kHz @100kHz UNITS
Phase Noise relative
to carrier
77.76MHz -75 -95
-125
-145
-155
dBc/Hz
Note: Phase Noise measured at VCON = 0V
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4
7. LVDS Electrical Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
V
OD
247
355
454
mV
V
DD
Magnitude Change
V
OD
-50 50 mV
Output High Voltage
V
OH
1.4
1.6
V
Output Low Voltage
V
OL
0.9
1.1
V
Offset Voltage
V
OS
1.125
1.2
1.375
V
Offset Magnitude Change
V
OS
R
L
= 100
(see figure)
0 3 25 mV
Power-off Leakage
I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1
10
uA
Output Short Circuit Current
I
OSD
-5.7 -8
mA
8. LVDS Switching Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
t
r
0.2 0.7 1.0 ns
Differential Clock Fall Time
t
f
R
L
= 100
C
L
= 10 pF
(see figure)
0.2 0.7 1.0 ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test Circuit
LVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF
PLL520-38/-39
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
9. PECL Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS
MIN. MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.620
V
10. PECL Switching Characteristics
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Clock Rise Time
t
r
@20/80% - PECL
0.6
1.5
ns
Clock Fall Time
t
f
@80/20% - PECL
0.5
1.5
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V