PLL520-80
Low Phase Noise VCXO (9.5-65MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 011/09/04 Page 1
FEATURES
19MHz to 65MHz fundamental crystal input.
Output range: 9.5MHz 65MHz
Complementary outputs: PECL or LVDS output.
Selectable OE Logic (enable high or enable low).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Integrated variable capacitors.
Supports 2.5V or 3.3V Power Supply.
Available in die form.
DESCRIPTION
The PLL520-80 is a VCXO IC specifically designed to
work with fundamental crystals between 19MHz and
65MHz. The selectable divide by two feature extends
the operation range from 9.5MHz to 65MHz. It
requires very low current into the crystal resulting in
better overall stability. The OE logic feature allows
selection of enable high or enable low. Furthermore,
it provides selectable CMOS, PECL or LVDS outputs.
DIE SPECIFICATIONS
Name Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness 10
mil
BLOCK DIAGRAM
DIE CONFIGURATION
OUTPUT SELECTION AND ENABLE
OUT_SEL1*
(Pad 18)
OUT_SEL0*
(Pad 25)
Selected Output*
0
0
High Drive CMOS
0 1
Standard
CMOS
1 0
LVDS
1 1
PECL
(default)
OE_SELECT
(Pad 9)
OE_CTRL
(Pad 30)
State
0 Tri-state
0
1 (Default) Output enabled
0 (Default) Output enabled
1 (Default)
1 Tri-state
Pads #9, #18 & #25: Bond to GND to set to "0",
No connection results to "default" setting
through internal pull-up.
OE_CTRL: Logical states defined by PECL levels if OE_SELECT is "1"
Logical states defined by CMOS levels if OE_SELECT is "0"
OUTPUT FREQUENCY SELECTOR
S2 Output
0 Input/2
1(Default)* Input
*Internally set to `Default' through 60K pull-up resistor
18
19
20
21
23
25
7
13
10
26
29
31
Y
X
(0,0)
(1550,1475)
62
mil
65 mil
24
22
17
16
15
14
12
11
9
8
6
1
2
3
4
5
27
28
30
GN
D
GN
D
GN
D
GN
D
GN
D
GN
D
B
UF
GND
B
U
F
OE_SEL^
PECL
LVDS
VDDBUF
VDDBUF
PECLB
LVDSB
CMOS
GNDBUF
OU
T
SEL
1^
Re
ser
v
ed
N/
C
VD
D
VD
D
VD
D
VD
D
OU
T
SEL
0^
XIN
XOUT
VCON
OE
CTRL
S2^
N/C
Re
se
r
v
ed
Die ID:
A2020-20C
C502A
XIN
XOUT
OE
Q
PLL520-80
VCON
Q
Oscillator
Amplifier
w/
integrated
varicaps
S2
PLL520-80
Low Phase Noise VCXO (9.5-65MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 011/09/04 Page
2
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6 V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5 V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5 V
Storage Temperature
T
S
-65 150
C
Ambient Operating Temperature*
T
A
-40 85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
Fundamental
19
65 MHz
Crystal Loading Rating
C
L (xtal)
Die
8*
pF
Interelectrode Capacitance
C
0
5
pF
Recommended ESR
R
E
AT cut
30
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific
limits.
3. Voltage Control Crystal Oscillator
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
VCXO Stabilization Time *
T
VCXOSTB
From power valid
10
ms
VCXO Tuning Range
F
XIN
= 100 200MHz;
XTAL C
0
/C
1
< 250
0V
VCON 3.3V
200* ppm
CLK output pullability
VCON=1.65V,
1.65V
100*
ppm
On-chip Varicaps control range
VCON = 0 to 3.3V
4 18*
pF
Linearity
10*
%
VCXO Tuning Characteristic
65
ppm/V
VCON input impedance
60
k
VCON modulation BW
0V
VCON 3.3V, -3dB
25 kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific
limits.
PLL520-80
Low Phase Noise VCXO (9.5-65MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 011/09/04 Page
3
4. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded Outputs)
I
DD
PECL/LVDS/CMOS
100/80/40
mA
Operating Voltage
V
DD
2.97
3.63
V
Output Clock Duty Cycle
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
1.3V (PECL)
45
45
45
50
50
50
55
55
55
%
Short Circuit Current
50
mA
5. Jitter Specifications
PARAMETERS CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS at 27MHz
2.3
Period jitter peak-to-peak at 27MHz
With capacitive decoupling between
VDD and GND. Over 10,000 cycles
18.5 20
ps
Accumulated jitter RMS at 27MHz
2.3
Accumulated jitter peak-to-peak at 27MHz
With capacitive decoupling between
VDD and GND. Over 1,000,000
cycles.
24 25
ps
Random Jitter
"RJ" measured on Wavecrest SIA
3000
2.3 ps
Measured on Wavecrest SIA 3000
6. Phase Noise Specifications
PARAMETERS FREQUENCY @10Hz
@100Hz @1kHz @10kHz @100kHz UNITS
Phase Noise relative
to carrier
27MHz -75
-100
-125
-140
-145
dBc/Hz
Note: Phase Noise measured on Agilent E5500
7. CMOS Output Electrical Specifications
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 30 mA
Output drive current
(High Drive)
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
30
mA
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V 10 mA
Output drive current
(Standard Drive)
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
10
mA
Output Clock Rise/Fall Time
(Standard Drive)
0.3V ~ 3.0V with 15 pF load
2.4
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
1.2
ns
PLL520-80
Low Phase Noise VCXO (9.5-65MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 011/09/04 Page
4
8. LVDS Electrical Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
V
OD
247
355 454 mV
V
DD
Magnitude Change
V
OD
-50
50 mV
Output High Voltage
V
OH
1.4 1.6 V
Output Low Voltage
V
OL
0.9
1.1 V
Offset Voltage
V
OS
1.125
1.2 1.375 V
Offset Magnitude Change
V
OS
R
L
= 100
(see figure)
0
3 25 mV
Power-off Leakage
I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1
10
uA
Output Short Circuit Current
I
OSD
-5.7 -8 mA
9. LVDS Switching Characteristics
PARAMETERS SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
t
r
0.2 0.7 1.0 ns
Differential Clock Fall Time
t
f
R
L
= 100
C
L
= 10 pF
(see figure)
0.2 0.7 1.0 ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test Circuit
LVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF
PLL520-80
Low Phase Noise VCXO (9.5-65MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 011/09/04 Page
5
10. PECL Electrical Characteristics
PARAMETERS SYMBOL CONDITIONS
MIN. MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.620
V
11. PECL Switching Characteristics
PARAMETERS SYMBOL CONDITIONS MIN.
TYP.
MAX.
UNITS
Clock Rise Time
t
r
@20/80% - PECL
0.6
1.5
ns
Clock Fall Time
t
f
@80/20% - PECL
0.5
1.5
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V
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