Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 08/12/04 Page 1
FEATURES
Low phase noise (-130 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable oscillator "on" or "off" ( Sleep Mode )
feature in output disable mode
Ultra Low current consumption ( <2mA, <1.5mA
at 27MHz, 3.3V respectively for PLL600-27 and
PLL600-37)
Ultra Low disable mode current (<2uA when
disabled with osc. off)
10 to 52MHz fundamental or 3
rd
OT crystal input.
12mA drive capability at TTL output.
Low jitter (RMS): 2.5ps period jitter.
1.8V, 2.5V and 3.3V DC operation.
Available in 8 pin SOIC, 6 pin SOT or DIE.
DESCRIPTION
The PLL600-27/-37 form a low cost family of XO
IC's, designed to consume the lowest current on the
market for the 10MHz to 52MHz range. It accepts
fundamental resonant mode crystal input from 10 to
52MHz. Providing less than -130dBc at 10kHz offset
at 30MHz and with a very low jitter (2.5 ps RMS pe-
riod jitter) makes this chip ideal for applications re-
quiring low current frequency sources.
BLOCK DIAGRAM
PIN ASSIGNMENT (PACKAGE)
8 pin SOIC
6 pin SOT
SELECTION TABLE
OE^
OSCSEL^*
OUTPUT
0
0
Disabled - osc. off
0
1
Disabled - osc. on
1
0
Enabled
1
1
Enabled
^ Internal Pull-up, default value is `1' when not connected.
* Not available in 6 pin SOT package.
XTAL
OSC
XIN/FIN
XOUT
CLK
OE
OSCSEL
1
2
3
4
XIN/FIN
5
6
7
8
N/C
GND
OSCSEL^
XOUT
OE^
VDD
CLK
P
L
L
6
0
0
-
x
7
^ : denotes internal pull-up
P
L
L
6
0
0
-
x
7
1
2
3
4
5
6
CLK
GND
XIN/FIN
VDD
XOUT
OE^
^: denotes internal Pull-up
Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 08/12/04 Page 2
PIN/PAD DESCRIPTION
Pin #
Name
8 pin
SOIC
6 pin
SOT
Type
Description
XIN
1
4
I
Crystal input or reference clock input pin.
N/C
2
n/a
I
No connect.
GND
3
2
P
Ground.
OSCSEL
4
n/a
I
Disable mode select. See Table on page 1.
CLK
5
1
O
Output clock.
VDD
6
6
P
Power supply.
OE
7
5
I
Output Enable input. See Table on page 1.
XOUT
8
3
I
Crystal output.
OE and OSCSEL have internal pull-ups, so the default value is `1' when not connected (OSCSEL not available on 6 pin package).
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6
V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5
V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5
V
Storage Temperature
T
S
-65
150
C
Ambient Operating Temperature*
T
A
-40
85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Electrical Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input Crystal Frequency
10
52
MHz
At power-up
(Vdd reaches 1.62V)
10
ms
Disable to enable, osc. Off
10
ms
Settling time
Disable to enable, osc. On
500
s
0.8V ~ 2.0V with 10 pF load
1.15
Output Clock Rise/Fall Time
0.3V ~ 3.0V with 15 pF load
2.4
ns
VDD sensitivity
Frequency vs. VDD +/- 10%
0.8
0.8
ppm
Output Clock Duty Cycle
Measured @ 50% V
DD
45
50
55
%
Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 08/12/04 Page 3
3. Jitter and Phase Noise Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
RMS Period Jitter
(1 sigma 1000 samples)
With capacitive decoupling
between VDD and GND.
2.1
2.5
ps
Phase Noise relative to carrier
30MHz @100Hz offset
-80
dBc/Hz
Phase Noise relative to carrier
30MHz @1kHz offset
-110
dBc/Hz
Phase Noise relative to carrier
30MHz @10kHz offset
-130
dBc/Hz
Phase Noise relative to carrier
30MHz @100kHz offset
-138
dBc/Hz
Phase Noise relative to carrier
30MHz @1MHz offset
-145
dBc/Hz
4. DC Specification
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
At 10MHz, Cload=15pF
1.0 / 0.75
1.1 / 0.9
At 13.5MHz, Cload=15pF
1.2 / 0.8
1.3 / 1.0
At 17.7MHz, Cload=15pF
1.5 / 1.0
1.6 / 1.1
At 27MHz, Cload=15pF
2.0 / 1.2
2.1 / 1.3
Supply Current, Dynamic,
with Loaded Outputs
(at VDD = 3.3V)
Respectively for PLL600
-27/-37
I
DD
At 48MHz, Cload=15pF
3.5 / 2.1
3.6 / 2.2
mA
Output disabled, Osc. off
2
4
A
Supply Current in tri-
state
I
DD
Output disabled, Osc. On
520
A
Operating Voltage
V
DD
1.62
3.63
V
I
OH
= -12mA* (3.3V)
2.4
V
Output High Voltage
V
OH
-37*, I
OH
= -12mA* (3.3V)
2.4
2.9
V
I
OL
= 12mA* (3.3V)
0.4
V
Output Low Voltage
V
OL
-37*, I
OL
= 12mA* (3.3V)
0.32
0.4
V
Output High Voltage at
CMOS level (PLL600-27)
V
OHC
I
OH
= -4mA
V
DD
0.4
V
Output drive current
(PLL600-27)
At TTL level (3.3V)
12
17
mA
Short Circuit Current
(3.3V)
50
mA
* Note: PLL600-37 has non-standard CMOS VOH and VOL levels for lower current consumption, but meets CMOS input stage needs. PLL600-37
should be used to drive pure capacitive loads only.
5. Crystal Specifications
PARAMETERS
SYMBOL
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
10
52
MHz
Crystal Loading Rating
C
L (xtal)
8.5
pF
Maximum Sustainable Drive Level
200
W
Operating Drive Level
50
W
C0 (for frequencies below 30MHz)
5
pF
C0 (for frequencies above 30MHz)
4
pF
ESR
R
S
30
Note: A detailed crystal specification document is also available for this part
Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 08/12/04 Page 4
PACKAGE INFORMATION
C
L
A
8-PIN SOIC ( dimensions in mm )
E
H
D
A
1
e
B
Narrow SOIC
Symbol
Min.
Max.
A
1.47
1.73
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
4.95
E
3.80
4.00
H
5.80
6.20
L
0.38
1.27
e
1.27 BSC
6-PIN SOIC ( dimensions in mm )
Preliminary
PLL600-27/-37
Ultra Low Current XO 10 MHz to 52 MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 08/12/04 Page 5
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL600-X7 x x
Temperature
C=Commercial
I=Industrial
Package
S=SOIC
T=SOT
Part Number
Order Number
Marking
Package Option
PLL600-27SC
P600-27 SC
8-Pin SOIC (Tube)
PLL600-27SC-R
P600-27 SC
8-Pin SOIC (Tape and Reel)
PLL600-27TC
A27A1
6-Pin SOT (Bulk)
PLL600-37SC
P600-37 SC
8-Pin SOIC (Tube)
PLL600-37SC-R
P600-37 SC
8-Pin SOIC (Tape and Reel)
PLL600-37TC
A37A2
6-Pin SOT (Bulk)
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