PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 1
FEATURES
100MHz to 200MHz Fundamental or 3
rd
Overtone Crystal input.
Output range: 100 200MHz (no multiplication),
200 400MHz (2x multiplier) or 400 700MHz
(4x multiplier).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DESCRIPTION
The PLL620-00 is an XO IC specifically designed to
work with high frequency fundamental and third
overtone crystals. Its design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. It
achieves very low current into the crystal resulting in
better overall stability. It is ideal for XO applications
requiring LVDS or PECL output levels at high
frequencies.
DIE SPECIFICATIONS
Name
Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
BLOCK DIAGRAM
DIE CONFIGURATION
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
OUTSEL0
(Pad #25)
Selected Output
0
0
High Drive CMOS
0
1
Standard CMOS
1
0
LVDS
1
1
PECL (default)
OE_SELECT
(Pad #9)
OE_CTRL
(Pad #30)
State
0
Tri-state
0
1 (Default) Output enabled
0 (Default) Output enabled
1 (Default)
1
Tri-state
Pad #9: Bond to GND to set to "0", bond to VDD to set to "1"
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad
#9) is "1"
Logical states defined by CMOS levels if OE_SELECT is
"0"
X+
X-
OE
Q
PLL620-00
Vin
Q
PLL by-pass
SEL
PLL
(Phase
Locked
Loop)
Oscillator
Amplifier
18
19
20
21
23
25
7
13
10
26
29
31
Y
X
(0,0)
(1550,1475)
6
2
m
i
l
65 mil
24
22
17
16
15
14
12
11
9
8
6
1
2
3
4
5
27
28
30
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
B
U
F
OE_SEL^
PECL
LVDS
VDDBUF
VDDBUF
PECLB
LVDSB
CMOS
GNDBUF
O
U
T
S
E
L
1
^
S
E
L
1
^
S
E
L
0
^
V
D
D
V
D
D
V
D
D
V
D
D
O
U
T
S
E
L
0
^
XIN
XOUT
NC
OE
CTRL
SEL2^
SEL3^
N
C
Die ID:
A1010-10A
C502A
PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 2
FREQUENCY SELECTION TABLE
SEL3
(Pad #28)
SEL2
(Pad #29)
SEL1
(Pad #19)
SEL0
(Pad #20)
Selected Multiplier
1
0
1
1
Fin x 4
1
1
1
0
Fin x 2
1
1
1
1
No multiplication (no PLL)
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6
V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5
V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5
V
Storage Temperature
T
S
-65
150
C
Ambient Operating Temperature*
T
A
-40
85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
3. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded
Outputs)
I
DD
PECL/LVDS/CMOS
100/80/40
mA
Operating Voltage
V
DD
2.97
3.63
V
Output Clock Duty Cycle
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
1.3V (PECL)
45
45
45
50
50
50
55
55
55
%
Short Circuit Current
50
mA
NAME
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Parallel Resonant mode
Fund. Or 3
rd
Overtone
N/A
Load capacitance (capacitance on
built-in on die seen by crystal)
C
L
Die only, no bond wire,
no package
3.2
pF
Inter-electrode capacitance
C
0
2
pF
Oscillation Frequency
Fund. Or 3
rd
Overtone
100
200
MHz
PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 3
4. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
2.5
Period jitter peak-to-peak
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
18.5
20
ps
Accumulated jitter RMS
2.5
Accumulated jitter peak-to-
peak
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
24
27
ps
Random Jitter
"RJ" measured on Wavecrest SIA 3000
2.5
ps
Integrated jitter RMS at
155MHz
Integrated 12 kHz to 20 MHz
0.3
0.4
ps
Period jitter RMS
11
Period jitter peak-to-peak
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
45
49
ps
Accumulated jitter RMS
11
Accumulated jitter peak-to-
peak
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
24
27
ps
Random Jitter
"RJ" measured on Wavecrest SIA 3000
3
ps
Integrated jitter RMS at
622MHz
Integrated 12 kHz to 20 MHz
1.6
1.8
ps
Note: Higher Q factor of 3
rd
overtone crystals will result in even better jitter performance.
Measured on Wavecrest SIA 3000
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz @1kHz @10kHz @100kHz UNITS
155.52MHz
-75
-95
-125
-140
-145
Phase Noise relative
to carrier
622.08MHz
-75
-95
-110
-125
-120
dBc/Hz
Note: Higher Q factor of 3
rd
overtone crystals will result in even better phase noise performance.
6. CMOS Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V
30
mA
Output drive current
(High Drive)
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
30
mA
I
OH
V
OH
= V
DD
-0.4V, V
DD
=3.3V
10
mA
Output drive current
(Standard Drive)
I
OL
V
OL
= 0.4V, V
DD
= 3.3V
10
mA
Output Clock Rise/Fall Time
(Standard Drive)
0.3V ~ 3.0V with 15 pF load
2.4
Output Clock Rise/Fall Time
(High Drive)
0.3V ~ 3.0V with 15 pF load
1.2
ns
PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 4
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
V
OD
247
355
454
mV
V
DD
Magnitude Change
V
OD
-50
50
mV
Output High Voltage
V
OH
1.4
1.6
V
Output Low Voltage
V
OL
0.9
1.1
V
Offset Voltage
V
OS
1.125
1.2
1.375
V
Offset Magnitude Change
V
OS
R
L
= 100
(see figure)
0
3
25
mV
Power-off Leakage
I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1
10
uA
Output Short Circuit Current
I
OSD
-5.7
-8
mA
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
t
r
0.2
0.7
1.0
ns
Differential Clock Fall Time
t
f
R
L
= 100
C
L
= 10 pF
(see figure)
0.2
0.7
1.0
ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test Circuit
LVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF
PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 5
9. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.620
V
10. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
t
r
@20/80% - PECL
0.6
1.5
ns
Clock Fall Time
t
f
@80/20% - PECL
0.5
1.5
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V
PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 6
PAD ASSIGNMENT
Pad #
Name
X (
m)
Y (
m)
Description
1
GND
248
109
Ground.
2
GND
361
109
Ground.
3
GND
473
109
Ground.
4
GND
587
109
Ground.
5
GND
702
109
Ground.
6
N/C
874
109
No Connection.
7
GND
1042
109
Ground.
8
GNDBUF
1171
109
Ground, Buffer circuitry.
9
OE_SELECT
1400
125
Used to select between PECL or CMOS logic states
for OE. See Output Selection and Enable table on
page 1. Internal pull up.
10
LVDS
1400
259
LVDS output.
11
PECL
1400
476
PECL output.
12
VDDBUF
1400
616
3.3V power supply, Buffer circuitry.
13
VDDBUF
1400
716
3.3V power supply, Buffer circuitry.
14
PECLB
1400
871
Complementary PECL output.
15
LVDSB
1400
1089
Complementary LVDS output.
16
CMOS
1400
1227
CMOS output
17
GNDBUF
1389
1365
Ground, Buffer Circuitry.
18
OUTSEL1
1232
1365
Used to select CMOS, PECL or LVDS output type.
See Output Selection and Enable table on page 1.
Internal pull up.
19
SEL1
1042
1365
Used to select multiplication factor. See Frequency
Selection table on page 1. Internal pull up.
20
SEL0
854
1365
Used to select multiplication factor. See Frequency
Selection table on page 1. Internal pull up.
21
VDD
659
1365
3.3V power supply.
22
VDD
559
1365
3.3V power supply.
23
VDD
459
1365
3.3V power supply.
24
VDD
358
1365
3.3V power supply.
25
OUTSEL0
194
1365
Used to select CMOS, PECL or LVDS output type.
See Output Selection and Enable table on page 1.
Internal pull up.
26
XIN
109
1223
Crystal input. See crystal specification page 2.
27
XOUT
109
1017
Crystal output. See crystal specification page 2.
28
SEL3
109
858
Used to select multiplication factor. See Frequency
Selection table on page 1. Internal pull up.
29
SEL2
109
646
Used to select multiplication factor. See Frequency
Selection table on page 1. Internal pull up.
30
OE_CTRL
109
397
Used to enable/disable the output(s). See Output
Selection and Enable table on page 1.
31
NC
109
181
No Connection.
PLL620-00
Low Phase Noise XO with multipliers (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 7
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL620-00 D C
Order Number
Marking
Package Option
PLL620-00DC
P620-00DC
Die Waffle Pack
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
D=DIE
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