Preliminary for proposal
PLL602-41
Low Phase Noise CMOS XO (48MHz to 96MHz)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 1
FEATURES
Low phase noise XO output for the 48MHz to
96MHz range (-137 dBc at 10kHz offset).
CMOS output.
12 to 24MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Low jitter (RMS): 3-6ps period, 7-10ps accum.
3.3V operation.
Available in 8-Pin TSSOP or SOIC.
DESCRIPTIONS
The PLL602-41 is a low cost, high performance and
low phase noise XO, providing less than -137dBc at
10kHz offset in the 48MHz to 96MHz operating
range. The very low jitter (3 to 6 ps RMS period jitter
and 7 to 10 ps RMS accumulated jitter) makes this
chip ideal for applications requiring reference fre-
quency sources. Input crystal can range from 12 to
24MHz (fundamental resonant mode).
PIN CONFIGURATION
OUTPUT RANGE
MULTIPLIER
FREQUENCY
RANGE
OUTPUT
BUFFER
X4
48 - 96MHz
CMOS
BLOCK DIAGRAM
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
VCO
Divider
XTAL
OSC
OE
XIN
XOUT
CLK
PLL602-41
1
2
3
4
5
6
7
8
CLK
VDD
OE
XIN
GND
N/C
XOUT
GND
Preliminary for proposal
PLL602-41
Low Phase Noise CMOS XO (48MHz to 96MHz)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
CLK
1
O
Output clock pin.
VDD
2
P
+3.3V VDD power supply pin.
OE
3
I
Output enable input pin. Disables (tri-state) output when low. Internal pull-
up enables output by default if pin is not connected to low.
XIN
4
I
Crystal input pin.
XOUT
5
I
Crystal output pin.
N/C
6
-
Not connected.
GND
7, 8
P
Ground pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
V
CC
-
0.5
7
V
Input Voltage Range
V
I
-
0.5
V
CC
+
0.5
V
Output Voltage Range
V
O
-
0.5
V
CC
+
0.5
V
Soldering Temperature
260
C
Storage Temperature
T
S
-65
150
C
Ambient Operating Temperature
0
70
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
2. AC Specification
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNITS
Input Frequency
12
24
MHz
Output Frequency
48
96
MHz
Output Rise Time
0.8V to 2.0V with no load
1.5
ns
Output Fall Time
2.0V to 0.8V with no load
1.5
ns
Duty Cycle
At VDD/2
45
50
55
%
Preliminary for proposal
PLL602-41
Low Phase Noise CMOS XO (48MHz to 96MHz)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 3
3. Jitter and Phase Noise specification
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNITS
Period jitter RMS
With capacitive decoupling
between VDD and GND.
VIN = 3.3V
TBM
ps
Accumulated jitter RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
VIN = 3.3V
TBM
ps
Phase Noise relative to carrier
100Hz offset, VIN = 3.3V
-101
dBc/Hz
Phase Noise relative to carrier
1kHz offset, VIN = 3.3V
-127
dBc/Hz
Phase Noise relative to carrier
10kHz offset, VIN = 3.3V
-137
dBc/Hz
Phase Noise relative to carrier
100kHz offset, VIN = 3.3V
-137
dBc/Hz
4. DC Specification
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Operating Voltage
VDD
3.135
3.465
V
Input High Voltage
V
IH
2
V
Input Low Voltage
V
IL
0.8
V
Input High Voltage
V
IH
For XIN pin
(VDD/2)
+
1
VDD/2
V
Input Low Voltage
V
IL
For XIN pin
VDD/2 (VDD/2)
-
1
V
Output High Voltage
V
OH
I
OH
= -25mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 25mA
0.4
V
Output High Voltage At
CMOS Level
V
OH
I
OH
= -8mA
VDD-0.4
V
Operating Supply Current
I
DD
No Load
35
mA
Short-circuit Current
I
S
120
mA
Input Capacitance
C
IN
OE, Select Pins
5
pF
5. Crystal Specifications
PARAMETERS
SYMBOL
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
12
24
MHz
Crystal Loading Capacitance Rating
C
L
(xtal)
TBD
pF
Driving power
1
mW
ESR
R
S
25
Preliminary for proposal
PLL602-41
Low Phase Noise CMOS XO (48MHz to 96MHz)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 4
PACKAGE INFORMATION
ORDERING INFORMATION
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY
: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL602-41 X C
PART NUMBER
TEMPERATURATURE
C=COMMERCIAL
M=MILITARY
I=INDUSTRAL
PACKAGE TYPE
S=SOIC, O=TSSOP, D=DIE
C
L
A
8 PIN ( dimensions in mm )
Narrow SOIC
Symbol
Min.
Max.
A
1.47
1.73
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
4.95
E
3.80
4.00
H
5.80
6.20
L
0.38
1.27
e
1.27 BSC
E
H
D
A1
e
B
TSSOP
Min.
Max.
-
1.20
0.05
0.15
0.19
0.30
0.09
0.20
2.90
3.10
4.30
4.50
6.20
6.60
0.45
0.75
0.65 BSC
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