PLL620-20
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 1
FEATURES
100MHz to 200MHz Fund. or 3
rd
OT Crystal.
Output range: 100 200MHz (no multiplication).
Available outputs: PECL, or LVDS.
OESEL/OECTRL for both PECL & LVDS.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Die thickness 10 mil.
DESCRIPTION
The PLL620-20 is an XO IC specifically designed to
work with high frequency fundamental and third
overtone crystals. Its design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. It
achieves very low current into the crystal resulting in
better overall stability. It is ideal for XO applications
requiring LVDS or PECL output levels at high
frequencies.
DIE SPECIFICATIONS
Name
Value
Size
62 x 65 mil
Reverse side
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
BLOCK DIAGRAM
DIE CONFIGURATION
OUTPUT SELECTION AND ENABLE
Pad #9
OUTSEL
Selected Output
0
LVDS
1
PECL (default)
Pad #9
OUTSEL
Pad #30
OE_CTRL
State
0
Tri-state
0
1
Output enabled (default)
0
Output enabled (default)
1
1
Tri-state
Pad #9: Bond to GND to set to "0", bond to VDD to set to "1"
Pad #30: Logical states defined by PECL levels if OUTSEL is "1"
Logical states defined by CMOS levels if OUTSEL is "0"
X+
X-
OE
Q
PLL620-20
Q
Oscillator
Amplifier
18
19
20
21
23
25
7
13
10
26
29
31
Y
X
(0,0)
(1550,1475)
6
2
m
i
l
65 mil
24
22
17
16
15
14
12
11
9
8
6
1
2
3
4
5
27
28
30
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
B
U
F
G
N
D
B
U
F
OUTSEL^
PECL
LVDS
VDDBUF
VDDBUF
PECLB
LVDSB
N/C
GNDBUF
R
e
s
e
r
v
e
d
R
e
s
e
r
v
e
d
N
/
C
V
D
D
V
D
D
V
D
D
V
D
D
N
/
C
XIN
XOUT
N/C
OE
CTRL
N/C
N/C
R
e
s
e
r
v
e
d
Die ID:
A1212-12
C502A
PLL620-20
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 2
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
4.6
V
Input Voltage, dc
V
I
-0.5
V
DD
+0.5
V
Output Voltage, dc
V
O
-0.5
V
DD
+0.5
V
Storage Temperature
T
S
-65
150
C
Ambient Operating Temperature*
T
A
-40
85
C
Junction Temperature
T
J
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Crystal Resonator Frequency
F
XIN
Fundamental or 3
rd
overtone*
100
200
MHz
Crystal Loading Rating
C
L (xtal)
Die
5
pF
Interelectrode Capacitance
C
0
5
pF
Recommended ESR
R
E
AT cut
30
* Note: 3
rd
overtone crystals require an external resistor between XIN and XOUT to prevent the fundamental from oscillating.
3. General Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (Loaded
Outputs)
I
DD
PECL/LVDS
100/80
mA
Operating Voltage
V
DD
2.97
3.63
V
Output Clock Duty Cycle
@ 1.25V (LVDS)
@ V
DD
1.3V (PECL)
45
45
50
50
55
55
%
Short Circuit Current
50
mA
PLL620-20
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 3
4. Jitter Specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS at 155MHz
2.5
Period jitter peak-to-peak at 155MHz
At 155.52MHz, with capacitive
decoupling between VDD and
GND. Over 10,000 cycles
18.5
20
ps
Accumulated jitter RMS at 155MHz
2.5
Accumulated jitter peak-to-peak at
155MHz
At 155.52MHz, with capacitive
decoupling between VDD and
GND. Over 1,000,000 cycles.
24
27
ps
Random Jitter
"RJ" measured on Wavecrest SIA
3000
2.5
ps
Integrated jitter RMS at 155MHz
Integrated 12 kHz to 20 MHz
0.3
0.4
ps
Note: Higher Q factor of 3
rd
overtone crystals will result in even better jitter performance.
5. Phase Noise Specifications
PARAMETERS
FREQUENCY
@10Hz
@100Hz @1kHz @10kHz @100kHz UNITS
Phase Noise relative
to carrier
155.52MHz
-75
-95
-125
-140
-145
dBc/Hz
Note: Higher Q factor of 3
rd
overtone crystals will result in even better phase noise performance.
PLL620-20
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 4
6
. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output Differential Voltage
V
OD
247
355
454
mV
V
DD
Magnitude Change
V
OD
-50
50
mV
Output High Voltage
V
OH
1.4
1.6
V
Output Low Voltage
V
OL
0.9
1.1
V
Offset Voltage
V
OS
1.125
1.2
1.375
V
Offset Magnitude Change
V
OS
R
L
= 100
(see figure)
0
3
25
mV
Power-off Leakage
I
OXD
V
out
= V
DD
or GND
V
DD
= 0V
1
10
uA
Output Short Circuit Current
I
OSD
-5.7
-8
mA
7. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
t
r
0.2
0.7
1.0
ns
Differential Clock Fall Time
t
f
R
L
= 100
C
L
= 10 pF
(see figure)
0.2
0.7
1.0
ns
OUT
OUT
V
OD
V
OS
50
50
OUT
V
DIFF
R
L
= 100
C
L
= 10pF
C
L
= 10pF
LVDS Switching Test Circuit
LVDS Levels Test Circuit
LVDS Transistion Time Waveform
OUT
OUT
OUT
0V (Differential)
0V
20%
80%
20%
80%
t
R
t
F
V
DIFF
PLL620-20
Low Phase Noise XO (for HF Fund. and 3
rd
O.T.)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com Rev 09/03/04 Page 5
8. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
V
OH
V
DD
1.025
V
Output Low Voltage
V
OL
R
L
= 50
to (V
DD
2V)
(see figure)
V
DD
1.620
V
9. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
t
r
@20/80% - PECL
0.6
1.5
ns
Clock Fall Time
t
f
@80/20% - PECL
0.5
1.5
ns
OUT
OUT
50
50
PECL Levels Test Circuit
PECL Transistion Time Waveform
OUT
OUT
50%
20%
80%
t
R
t
F
VDD
DUTY CYCLE
45 - 55%
55 - 45%
50%
OUT
OUT
t
SKEW
PECL Output Skew
2.0V
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