NetChip
Technology, Inc.
335 Pioneer Way
Mt View, California 94041
(650) 526-1490 Fax (650) 526-1494
e-mail: sales@netchip.com
Internet: www.netchip.com
NET1031 USB Scanner Controller
PRELIMINARY SPECIFICATION
ADVANCE INFORMATION
Doc #: 605-0073-0011
Revision: 1.0
Date: 3 / 19 / 99
Preliminary Specification
NET1031 USB Scanner Controller
NetChip Technology, Inc., 1999
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Revision 1.0, Mar 19, 1999
2
This document contains material that is confidential to NetChip. Reproduction without the express written
consent of NetChip is prohibited. All reasonable attempts were made to ensure the contents of this document are
accurate; however no liability, expressed or implied is guaranteed. NetChip reserves the right to modify this
document, without notification, at any time.
Revision History
Revision
Issue Date
Comments
0.1
October 17, 1997
NET1031 Initial Draft Specification Proposal
0.2
March 30, 1998
16-Bit Register initial draft
0.3
July 22, 1998
Move Applications information to AppNote.
Update Register layout
0.4
July 23, 1998
Re-organize the endpoint structure
0.5
Aug 27, 1998
Re-organize registers; add new SRAM and initialization features
0.6
Sept 11, 1998
Add some new registers
0.7
Oct 7, 1998
Add some more new registers
0.8
Nov 9, 1998
Clarify some text. Modify some registers
0.9
Jan 4, 1999
Modify some registers
0.10
Jan 8, 1999
Change pinouts, modify some defaults
0.11
Jan 17, 1999
Modify some defaults
1.0
Mar 19, 1999
Modify some defaults, remove references to PRNU and B/W
threshold
Preliminary Specification
NET1031 USB Scanner Controller
NetChip Technology, Inc., 1999
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Revision 1.0, Mar 19, 1999
3
NET1031 USB Scanner Controller
1
Highlights .................................................................................................................................................... 7
1.1
Introduction ............................................................................................................................................. 7
1.2
Features.................................................................................................................................................... 7
1.2.1
General Features ............................................................................................................................. 7
1.2.2
Scanner Features ............................................................................................................................. 7
1.2.3
USB Features .................................................................................................................................. 7
1.3
Overview.................................................................................................................................................. 7
1.4
NET1031 Block Diagram ......................................................................................................................... 9
NET1031 CIS Scanner System Block Diagram................................................................................................ 10
NET1031 CCD Scanner System Block Diagram.............................................................................................. 10
2
Pin Connection Diagram........................................................................................................................... 11
3
Pin Description.......................................................................................................................................... 12
4
Functional Description .............................................................................................................................. 18
4.1
Start-Up ................................................................................................................................................. 18
4.1.1
Reading from Initialization Device................................................................................................ 18
4.1.2
Enumeration by the Host PC ......................................................................................................... 18
4.1.3
Configuration by the Scanner Driver ............................................................................................. 18
4.1.4
Global Calibration......................................................................................................................... 18
4.2
Initialization Interface ............................................................................................................................ 19
4.2.1
E
2
PROMs (93CS06, 93CS46, 93CS56, 93CS66) ........................................................................... 19
4.2.2
IDSEL Pin Initialization................................................................................................................ 20
4.3
Scanner Functions .................................................................................................................................. 21
4.3.1
CCD/CIS Control.......................................................................................................................... 21
4.3.2
General Data Flow ........................................................................................................................ 21
4.3.3
Analog Block Interface.................................................................................................................. 22
4.3.4
Stepper Motor Control................................................................................................................... 22
4.3.5
Image Buffering in SRAM ............................................................................................................ 22
4.3.6
General I/O Pins ........................................................................................................................... 22
4.3.7
Abort# Pin .................................................................................................................................... 23
4.4
USB Interface......................................................................................................................................... 23
4.4.1
Default Control Pipe (Endpoint 0x00) ........................................................................................... 23
4.4.2
SRAM Write Pipe (Endpoint 0x01) ............................................................................................... 23
4.4.3
SRAM/Image Data Read Pipe (Endpoint 0x81) ............................................................................. 23
4.4.4
Status Input Pipe (Endpoint 0x82)................................................................................................. 23
4.5
I/O Space Access.................................................................................................................................... 24
4.6
Suspend Mode........................................................................................................................................ 24
4.6.1
The Suspend Sequence .................................................................................................................. 24
4.6.2
Host-Initiated Wake-Up................................................................................................................. 24
4.6.3
Device-Remote Wake-Up .............................................................................................................. 24
4.7
Root Port Reset....................................................................................................................................... 25
4.8
NET1031 Power Configuration .............................................................................................................. 25
4.8.1
Bus-Powered Device...................................................................................................................... 25
4.8.2
Self-Powered Device ..................................................................................................................... 25
5
Register Descriptions ................................................................................................................................ 26
5.1
Control Registers Description................................................................................................................. 27
5.1.1
Control Registers Summary........................................................................................................... 27
5.1.2
(Address 00h; MASTERCTL) Master Control............................................................................... 28
5.1.3
(Address 01h; MEMIOCTL) Memory, I/O Control ....................................................................... 28
5.1.4
(Address 02h; PIXCTL) Pixel Control........................................................................................... 29
5.1.5
(Address 03h; IOCFG) I/O Pin Configuration ............................................................................... 29
Preliminary Specification
NET1031 USB Scanner Controller
NetChip Technology, Inc., 1999
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Revision 1.0, Mar 19, 1999
4
5.1.6
(Address 04h; SCANSTAT) Scanner Status .................................................................................. 30
5.1.7
(Address 05h; IOSTAT) I/O Pin Status ......................................................................................... 30
5.1.8
(Address 06h; SCANCHG) Scanner Status Change Register ......................................................... 31
5.1.9
(Address 07h; IOCHG) I/O Pin Status Change Register ................................................................ 31
5.1.10
(Address 08h; SRAMADDR1) SRAM Address, Most-Significant Word....................................... 31
5.1.11
(Address 09h; SRAMADDR0) SRAM Address, Least-Significant Word ...................................... 31
5.1.12
(Address 0Ah - 0Fh; RESERVED) Reserved for future use ........................................................... 31
5.1.13
(Address 10h; SRAMBASE1) SRAM FIFO Address Base, Most-Significant Word ...................... 31
5.1.14
(Address 11h; SRAMBASE0) SRAM FIFO Address Base, Least-Significant Word...................... 31
5.1.15
(Address 12h; SRAMTOP1) SRAM FIFO Address Top, Most-Significant Word.......................... 32
5.1.16
(Address 13h; SRAMTOP0) SRAM FIFO Address Top, Least-Significant Word ......................... 32
5.1.17
(Address 14h; FIFOFSTHR1) FIFO Full-Speed Threshold, Most-Significant Word...................... 32
5.1.18
(Address 15h; FIFOFSTHR0) FIFO Full-Speed Threshold, Least-Significant Word ..................... 32
5.1.19
(Address 16h; FIFOHSTHR1) FIFO Half-Speed Threshold, Most-Significant Word..................... 32
5.1.20
(Address 17h; FIFOHSTHR0) FIFO Half-Speed Threshold, Least-Significant Word .................... 33
5.1.21
(Address 18h; FIFOSTOPTHR1) FIFO Stop Threshold, Most-Significant Word .......................... 33
5.1.22
(Address 19h; FIFOSTOPTHR0) FIFO Stop Threshold, Least-Significant Word .......................... 33
5.1.23
(Address 1Ah; FIFOCOUNT1) FIFO Byte Count, Most-Significant Word.................................... 33
5.1.24
(Address 1Bh; FIFOCOUNT0) FIFO Byte Count, Least-Significant Word ................................... 33
5.1.25
(Address 1Ch; FIFOSTAT) FIFO Status........................................................................................ 34
5.1.26
(Address 1Dh - 1Fh; RESERVED) Reserved for future use ........................................................... 34
5.1.27
(Address 20h; COLORCYCLE) Color Cycle Time Period ............................................................. 34
5.1.28
(Address 21h; PELCYCLE) Pixel Cycle Time Period.................................................................... 34
5.1.29
(Address 22h; LINECYCLE) Line Cycle Time Period................................................................... 34
5.1.30
(Address 23h; STEPCYCLE) Stepper Cycle Time Period.............................................................. 34
5.1.31
(Address 25h; PELSTROBE) Pixel Strobe..................................................................................... 35
5.1.32
(Address 26h; COLORSTART) Color Cycle Start Offset............................................................... 35
5.1.33
(Address 27h; PELSTART) Pixel Cycle Start Offset...................................................................... 35
5.1.34
(Address 28h; FIRSTPEL) First Active Pixel................................................................................. 35
5.1.35
(Address 29h; LASTPEL) Last Active Pixel .................................................................................. 35
5.1.36
(Address 2Ah; FIRSTLINE) First Scan Line ................................................................................. 36
5.1.37
(Address 2Bh; LASTLINE) Last Scan Line................................................................................... 36
5.2
Pixel-based Waveform Register Description ........................................................................................... 37
5.2.1
Pixel-based Waveform Register Summary ..................................................................................... 37
5.2.2
(xxxxHIGH) Pixel-based Waveform High Offset ........................................................................... 38
5.2.3
(xxxxLOW) Pixel-based Waveform Low Offset............................................................................. 38
5.2.4
(xxxxCTL) Pixel-based Waveform Control.................................................................................... 38
5.3
Line-based Waveform Register Description ............................................................................................ 39
5.3.1
Line-based Waveform Register Summary ...................................................................................... 39
5.3.2
(xxxxHIGH) Line-based Waveform High Offset ............................................................................ 40
5.3.3
(xxxxLOW) Line-based Waveform Low Offset.............................................................................. 40
5.3.4
(xxxxCTL) Line-based Waveform Control .................................................................................... 40
5.4
Stepper-based Waveform Register Description ....................................................................................... 41
5.4.1
Stepper-based Waveform Register Summary ................................................................................. 41
5.4.2
(xxxxHIGH) Stepper-based Waveform High Offset ....................................................................... 42
5.4.3
(xxxxLOW) Stepper-based Waveform Low Offset ......................................................................... 42
5.4.4
(xxxxCTL) Stepper-based Waveform Control................................................................................ 42
5.5
USB Register Description....................................................................................................................... 43
5.5.1
USB Register Summary................................................................................................................. 43
5.5.2
(Address F0h; VID) Vendor ID ..................................................................................................... 43
5.5.3
(Address F1h; PID) Product ID ..................................................................................................... 43
5.5.4
(Address F2h; REL) Release Number ............................................................................................ 43
Preliminary Specification
NET1031 USB Scanner Controller
NetChip Technology, Inc., 1999
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
Revision 1.0, Mar 19, 1999
5
5.5.5
(Address F3h; MAXPWR) Maximum Power................................................................................. 43
5.5.6
(Address F4h; USBCTL1) USB Control Register 1........................................................................ 44
5.5.7
(Address F5h; USBCTL2) USB Control Register 2........................................................................ 45
5.5.8
(Address F6h; STRINDEX1) String Index 1 ................................................................................. 46
5.5.9
(Address F7h; STRINDEX2) String Index 2 ................................................................................. 46
5.5.10
(Address F8h - FBh; RESERVED) Reserved for future use............................................................ 46
5.5.11
(Address FCh; EECTL) EEPROM Control.................................................................................... 46
5.5.12
(Address FDh; EEADDR) EEPROM Address ............................................................................... 47
5.5.13
(Address FEh; EEDATA) EEPROM Data ..................................................................................... 47
5.5.14
(Address FFh; REVISION) NET1031 Silicon Revision ................................................................. 47
6
USB Vendor-Specific Device Requests (Endpoint 0)................................................................................ 48
6.1
Register Write ........................................................................................................................................ 48
6.2
Register Read ......................................................................................................................................... 49
6.3
I/O Write................................................................................................................................................ 49
6.4
I/O Read................................................................................................................................................. 50
6.5
Manufacturer Test Mode ........................................................................................................................ 50
6.5.1
6.5.1 Device Clear Feature (Timing Test Mode) ............................................................................ 50
6.5.2
6.5.2 Device Set Feature (Timing Test Mode)................................................................................ 50
7
USB Standard Device Requests (Endpoint 0)........................................................................................... 51
7.1
Control `IN' Transactions ...................................................................................................................... 51
7.1.1
Get Device Status .......................................................................................................................... 51
7.1.2
Get Interface Status ....................................................................................................................... 51
7.1.3
Get Endpoint 0x00, 0x01, 0x81, 0x82 Status................................................................................. 51
7.1.4
Get Device Descriptor (18 Bytes)................................................................................................... 51
7.1.5
Get Configuration Descriptor (39 bytes) ........................................................................................ 52
7.1.6
Get String Descriptor 0 ................................................................................................................. 53
7.1.7
Get String Descriptor 1 ................................................................................................................. 53
7.1.8
Get String Descriptor 2 ................................................................................................................. 54
7.1.9
Get String Descriptor 3 ................................................................................................................. 54
7.1.10
Get Configuration ......................................................................................................................... 54
7.1.11
Get Interface ................................................................................................................................. 54
7.2
Control `OUT' Transactions................................................................................................................... 55
7.2.1
Set Address ................................................................................................................................... 55
7.2.2
Set Configuration .......................................................................................................................... 55
7.2.3
Set Interface .................................................................................................................................. 55
7.2.4
Device Clear Feature ..................................................................................................................... 55
7.2.5
Device Set Feature......................................................................................................................... 55
7.2.6
Endpoint Clear Feature ................................................................................................................. 55
7.2.7
Endpoint Set Feature ..................................................................................................................... 55
8
Bulk and Interrupt Endpoints .................................................................................................................. 56
8.1
Endpoint 0x01 `OUT' Transactions (SRAM Write Pipe) ........................................................................ 56
8.2
Endpoint 0x81 `IN' Transactions (SRAM/Image Data Read Pipe).......................................................... 56
8.3
Endpoint 0x82 `IN' Transactions (Status Input Pipe).............................................................................. 56
9
Signal Timing ............................................................................................................................................ 57
9.1
Signal Timing ........................................................................................................................................ 57
9.1.1
Color- and Pixel-Based Signal Timing .......................................................................................... 57
9.1.2
Line-Based Signal Timing............................................................................................................. 57
9.1.3
Stepper-Based Signal Timing ........................................................................................................ 58
9.2
SRAM Write Timing.............................................................................................................................. 59
9.3
SRAM Read Timing............................................................................................................................... 59
9.4
I/O Write Timing ................................................................................................................................... 60
9.5
I/O Read Timing .................................................................................................................................... 60
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