Document Outline

• Contents
• Figures
• Tables
• Registers
• Timing Diagrams
• Preface
  • Supplemental Documentation
  • Terms and Definitions
  • Revision History
• 1 Introduction
  • 1.1 Company and Product Background
  • 1.2 General Description
  • 1.3 PCI90501 Major Features
  • 1.4 Pin Compatibility
  • 1.5 PCI90501 Comparison with Other PLX Chips
• 2 Bus Operation
  • 2.1 PCI Bus
    • 2.1.1 PCI Bus Interface and Bus Cycles
      • 2.1.1.1 PCI Target (Direct Slave) Command Codes
      • 2.1.1.2 Wait States�PCI Bus
      • 2.1.1.3 PCI Bus Little Endian Mode
      • 2.1.1.4 PCI Prefetchable MemoryMapping
      • 2.1.1.5 PCI Target (Direct Slave) Accesses to an 8or16Bit Local Bus Device
  • 2.2 Local Bus
    • 2.2.1 Introduction
      • 2.2.1.1 Transactions
      • 2.2.1.2 Basic Bus States
    • 2.2.2 Local Bus Signals Used inTimingDiagram
    • 2.2.3 Local Bus Signals
      • 2.2.3.1 Clock
      • 2.2.3.2 Address/Data
        • 2.2.3.2.1 LA[27:2]
        • 2.2.3.2.2 LAD[31:0]
      • 2.2.3.3 Control/Status
        • 2.2.3.3.1 ADS#, ALE
        • 2.2.3.3.2 LBE[3:0]#
        • 2.2.3.3.3 LRDYi#
        • 2.2.3.3.4 LW/R#
        • 2.2.3.3.5 WAITO#
        • 2.2.3.3.6 LLOCKo#
        • 2.2.3.3.7 RD#
        • 2.2.3.3.8 WR#
      • 2.2.3.4 Local Bus Arbitration
        • 2.2.3.4.1 LHOLD
        • 2.2.3.4.2 LHOLDA
    • 2.2.4 Local Bus Interface andBusCycles
      • 2.2.4.1 Bus Cycles
      • 2.2.4.2 Wait State Control
        • 2.2.4.2.1 Internal Wait State Generator
        • 2.2.4.2.2 Ready Signaling
      • 2.2.4.3 Burst Mode and Continuous BurstMode (Bterm �Burst Terminate� Mode)
        • 2.2.4.3.1 Burst and Bterm Modes
        • 2.2.4.3.2 Burst-4 Lword Mode
          • 2.2.4.3.2.1 Continuous Burst Mode (Bterm�Burst Terminate� Mode)
        • 2.2.4.3.3 Partial Lword Accesses
      • 2.2.4.4 Recovery States
      • 2.2.4.5 Local Bus Read Accesses
      • 2.2.4.6 Local Bus Write Accesses
    • 2.2.5 Local Bus Big/Little Endian Mode
      • 2.2.5.1 32-Bit Local Bus� BigEndianMode
      • 2.2.5.2 16-Bit Local Bus� BigEndianMode
      • 2.2.5.3 8-Bit Local Bus� BigEndianMode
  • 2.3 Arbitration Timing Diagram
• 3 Reset and Serial EEPROM Initialization
  • 3.1 Initialization
  • 3.2 Reset
    • 3.2.1 PCI Bus RST# Input
    • 3.2.2 Software Reset
    • 3.2.3 Local Bus Output LRESET#
  • 3.3 Serial EEPROM
    • 3.3.1 Serial EEPROM Load Sequence
      • 3.3.1.1 Serial EEPROM Load
      • 3.3.1.2 Recommended Serial EEPROMs
  • 3.4 Internal Registers
    • 3.4.1 PCI Configuration Registers
    • 3.4.2 PCI Bus Access to InternalRegisters
  • 3.5 Timing Diagrams
• 4 Direct Slave Operation
  • 4.1 Overview
  • 4.2 Direct Data Transfer Mode
    • 4.2.1 Direct Slave Operation (PCI Masterto-Local Bus Access)
      • 4.2.1.1 Direct Slave Lock
      • 4.2.1.2 PCIr2.1 Features Enable
        • 4.2.1.2.1 Direct Slave Delayed Read Mode Operation
        • 4.2.1.2.2 32000 PCI Clock Timeout
        • 4.2.1.2.3 PCIr2.1 16- and 8-Clock Rule
      • 4.2.1.3 Direct Slave Read Ahead Mode
      • 4.2.1.4 Direct Slave Transfer
      • 4.2.1.5 Direct Slave PCI-to-Local AddressMapping
        • 4.2.1.5.1 Direct Slave Local Bus Initialization
        • 4.2.1.5.2 Direct Slave Initialization
        • 4.2.1.5.3 Direct Slave Example
        • 4.2.1.5.4 Direct Slave Byte Enables (Non-Multiplexed Mode)
        • 4.2.1.5.5 Direct Slave Byte Enables (Multiplexed Mode)
  • 4.3 Response to FIFO FullorEmpty
  • 4.4 Timing Diagrams
    • 4.4.1 Serial EEPROM and Configuration Initialization
    • 4.4.2 Non-Multiplexed Mode Local Bus
    • 4.4.3 Big Endian Mode and Multiplexed Mode Local Bus
• 5 Local Chip Select
  • 5.1 Overview
  • 5.2 Chip Select Base AddressRegisters
  • 5.3 Procedure for Using ChipSelect Base AddressRegisters
    • 5.3.1 Chip Select Base Address Register Programming Example
  • 5.4 Timing Diagram
• 6 PCI/Local Interrupts and User I/O
  • 6.1 Overview
  • 6.2 Interrupts
    • 6.2.1 PCI Interrupts (INTA#)
    • 6.2.2 Local Interrupt Input (LINTi[2:1])
    • 6.2.3 All Modes PCI SERR# (PCINMI)
  • 6.3 User I/O
  • 6.4 Timing Diagrams
• 7 Registers
  • 7.1 Register Address Mapping
  • 7.2 PCI Configuration Registers
  • 7.3 Local Configuration Registers
    • 7.3.1 Chip Select Registers
    • 7.3.2 Control Registers
• 8 Pin Descriptions
  • 8.1 Pin Summary
  • 8.2 Pull-Up and Pull-Down Resistor Recommendations
    • 8.2.1 NC Pins
    • 8.2.2 Input Pins (Pin Type I)
    • 8.2.3 Output Pins (Pin Type O)
    • 8.2.4 I/O Pins (Pin Type I/O)
  • 8.3 Pinout
• 9 Electrical Specifications
  • 9.1 General Electrical Specifications
  • 9.2 Local Inputs
  • 9.3 Local Outputs
• 10 Physical Specifications
  • 10.1 Mechanical Layout
  • 10.2 Typical Adapter Block Diagram
  • 10.3 Pin Assignments
• A General Information
• Index
  • A
  • B
  • C
  • D
  • E
  • F
  • G
  • H
  • I
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • T
  • U
  • V
  • W
  • Z