Document Outline

• Contents
• Figures
• Tables
• Registers
• Timing Diagrams
• Preface
  • Supplemental Documentation
  • Terms and Definitions
  • Revision History
• 1 Introduction
  • 1.1 Company and Product Background
  • 1.2 General Description
  • 1.3 PCI 9052 Major Features
  • 1.4 PCI 9052 and PCI 9050 Compatibility
    • 1.4.1 PCI 9052 New Features
    • 1.4.2 Errata
      • 1.4.2.1 PCI 9050 Issues Resolved in PCI 9052
      • 1.4.2.2 PCI 9052 Issues Not Present in PCI 9050
    • 1.4.3 Signaling
      • 1.4.3.1 PCI Bus
      • 1.4.3.2 Local Bus
      • 1.4.3.3 Pull-Up and Pull-Down Resistor Recommendations
  • 1.5 PCI 9052 Comparison with Other PLX Chips
• 2 Bus Operation
  • 2.1 PCI Bus
    • 2.1.1 PCI Bus Interface and Bus Cycles
      • 2.1.1.1 PCI Target (Direct Slave) Command Codes
      • 2.1.1.2 Wait States�PCI Bus
      • 2.1.1.3 PCI Bus Little Endian Mode
      • 2.1.1.4 PCI Prefetchable Memory Mapping
      • 2.1.1.5 PCI Target (Direct Slave) Accesses to an 8- or 16-Bit Local Bus Device
  • 2.2 Local Bus
    • 2.2.1 Introduction
      • 2.2.1.1 Transactions
      • 2.2.1.2 Basic Bus States
    • 2.2.2 Local Bus Signals Used in Timing Diagrams
    • 2.2.3 Local Bus Signals
      • 2.2.3.1 Clock
      • 2.2.3.2 Address/Data
        • 2.2.3.2.1 LA[27:2]
        • 2.2.3.2.2 LAD[31:0]
      • 2.2.3.3 Control/Status
        • 2.2.3.3.1 ADS#, ALE
        • 2.2.3.3.2 LBE[3:0]#
        • 2.2.3.3.3 LLOCKo#
        • 2.2.3.3.4 LRDYi#
        • 2.2.3.3.5 LW/R#
        • 2.2.3.3.6 RD#
        • 2.2.3.3.7 WAITO#
        • 2.2.3.3.8 WR#
      • 2.2.3.4 Local Bus Arbitration
        • 2.2.3.4.1 LHOLD
        • 2.2.3.4.2 LHOLDA
    • 2.2.4 Local Bus Interface and Bus Cycles
      • 2.2.4.1 Bus Cycles
      • 2.2.4.2 Wait State Control
        • 2.2.4.2.1 Internal Wait State Generator
        • 2.2.4.2.2 Ready Signaling
      • 2.2.4.3 Burst Mode and Continuous Burst Mode (Bterm �Burst Terminate� Mode)
        • 2.2.4.3.1 Burst and Bterm Modes
        • 2.2.4.3.2 Burst-4 Lword Mode
          • 2.2.4.3.2.1 Continuous Burst Mode (Bterm �Burst Terminate� Mode)
        • 2.2.4.3.3 Partial Lword Accesses
      • 2.2.4.4 Recovery States
      • 2.2.4.5 Local Bus Read Accesses
      • 2.2.4.6 Local Bus Write Accesses
    • 2.2.5 Local Bus Big/Little Endian Mode
      • 2.2.5.1 32-Bit Local Bus� BigEndianMode
      • 2.2.5.2 16-Bit Local Bus� BigEndianMode
      • 2.2.5.3 8-Bit Local Bus� BigEndianMode
  • 2.3 Arbitration Timing Diagram
• 3 Reset and Serial EEPROM Initialization
  • 3.1 Initialization
  • 3.2 Reset
    • 3.2.1 PCI Bus RST# Input
    • 3.2.2 Software Reset
    • 3.2.3 Local Bus Output LRESET#
  • 3.3 Serial EEPROM
    • 3.3.1 Serial EEPROM Load Sequence
      • 3.3.1.1 Serial EEPROM Load
      • 3.3.1.2 Recommended Serial EEPROMs
  • 3.4 Internal Registers
    • 3.4.1 PCI Configuration Registers
    • 3.4.2 PCI Bus Access to InternalRegisters
  • 3.5 Timing Diagrams
• 4 Direct Slave Operation
  • 4.1 Overview
  • 4.2 Direct Data Transfer Mode
    • 4.2.1 Direct Slave Operation (PCI Master-to-Local Bus Access)
      • 4.2.1.1 DirectSlave Lock
      • 4.2.1.2 PCIr2.1 Features Enable
        • 4.2.1.2.1 DirectSlave Delayed Read Mode Operation
        • 4.2.1.2.2 32000 PCI Clock Timeout
        • 4.2.1.2.3 PCIr2.1 16- and 8-Clock Rule
      • 4.2.1.3 DirectSlave Read Ahead Mode
      • 4.2.1.4 DirectSlave Transfer
      • 4.2.1.5 DirectSlave PCI-to-Local AddressMapping
        • 4.2.1.5.1 DirectSlave Local Bus Initialization
        • 4.2.1.5.2 DirectSlave Initialization
        • 4.2.1.5.3 DirectSlave Example
        • 4.2.1.5.4 DirectSlave Byte Enables (NonMultiplexed Mode)
        • 4.2.1.5.5 DirectSlave Byte Enables (MultiplexedMode)
  • 4.3 Response to FIFO Full or Empty
  • 4.4 Timing Diagrams
    • 4.4.1 Serial EEPROM and Configuration Initialization
    • 4.4.2 Non-Multiplexed Mode Local Bus
    • 4.4.3 Big Endian Mode and Multiplexed Mode Local Bus
• 5 ISA Interface Mode
  • 5.1 Architecture
  • 5.2 Pin Definitions
    • 5.2.1 LRESET#/LRESET
    • 5.2.2 CS0#/MEMRD# and CS1#/MEMWR#
    • 5.2.3 USER0/WAITO#/IORD# and USER1/LLOCKo#/IOWR#
    • 5.2.4 ALE/BALE
    • 5.2.5 NC/CHRDY
    • 5.2.6 NC/NOWS#
    • 5.2.7 Other Local Bus Signals
  • 5.3 Configuring Local Registers for ISAInterfaceMode
  • 5.4 Design Considerations
    • 5.4.1 Interrupts
    • 5.4.2 Address and Control Signals
    • 5.4.3 Ready Signaling Protocol and Timing
      • 5.4.3.1 Legacy ISA
      • 5.4.3.2 ISA Interface Mode
        • 5.4.3.2.1 NOWS# Input Sampling
  • 5.5 Timing Diagrams
• 6 Local Chip Select
  • 6.1 Overview
  • 6.2 Chip Select Base Address Registers
  • 6.3 Procedure for Using Chip Select Base Address Registers
    • 6.3.1 Chip Select Base Address Register Programming Example
  • 6.4 Timing Diagram
• 7 PCI/Local Interrupts and User I/O
  • 7.1 Overview
  • 7.2 Interrupts
    • 7.2.1 PCI Interrupts (INTA#)
    • 7.2.2 Local Interrupt Input (LINTi[2:1])
    • 7.2.3 All Modes PCI SERR# (PCINMI)
  • 7.3 User I/O
  • 7.4 Timing Diagrams
• 8 Registers
  • 8.1 Register Address Mapping
  • 8.2 PCI Configuration Registers
  • 8.3 Local Configuration Registers
    • 8.3.1 Chip Select Registers
    • 8.3.2 Control Registers
• 9 Pin Descriptions
  • 9.1 Pin Summary
  • 9.2 Pull-Up/Pull-Down Resistor Recommendations
    • 9.2.1 Input Pins (Pin Type I)
    • 9.2.2 Output Pins (Pin Type O)
    • 9.2.3 I/O Pins (Pin Type I/O)
  • 9.3 Pinout
• 10 Electrical Specifications
  • 10.1 General Electrical Specifications
  • 10.2 Local Inputs
  • 10.3 Local Outputs
• 11 Physical Specifications
  • 11.1 Mechanical Layout
  • 11.2 Typical Adapter Block Diagram
  • 11.3 Pin Assignments
• A General Information
• Index
  • A
  • B
  • C
  • D
  • E
  • F
  • G
  • H
  • I
  • L
  • M
  • N
  • O
  • P
  • R
  • S
  • T
  • U
  • V
  • W
  • Z