Document Outline

• TITLE PAGE
• REVISION HISTORY
• CONTENTS
• LIST OF REGISTERS
• LIST OF TABLES
• LIST OF FIGURES
• FEATURES
  • General
  • SONET Section and Line / SDH Regenerator and Multiplexer Section
  • SONET Path / SDH High Order Path
  • System Side Interfaces
• APPLICATIONS
• REFERENCES
• DEFINITIONS
• APPLICATION EXAMPLES
• BLOCK DIAGRAM
• LOOPBACK MODES
• DESCRIPTION
• PIN DIAGRAMS
• PIN DESCRIPTION (520)
  • Serial Line side Interface Signals
  • Parallel Line Side Interface Signals
• FUNCTIONAL DESCRIPTION
  • Receive Section Overhead Processor (RSOP)
  • Receive Section Trace Buffer (SSTB)
  • Receive Line Overhead Processor (RLOP)
  • Receive Transport Overhead Controller (RTOC)
  • Ring Control Port
  • Receive Path Processing Slice (RPPS)
    • Receive Path Overhead Processor (RPOP)
      • Pointer Interpreter
      • Multiframe Framer
      • Error Monitoring
      • Path Overhead Extract
      • Receive Alarm Port
    • Receive Path Trace Buffer (SPTB)
    • Receive Telecombus Aligner (RTAL)
      • Elastic Store
      • Pointer Generator
      • Bypass
    • DS3 Mapper DROP Side (D3MD)
      • DS3 Demapper
      • Elastic Store
      • DS3 Desynchronizer
    • DROP Bus PRBS Generator and Monitor (DPGM)
  • Transmit Path Processing Slice (TPPS)
    • ADD Bus PRBS Generator and Monitor (APGM)
    • DS3 Mapper ADD Side (D3MA)
      • DS3 Serializer and Elastic Store
      • DS3 Synchronizer
    • Transmit Pointer Interpreter Processor (TPIP)
    • Transmit Telecombus Aligner (TTAL)
      • Elastic Store
      • Pointer Generator
      • Bypass
    • Transmit Path Trace Buffer (SPTB)
    • Transmit Path Overhead Processor (TPOP)
      • BIP-8 Calculate
      • Path REI Calculate
      • Transmit Alarm Port
      • Path Overhead Insert
      • SPE Multiplexer
  • Transmit Transport Overhead Controller (TTOC)
  • Transmit Line Overhead Processor (TLOP)
  • Transmit Section Overhead Processor (TSOP)
  • Transmit Section Trace Buffer (SSTB)
  • Transmit Line Interface
    • Clock Synthesis
    • Parallel to Serial Converter
  • WAN Synchronization Controller (WANS)
  • ADD/DROP Bus Time-Slot Interchange (TSI)
  • System Side Interfaces
    • Telecombus Interface
    • Serial DS3 Interface
  • JTAG Test Access Port Interface
  • Microprocessor Interface
• NORMAL MODE REGISTER DESCRIPTION
• TEST FEATURES DESCRIPTION
  • Master Test and Test Configuration Registers
  • JTAG Test Port
    • Boundary Scan Cells
• OPERATION
  • Software Initialization Sequence
  • Transport and Path Overhead Bytes
  • Line Configuration Options
    • STS12/12c (STM-4/AU3/AU4/AU4-Xc) Mode
  • Path Processing Slice Configuration Options
    • Basic Configuration
    • Additional Configuration for Transmit Concatenated Stream Support
    • Concatenated and Non-concatenated Streams detection
    • PRBS Generator/Monitor Configuration for Concatenated streams
  • Time Slot Interchange (Grooming) Configuration Options
  • System Interface Configuration Options
    • Single 77.76 MHz Byte Telecom Bus Mode
    • Four 19.44 MHz Byte Telecom Bus Mode
    • Serial DS3 Mode
    • DROP Bus Mode
  • Bit Error Rate Monitor
  • Clocking Options
  • WAN Synchronization Parameters
    • PLL Gain
    • Phase Comparator
    • Phase Sample Averaging
    • Implementation Example
  • Loopback Operation
  • JTAG Support
    • TAP Controller
    • States
    • Instructions
  • Board Design Recommendations
  • Power Supplies
  • Interfacing to ECL or PECL Devices
  • Clock Recovery
• FUNCTIONAL TIMING
  • Parallel Line Interface
  • Receive Transport Overhead Extraction
    • Receive Transport Overhead (RTOH) Functional Timing
    • Receive Section and Line DCC Functional Timing
    • Receive Order Wire and User Channel Functional Output Timing
    • Receive Overhead (ROH) Functional Output Timings
  • Transmit Transport Overhead Insertion
    • Transmit Transport Overhead (TTOH) Functional Timing
    • Transmit Section and Line DCC Functional Timing
    • Transmit Order Wire and User Channel Functional Timing
    • Transmit Overhead (TOH) Functional Timing
  • Path Overhead Extraction and Insertion
  • Mate SPECTRA-622 Interfaces
  • Telecom Bus System Side
    • DROP Bus
    • ADD Bus
  • DS3 Mode System Side
  • System Side Path and DS3 AIS Control Port
• ABSOLUTE MAXIMUM RATINGS
• D.C. CHARACTERISTICS
• MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
• A.C. TIMING CHARACTERISTICS
  • System Reset Timing
  • Parallel Line Interface Timing
  • Serial Line Interface Timing
  • Receive Timing
  • DROP Bus Timing
  • Path AIS Input Timing
  • ADD Bus Timing
  • Transmit Timing
  • JTAG Timing
• ORDERING AND THERMAL INFORMATION
• MECHANICAL INFORMATION