PMC-1981279 (R3)
2001 PMC-Sierra, Inc.
PM5356
PMC-Sierra,Inc.
622 Mbit/s ATM Physical Layer Device
S/UNI-622-MAX
FEATURES
GENERAL
ATM OC-12c (622 Mbit/s) PHY
Provides on-chip clock and data
recovery and clock synthesis.
Exceeds Bellcore-GR-253 jitter
tolerance and transmit jitter
requirements.
Provides a generic 8-bit
microprocessor interface for device
control and register access.
Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
SONET RECEIVER
Recovers clock and data.
Frames to and descrambles recovered
stream.
Filters and captures Automatic
Protection Switch bytes (K1,K2) and
detects APS byte failure.
Detects signal degrade and signal
failure threshold crossing alarms.
Captures and debounces
synchronization status byte (S1).
Counts received section BIP-8 (B1),
line BIP-24 (B2), and path BIP-8 (B3)
errors, and line and path FEBEs.
Detects LOS, OOF, LOF, LAIS, LRDI,
LOP, PAIS, PRDI and PERDI.
Provides divide by 8 recovered clock.
Provides 8 KHz receive frame pulses.
SONET TRANSMITTER
Provides a transmit frame pulse input
to align the transport frame to a system
reference.
Provides transmit clock as timing
reference for transmit outputs.
Inserts register programmable APS
(K1, K2) and synchronization status
(S1) bytes.
Inserts PAIS, PRDI, LAIS and LRDI.
Scrambles transmit data stream.
ATM PROCESSOR
Implements the ATM Forum User
Network Interface Specification.
Inserts and extracts ATM cells into and
from the SONET SPE.
Performs cell payload scrambling and
descrambling.
Provides UTOPIA Level 2 and 8-bit
100 MHz UTOPIA Level 3 compliant
system interfaces.
Provides synchronous 4 cell transmit
and receive FIFO buffers.
PACKAGING
Implemented in low power 3.3 Volt
CMOS technology.
Packaged in a 304 pin ball grid array
(BGA) package.
Industrial temperature range (-40C to
+85C).
APPLICATIONS
Enterprise and Edge ATM switches.
ATM switches and hubs.
Multiprotocol switches.
BLOCK DIAGRAM
Ut
opi
a A
T
M
Lev
el
2
Ut
opi
a A
T
M
Lev
el
3
Syste
m
In
te
r
f
a
c
e
Tx
Line
I/F
TFCLK
TENB
TPRTY
TDAT[15:0]
TCA
TSOC
Rx
Line
I/F
JTAG Test
Access Port
TFP
I
TFP
O
TC
LK
TR
S
T
B
TC
K
TMS
TD
I
TD
O
SYSSEL
RFCLK
RENB
RCA
RSOC
RPRTY
RVAL
RDAT[15:0]
Rx APS, Sync
Status, BERM
Microprocessor
Interfaces
D
[
7:0]
RST
B
RDB
WRB
CSB
AL
E
A
[
8:0]
INT
B
Tx Line O/H
Processor
Rx Line O/H
Processor
Path Trace
Buffer
Tx Section
O/H
Processor
Section
Trace Buffer
Tx Path O/H
Processor
Rx Path O/H
Processor
Tx ATM Cell
Processor
Rx ATM Cell
Processor
APSP[
4
:
0
]
FPIN
PIN[7:0]
PICLK
OOF
ATP[1]
SD
RRCLK+/-
RXD+/-
REFCLK+/-
PECLV
RBYP
ATP[0]
TXD+/-
TDREF1,TDREF0
FPOUT
POUT[7:0]
PTCLK
L
I
F
SEL
RF
PO
RCL
K
RAL
A
RM
Rx Section
O/H
Processor
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
PM5356 S/UNI-622-MAX
622 Mbit/s ATM Physical Layer Device
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC-1981279 (R3)
2001 PMC-Sierra, Inc.
TYPICAL APPLICATIONS
UTOPIA LEVEL 2 APPLICATION
UTOPIA LEVEL 3 APPLICATION
PM5356
S/UNI-622-MAX
UTOPIA Level 2
Interface
TFCLK
TENB
TCA
TSOC
TPRTY
TDAT[15:0]
RFCLK
RENB
RCA
RSOC
RPRTY
RDAT[15:0]
Optical
Transceiver
ATM Layer Device
TxClk
TxEnb
TxClav
TxSOC
TxPrty
TxData[15:0]
RxClk
RxEnb
RxClav
RxSOC
RxPrty
RxData[15:0]
RXD+/-
SD
TXD+/-
SYSSEL
LIFSEL
0
1
PM5356
S/UNI-622-MAX
UTOPIA Level 3
Interface
TFCLK
TENB
TCA
TSOC
TPRTY
TDAT[7:0]
RFCLK
RENB
RVAL
RSOC
RPRTY
RDAT[7:0]
Optical
Transceiver
ATM Layer Device
TxClk
TxEnb
TxClav
TxSOC
TxPrty
TxData[7:0]
RxClk
RxEnb
RxVal
RxSOC
RxPrty
RxData[7:0]
RXD+/-
SD
TXD+/-
LIFSEL
1
SYSSEL
1
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