PMC-981280 (R2)
1999 PMC-Sierra, Inc. January, 1999
PM5357
PMC-Sierra,Inc.
622 Mbit/s ATM and Packet Over SONET Physical Layer Device
S/UNI-622-POS
FEATURES
GENERAL
ATM and Packet over SONET/SDH
(POS) OC-12c (622 Mbit/s) PHY
Provides on-chip clock and data
recovery and clock synthesis
Exceeds Bellcore-GR-253 jitter
requirements
Inserts and extracts ATM cells or POS
packets into/from SONET SPE
Filters and captures Automatic
Protection Switch bytes (K1,K2) and
detects APS byte failure
Detects signal degrade and signal
failure thresholds crossing alarms
Captures and debounces
synchronization status byte (S1)
Extracts and Inserts the 16 or 64-byte
section trace (J0) and path trace (J1)
messages
Extracts and inserts section/line data
communication channels (DCC)
Provides circuitry to meet holdover,
wander and long term stability
Provides a generic 8-bit
microprocessor interface for device
control and register access
Provides standard IEEE 1149.1 JTAG
test port for boundary scan
ATM
Implements the ATM Forum User
Network Interface Specification
Performs cell payload scrambling and
descrambling
Provides a UTOPIA Level 2 and an 8-
bit 100MHz UTOPIA Level 3 compliant
system interface
Provides synchronous 4 cell transmit
and receive FIFO buffers
PACKET OVER SONET/SDH
Supports direct packet mapping into
SONET/SDH such as PPP, HDLC and
Frame Relay
Implements the PPP over SONET/
SDH specification according to RFC
1619 and 1662 of the IETF
Performs flag sequence detection and
insertion
Performs CRC-CCITT and CRC-32
FCS generation and validation
Performs byte stuffing and destuffing
Checks for minimum and maximum
packet lengths
Checks for packet abort sequence
Performs X
43
+1 payload scrambling
Provides a SATURN POS-PHY Level
2 and an 8-bit 100MHz POS-PHY
Level 3 system interface
Provides synchronous 256 byte
transmit and receive FIFO buffers
PACKAGING
Implemented in low power 3.3 Volt
CMOS technology
Packaged in a 304 SBGA
Industrial temperature range (-40C to
+85C)
APPLICATIONS
WAN and Edge ATM switches
Multiprotocol switches
Layer 3 switches
Routers, Packet switches and Hubs
BLOCK DIAGRAM
Ut
opi
a A
T
M
Lev
el
2/
3
PO
S-
PH
Y ATM L
e
v
e
l
2
/
3
Syste
m
In
te
r
f
a
c
e
Tx
Line
I/F
Rx
Line
I/F
JTAG Test
Access Port
TFP
I
TFP
O
TC
LK
TR
S
T
B
TC
K
TMS
TD
I
TD
O
SYSSEL
Tx Line O/H
Processor
Rx Line O/H
Processor
Path Trace
Buffer
Tx Section
O/H
Processor
Section
Trace Buffer
Tx Path O/H
Processor
Rx Path O/H
Processor
Tx POS
Frame
Processor
Rx POS
Frame
Processor
ATP[0]
TXD+/-
TDREF1,TDREF0
FPOUT
POUT[7:0]
PTCLK
L
I
F
SEL
RF
PO
RCL
K
RAL
A
RM
Rx Section
O/H
Processor
FPIN
PIN[7:0]
PICLK
OOF
C1,C0
SD
RRCLK+/-
RXD+/-
REFCLK+/-
PECLV
RBYP
ATP[1]
Microprocessor
Interfaces
D
[
7:0]
RST
B
RDB
WRB
CSB
AL
E
A
[
8:0]
INT
B
Rx APS, Sync
Status, BERM
APSP[
4
:
0
]
Section/Line
DCC Extract
RSDCL
K
RSD
RL
D
RL
DCL
K
WAN
Synch.
Rx ATM Cell
Processor
Tx ATM Cell
Processor
Section/Line
DCC Insert
TLD
T
L
DCL
K
TS
D
T
S
DCL
K
PO
S_
AT
M
B
TFCLK
TENB
TSOC/TSOP
TCA/TPA
TPRTY
TMOD
TDAT[15:0]
TEOP
TERR
RENB
RFCLK
RCA/RPA
RPRTY
RDAT[15:0]
RVAL
RERR
REOP
RMOD
RSOC/RSOP
Head Office:
PMC-Sierra, Inc.
#105 - 8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
PM5357 S/UNI-622-POS
622 Mbit/s ATM and Packet Over SONET Physical Layer Device
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC-981280 (R2)
1999 PMC-Sierra, Inc.
January, 1999
TYPICAL APPLICATIONS
POS-PHY LEVEL 2 APPLICATION
PM5357
S/UNI-622-POS
POS-PHY Level 2
Interface
TFCLK
TENB
TPA
TSOP
TPRTY
TDAT[15:0]
RFCLK
RENB
RPA
RSOP
RPRTY
RDAT[15:0]
Link Layer Device
TFCLK
TENB
TPA
TSOP
TPRTY
TDAT[15:0]
RFCLK
RENB
RPA
RSOP
RPRTY
RDAT[15:0]
Optical
Transceiver
RXD+/-
SD
TXD+/-
TMOD
TMOD
TEOP
TEOP
TERR
TERR
RMOD
RMOD
REOP
REOP
RERR
RERR
LIFSEL
1
ATM_POS
SYSSEL
1
0
RVAL
RVAL
POS-PHY LEVEL 3 APPLICATION
PM5357
S/UNI-622-POS
POS-PHY Level 3
Interface
TFCLK
TENB
TPA
TSOP
TPRTY
TDAT[7:0]
RFCLK
RENB
RSOP
RPRTY
RDAT[7:0]
Link Layer Device
TFCLK
TENB
TPA
TSOP
TPRTY
TDAT[7:0]
RFCLK
RENB
RSOP
RPRTY
RDAT[7:0]
Optical
Transceiver
RXD+/-
SD
TXD+/-
TMOD
TMOD
TEOP
TEOP
TERR
TERR
REOP
REOP
RERR
RERR
RVAL
RVAL
LIFSEL
1
ATM_POS
SYSSEL
1
1
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