PMC-Sierra, Inc.
PM73121
AAL1gator II
PMC-980620
Issue 3
AAL1 SAR Processor
Data Sheet
QSPQSD@U6S`6I98PIAD9@IUD6GUPQH8TD@SS6DI86I9APSDUT8VTUPH@STDIU@SI6GVT@
AAL1gator II is a trademark of PMC-Sierra, Inc.
AT&T is a registered trademark of AT&T
ECLIPTEK is a registered trademark of ECLIPTEK Corporation
Level One is a registered trademark of Level One Communications, Inc.
SyncFIFO is a trademark of Integrated Device Technology, Inc.
MITEL is a registered trademark of MITEL Corporation
All other brand or product names are trademarks or registered trademarks
of their respective companies or organizations.
NOTE:
The AAL1gator II device contains SRTS logic that Bellcore holds the patent on.
Please refer to the NOTE on
page 172
for more information regarding Bellcore's SRTS patent.
PMC-Sierra, Inc.
PM73121 AAL1gator II
Long Form Dat
a
Sheet
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
QSPQSD@U6S`6I98PIAD9@IUD6GUPQH8TD@SS6DI86I9APSDUT8VTUPH@STDIU@SI6GVT@
WHAT'S NEW IN THIS DATA SHEET?
This revision history documents the changes that occur from one data sheet version to the next version.
From Version
To Version
Major Changes
Issue 2
Issue 3
Corrected the Function description in
section 7.8.12
"R_OAM_QUEUE", on page 163
.
Removed "Preliminary" from the headers.
Removed the "P" suffix from the part number in
Appendix 29,
"Ordering Information", on page 205
.
Changed the following timing parameters:
Interrupt Timing: PROC_INTR Tq(max) from 16.5 ns to 17
ns.
Microprocessor RAM Read Cycle: /MEM_CS Tq(max)
from 17.7 ns to 18 ns.
Microprocessor RAM Read Cycle: Tqmoe(max) from 24.7
ns to 25 ns.
Microprocessor RAM Write Cycle: /PROC_ACK Tq(max)
from 17.5 ns to 18 ns.
Microprocessor RAM Write Cycle: /MEM_CS Tq(max)
from 17.7 ns to 18 ns.
Microprocessor Write Command Register: /PROC_ACK
Tq(max) from 17.5 ns to 18 ns.
Transmit Side Interface: RL_SER Th(min) from 1.2 ns to 2
ns.
Transmit Side High-Speed Interface: RL_SER Th(min) from
1.2 ns to 2 ns.
Transmit UTOPIA ATM Timing: TATM_DATA Tq(max)
from 12.7 ns to 13 ns.
TUTOPIA SPHY Timing: RPHY_DATA Tq(max) from
12.7 ns to 13 ns.
TUTOPIA MPHY Timing: RPHY_DATA Tq(max) from
12.7 ns to 13 ns.
PMC-Sierra, Inc.
PM73121 AAL1gator II
Long Form Dat
a
Sheet
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
QSPQSD@U6S`6I98PIAD9@IUD6GUPQH8TD@SS6DI86I9APSDUT8VTUPH@STDIU@SI6GVT@
Issue 1
Issue 2
Removed Pin 237, P_OUT, from Pinout Table.
In T_QUEUE_TBL, added clarifications to QUEUE_CREDITS
and AVG_SUB_VALU fields for single DS0 no pointer mode.
Changed ItypE3 to ItypDS3 in DC Operating Conditions Table.
Changed the following timing parameters:
Interrupt Timing: PROC_INTR Tq(max) from 16 ns to 16.5
ns.
Microprocessor RAM Read Cycle: /MEM_CS Tq(max)
from 15 ns to 17.7 ns.
Microprocessor RAM Read Cycle: Tqmoe(max) from 22 ns
to 24.7 ns.
Tzsu, Tded, and Tzen are now specified as typical, instead
of minimum and maximum.
Microprocessor RAM Write Cycle: /PROC_ACK Tq(max)
from 15 ns to 17.5 ns.
Microprocessor RAM Write Cycle: /MEM_CS Tq(max)
from 15 ns to 17.7 ns.
Microprocessor Write Command Register: /PROC_ACK
Tq(max) from 15 to 17.5 ns.
RAM Write Cycle: /MEM_WE Twp(min) from Tch - 1 to
Tch - 1.3, and Twp(max) from Tch to Tch +0.3.
Receive Side Low Speed Interface: TL_SER, TL_SIG
Tq(max) from 12 ns to 14 ns.
Transmit Side Interface: RL_SER Th(min) from 1.0 to 1.2
ns.
Transmit Side High-Speed Interface: RL_SER Th(min) from
1.0 to 1.2 ns.
Transmit UTOPIA ATM Timing: TATM_DATA Tq(max)
from 12 ns to 12.7 ns.
TUTOPIA SPHY Timing: RPHY_DATA Tq(max) from 12
ns to 12.7 ns.
TUTOPIA MPHY Timing: RPHY_DATA Tq(max) from 12
ns to 12.7 ns.
Added DC Operating Conditions: I
TYPE1
(max)=420mA and
I
TYPDS3
(max)=482mA.
In Absolute Maximum Ratings section, removed undershoot/
overshoot specification, and replaced with absolute maximum
voltage range for TTL inputs.
Moved all timing requirements on external logic for RAM and
Microprocessor interface from section 6.5 to section 8.11.
From Version
To Version
Major Changes
PMC-Sierra, Inc.
PM73121 AAL1gator II
Long Form Dat
a
Sheet
PMC-980620
,VVXH
AAL1 SAR Processor
Data Sheet
QSPQSD@U6S`6I98PIAD9@IUD6GUPQH8TD@SS6DI86I9APSDUT8VTUPH@STDIU@SI6GVT@
04/17/98
Issue 1
Changed from WAC-121-A to PM73121.
Changed from User's Manual to Long Form Data Sheet.
Deleted references to the BT_Mode and default mode.
Added PMC part numbers to
Figure 5 on page 11
,
Figure 6 on
page 12
,
Figure 7 on page 13
, and
Figure 86 on page 168
.
Under the
"R_LINE_STATE Word Format" section on page 156
,
added "Not used in UDF-HS mode." for the R_UNDERRUN and
R_RESUME field descriptions.
Under
section 7.11 "Activating a New Queue on an Active Line",
on page 167
, changed from "CMD_REG_ATTN" to
"CSD_REG_ATTN bit".
01/21/98
04/17/98
Changed references from SRTS_PORT to SRTS_LINE
throughout the manual.
Added the sixth bullet on page 6.
Under
"Potential System Impacts" on page 7
, added "Hardware
Considerations".
Deleted the first paragraph on page 65.
Replaced section 3.7.1 "SRTS for the Receive Side" starting on
page 66 with
section 3.7.1 "Generation of TL_CLK" starting on
page 68
.
Added
section 3.7.1.1 "Recovered Mode" starting on page 69
,
section 3.7.1.2 "Synthesize a Nominal E1 or T1 Clock" starting on
page 69
, and
section 3.7.1.3 "Synthesize an E1 or T1 Clock based
on SRTS" starting on page 70
.
In
Table 9 on page 88
, changed the last sentence of the
"SYS_CLK" description to read "The maximum frequency is
40 MHz.
In
Table 10 on page 89
, added the note to the description of "/
SCAN_TRST" on page 89.
Under section 6.5 "RAM and Microprocessor Timing" starting on
page 104, changed the first sentence of the third paragraph from
"running at 38.88 MHz" to "running near maximum speed".
The first sentence of the fourth paragraph changed from
"(38.88 MHz)" to "(40.00 MHz)".
In Figure 69 on page 105, changed SYS_CLK from "38.88 MHz"
to "40.00 MHz".
In Table 21 on page 105, changed the maximum value of Number
12 from "8" to "7".
From Version
To Version
Major Changes
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