PM7326 S/UNI APEX
DATA SHEET
PMC-1981224
ISSUE 6
ATM/PACKET TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM7326
S
/UNI
-
APEX
TM
S/UNI APEX
ATM/PACKET TRAFFIC MANAGER AND SWITCH
DATA SHEET
ISSUE 6: APRIL 2000
PM7326 S/UNI APEX
DATA SHEET
PMC-1981224
ISSUE 6
ATM/PACKET TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
REVISION HISTORY
Issue No.
Issue Date
Details of Change
Issue 6
April, 2000
Final update for production release.
Changes from Issue 5 marked with
change bars
Issue 5
December, 1999
Removed Applications Examples and
Operations sections, replaced with
dedicated documents. IDDOP
(operating current) value inserted.
Issue 4
August, 1999
Datasheet re-written to incorporate
extensive updates and clarifications.
Issue 3
June, 1999
No material change from Issue 2,
formatted for web site.
Issue 2
February, 1999
Updates and clarifications throughout
Issue 1
November, 1998
Document created.
PM7326 S/UNI APEX
DATA SHEET
PMC-1981224
ISSUE 6
ATM/PACKET TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
CONTENTS
1
DEFINITIONS .......................................................................................... 1
2
FEATURES .............................................................................................. 3
3
APPLICATIONS ....................................................................................... 7
4
REFERENCES......................................................................................... 8
5
APPLICATION EXAMPLES ..................................................................... 9
6
BLOCK DIAGRAM ................................................................................. 10
7
DESCRIPTION ...................................................................................... 12
8
PIN DIAGRAM ....................................................................................... 16
9
PIN DESCRIPTION................................................................................ 17
9.1
LOOP ANY-PHY RECEIVE MASTER/TRANSMIT SLAVE
INTERFACE (28 SIGNALS) ........................................................ 17
9.2
LOOP ANY-PHY TRANSMIT MASTER/RECEIVE SLAVE
INTERFACE (34 SIGNALS) ........................................................ 22
9.3
WAN ANY-PHY RECEIVE MASTER/TRANSMIT SLAVE
INTERFACE (25 SIGNALS) ........................................................ 26
9.4
WAN ANY-PHY TRANSMIT MASTER/RECEIVE SLAVE
INTERFACE (25 SIGNALS) ........................................................ 31
9.5
CONTEXT MEMORY SYNCHRONOUS SSRAM INTERFACE (60
SIGNALS).................................................................................... 36
9.6
CELL BUFFER SDRAM INTERFACE (52 SIGNALS) ................. 38
9.7
MICROPROCESSOR INTERFACE (44 SIGNALS)..................... 40
9.8
GENERAL (9 SIGNALS) ............................................................. 44
9.9
JTAG & SCAN INTERFACE (7 SIGNALS) .................................. 45
9.10 POWER....................................................................................... 46
10
FUNCTIONAL DESCRIPTION............................................................... 48
PM7326 S/UNI APEX
DATA SHEET
PMC-1981224
ISSUE 6
ATM/PACKET TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
ii
10.1 ANY-PHY INTERFACES ............................................................. 48
10.1.1 RECEIVE INTERFACE..................................................... 48
10.1.2 TRANSMIT INTERFACE .................................................. 50
10.2 LOOP PORT SCHEDULER ........................................................ 53
10.3 WAN PORT SCHEDULER .......................................................... 54
10.4 WAN PORT ALIASING................................................................ 56
10.5 WAN AND LOOP ICI SELECTION.............................................. 57
10.6 MICROPROCESSOR INTERFACE ............................................ 57
10.7 MEMORY PORT ......................................................................... 61
10.8 SAR ASSIST ............................................................................... 62
10.8.1 TRANSMIT ....................................................................... 62
10.8.2 RECEIVE.......................................................................... 63
10.9 QUEUE ENGINE......................................................................... 64
10.9.1 SERVICE ARBITRATION ................................................. 65
10.9.2 CELL QUEUING ............................................................... 66
10.9.3 CLASS SCHEDULING ..................................................... 73
10.9.4 CONGESTION CONTROL ............................................... 75
10.9.5 STATISTICS ..................................................................... 82
10.9.6 MICROPROCESSOR QUEUE BUFFER RE-
ALLOCATION/TEAR DOWN ............................................ 84
10.10 CONTEXT MEMORY SSRAM INTERFACE ............................... 84
10.11 CELL BUFFER SDRAM INTERFACE ......................................... 89
10.12 JTAG TEST ACCESS PORT....................................................... 93
11
PERFORMANCE ................................................................................... 94
11.1 THROUGHPUT ........................................................................... 94
PM7326 S/UNI APEX
DATA SHEET
PMC-1981224
ISSUE 6
ATM/PACKET TRAFFIC MANAGER AND SWITCH
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
11.2 LATENCY .................................................................................... 96
11.3 CDV............................................................................................. 96
12
REGISTER............................................................................................. 97
12.1 GENERAL CONFIGURATION AND STATUS.............................. 98
12.2 LOOP CELL INTERFACE ......................................................... 107
12.3 WAN CELL INTERFACE............................................................113
12.4 MEMORY PORT ........................................................................119
12.5 SAR........................................................................................... 125
12.5.1 RECEIVE........................................................................ 125
12.5.2 TRANSMIT ..................................................................... 127
12.5.3 CELL BUFFER DIAGNOSTIC ACCESS......................... 128
12.6 QUEUE ENGINE....................................................................... 129
12.7 MEMORY INTERFACE ............................................................. 144
12.8 TEST INTERFACE .................................................................... 145
12.9 CBI INTERFACE ....................................................................... 149
13
CBI REGISTER PORT MAPPING ....................................................... 151
14
MEMORY PORT MAPPING................................................................. 157
14.1 CONTEXT SIZE AND LOCATION............................................. 157
14.2 QUEUE CONTEXT DEFINITION .............................................. 160
14.2.1 VC CONTEXT RECORDS.............................................. 161
14.2.2 PORT CONTEXT RECORDS......................................... 169
14.2.3 CLASS CONTEXT RECORDS....................................... 173
14.2.4 SHAPING CONTEXT RECORDS................................... 178
14.2.5 CELL CONTEXT RECORD ............................................ 180
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