PM7342
Preliminary
32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY
S/UNI-IMA-32
PMC-2001523 (p5)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
Copyright PMC-Sierra, Inc. 2002
FEATURES
IMA
Supports up to 32 T1, E1, G.SHDSL or
unchannelized links and up to 32 IMA
groups with 1 to 32 links/group.
Link and Group State Machines
implemented on-chip requiring no real
time software in the data path.
Fully compliant with the ATM Forum
Inverse Multiplexer for ATM (IMA)
1.1 specification and backward
compatible to IMA 1.0.
Supports both independent transmit
clock (ITC) and common transmit clock
(CTC) modes.
Supports all IMA Group Symmetry
modes: Symmetric/Asymmetric
configuration and operation.
Differential delay tolerance of 279 ms
(for T1 links) and 226 ms (for E1 links).
Performs IMA differential delay
calculation and synchronization.
Provides programmable limit on
allowable differential delay and
minimum number of links per group.
Performs ICP and stuff-cell insertion
and removal.
Supports IMA frame length (M) equal
to 32, 64, 128, or 256.
Provides IMA layer statistic counts and
alarms for support of IMA Performance
and Failure Alarm Monitoring and MIB
support.
Provides per link counters for statistics
and performance monitoring.
UNI
Each link is software configurable as
either a UNI or part of an IMA group.
Performs receive cell Header Error
Check (HEC) checking and transmit
cell HEC generation.
Optionally supports receive cell
payload unscrambling and transmit cell
payload scrambling.
Provides TC layer statistics counts and
alarms for MIB support.
ATM OVER FRACTIONAL T1/E1
Supports ATM over Fractional T1/E1
compliant with the ATM Forum
AF-PHY-0130.00 specification.
LINE INTERFACE
32 T1, E1, G.SHDSL or unchannelized
links via 2-pin line interfaces.
Supports a 19.44 MHz Scalable Band-
width Interconnect (SBI) bus interface for
seamless interconnect to the PM8315
TEMUX and PM8316 TEMUX-84.
SBI supports two Synchronous
Payload Envelopes (SPE). Each SPE
can carry up to 16 T1s or 16 E1s.
UTOPIA / ANY-PHY INTERFACE
Supports 8- and 16-bit UTOPIA L2 and
Any-PHY cell interfaces at clock rates
up to 52 MHz.
Any-PHY transmit slave appears as a
32 port multi-PHY. The PHY-ID of
each cell is identified using in-band
addressing.
Any-PHY receive slave appears as a
single device. The PHY-ID of each cell
is identified using in-band addressing.
UTOPIA L2 transmit and receive slave
appears as a 31-port multi-PHY.
UTOPIA L2 receive slave can also
appear as a single port with the logical
port provided as a prepend.
TC Layer
(RTTC32)
INSBI
EXSBI
De-
Framer
(SDDF32)
TC Layer
(TTTC32)
Rx IMA
Protocol
Processor
(RIPP)
IDCC
32-chan
x 7 cell
FIFO
(MCFD)
32-chan
x
3 cell
FIFO
Tx IMA Processor
(TIMA)
Any-PHY/
UTOPIA
Tx Slave
(TXAPS)
Any-PHY/
UTOPIA
Rx Slave
(RXAPS)
31
chan
4 cell
FIFO
MicroProcess I/F
JTAG
IDCC
DLL
32-chan
x 2 cell
FIFO
Null
Framer
(SDFR32)
Tx Slave
ATM I/F
Rx Slave
ATM I/F
SBI Drop Bus I/F
32 Clk/Data
RCAS
TCAS
Internal Bus
Rx IMA
Data Processor
(RDAT)
Cell Writer Cell Reader
Memory Interface
(MEMI)
CB
CS
B
CB
RA
S
B
CB
CA
S
B
CB
W
E
B
C
BA[1
1
:0
]
C
BBS[1
:
0
]
CB
D
Q
M
CB
D
Q
[15
:
0]
RCLK
RADR[4:0]
RENB
RPA
RCSB
RSOP
RSX
RDAT[15:0]
RPRTY
TCLK
TADR[10:0]
TENB
TPA
TCSB
TSOP
TSX
TDAT[15:0]
TPRTY
D[
1
5
:
0
]
A[1
0
:1
]
AL
E
WR
B
RD
B
CS
B
IN
T
B
TC
K
TMS
TD
I
TR
STB
TD
O
SY
SC
L
K
RS
T
B
OE
DC1FP
DPL
DDP
DDATA[7:0]
DV5
AC1FP
ADATA[7:0]
ADP
APL
AV5
AJUST_REQ
AACTIVE
ADETECT
SBI Add Bus I/F
TSCLK[31:0]
TSDATA[31:0]
32 Clk/Data
RSCLK[31:0]
RSDATA[31:0]
CTSCLK
RE
F
C
L
K
BLOCK DIAGRAM
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: +1.604.415.6000
Fax: +1.604.415.6200
32 Link Inverse Multiplexer for ATM (IMA) / UNI PHY
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
PMC-2001523 (p5)
Copyright PMC-Sierra, Inc. 2002.
All rights reserved. February 2002.
S/UNI is a registered trademark of
PMC-Sierra, Inc. SBI, AAL1gator,
FREEDM, SPECTRA, COMET-QUAD,
VORTEX, TEMUX, Any-PHY and PMC-
Sierra are trademarks of PMC-Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
Preliminary
PM7342 S/UNI-IMA-32
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
LOOPBACK AND DIAGNOSTICS
Supports UTOPIA Side Loopback.
Supports Line Side Loopback.
Supports per group ICP cell trace
capability.
SOFTWARE
The S/UNI-IMA device driver, written in
ANSI C, provides a well-defined
Application Programming Interface
(API) and low level utility functions for
diagnostics and debugging purposes.
Software wrappers are used for RTOS-
related functions making the S/UNI-
IMA device driver portable to any Real
Time Operating System (RTOS)
environment.
GENERAL
16-bit interface for 1M x 16 SDRAM.
Provides a 16-bit microprocessor
interface for configuration, statistics
gathering and Link and Unit
Management.
Provides a standard 5-pin P1149
JTAG port.
Low-power 1.8 V CMOS with TTL-
compatible I/O.
416-pin plastic ball grid array (PBGA)
package.
APPLICATIONS
Multiservice Switches.
Optical Access Switches.
DSLAMs.
Wireless Basestation Controllers.
Access Concentrators.
WIRELESS BASESTATION CONTROLLER
PM7329
S/UNI-APEX-
1K800
PM7328
S/UNI-ATLAS-
1K800
SBI Bus
SBI Bus
RM7000
uP
PM7381
FREEDM-
32A672
PM4328
TECT3
L2
Address
Resolution
and SAR
PM7342
S/UNI-IMA-32
PM4332
TE-32
PM4319
OCTLIU
32-port T1/E1 ATM Card
DS-3 Packet Card
HMVIP
UTOPIA Bus
AAL2
Processing
UTOPIA L2/
Any-PHY
DS3 LIU
TYPICAL APPLICATIONS
DSLAM WITH IMA OVER DSL
xN
LVDS
PM7346
S/UNI-QJET
PM7326
S/UNI-APEX
PM7324
S/UNI-ATLAS
PM7350
S/UNI-DUPLEX
32
Clock/Data
PM7342
S/UNI-IMA-32
x32
(x31 with UL2)
xDSL MODEM
PM7351
S/UNI-VORTEX
UTOPIA L2 / Any-PHY
UTOPIA L2/
Any-PHY
UTOPIA L2
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