RELEASED
PM7364 FREEDM-32
DATA SHEET
PMC-1960758
ISSUE 6
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE
PM7364
FREEDMTM-32
FRAME ENGINE AND DATALINK
MANAGER
DATA SHEET
ISSUE 6: AUGUST 2001
RELEASED
PM7364 FREEDM-32
DATA SHEET
PMC-1960758
ISSUE 6
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE
i
PUBLIC REVISION HISTORY
Issue No. Issue Date Details of Change
6 August
2001
Patent information added to legal footer.
5
May 1998
Document re-issue.
4
April 1998
Document re-issue.
3 October
1997
Document re-formatted.
2 April
23,
1997
Pin Diagram page replaced.
Two entries added to Pin table diagram.
Added AC, DC Timing section and 256 BGA
mechanical package information.
1 July
24,
1996
Creation of Data Sheet
RELEASED
PM7364 FREEDM-32
DATA SHEET
PMC-1960758
ISSUE 6
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE
ii
CONTENTS
1 FEATURES...............................................................................................1
2 APPLICATIONS........................................................................................3
3 REFERENCES .........................................................................................4
4 APPLICATION
EXAMPLES ......................................................................5
5 BLOCK
DIAGRAM....................................................................................6
6 DESCRIPTION .........................................................................................7
7 PIN
DIAGRAM ..........................................................................................9
8 PIN
DESCRIPTION ................................................................................10
9 FUNCTIONAL
DESCRIPTION ...............................................................31
9.1
HIGH-LEVEL DATA LINK CONTROL PROTOCOL......................31
9.2 RECEIVE
CHANNEL
ASSIGNER ................................................32
9.2.1 LINE
INTERFACE..........................................................33
9.2.2 PRIORITY
ENCODER ...................................................33
9.2.3 CHANNEL
ASSIGNER ..................................................33
9.2.4 LOOPBACK
CONTROLLER .........................................34
9.3
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...34
9.3.1 HDLC
PROCESSOR .....................................................34
9.3.2
PARTIAL PACKET BUFFER PROCESSOR ..................35
9.4
RECEIVE DMA CONTROLLER ...................................................37
9.4.1 DATA
STRUCTURES ....................................................37
9.4.2 DMA
TRANSACTION
CONTROLLER...........................47
9.4.3
WRITE DATA PIPELINE/MUX .......................................47
RELEASED
PM7364 FREEDM-32
DATA SHEET
PMC-1960758
ISSUE 6
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE
iii
9.4.4
DESCRIPTOR INFORMATION CACHE ........................47
9.4.5
FREE QUEUE CACHE ..................................................47
9.5 PCI
CONTROLLER......................................................................48
9.5.1 MASTER
MACHINE ......................................................49
9.5.2
MASTER LOCAL BUS INTERFACE..............................51
9.5.3 TARGET
MACHINE .......................................................52
9.5.4
CBI BUS INTERFACE ...................................................54
9.5.5
ERROR / BUS CONTROL .............................................54
9.6
TRANSMIT DMA CONTROLLER.................................................54
9.6.1 DATA
STRUCTURES ....................................................55
9.6.2 TASK
PRIORITIES ........................................................67
9.6.3 DMA
TRANSACTION
CONTROLLER...........................67
9.6.4
READ DATA PIPELINE..................................................67
9.6.5
DESCRIPTOR INFORMATION CACHE ........................67
9.6.6
FREE QUEUE CACHE ..................................................67
9.7
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER68
9.7.1
TRANSMIT HDLC PROCESSOR..................................68
9.7.2
TRANSMIT PARTIAL PACKET BUFFER PROCESSOR69
9.8 TRANSMIT
CHANNEL
ASSIGNER .............................................71
9.8.1 LINE
INTERFACE..........................................................72
9.8.2 PRIORITY
ENCODER ...................................................72
9.8.3 CHANNEL
ASSIGNER ..................................................73
9.9 PERFORMANCE
MONITOR .......................................................73
9.10 JTAG TEST ACCESS PORT INTERFACE...................................73
RELEASED
PM7364 FREEDM-32
DATA SHEET
PMC-1960758
ISSUE 6
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER'S INTERNAL USE
iv
9.11 PCI HOST INTERFACE ...............................................................73
10
NORMAL MODE REGISTER DESCRIPTION ........................................79
10.1 PCI HOST ACCESSIBLE REGISTERS .......................................79
11
PCI CONFIGURATION REGISTER DESCRIPTION ............................251
11.1 PCI CONFIGURATION REGISTERS.........................................251
12
TEST FEATURES DESCRIPTION .......................................................262
12.1 TEST MODE REGISTERS ........................................................262
12.2 JTAG
TEST
PORT .....................................................................263
12.2.1 IDENTIFICATION
REGISTER .....................................264
12.2.2 BOUNDARY SCAN REGISTER ..................................264
13 OPERATIONS ......................................................................................278
13.1 EQUAD
CONNECTIONS...........................................................278
13.2 TOCTL
CONNECTIONS ............................................................278
13.3 JTAG
SUPPORT........................................................................279
14 FUNCTIONAL
TIMING .........................................................................285
14.1 RECEIVE LINK INPUT TIMING .................................................285
14.2 TRANSMIT LINK OUTPUT TIMING...........................................286
14.3 PCI
INTERFACE ........................................................................288
14.4 BERT
INTERFACE ....................................................................297
15
ABSOLUTE MAXIMUM RATINGS........................................................299
16 D.C.
CHARACTERISTICS....................................................................300
17 FREEDM-32
TIMING
CHARACTERISTICS .........................................302
18 ORDERING
AND
THERMAL INFORMATION ......................................308
19 MECHANICAL
INFORMATION.............................................................309
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