RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM7366
FREEDMTM-8
EIGHT CHANNEL FRAME ENGINE AND
DATALINK MANAGER
PROPRIETARY AND CONFIDENTIAL
ISSUE 4: AUGUST 2001
RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS' INTERNAL USE
REVISION HISTORY
Issue No.
Issue Date
Details of Change
Issue 4
August 2001
Added patent information to legal footer, last page. Change
bars pertain to issue 3.
Issue 3
August 1999
Updated to include PBGA package option
Addition of new pinout, pin description, and mechanical
diagram.
Incorporated Documentation Errata from PMC-980452,
"PM7366 FREEDM-8 Revision D Device Errata Sheet" Issue 4.
Issue 2
May 1998
Updated for Freedm-8 Release to Production
Issue 1
Sept. 1997
Document created for Prototype release
RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
CONTENTS
1 FEATURES ....................................................................................................................... 1
2 APPLICATIONS ................................................................................................................ 3
3 REFERENCES.................................................................................................................. 4
4 APPLICATION
EXAMPLES .............................................................................................. 5
5 BLOCK
DIAGRAM ............................................................................................................ 6
6 DESCRIPTION.................................................................................................................. 7
7 PIN
DIAGRAM................................................................................................................... 9
8 PIN
DESCRIPTION..........................................................................................................11
9 FUNCTIONAL
DESCRIPTION........................................................................................ 33
9.1
HIGH-LEVEL DATA LINK CONTROL PROTOCOL ........................................... 33
9.2 RECEIVE
CHANNEL ASSIGNER ...................................................................... 34
9.2.1 LINE
INTERFACE............................................................................. 34
9.2.2 PRIORITY
ENCODER...................................................................... 34
9.2.3 CHANNEL
ASSIGNER ..................................................................... 35
9.2.4 LOOPBACK
CONTROLLER ............................................................ 35
9.3
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER ........................ 35
9.3.1 HDLC
PROCESSOR ........................................................................ 36
9.3.2 PARTIAL
PACKET BUFFER PROCESSOR..................................... 36
9.4
RECEIVE DMA CONTROLLER ......................................................................... 38
9.4.1 DATA
STRUCTURES ....................................................................... 38
9.4.2 DMA
TRANSACTION
CONTROLLER ............................................. 48
9.4.3
WRITE DATA PIPELINE/MUX .......................................................... 48
9.4.4
DESCRIPTOR INFORMATION CACHE........................................... 48
RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS' INTERNAL USE
ii
9.4.5
FREE QUEUE CACHE..................................................................... 48
9.5 PCI
CONTROLLER............................................................................................ 49
9.5.1 MASTER
MACHINE ......................................................................... 49
9.5.2 MASTER
LOCAL
BUS INTERFACE................................................. 51
9.5.3 TARGET
MACHINE.......................................................................... 52
9.5.4
CBI BUS INTERFACE ...................................................................... 54
9.5.5
ERROR / BUS CONTROL................................................................ 54
9.6
TRANSMIT DMA CONTROLLER ...................................................................... 54
9.6.1 DATA
STRUCTURES ....................................................................... 55
9.6.2 TASK
PRIORITIES ........................................................................... 66
9.6.3 DMA
TRANSACTION
CONTROLLER ............................................. 66
9.6.4
READ DATA PIPELINE..................................................................... 66
9.6.5
DESCRIPTOR INFORMATION CACHE........................................... 66
9.6.6
FREE QUEUE CACHE..................................................................... 66
9.7
TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER .................... 67
9.7.1
TRANSMIT HDLC PROCESSOR..................................................... 67
9.7.2
TRANSMIT PARTIAL PACKET BUFFER PROCESSOR ................. 67
9.8 TRANSMIT
CHANNEL ASSIGNER ................................................................... 69
9.8.1 LINE
INTERFACE............................................................................. 70
9.8.2 PRIORITY
ENCODER...................................................................... 70
9.8.3 CHANNEL
ASSIGNER ..................................................................... 71
9.9 PERFORMANCE
MONITOR ............................................................................. 71
9.10 JTAG
TEST
ACCESS
PORT INTERFACE ........................................................ 71
9.11
PCI HOST INTERFACE ..................................................................................... 71
RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
10
NORMAL MODE REGISTER DESCRIPTION ................................................................ 76
10.1 PCI
HOST
ACCESSIBLE REGISTERS ............................................................. 76
11
PCI CONFIGURATION REGISTER DESCRIPTION .................................................... 216
11.1
PCI CONFIGURATION REGISTERS .............................................................. 216
12 TEST
FEATURES
DESCRIPTION ............................................................................... 226
12.1 TEST
MODE
REGISTERS .............................................................................. 226
12.2 JTAG
TEST
PORT ........................................................................................... 227
12.2.1 IDENTIFICATION
REGISTER........................................................ 228
12.2.2 BOUNDARY
SCAN REGISTER ..................................................... 228
13 OPERATIONS............................................................................................................... 241
13.1 EQUAD
CONNECTIONS................................................................................. 241
13.2 TOCTL
CONNECTIONS.................................................................................. 241
13.3 JTAG
SUPPORT.............................................................................................. 242
14 FUNCTIONAL
TIMING.................................................................................................. 248
14.1
RECEIVE LINK INPUT TIMING ....................................................................... 248
14.2
TRANSMIT LINK OUTPUT TIMING ................................................................ 249
14.3 PCI
INTERFACE .............................................................................................. 250
14.4 BERT
INTERFACE .......................................................................................... 258
15
ABSOLUTE MAXIMUM RATINGS................................................................................ 260
16 D.C.
CHARACTERISTICS ............................................................................................ 261
17 FREEDM-8
TIMING
CHARACTERISTICS ................................................................... 263
18 ORDERING
AND
THERMAL
INFORMATION .............................................................. 269
19 MECHANICAL
INFORMATION..................................................................................... 270
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