RM5231ATM Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use
2
Document ID: PMC-2002174, Issue 2
Legal Information
Copyright
2001 PMC-Sierra, Inc.
The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers' internal use. In
any event, you cannot reproduce any part of this document, in any form, without the express written
consent of PMC-Sierra, Inc.
PMC-2002174 (P2)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by PMC-
Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the
fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts
or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document.
PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents
or use of the information, including, but not limited to, express and implied warranties of accuracy,
completeness, merchantability, fitness for a particular use, or non-infringement.
In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential
damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or
reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such
damage.
Trademarks
RM5231A is a trademark of PMC-Sierra, Inc.
Contacting PMC-Sierra
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC
Canada V5A 4V7
Tel: (604) 415-6000
Fax: (604) 415-6200
Document Information: document@pmc-sierra.com
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Web Site: http://www.pmc-sierra.com
RM5231ATM Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use
3
Document ID: PMC-2002174, Issue 2
Revision History
Issue
No.
Issue Date
Details of Change
2 September 2001 Added 1.8 V to the feature: 1.65 V or 1.8 V core with 3.3 V or 2.5 V I/O (p9).
Changed recommended operating conditions VccInt to 1.57 V to 1.85 V and
VccP to 1.57 V to 1.85 V. Added VssP commercial and industrial values.
Modified Note 4.
Added reference to VccInt to Power Consumption table. Changed standby
modes to 350. Modified Note 1.
Modified SysClock Frequency and SysClock Period values in the Clock
Parameters table.
1
March 2001
Applied PMC-Sierra template to existing MPD (QED) FrameMaker document.
Revised the Absolute Maximum Ratings table to include industrial operating
temperatures. Revised the Recommended Operating conditions table (VccIO).
Revised the DC Electrical Characteristics section. Included 350 MHz Power
CPU Speed Power Consumption and Clock Parameter values. Revised the
System Interface Parameters table.
RM5231ATM Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use
4
Document ID: PMC-2002174, Issue 2
Document Conventions
The following conventions are used in this datasheet:
All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface
typeface.
All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold
typeface.
All instruction names, such as
MFHI
, are in san serif typeface.
RM5231ATM Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use
5
Document ID: PMC-2002174, Issue 2
Table of Contents
Legal Information ...........................................................................................................................2
Revision History .............................................................................................................................3
Document Conventions .................................................................................................................4
Table of Contents ..........................................................................................................................5
List of Figures ................................................................................................................................7
List of Tables .................................................................................................................................8
1
Features ..................................................................................................................................9
2
Block Diagram .......................................................................................................................10
3
Hardware Overview ...............................................................................................................11
3.1
Superscalar Dispatch ...................................................................................................11
3.2
CPU Registers .............................................................................................................11
3.3
Pipeline ........................................................................................................................11
3.4
Integer Unit ..................................................................................................................12
3.5
Register File .................................................................................................................12
3.6
ALU ..............................................................................................................................12
3.7
Integer Multiply/Divide ..................................................................................................12
3.8
Floating-Point Co-Processor ........................................................................................13
3.9
Floating-Point Unit .......................................................................................................13
3.10 Floating-Point General Register File ............................................................................15
3.11 System Control Coprocessor (CP0) .............................................................................16
3.12 System Control Co-Processor Registers .....................................................................16
3.13 Virtual to Physical Address Mapping ............................................................................17
3.14 Joint TLB ......................................................................................................................18
3.15 Instruction TLB .............................................................................................................19
3.16 Data TLB ......................................................................................................................19
3.17 Cache Memory .............................................................................................................19
3.18 Instruction Cache .........................................................................................................19
3.19 Data Cache ..................................................................................................................20
3.20 Write Buffer ..................................................................................................................21
3.21 System Interface ..........................................................................................................22
3.22 System Address/Data Bus ...........................................................................................22
3.23 System Command Bus ................................................................................................22
3.24 Handshake Signals ......................................................................................................23
3.25 Non-overlapping System Interface ...............................................................................23
3.26 Enhanced Write Modes ................................................................................................24
3.27 External Requests ........................................................................................................25
3.28 Interrupt Handling ........................................................................................................25
3.29 Standby Mode ..............................................................................................................25
3.30 JTAG Interface .............................................................................................................25
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