MC3410 Technical Specifications

iii

Warranty

PMD warrants performance of its products to the specifications applicable at the time of sale in
accordance with PMD's standard warranty. Testing and other quality control techniques are utilized
to the extent PMD deems necessary to support this warranty. Specific testing of all parameters of
each device is not necessarily performed, except those mandated by government requirements.
Performance Motion Devices, Inc. (PMD) reserves the right to make changes to its products or to
discontinue any product or service without notice, and advises customers to obtain the latest version
of relevant information to verify, before placing orders, that information being relied on is current
and complete. All products are sold subject to the terms and conditions of sale supplied at the time
of order acknowledgement, including those pertaining to warranty, patent infringement, and
limitation of liability.

Safety Notice

Certain applications using semiconductor products may involve potential risks of death, personal
injury, or severe property or environmental damage. Products are not designed, authorized, or
warranted to be suitable for use in life support devices or systems or other critical applications.
Inclusion of PMD products in such applications is understood to be fully at the customer's risk.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent procedural hazards.

Disclaimer

PMD assumes no liability for applications assistance or customer product design. PMD does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of PMD covering or relating to any
combination, machine, or process in which such products or services might be or are used. PMD's
publication of information regarding any third party's products or services does not constitute PMD's
approval, warranty or endorsement thereof.

MC3410 Technical Specifications

vii

Table of Contents

Warranty...................................................................................................................................................... iii

Safety Notice ................................................................................................................................................ iii

Disclaimer..................................................................................................................................................... iii

Related Documents....................................................................................................................................... v

Table of Contents........................................................................................................................................ vii

1 The Pilot Family ........................................................................................................................................ 9

2 Functional Characteristics...................................................................................................................... 11

2.1

Configurations, parameters, and performance .............................................................................. 11

2.2

Physical characteristics and mounting dimensions....................................................................... 13

2.3

Environmental and electrical ratings ............................................................................................ 14

2.4

System configuration.................................................................................................................... 14

2.5

Peripheral device address mapping............................................................................................... 15

3 Electrical Characteristics........................................................................................................................ 16

3.1

DC characteristics......................................................................................................................... 16

3.2

AC characteristics......................................................................................................................... 16

4 I/O Timing Diagrams .............................................................................................................................. 18

4.1

Clock ............................................................................................................................................ 18

4.2

Quadrature encoder input ............................................................................................................. 18

4.3

Reset ............................................................................................................................................. 18

4.4

Host interface, 8/16 mode (requires external logic device) .......................................................... 19

4.4.1

Instruction write, 8/16 mode................................................................................................. 19

4.4.2

Data write, 8/16 mode........................................................................................................... 19

4.4.3

Data read, 8/16 mode............................................................................................................ 20

4.4.4

Status read, 8/16 mode.......................................................................................................... 20

4.5

Host interface, 16/16 mode (requires external logic device) ........................................................ 21

4.5.1

Instruction write, 16/16 mode............................................................................................... 21

4.5.2

Data write, 16/16 mode......................................................................................................... 21

4.5.3

Data read, 16/16 mode.......................................................................................................... 22

4.5.4

Status read, 16/16 mode........................................................................................................ 22

4.6

External memory timing............................................................................................................... 23

4.6.1

External memory read........................................................................................................... 23

4.6.2

External memory write ......................................................................................................... 23

4.7

Peripheral device timing............................................................................................................... 24

4.7.1

Peripheral device read........................................................................................................... 24

4.7.2

Peripheral device write ......................................................................................................... 24

5 Pinouts and Pin Descriptions.................................................................................................................. 25

5.1

Pinouts for MC3410 ..................................................................................................................... 25

5.2

CP chip pin description table........................................................................................................ 26

MC3410 Technical Specifications

viii

6 Parallel Communication ......................................................................................................................... 30

6.1

Host interface pin description table .............................................................................................. 30

6.2

16-bit Host Interface (IOPIL16) ................................................................................................... 32

6.3

8-bit Host Interface (IOPIL8) ....................................................................................................... 46

7 Application Notes..................................................................................................................................... 62

7.1

Design Tips................................................................................................................................... 62

7.2

RS-232 Serial Interface ................................................................................................................ 64

7.3

RS 422/485 Serial Interface.......................................................................................................... 66

7.4

PWM Motor Interface .................................................................................................................. 68

7.5

12-bit Parallel DAC Interface....................................................................................................... 70

7.6

16-bit Serial DAC Interface.......................................................................................................... 72

7.7

RAM Interface.............................................................................................................................. 74

7.8

User-defined I/O........................................................................................................................... 76

7.9

12-bit A/D Interface...................................................................................................................... 78

7.10

16-bit A/D Input ........................................................................................................................... 80

7.11

External Gating Logic Index ........................................................................................................ 82

MC3410 Technical Specifications

1 The Pilot Family

MC3110 MC3310 MC3410 MC3510

Number of axes

1 1 1 1

Motor type supported

Brushed servo

Brushless servo

Stepping

Output format

Brushed servo

(single phase)

Commutated (6-

step or sinusoidal)

Microstepping

Pulse and Direction

Incremental encoder

input

Parallel word device

input

Parallel communication

Serial communication

S-curve profiling

On-the-fly changes

Directional limit

switches

Programmable bit output

Software-invertable
signals

PID servo control

- -

Feedforward (accel &
vel)

- -

Derivative sampling time

- -

Data trace/diagnostics

PWM output

Pulse & direction output

Index & Home signals

Motion error detection

(with encoder)

Axis settled indicator

(with encoder)

DAC-compatible output

Position capture

Analog input

User-defined I/O

External RAM support

Multi-chip
synchronization

(MC3113)

(MC3313)

(MC3413)

Chip part numbers

MC3110 MC3310 MC3410 MC3510

Developer's Kit p/n's:

DK3110 DK3310 DK3410 DK3510

Parallel communication is available via an additional logic device

Introduction

This manual describes the operational characteristics of the MC3410 Motion Processor from PMD.
This device is a member of the MC3000 family of single-chip, single-axis motion processors.

MC3410 Technical Specifications

Each device of the MC3000 family is a complete chip-based motion processor providing trajectory
generation and related motion control functions for one axis including servo loop closure or on-
board commutation where appropriate. This family of products provides a software-compatible
selection of dedicated motion processors that can handle a large variety of system configurations.

The chip architecture not only makes it ideal for the task of motion control, it allows for similarities
in software commands, so software written for one motor type can be re-used if the motor type is
changed.

Pilot Family Summary

MC3110 � This single-chip, single-axis motion processor outputs motor commands in either
Sign/Magnitude PWM or DAC-compatible format for use with brushed servo motors, or with
brushless servo motors having external commutation.

MC3310 � This single-chip, single-axis motion processor outputs sinusoidally commutated motor
signals appropriate for driving brushless motors. Depending on the motor type, the output is a two-
phase or three-phase signal in either PWM or DAC-compatible format.

MC3410 � This single-chip, single-axis motion processor outputs microstepping signals for stepping
motors. Two phased signals per axis are generated in either PWM or DAC-compatible format.

MC3510 � This single-chip, single-axis motion processor outputs pulse and direction signals for
stepping motor systems.

MC3410 Technical Specifications

2 Functional Characteristics

2.1

Configurations, parameters, and performance

Configuration

Single axis, single chip.

Operating modes

Open loop (motor command is driven from output of trajectory generator and

microstep generator, encoder input used for stall detection)

Communication modes

8/16 parallel (8 bit external parallel bus with 16 bit internal command word size)
16/16 parallel (16 bit external parallel bus with 16 bit internal command word
size)
Point to point asynchronous serial
Multi-drop asynchronous serial

Serial port baud rate range

1,200 baud to 416,667 baud

Position range

-2,147,483,648 to +2,147,483,647 counts

Velocity range

-32,768 to +32,767 counts/sample with a resolution of 1/65,536 counts/sample

Acceleration/ deceleration ranges

-32,768 to +32,767 counts/sample

with a resolution of 1/65,536 counts/sample

Jerk range

0 to � counts/sample

, with a resolution of 1/4,294,967,296 counts/sample

Profile modes

S-curve point-to-point (Velocity, acceleration, jerk, and position parameters)
Trapezoidal point-to-point (Velocity, acceleration, deceleration, and position

parameters)
Velocity-contouring (Velocity, acceleration, and deceleration parameters)

Filter modes

Scalable PID + Velocity feedforward + Acceleration feedforward + Bias. Also
includes integration limit, settable derivative sampling time, and output motor

command limiting

Filter parameter resolution

16 bits

Position error tracking

Motion error window (allows axis to be stopped upon exceeding programmable
window)
Tracking window (allows flag to be set if axis exceeds a programmable position

window)
Axis settled (allows flag to be set if axis exceeds a programmable position
window for a programmable amount of time after trajectory motion is compete)

Motor output modes

PWM (80 kHz, 8-bit*)
DAC (16 bits)

Commutation rate

20 kHz

Microstepping waveform

Sinusoidal

Number of microsteps per full step Programmable 1 to 256
Maximum encoder rate

Incremental (up to 5 million counts/sec)
Parallel-word (up to 160 million counts/sec)

Parallel encoder word size

16 bits

Parallel encoder read rate

20 kHz (reads all axes every 50

�sec)

Cycle loop timing range

153.6

�sec to 32.767 milliseconds

Minimum cycle loop time

153.6

�sec

Limit switches

2 per axis: one for each direction of travel

Position-capture triggers

2 per axis: index and home signals

MC3410 Technical Specifications

2.3

Environmental and electrical ratings

Storage Temperature (T

)

-55

�C to 150 �C

Operating Temperature (T

)

�C to 70 �C*

Power Dissipation (P

)

400 mW

Nominal Clock Frequency (F

clk

)

20.0 MHz

Supply Voltage limits (V

)

-0.3V to +7.0V

Supply Voltage operating range (V

)

4.75V to 5.25V

* An industrial version with an operating range of -40�C to 85�C is also available. Please contact
PMD for more information.

2.4 System

configuration

The following figure shows the principal control and data paths in an MC3410 system.

Host

s
t
Da

t
a

s
t
S

l
c
t

Parallel port

Serial Port

System clock

(40 MHz)

HostIntrpt

t
W

r
i
t
e

s
t
C

t
R

Parallel-word input

External memory

User I/O

Serial port configuration

Parallel Communication

PLD/FPGA

20MHz clock

16 bit data/address bus

i
s
O

gat

i
v
e

t
i
ve

i
s
I
n

l
l
sens

r
s

(
M

331

0 on

l
y
)

Motor

Amplifier

out

DAC output

D/A

converter

Home

Index

coder

Pilot Motion Processor

Limit

switches

The shaded area shows the CPLD/FPGA that must be provided by the designer if parallel
communication is required. A description and the necessary logic (in the form of schematics) of this
device are detailed in section 6 of this manual. The CP chip contains the profile generator, which
calculates velocity, acceleration, and position values for a trajectory; and the commutation unit, which

MC3410 Technical Specifications

3 Electrical Characteristics

3.1 DC

characteristics

and T

per operating ratings, F

clk

= 20.0 MHz)

Symbol Parameter

Minimum

Maximum

Conditions

Supply Voltage

4.75 V

5.25 V

Supply Current

80 mA

open outputs

Input Voltages

Logic 1 input voltage

2.0 V

+ 0.3 V

Logic 0 input voltage

-0.3 V

0.8 V

ihclk

Logic 1 voltage for clock pin

(ClockIn)

3.0 V

+ 0.3 V

oclk

Logic 0 voltage for clock pin

(ClockIn)

-0.3 V

0.7 V

ihreset

Logic 1 voltage for reset pin (reset) 2.2 V

+ 0.3 V

Output Voltages

Logic 1 Output Voltage

2.4 V

@CP I

= -23 mA

Logic 0 Output Voltage

0.33 V

@CP I

= 6 mA

Other

out

Tri-State output leakage current

-5

�A 5

�A

@CP

0 < V

out

< V

Input

current

-10

�A

@CP

0 < V

< V

Input/Output capacitance

15 pF

@CP typical

Analog Input

Analog input source impedance

dnl

Differential nonlinearity error.
Difference between the step width

and the ideal value.

-1 1.5

LSB

inl

Integral nonlinearity error.

Maximum deviation from the best

straight line through the ADC

transfer characteristics, excluding
the quantization error.

+/-1.5

LSB

3.2 AC

characteristics

See timing diagrams, Section 4, for Tn numbers. The symbol "~" indicates active low signal.

Timing Interval

Minimum Maximum

Clock Frequency (F

clk

)

> 0 MHz

20 MHz (note 1)

Clock Pulse Width

25 nsec

Clock Period (note 2) T2

nsec

Encoder Pulse Width

150 nsec

Dwell Time Per State

75 nsec

~HostSlct Hold Time

0 nsec

MC3410 Technical Specifications

Timing Interval

Minimum Maximum

~HostSlct Setup Time

0 nsec

HostCmd Setup Time

0 nsec

HostCmd Hold Time

0 nsec

Read Data Access Time

T10

25 nsec

Read Data Hold Time

T11

10 nsec

~HostRead High to HI-Z Time

T12

20 nsec

HostRdy Delay Time

T13

100 nsec

150 nsec

~HostWrite Pulse Width

T14

70 nsec

Write Data Delay Time

T15

35 nsec

Write Data Hold Time

T16

0 nsec

Read Recovery Time (note 2)

T17 60

nsec

Write Recovery Time (note 2) T18 60

nsec

Read Pulse Width

T19

70 nsec

Address Setup Delay Time

T20

7 nsec

Data Access Time

T21

19 nsec

Data Hold Time

T22

2 nsec

Address Setup Delay Time

T23

7 nsec

Address Setup to WriteEnable High

T24

72 nsec

RAMSlct Low to WriteEnable High

T25

79 nsec

Address Hold Time

T26

17 nsec

WriteEnable Pulse Width

T27

39 nsec

Data Setup Time

T28

3 nsec

Data Setup before Write High Time

T29

42 nsec

Address Setup Delay Time

T30

7 nsec

Data Access Time

T31

71 nsec

Data Hold Time

T32

2 nsec

Address Setup Delay Time

T33

7 nsec

Address Setup to WriteEnable High

T34

122 nsec

PeriphSlct Low to WriteEnable High

T35

129 nsec

Address Hold Time

T36

17 nsec

WriteEnable Pulse Width

T37

89 nsec

Data Setup Time

T38

3 nsec

Data Setup before Write High Time

T39

92 nsec

Read to Write Delay Time

T40

50 nsec

Reset Low Pulse Width

T50

5.0

�sec

RAMSlct Low to Strobe Low

T51

1 nsec

Strobe High to RAMSlct High

T52

4 nsec

WriteEnable Low to Strobe Low

T53

1 nsec

Strobe High to WriteEnable High

T54

3 nsec

PeriphSlct Low to Strobe Low

T55

1 nsec

Strobe High to PeriphSlct High

T56

4 nsec

Note 1 Performance figures and timing information valid at F

clk

= 20.0 MHz only. For timing

information and performance parameters at F

clk

< 20.0 MHz, refer to section 7.1.

Note 2 The clock low/high split has an allowable range of 45-55%.

MC3410 Technical Specifications

5 Pinouts and Pin Descriptions

5.1 Pinouts

for

MC3410

~WriteEnbl

~PeriphSlct

GND

3, 8, 14, 20, 29, 37, 46, 56, 59,

61, 71, 92, 104, 113, 120

Unassigned

5, 30-34, 38, 39, 42, 45, 48, 49,

51, 55, 57, 73, 90, 91, 95, 105,

106, 107-109, 131

VCC

2, 7, 13, 21, 35, 36, 40, 47, 50,

52, 60, 62, 66, 93, 103, 121

11
12
15
16
17
18
19
22
23
24
25
26
27
28

111
112
114
115
116
117
118
119
122
123
124
125
126
127
128

43
44
99
98
58

SrlRcv
SrlXmt
SrlEnable
~HostIntrpt
ClockIn

Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
Data12
Data13
Data14
Data15

Addr1
Addr2
Addr3
Addr4
Addr5
Addr6
Addr7
Addr8
Addr9
Addr10
Addr11
Addr12
Addr13
Addr14
Addr15

4
6

130
129

R/~W
~Strobe

~RAMSlct
~Reset

W/~R

132

PosLim1

NegLim1

85
86
87

94
72

74
89
75
88
76
83
77
82

AxisOut1

AxisIn1

Analog1
Analog2
Analog3
Analog4
Analog5
Analog6
Analog7
Analog8

AnalogVcc

AnalogRefHigh

AnalogRefLow

AnalogGnd

QuadA1
QuadB1

69
70

100
101

~Index1

~Home1

PWMMag1
PWMMag2

110

Addr0

102

PWMMag3

PWMSign1

PWMSign2

NC/Synch

I/OIntrpt

PrlEnable

AGND

78-81

MC3410 Technical Specifications

5.2

CP chip pin description table

Pin Name and number Direction

Description

~WriteEnbl 1

output When

low, this signal enables data to be written to the bus.

R/~W 4

output

This signal is high when the CP chip is performing a read, and low when it is

performing a write.

~Strobe 6

output

This signal is low when the data and address are valid during CP

communications.

~PeriphSlct 130

output

This signal is low when peripheral devices on the data bus are being addressed.

~RAMSlct 129

output

This signal is low when external memory is being accessed.

~Reset 41

input

This is the master reset signal. When brought low, this pin resets the processor to
its initial conditions.

W/~R 132

output

This signal is the inverse of

R/~W

; it is high when

R/~W

is low, and vice versa. For

some decode circuits, this is more convenient than

R/~W

SrlRcv 43

input

This pin receives serial data from the asynchronous serial port. If serial

communication is not used, this pin should be tied to V

SrlXmt 44

output

This pin transmits serial data to the asynchronous serial port.

SrlEnable 99

output

This pin sets the serial port enable line. SrlEnable is always high for the point-to-
point protocol and is high during transmission for the multi-drop protocol.

~HostIntrpt 98

output When

low, this signal causes an interrupt to be sent to the host processor.

I/OIntrpt 53

input

This signal interrupts the CP chip when a host I/O transfer is complete. It
should be connected to

CPIntrpt

of the parallel interface chip.

If the parallel interface is disabled (see below) this signal can be left unconnected

or tied to V

PrlEnable 65

input

This signal enables/disables the parallel communication with the host. If this
signal is tied high, the parallel interface is enabled. If this signal is tied low the

parallel interface is disabled. See section 6 of this manual for more information
on parallel communication.

WARNING! This signal should only be tied high if an external
logic device that implements the parallel communication logic
included in the design. This signal is an output during device reset
and as such any connection to GND or V

must be via a series

resistor.

Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
Data12
Data13
Data14
Data15

9
10
11
12
15
16
17
18
19
22
23
24
25
26
27
28

bi-directional Multi-purpose

data

lines. These pins comprise the CP chip's external data bus,

used for all communications with peripheral devices such as external memory or
DACs. They may also be used for parallel-word input and for user-defined I/O

operations.

MC3410 Technical Specifications

Pin Name and number Direction

Description

Addr0
Addr1
Addr2
Addr3
Addr4
Addr5
Addr6
Addr7
Addr8
Addr9
Addr10
Addr11
Addr12
Addr13
Addr14
Addr15

110
111
112
114
115
116
117
118
119
122
123
124
125
126
127
128

output

Multi-purpose Address lines. These pins comprise the CP chip's external address

bus, used to select devices for communication over the data bus.
They may be used for DAC output, parallel word input, or user-defined I/O
operations. See the Pilot Motion Processor User's Guide for a complete memory map.

ClockIn 58

input

This is the clock signal for the Motion Processor. It is driven at a nominal
20MHz.

AnalogVcc 84

input

CP chip analog power supply voltage. This pin must be connected to the analog
input supply voltage, which must be in the range 4.5-5.5 V
If the analog input circuitry is not used, this pin must be connected to V

AnalogRefHigh 85

input

CP chip analog high voltage reference for A/D input. The allowed range is

AnalogRefLow

AnalogVcc

If the analog input circuitry is not used, this pin must be connected to V

AnalogRefLow 86

input

CP chip analog low voltage reference for A/D input. The allowed range is

AnalogGND

AnalogRefHigh

If the analog input circuitry is not used, this pin must be connected to GND.

AnalogGND 87

CP chip analog input ground. This pin must be connected to the analog input

power supply return.
If the analog input circuitry is not used, this pin must be connected to GND.

Analog1
Analog2
Analog3
Analog4
Analog5
Analog6
Analog7
Analog8

74
89
75
88
76
83
77
82

input

These signals provide general-purpose analog voltage levels, which are sampled
by an internal A/D converter. The A/D resolution is 10 bits.
The allowed range is

AnalogRefLow

AnalogRefHigh

Any unused pins should be tied to AnalogGND.
If the analog input circuitry is not used, these pins should be tied to GND.

PWMMag1
PWMMag2
PWMMag3
PWMSign1
PWMSign2

100
101
102
96
97

output

These pin provide the Pulse Width Modulated signals for each phase to the

motor. The PWM resolution is 9 bits at a frequency of 20.0 KHz.

In 2 or 3-phase PWM 50/50 mode, PWMMag1/2/3 are the only signals and
encode both the magnitude and direction in the one signal.

In single-phase PWM sign/magnitude mode, PWMMag1 and PWMSign1 are the
PWM magnitude and direction signals respectively.

In 2-phase PWM sign/magnitude mode, PWMMag1 and PWMSign1 are the
PWM magnitude and direction signals for Phase A. PWMMag2 and PWMSign2,

are the PWM magnitude and direction signals for Phase B.

Unused pins may be left unconnected.

MC3410 Technical Specifications

Pin Name and number Direction

Description

QuadA1
QuadB1

67
68

input

These pins provide the A and B quadrature signals for the incremental encoder.

When the axis is moving in the positive (forward) direction, signal A leads signal
B by 90�.
The theoretical maximum encoder pulse rate is 5.1 MHz. Actual maximum rate

will vary, depending on signal noise.
NOTE: Many encoders require a pull-up resistor on each signal to establish a
proper high signal. Check your encoder's electrical specification.

~Index1 69

input

This pin provides the Index signal for the incremental encoder. A valid index

pulse is recognized by the chip when

this signal transitions from

high

low.

There is no internal gating of the index signal with the encoder A
and B inputs. This must be performed externally if desired. Refer
to the Application Notes section at the end of this manual for an
example.

~Home1 70

input

This pin provides the Home signal, general-purpose inputs to the position-

capture mechanism. A valid Home signal is recognized by the chip when

~Home

goes low.

WARNING! If this pin is not used, its signal should be tied high.

PosLim1

input

This signal provides input from the positive-side (forward) travel limit switch.
On power-up or

Reset

this signal defaults to active low interpretation, but the

interpretation can be set explicitly using the

SetSignalSense

instruction.

WARNING! If this pin is not used, its signal should be tied high.

NegLim1 64

input

This signal provides input from the negative-side (reverse) travel limit switch. On
power-up or

Reset

this signal defaults to active low interpretation, but the

interpretation can be set explicitly using the

SetSignalSense

instruction.

WARNING! If this pin is not used, its signal should be tied high.
This signal is an output during device reset and as such any
connection to GND or V

must be via a series resistor.

AxisOut1 94

output

This pin can be programmed to track the state of any bit in the Status registers.
If this pin is not used it may be left unconnected.

AxisIn1 72

input

This is a general-purpose or programmable input. It can be used as a breakpoint
input, to stop a motion axis, or to cause an

Update

to occur.

If this pin is not used it may be left unconnected.

NC/Synch 54

input/output On the MC3410 this pin is not used.

On the MC3413 this pin is the synchronization signal. In the disabled mode, the

pin is configured as an input and is not used. In the master mode, the pin
outputs a synchronization pulse that can be used by slave nodes or other devices

to synchronize with the internal chip cycle of the master node. In the slave
mode, the pin is configured as an input and a pulse on the pin synchronizes the

internal chip cycle.

2, 7, 13, 21, 35, 36, 40,

47, 50, 52, 60, 66, 62,
93, 103, 121

CP digital supply voltage. All of these pins must be connected to the supply

voltage. V

must be in the range 4.75 - 5.25 V

WARNING! Pin 35 must be tied HIGH with a pull-up resistor. A
nominal value of 22K Ohms is suggested.

GND

3, 8, 14, 20, 29, 37, 46,

56, 59, 61, 71, 92, 104,
113, 120

CP ground. All of these pins must be connected to the power supply return.

MC3410 Technical Specifications

6 Parallel Communication

With the addition of an external logic device, the Pilot motion processor can communicate with a
host processor using a parallel data stream. This offers a higher communication rate than a serial
interface and may be used in configurations where a serial connection is not available or not
convenient. This section details the required logic that must be implemented in the external device
as well as the necessary connections to the CP chip.
The reference design files for the parallel interface chip, in Actel/ViewLogic format, are available
from PMD. There are two versions of the design, one for interfacing with host processors that have
an 8-bit data bus and one for host processors that have a 16-bit data bus. The designs are called
IOPIL8 and IOPIL16 respectively. The interface to the CP chip is essentially identical in both.
The function of the I/O chip is to provide a shared-memory style interface between the host and CP
chip, comprised of four 16-bit wide locations. These are used for transferring commands and data
between the host and Pilot motion processor. The CP chip accesses the command/data registers
using its 16-bit external data bus while the host accesses the registers via a parallel interface with chip
select, read, write and command/data signals. If necessary, the host side interface can be modified
by the designer to match specific requirements of the host processor.

6.1

Host interface pin description table

Pin Name

Direction

Description

HostCmd

input

This signal is asserted high to write a host instruction to the motion processor, or to

read the status of the

HostRdy

and

HostIntrpt

signals. It is asserted low to read or write

a data word.

HostRdy

output

This signal is used to synchronize communication between the motion processor
and the host.

HostRdy

will go low (indicating host port busy) at the end of a read or

write operation according to the interface mode in use, as follows:
Interface Mode

HostRdy

goes low

8/16

after the second byte of the instruction word

after the second byte of each data word is transferred

16/16

after the 16-bit instruction word

after each 16-bit data word

serial

n/a

HostRdy

will go high, indicating that the host port is ready to transmit, when the last

transmission has been processed. All host port communications must be made
with

HostRdy

high (ready).

A typical busy-to-ready cycle is 12.5 microseconds, but can be substantially longer,
up to 100 microseconds.

~HostRead

input When

~HostRead

is low, a data word is read from the motion processor.

~HostWrite

input When

~HostWrite

is low, a data word is written to the motion processor.

~HostSlct

input When

~HostSlct

is low, the host port is selected for reading or writing operations.

CPIntrpt

output

I/O chip to CP chip interrupt. This signal sends an interrupt to the CP chip

whenever a host�chipset transmission occurs. It should be connected to CP chip
pin 53,

I/OIntrpt

CPR/~W

input

This signal is high when the I/O chip is reading data from the I/O chip, and low
when it is writing data. It should be connected to CP chip pin 4,

R/W

CPStrobe

input

This signal goes low when the data and address become valid during Motion
processor communication with peripheral devices on the data bus, such as external

memory or a DAC. It should be connected to CP chip pin 6,

Strobe

MC3410 Technical Specifications

Pin Name

Direction

Description

CPPeriphSlct

input

This signal goes low when a peripheral device on the data bus is being addressed. It

should be connected to CP chip pin 130,

PeriphSlct.

CPAddr0
CPAddr1
CPAddr15

input These

signals

are

high when the CP chip is communicating with the I/O chip (as

distinguished from any other device on the data bus). They should be connected to
CP chip pins 110 (

Addr0

), 111 (

Addr1

), and 128 (

Addr15

MasterClkIn

input

This is the master clock signal for the motion processor. It is driven at a nominal
40 MHz

CPClk

output

This signal provides the clock pulse for the CP chip. Its frequency is half that of

MasterClkIn

(pin 89), or 20 MHz nominal. It is connected directly to the CP chip

I/Oclk

signal (pin 58).

HostData0
HostData1
HostData2
HostData3
HostData4
HostData5
HostData6
HostData7
HostData8
HostData9
HostData10
HostData11
HostData12
HostData13
HostData14
HostData15

bi-directional,

tri-state

These signals transmit data between the host and the Motion processor through

the parallel port. Transmission is mediated by the control signals

~HostSlct,

~HostWrite, ~HostRead and HostCmd

In 16-bit mode, all 16 bits are used (

HostData0-15

). In 8-bit mode, only the low-

order 8 bits of data are used (

HostData0-7

CPData0
CPData1
CPData2
CPData3
CPData4
CPData5
CPData6
CPData7
CPData8
CPData9
CPData10
CPData11
CPData12
CPData13
CPData14
CPData15

bi-directional These

signals

transmit

data between the I/O chip and pins

Data0-15

of the CP chip,

via the motion processor data bus.

MC3410 Technical Specifications

6.2

16-bit Host Interface (IOPIL16)

This design implements a parallel interface with a host processor utilizing a 16-bit data bus. An
understanding of the underlying operation of the design is only necessary if the designer intends to
make modifications. In most cases this design can be implemented without changes. The following
notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The
timing for the host to I/O chip communication can be found in section 4.5 and the timing for the
CP to I/O chip communication can be found in section 4.7.
The description below identifies the key elements of each schematic starting with the host side
signals. The paragraph title identifies the key schematic(s) being described in the text.

IOPIL16 3
The host interface is shown in sheet IOPIL16 3. The incoming data HD[15:0] is latched in the
transparent latches when ~HG1 and ~HG2 go high. This would be the result of a write from the
host to the CP. The latched data HI[15:8] and HI[7:0] go to schematic IOPIL16 1 and IOPIL16 5.
Data from the interface to the host, HO[15:8] and HO[7:0] is enabled onto the host bus, HD[15:0],
by HOES2 and HOES1 respectively. The output latches, which present the data during a host read,
are always transparent because GOUT is connected to VDD. The latched I/O is an I/O option on
the Actel part used and could be omitted in the host interface if a different CPLD or FPGA does not
have this feature.

IOPIL16 1
The control for the host interface starts on IOPIL16 1. HOES1 and HOES2 are the AND of
~HSEL and ~HRD and enable read data onto the host bus, as previously described. HRDY is a
handshaking signal to the host to allow asynchronous communication between the host and the CP.
The host must wait until HRDY is true before attempting to communicate with the CP. This signal
is copied as a bit in the host status register. The host status register may be read at any time to
determine the state of HRDY, or the HRDY output may be used as an interrupt to the host.
~HSEL, ~HRD, ~HWR, and HA0 are the buffered inputs of the host control signals.

HOST INTERFACE/IOPIL16 5
Data from the host HI[15:8] and HI[7:0] is written into REG1 and REG2 on the schematic HOST
INTERFACE by ~EN1 and ~EN2. These registers have a 2 to 1 multiplexed input with both the
host data and the CP data being written to these registers. This is convenient for diagnostic purposes
and is very efficient in the Actel A42MX FPGA's, which are multiplexer based but if the
configuration of the logic device used demands it, separate registers could be used for the host and
CP data. The schematic for this register is shown as DFME8. Only commands and checksums are
written to registers REG1 and REG2 while data is written and read from the set of data registers,
DATREG shown on IOPIL16 5. These 3 data registers buffer data sent to and from the CP,
reducing the number of interrupts the CP must handle. The output from REG1 and REG2,
CIQ[15:8] and CIQ[7:0] go to IOPIL16 5, where they are multiplexed with the other data registers.
The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] - the
output of the host status registers REG3 and REG4. As previously mentioned, HRDY becomes
HST15 so it can be read by the host. The rest of the status register is written by the CP to provide
information to the host. HA0 acts as an address bit, and usually is an address bit on the bus. When
the host is writing, HA0 low indicates data and HA0 high indicates a command. When the host is
reading, HAO low indicates data and HA0 high indicates status. Read status is the only transaction

MC3410 Technical Specifications

allowed while HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two
flops latch the incoming data in the interface latches by driving ~HG1, and ~HG2 low from the
start of the write transaction until the first negative clock transition after the first positive transition
following the start of the write cycle. This tail-biting circuit removes the requirement for hold time
on the data bus.

IOPIL16 4
The CP interface is shown in sheet IOPIL16 4. The incoming data DSD[15:0] is latched in the
transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from
the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL16 1 and
IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and
DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output
latches, which present the data during a CP read, are always transparent because GOUT is connected
to VDD. The latched I/O in the Actel part contains both input and output latches. The output
latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature.
The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal
is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.

IOPIL16 2
The CP control starts on IOPIL16 2. The I/O control is generated from ~CPSTRB, ~CPIS,
CPSEL and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-
enable the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold
times on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be
used for this interface and the CP.

MC3410 Technical Specifications

DSPWA
The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to
save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits,
LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register
and selecting the page for the successive transfers. A read from address 0 reads the status register on
all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The
write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown
on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY.
DSWST writes to the host status register also shown on the HOST INTERFACE schematic.
DSWDREG implements writing to the data registers shown on IOPIL16 5 and DATREG. Finally
the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over
that implements the actual writes to the registers. The use of the data bus latches and the post bus
cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices,
without requiring clocking at several times the bus speed.

DSPRA
The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the
CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15
(indicating the CP is interrupting the host), bits 13 and 14 (both 0 indicating a 16 bit host interface)
and bit 0 (set to 1 during a host command transfer and 0 during data transfer).

HOST INTERFACE
Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts.
This special mode is under the control of the CP and is transparent to the host. When the CP
receives a command from the host it initializes the transfer by setting the number of transfers
expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST
INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on
IOPIL16 5. Note that a Q8 low, which indicates a host command, asynchronously clears this
register enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating
a host data transfer, and SINT goes high indicating the end of a host cycle the counter is
decremented. MXAD2 selects address RA from the CP latched address bits if the page register
contains 6, or the counter contents DPNT[1:0] if not. This allows the CP to have direct access to
registers 1, 2, and 3, using addresses 1,2,and 3 on page 6. The host on the other hand can only read
or write to the data register, HA0 low and the counter will auto decrement from 3 down to 0
allowing the host to access the registers on DATREG where REG1=R1 and R2, REG2=R3 and R4,
and REG3=R5 and R6. The writes are enabled by the two decoders DECE2X4, while the reads are
selected by the two 4x8 muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and
MDS0. The output data IQ[15:0] goes to HOST INTERFACE schematic below IOPIL16 1 and to
DSPRA below IOPIL16 2. The write data is HI[15:8], HI[7:0] from the host and DSI[15:8] and
DSI[7:0] from the CP.

VDD

HD0

HD1

HD2

HD3

HD4

HD5

HD7

HD8

HD9

HD10

HD11

HD13

HD14

HD15

HG1

HI8

HI9

HI10

HI11

HI12

HI13

HI14

HI15

HI[15:0]

HG2

HG1

HO0

HO1

HO2

HO3

HO5

HO6

HO7

HO4

HO[7:0]

VDD

HOES1

HOES2

HG2

VDD

HO8

HO9

HO10

HO11

HO12

HO14

HO15

HO[15:8]

HO13

VDD

HI1

HI2

HI3

HI4

HI5

HI6

HI7

HI[7:0]

HI0

HD6

HD12

VCC

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

DRAWN BY:

IOPIL16 3

21 OCT 2002

DBS

LA1

DSD0

DSD1

DSD12

DSD13

DSD14

DG2

DSI3

DSI4

DSI5

DSI6

DSI7

DSI2

DSI1

DSI[7:0]

DO9

DO10

DO11

DO15

DO14

DO13

DO12

DO[15:8]

DO8

DOE2

DOE1

CPA0

CPA1

LA0

DO3

DO7

DO6

DO5

DO4

DO[7:0]

DO1

DO2

DO0

DSI8

DSI9

DSI10

DSI15

DSI14

DSI13

DSI[15:8]

DG1

VDD

GND

DG3

CLKOUT

20CK

DOE2

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

DRAWN BY:

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

PAD

OUTBUF

VCC

DBS

IOPIL16 4

21 OCT 2002

DOE1

DSI0

DSD2

DSD3

DOE1

DSD7

DSD6

DSD5

DSD4

DOE2

DSD8

DSD9

DSD10

DSD11

DSI11

DOE2

DSI12

DSD15

ENHD1

EN1

EN2

VDD

HCYC

HSEL

DSPINTR

LRDST

HCYC

HA0

HRD

HSEL

HRD

HWR

HRD

HSEL

CLRFLGS

HWR

HSEL

HWR

GND

HCYC

HSEL

HWR

HA0

HCYC

VDD

INV3

HCMD

INV4

SHCMD

SLRDST

INV1

HCYC

HRDY

F10

G21

HCMDFL

HWR

LRDST

SINTR

WREN

RDEN

DPNT[1:0]

DPNT1

DPNT0

INV2

HWR

SHWR

F13

LWR

EBSY

HCYC

HCMD

G19

HCCYC

DSIW

DSPINTR

ENHD2

HCYC

DSIW

G10

VDD

HRD

HWR

LWR

CLRFLGS

SINT

INTEN

INV

AND2A

NAND2

NAND3B

NOR2

OA4

CLK

DF1

CLK

DF1

VCC

D0
D1

D2
D3

S0
S1

CLK

CLR

DFM6A

AND2B

OA1C

CLK

CLR

JKF2C

INV

CLK

CLR

JKF2C

INV

AND3B

CLK

JKF

INV

CLK

DF1

NOR4

CLK

JKF

CLK

DF1

AND3

INV

AND2B

CLK

CLR

JKF2C

AND2

OR3C

NAND2B

NAND2

DRAWN BY:

AND3B

DBS

21 OCT 2002

HICTLA

GND

RA1

DSPSEL1

HI[7:0]

DSI[7:0]

HIH[15:8]

DSI[15:8]

EN1R3

EN2R3

DSPSEL2

DSPSEL1

R2[7:0]

EN2R2

EN1R2

DSI[15:8]

CLK

HIH[15:8]

DSI[7:0]

HI[7:0]

DSI[7:0]

HIH[15:8]

DSI[15:8]

EN1R1

EN2R1

R1[15:8]

DSPSEL

R2[15:8]

R1[7:0]

MDS1

MDS0

MDS1

MDS0

EN2R1

EN2R2

EN2R3

EN1R1

EN1R2

EN1R3

DSPSEL

PP6

MUX1

R3[7:0]

R3[15:8]

LA0

LA1

PP4

DOE1

IQ[15:8]

IQ[7:0]

LA[1:0]

DSPSEL2

RA[1:0]

RA0

RA1

END1

END2

DEC1

DEC2

MDS0

RA0

GND

MDS1

DSIR

CLK

CIQ[7:0]

R1[7:0]

R3[7:0]

R2[7:0]

CIQ[15:8]

R1[15:8]

R3[15:8]

MUX2

R2[15:8]

GND

DRAWN BY:

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

DATA3_[7:0]

DATA2_[7:0]

DATA1_[7:0]

DATA0_[7:0]

RESULT[7:0]

SEL1

SEL0

MUX4X8

BUF

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

DATA0

ENABLE

DATA1

EQ3

EQ2

EQ1

EQ0

DECE2X4

DATA0

ENABLE

DATA1

EQ3

EQ2

EQ1

EQ0

DECE2X4

AND4A

MX2

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

DATA3_[7:0]

DATA2_[7:0]

DATA1_[7:0]

DATA0_[7:0]

RESULT[7:0]

SEL1

SEL0

MUX4X8

DBS

24 OCT 2002

DATREG

MC3410 Technical Specifications

6.3

8-bit Host Interface (IOPIL8)

This design implements a parallel interface with a host processor utilizing an 8-bit data bus. An
understanding of the underlying operation of the design is only necessary if the designer intends to
make modifications. In most cases this design can be implemented without changes. The following
notes should be read while referencing the schematics. IOPIL16 1 is the top level schematic. The
timing for the host to I/O chip communication can be found in section 4.4 and the timing for the
CP to I/O chip communication can be found in section 4.7.
The description below identifies the key elements of each schematic starting with the host side
signals. The paragraph title identifies the key schematic(s) being described in the text.

IOPIL8 3
The host interface for IOPIL8 is shown in sheet IOPIL8 3. The incoming data HD[7:0] is latched in
the transparent latches when ~HG1 goes high. This would be a write from the host to the CP. The
latched data HI[7:0] goes to IOPIL8 1 and IOPIL8 5. Data from the interface to the host, HO[7:0]
is enabled onto the host bus, HD[7:0], by HOES1. The output latches, which present the data
during a host read, are always transparent because GOUT is connected to VDD. The latched I/O is
an I/O option on the Actel part used and could be omitted in the host interface if a different CPLD
or FPGA does not have this feature. HD[15:8] are tri-stated outputs because Actel grounds unused
I/O pins and this would interfere with using existing PMD test equipment. These reserved I/O's can
be ommitted in a different implementation with an 8 bit bus.

IOPIL8 1
The control for the host interface starts on IOPIL8 1. HOES1 is the AND of ~HSEL and ~HRD,
and enable read data onto the host bus, as previously described. HRDY is a handshaking signal to
the host to allow asynchronous communication between the host and the CP. The host must wait
until HRDY is true before attempting to communicate with the CP. This signal is copied as a bit in
the host status register. The host status register may be read at any time to determine the state of
HRDY, or the HRDY output may be used as an interrupt to the host. ~HSEL, ~HRD, ~HWR, and
HA0 are the buffered inputs of the host control signals.

HOST INTERFACE/IOPIL8 5
Data from the host HI[7:0] is written into REG1 and REG2 on the schematic HOST INTERFACE
by ~EN1 and ~EN2. All transfers are 16 bits and take two writes or reads on the 8-bit bus. These
registers have a 2 to 1 multiplexed input with both the host data and the CP data being written to this
register.
This is convenient for diagnostic purposes and is very efficient in the Actel A42MX FPGA's, which
are multiplexer based but if the configuration of the logic device used demands it, separate registers
could be used for the host and CP data. The schematic for this register is shown as DFME8. Only
commands and checksums are written to registers REG1 and REG2 while data is written and read
from the set of data registers, DATREG shown on IOPIL8 5. These 3 data registers buffer data sent
to and from the CP, reducing the number of interrupts the CP must handle. The output from REG1
and REG2, CIQ[15:8] and CIQ[7:0] go to IOPIL8 5, where they are multiplexed with the other data
registers. The multiplexed result, IQ[15:8] and IQ[7:0], is multiplexed with HST[15:8] and HST[7:0] -
the output of the host status registers REG3 and REG4. This four input mux, MUX4X8, also
muxes the 16 bit data onto the 8-bit bus. As previously mentioned HRDY becomes HST15 so it can
be read by the host. The rest of the status register is written by the CP to provide information to the

MC3410 Technical Specifications

host. HA0 acts as an address bit, and usually is an address bit on the bus. When the host is writing,
HA0 low indicates data and HA0 high indicates a command. When the host is reading, HAO low
indicates data and HA0 high indicates status. Read status is the only transaction allowed while
HRDY is low. During a host write the AND gate (G1:HOST INTERFACE) and two flops latch the
incoming data in the interface latches by driving ~HG1 low from the start of the write transaction
until the first negative clock transition after the first positive transition following the start of the write
cycle. This tail-biting circuit removes the requirement for hold time on the data bus.

HICTLA
Most of the control logic for the host interface is shown on schematic HICTLA. The sequencer at
the top generates HCYC one clock interval after the interface has been accessed and the host has
finished the transaction. The nature of the transaction, rd/wr, command/data, and read status is
preserved in the three flops F13, F8, and F9. Since 16 bit transfers must take place over an 8 bit bus
two transfers are required. The toggle flop is used to determine whether a cycle is the first or second
of the 2 required. The toggle flop may be initialized to the 0 state, which indicates that this is the
first transfer (high byte), by the CP writing a one to host status bit 15. This status bit is read by the
host as the HRDY bit and is not writable by the CP. In addition flop F12 and the associated gating
determine if the present command transaction is the first or second byte of a command. If the
toggle flop gets into the wrong state due to a missed or aborted transfer the next command will set it
back to the correct state. A host write or a CP write, DSIW, enable REG1 and REG2 on the HOST
INTERFACE schematic discussed previously. A host data write generates ~ENHD1 and
~ENHD2 for the data registers on the DATAREG schematic. For host writes ~EN2, ~EN1,
~ENHD2, and ~ENHD1 are also determined by the state of the toggle flop using HIEN and
LOEN. 1CMD is used in this logic to ensure correct behavior when the command is correcting the
state of the toggle. The logic at the bottom of the page generates the CP interrupt, the HRDY and
the HCMDFL. The HCMDFL is used in the CP status to indicate a command. DSIW, the CP
writing to REG1 and REG2 on the HOST INTERFACE schematic clears the interrupt and reasserts
HRDY. HRDY is de-asserted during all host transactions except read status, and stays de-asserted
until the CP has completed the DSIW cycle that clears the interrupt and reasserts HRDY. As
mentioned previously data transfers to and from the host use the data registers and do not interrupt
the CP. The CP knows the number of data transfers that must take place after decoding the
command. It places this number, 0-3, in the 2 least significant bits of the host status register,
HST[1:0]. These become DPNT[1:0] on this page of the schematic and enable an interrupt at 0 for a
read and 1 or 0 for a write. The CP always leaves these bits at 0 unless setting up a multiple word
data transfer. If INTEN is true and LRDST, latched read status, is false, HCYC will generate an
interrupt to the CP. This will also hold HRDY false until after the CP writes to the interface register,
DSIW, thereby generating ~CLRFLGS.

IOPIL8 4
The CP interface is shown in sheet IOPIL8 4. The incoming data DSD[15:0] is latched in the
transparent latches when ~DG1 and ~DG2 go high. This occurs at the completion of a write from
the CP to the I/O chip. The latched data DSI[15:8] and DSI[7:0] go to schematic IOPIL8 1 and
IOPIL16 5. DSI[7:0] also goes to IOPIL16 2. Data from the interface to the CP, DO[15:8] and
DO[7:0] is enabled onto the CP bus, DSD[15:0], by DOE2 and DOE1 respectively. The output
latches, which present the data during a CP read, are always transparent because GOUT is connected
to VDD. The latched I/O in the Actel part contains both input and output latches. The output
latches could be omitted in the CP interface if a different CPLD or FPGA does not have this feature.
The two incoming CP address bits CPA0 and CPA1 are also latched using ~DG3. The 20CK signal
is the clock for the CP. This is a 20 MHz clock derived from a 40 MHz clock input.

MC3410 Technical Specifications

IOPIL8 2
The CP control starts on IOPIL8 2. The I/O control is generated from ~CPSTRB, ~CPIS, CPSEL
and R/W. ~DG1, ~DG2, and ~DG3 latch the incoming data and DOE1 and DOE2 out-enable
the data from this chip to the CP. F2 and F4 tail-bite the write to avoid having to specify hold times
on the data. Flop F1 divides the 40MHz clock down to 20 MHz. A 20 MHz clock could be used for
this interface and the CP.

DSPWA
The CP write control is contained on schematic DSPWA. The CP interface uses page addressing to
save I/O pins. F0, F1 and F2 make up the page register. In addition there are the 2 address bits,
LA0 and LA1. A write to address 0 selects the page register with DSI[2:0] going to the page register
and selecting the page for the successive transfers. A read from address 0 reads the status register on
all pages. Pages 4 and 6 are the only ones implemented in this device. L1 latches the r/w level. The
write decoding generates DSIW which enables writes to the DFME8 registers reg1 and reg2 shown
on the HOST INTERFACE schematic. DSIW also clears the CP interrupt and restores HRDY.
DSWST writes to the host status register also shown on the HOST INTERFACE schematic.
DSWDREG implements writing to the data registers shown on IOPIL8 5 and DATREG. Finally
the logic at the bottom of the page generates CPCYC, a 1-clock interval after the CP cycle is over
that implements the actual writes to the registers. The use of the data bus latches and the post bus
cycle transfers keeps as much of the logic synchronous as possible given two asynchronous devices,
without requiring clocking at several times the bus speed.

DSPRA
The CP read control is contained on schematic DSPRA. The 2 by 16 bit mux selects CP status if the
CP latched address is 0 and IQ[15:0] if the address is not 0. The only significant status bits are bits 15
(indicating the CP is interrupting the host), bit 14 (1 indicating an 8-bit host interface) and bit 0 (set
to 1 during a host command transfer and 0 during data transfer).

HOST INTERFACE
Both the CP and the host use a special mode to transfer data to avoid unnecessary CP interrupts.
This special mode is under the control of the CP and is transparent to the host. When the CP
receives a command from the host it initializes the transfer by setting the number of transfers
expected (0,1,2 or 3) in the 2 LSB's of the host status register, REG3 and REG4 on HOST
INTERFACE. This write (DSWST) also loads these bits into the 2 bit down counter DCNT2 on
IOPIL8 5. Note that a Q8 low, which indicates a host command, asynchronously clears this register
enabling interrupts on schematic HICTLA. If DPNT[1:0] is not 0 and Q8 is high, indicating a host
data transfer, and SINT goes high indicating the end of a host cycle the counter is decremented.
MXAD2 selects address RA from the CP latched address bits if the page register contains 6, or the
counter contents DPNT[1:0] if not. This allows the CP to have direct access to registers 1, 2, and 3,
using address 1,2,and 3 on page 6. The host on the other hand can only read or write to the data
register, HA0 low and the counter will auto decrement from 3 down to 0 allowing the host to access
the registers on DATAREG where REG1=R1 and R2, REG2=R3 and R4, and REG3=R5 and R6.
The writes are enabled by the two decoders DECE2X4 while the reads are selected by the two 4x8
muxes, MUX1 and MUX2 controlled by the two 2x1 muxes MDS1 and MDS0. The output data
IQ[15:0] goes to HOST INTERFACE schematic below IOPIL8 1 and to DSPRA below IOPIL8 2.
The write data is HI[7:0] from the host and DSI[15:8] and DSI[7:0] from the CP. Note that END1

LA1

DSD0

DSD1

DSD2

DSD3

DSD4

DSD5

DSD6

DSD7

DSD8

DSD9

DSD10

DSD11

DSD12

DSD13

DSD14

DSD15

DG2

DO9

DO10

DO11

DO15

DO14

DO13

DO12

DO[15:8]

DO8

DOE2

CPA0

CPA1

LA0

DO3

DO7

DO6

DO5

DO4

DO[7:0]

DO1

DO2

DO0

DSI8

DSI9

DSI10

DSI11

DSI15

DSI14

DSI13

DSI12

DSI[15:8]

DG1

VDD

GND

DG3

CLKOUT

20CK

DOE2

DSI4

DSI5

DSI6

DSI7

DSI2

DSI1

DSI0

DSI[7:0]

DSI3

DOE1

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

DRAWN BY:

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

GOUT

GIN

PAD

HIGH SLEW

BBDLHS

PAD

OUTBUF

VCC

DBS

22 OCT 2002

IOPIL8 4

VDD

HCYC

HSEL

HCYC

DSPINTR

LRDST

VDD

HCYC

HA0

HRD

HSEL

LOEN

HWR

HRD

HSEL

CLRFLGS

HWR

HSEL

HWR

HIEN

GND

HCYC

G12

G14

HSEL

HWR

HA0

HCYC

VDD

INV3

HCMD

SHCMD

HCYC

HRDY

F10

G21

HCMDFL

LCMD

HCYC

F12

EN1

EN2

HIEN

HWR

ENHD2

ENHD1

ENINTR

LRDST

SINTR

CLRFLGS

SINT

INTEN

WREN

RDEN

DPNT[1:0]

DPNT1

DPNT0

INV2

HWR

SHWR

F13

LWR

EBSY

HCYC

HCMD

G19

HCCYC

HCYC

RSTOG

TOGGLE

1CMD

TOGGLE

1CMD

TOGGLE

1CMD

TOGGLE

1CMD

DSIW

1CMD

HWR

INV1

HRD

DSIW

LWR

LOEN

G10

SLRDST

INV4

INV

AND2A

NAND2A

OA4

CLK

DF1

CLK

DF1

VCC

D0
D1

D2
D3

S0
S1

CLK

CLR

DFM6A

AND2B

AOI1

INV

AND3B

CLK

JKF

CLK

DF1

NOR4

CLK

JKF

CLK

DF1

CLK

CLR

DFE3A

CLK

DFE

NAND3

AND3

NAND3B

NAND2B

OR3C

INV

AND2B

CLK

CLR

JKF2C

AND2

AND2A

OR2A

AND3A

DRAWN BY:

OA1C

INV

AND3B

CLK

CLR

JKF2C

CLK

CLR

JKF2C

INV

TOGGLE LO (1ST BYTE) LD HI, RD HI

HICTLA

22 OCT 2002

DBS

GND

END2

END1

RA1

RA0

RA[1:0]

DSPSEL2

DSPSEL1

HI[7:0]

DSI[7:0]

HI[7:0]

CLK

DSI[15:8]

EN1R3

EN2R3

DSPSEL2

DSPSEL1

R2[7:0]

EN2R2

EN1R2

DSI[15:8]

CLK

HI[7:0]

DSI[7:0]

HI[7:0]

DSI[7:0]

HI[7:0]

DSI[15:8]

EN1R1

R1[15:8]

DSPSEL

R2[15:8]

R1[7:0]

MDS1

MDS0

LA[1:0]

DSPSEL

PP6

MUX1

MUX2

R3[7:0]

R3[15:8]

LA0

PP4

DOE1

IQ[15:8]

IQ[7:0]

EN1R3

EN1R2

EN1R1

EN2R3

EN2R2

EN2R1

DSIR

LA1

RA0

GND

RA1

MDS0

MDS1

EN2R1

CLK

CIQ[7:0]

R1[7:0]

R3[7:0]

R2[7:0]

MDS1

R1[15:8]

R3[15:8]

CIQ[15:8]

R2[15:8]

MX2

DRAWN BY:

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

DATA3_[7:0]

DATA2_[7:0]

DATA1_[7:0]

DATA0_[7:0]

RESULT[7:0]

SEL1

SEL0

MUX4X8

DATA3_[7:0]

DATA2_[7:0]

DATA1_[7:0]

DATA0_[7:0]

RESULT[7:0]

SEL1

SEL0

MUX4X8

BUF

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

DATA0

DATA1

ENABLE

EQ0

EQ1

EQ2

EQ3

DECE2X4

DATA0

DATA1

ENABLE

EQ0

EQ1

EQ2

EQ3

DECE2X4

AND4A

GND

MX2

DBS

30 OCT 2002

DATREG

A[7:0]

B[7:0]

Q[7:0]

EN1

DFME8

MC3410 Technical Specifications

7 Application Notes

7.1 Design

Tips

The following are recommendations for the design of circuits that utilize a PMD Motion Processor.

Serial Interface
If the serial configuration decode logic is not implemented (see section 7.2) the CP data bus should
be tied high. This places the serial interface in a default configuration of 9600,n,8,1 after power on
or reset.

Controlling PWM output during reset
When the motion processor is in a reset state (when the reset line is held low) or immediately after a
power on, the PWM outputs can be in an unknown state, causing undesirable motor movement. It is
recommended that the enable line of any motor amplifier be held in a disabled state by the host
processor or some logic circuitry until communication to the motion processor is established. This
can be in the form of a delay circuit on the amplifier enable line after power up, or the enable line can
be ANDed with the CP reset line.

Parallel word encoder input
When using parallel word input for motor position, it is useful to also decode this information into
the User I/O space. This allows the current input value to be read using the chip instruction ReadIO
for diagnostic purposes.

Using a non standard system clock frequency
It is often desirable to share a common clock among several components in a design. In the case of
the PMD Motion Processors it is possible to use a clock below the standard value of 20MHz. In this
case all system frequencies will be reduced as a fraction of the input clock verses the standard
20MHz clock. The list below shows the affected system parameters:-

� Serial baud rate
� PWM carrier frequency
� Timing characteristics as shown in section 3.2
� Cycle time
� Commutation rate

For example, if an input clock of 17MHz is used with a serial baud rate of 9600 the following timing
changes will result:-

� Serial baud rate decreases to 9600 bps *17/20 = 8160 bps
� PWM frequency decreases to 20 KHz *17/20 = 17 KHz
� Cycle time increases to 153.6 �sec *20/17 = 180.71 �sec

FEMALE DB9 WIRED

AS SHOWN WILL

CONNECT TO A PC

WITHOUT A DUMMY

MODEM.

U2 AND U3 COULD BE IMPLEMENTED IN A PLD

RS232 SERIAL INTERFACE

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Monday, July 07, 2003

Title

Size

Document Number

Rev

Date:

Sheet

VCC

A0
A1

DS0

DS1

DS2

DS3

DS4

DS5

DS6

DS7

DS8

A10

DS9

A11

DS10

A12

DS11

A13

DS12

A14

DS13

A15

DS14

DS15

IS-

R/W

STRB-

VCC

C1+

C1-

V+

C2+

V-

C2-

SERXMIT

TXD

SERRCV

RXD

GND

RS-

CLK

GND

DS[0..15]

A[0..15]

DS4

SW8

SW6

VCC

SW7

DS1

SW6

DS6

SW1

DS7

SW15

SW13

SW14

SW8

DS5

DS[0..15]

DS10

SW2

DS12

DS8

SW16

SW5

SW16

SW10

SW12

DS14

SW3

SW9

SW15

SW11

DS15

DS9

IS-

DS0

SW9

SW4

DS[0..15]

SW12

SW11

SW1

SW2

DS3

SW14

SW4

R/W

DS13

DS2

SW5

DS11

SW7

VCC

SW10

SW3

STRB-

.1UF

50V

RS1

RSIP9

1
2

6
7

COM

R5
R6

.1UF

50V

.1UF

50V

RS2

RSIP9

1
2

6
7

COM

R5
R6

SW DIP-8

3
4

14
13

AD232

11
10

14
7

C1+

C1-

C2-

T1IN
T2IN

R1OUT

R2OUT

V+

V-

T1OUT
T2OUT

R1IN

R2IN

NOT

CONNECTOR DB9

9
4

2
6

NOT

.1UF

50V

22K

74LS244

6
8

14
12

1A1

1A2

1A3
1A4

2A1

2A2

2A3

2A4

1Y1

1Y2

1Y3
1Y4

2Y1

2Y2

2Y3

2Y4

.1UF

50V

SW DIP-8

3
4

14
13

NAND4

74LS244

6
8

14
12

1A1

1A2

1A3
1A4

2A1

2A2

2A3

2A4

1Y1

1Y2

1Y3
1Y4

2Y1

2Y2

2Y3

2Y4

CP2N11

11
12

18
19

110

111

112

114

115
116

117

118

119

122
123

124

125

126

127
128

129

130

4
6

25
26

59 61 71 92 104

113 120

62 93 103 121

132

100

88
76

3 8

131

101

102

73
90

GND

DATA0

DATA1

DATA2
DATA3

DATA4

DATA5

DATA6

DATA7
DATA8

DATA9

DATA10

DATA11

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4
ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14
ADDR15

~RAMSLCT

~PERIPHSLCT

R/~W

~STROBE

~WRITEENBL

DATA12
DATA13

DATA14

DATA15

GND

GND GND GND GND GND

GND GND

CLOCKIN

~RESET

GND

~RS

W/~R

POSLIM1

NEGLIM1

AXISOUT1

PWMMAG1

PWMSIGN1

AXISIN1

~HOSTINTRPT

SRLRCV

SRLXMT

I/OINTRPT

SRLENABLE

ANALOG1

ANALOG2

ANALOG3

ANALOG4
ANALOG5

ANALOG6

ANALOG7

ANALOG8

ANALOGVCC

ANALOGREFHIGH

ANALOGREFLOW

ANALOGGND

GND GND

GND

N/C

QUADA1

~INDEX1

~HOME1

QUADB1

PWMMAG2

PWMMAG3

PWMSIGN2

HALL1A
HALL1B

HALL1C

PRLENABLE

SYNCH

MC3410 Technical Specifications

7.4

PWM Motor Interface

The following schematic shows a typical interface circuit between the MC3410 and an amplifier that
accepts an analog current command and a separate sign bit.

Comments on Schematic

The A3952 from Allegro Microsystems is an integrated H-bridge package with internal current loop
control which provides all TTL and power-level circuitry to form a complete amplifier-on-a-chip.
The only other components needed are capacitors and resistors.

The analog current command input to the amplifier chip is constructed by low pass filtering the
digital magnitude output signal from the chipset. The sign bit is connected directly from the MC3410
chipset to the amplifier.

The amplifier performs the current control by continuously comparing the analog input signal from
the chipset (current command) to the measured current and tuning on or off the H-bridge drivers
accordingly to maintain the actual current close to the desired current.

Some of the resistor and capacitor values for the circuit may need to be adjusted depending on the
particular values for the motor resistance and inductance. In particular the value shown for R7 (.175
Ohm) may change if a maximum current of less than 2 Amps is desired. Other values which may be
adjusted are R1 and C1. These adjust the overall PWM frequency (off-time duration) as well as the
blanking interval. See the Allegro application notes for more information.

AXIS1

2 PHASES PER AXIS.

FILTER AND A3952SW REPEATED 2 TIMES

2 Phase PWM Sign Magnitude

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Tuesday, November 19, 2002

Title

Size

Document Number

Rev

Date:

Sheet

HOME1

SIGN1A

QUADA1

QUADB1

MAG1A

INDX1

GND

VCC

SIGN1A

VBB

MAG1B

GND

MAG1A

VCC

SIGN1B

GND

VCC

MAG1B

SIGN1B

.0047UF

15K

7.5K

1/4W MF

.0047UF

FILTBR

DIR

OUTA

OUTB

.1UF

63V

A3952SW

MODE

PHASE

ENABLE

BRAKE

REF

SENSE

OUTA

OUTB

VCC

MV+

GND

22K

47UF

63V

0.175

7.5K

1/4W MF

.1UF

CP24N11

14 20

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

129

130

59 61 71 92 104 113 120

62 93 103 121

132

100

3 8

131

101

102

VCC

GND GND

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

VCC

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

~RAMSLCT

~PERIPHSLCT

R/~W

~STROBE

~WRITEENBL

DATA12

DATA13

DATA14

DATA15

GND

GND GND GND GND GND GND GND

VCC

VCC VCC VCC VCC

CLOCKIN

VCC

~RESET

VCC

GND

~RS

W/~R

POSLIM1

NEGLIM1

AXISOUT1

PWMMAG1

PWMSIGN1

AXISIN1

~HOSTINTRPT

SRLRCV

SRLXMT

I/OINTRPT

SRLENABLE

ANALOG1

ANALOG2

ANALOG3

ANALOG4

ANALOG5

ANALOG6

ANALOG7

ANALOG8

ANALOGVCC

ANALOGREFHIGH

ANALOGREFLOW

ANALOGGND

GND GND

GND

N/C

QUADA1

~INDEX1

~HOME1

QUADB1

VCC

PWMMAG2

PWMMAG3

PWMSIGN2

HALL1A

HALL1B

HALL1C

PRLENABLE

SYNCH

1200PF

OUT1A-

OUT1B+

OUT1B-

OUT1A+

IT IS GENERALLY NOT NECESSARY

PROVIDED FOR VREFH AND VREFL

IF CLEAN SUPPLIES +- 10V ARE

0X4000+ 0,1,2,3.

TO PROVIDE OFFSET ADJUST.

4 DACS @ CP ADR

THE LOGIC WITHIN THE DOTTED LINES

IS EASILY IMPLEMENTED WITHIN A CPLD.

2 or 3 Phase 12-bit DAC OUT

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Tuesday, November 19, 2002

Title

Size

Document Number

Rev

Date:

Sheet

VCC

DS0

DS1

DS2

DS3

DS4

DS5

DS6

DS7

DS8

DS9

DS10

DS11

DS12

DS13

DS14

DS15

IS-

STRB-

WE-

RS-

CLK

GND

DS[0..15]

VREFH

DS13

VREFL

DS7

DACVA2

DS6

GND

DS11

DS12

VSS

GND

DS9

DS8

VDD

DS[4..15]

DS5

DS10

GND

RS-

DACVB1

DACVB2

DS4

CS1-

VCC

DACVA1

DS15

DS14

A14-

A12

A[0..15]

IS-

CS1-

A11

A10

A13

WE-

A14

A15

STRB-

CP24N1

14 20

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

129

130

59 61 71 92 104 113 120

62 93 103 121

132

100

3 8

131

101

102

VCC

GND GND

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

VCC

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

~RAMSLCT

~PERIPHSLCT

R/~W

~STROBE

~WRITEENBL

DATA12

DATA13

DATA14

DATA15

GND

GND GND GND GND GND GND GND

VCC

VCC VCC VCC VCC

CLOCKIN

VCC

~RESET

VCC

GND

~RS

W/~R

POSLIM1

NEGLIM1

AXISOUT1

PWMMAG1

PWMSIGN1

AXISIN1

~HOSTINTRPT

SRLRCV

SRLXMT

I/OINTRPT

SRLENABLE

ANALOG1

ANALOG2

ANALOG3

ANALOG4

ANALOG5

ANALOG6

ANALOG7

ANALOG8

ANALOGVCC

ANALOGREFHIGH

ANALOGREFLOW

ANALOGGND

GND GND

GND

N/C

QUADA1

~INDEX1

~HOME1

QUADB1

VCC

PWMMAG2

PWMMAG3

PWMSIGN2

HALL1A

HALL1B

HALL1C

PRLENABLE

SYNCH

22K

OR5

BURR-BROWN 7724,7725

SO or PLCC

VLOG

VDD

VREFH

GND

VSS

VREFL

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

R/W

/CS

/LDAC

VOUTA

VOUTB

VOUTC

VOUTD

/RESET

MC3410 Technical Specifications

7.6

16-bit Serial DAC Interface

The following schematic shows an interface circuit between the MC3410 and a dual 16-bit serial
DAC.

Comments on Schematic

The 16 data bits from the CP chip are latched in the two 74H165 shift registers when the CP writes
to address 400x hex, and the address bits A1 and A2 are latched in the 2 DLAT latches and decoded
by the 138 CPU cycle. The fed-back and-or gate latches, the decoded WRF, and the next clock will
clear the 1

sequencer flop DFF3. This will disable the WRF latch and the second clock will clear

the second DFF3 flop, forcing DACWRN low, and setting the first flop since WRF will have gone
high. DACWRN low will clear the 74109, SHFTCNTN. The 4 bit counter, 74161, is also parallel
loaded to 0, and the counter is enabled by ENP going high. The counter will not start counting nor
the shift register start shifting until the clock after the DACWRN flop sets since the load overrides
the count enable. When the DACWR flop is set the shift register will start shifting and the counter
will count the shifts. After 15 shifts CNT15 from the counter will go high and the next clock will set
the DACLAT flop and set the SHFTCNTN flop. This will stop the shift after 16 shifts and assert
L1 through L4 depending on the address stored in the latch. The 16th clock also was counted
causing the counter to roll over to 0 and CNT15 to go low. The next clock will therefore clear the
DACLAT flop causing the DAC latch signal L1 through L4 to terminate and the 16 bits of data to be
latched in the addressed DAC. The control logic is now back in its original state waiting for the next
write to the DACs by the CP. SERCK is a 10MHz clock, the 20MHz CP clock divided by 2, since
the AD1866 DACs will not run at 20MHz.

AXIS 1 AMP SHOWN TYPICAL OF ALL 4 AXIS

THE MODULE PORTS REPRESENT INPUTS AND OUTPUTS FROM THE CPLD

ALL LOGIC LABELLED U2 MAY BE IMPLEMENTED IN A CPLD

ALL INPUT SIGNALS ARE COMMON TO THE CP.

SERIAL DAC OUT

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Thursday, April 11, 2002

Title

Size

Document Number

Rev

Date:

Sheet

DACL

SERCK

GND

CLK

DS0

DS1

DS2

DS3

DS4

A14

A14N

DS5

IS-

DS6

WRF

DS7

R/W

LDN

A14

STRB-

IS-

CLKINH

R/W

SHTCNTN

STRB-

CLK

RS-

WRF

DACWRN

DS8

DS9

DS10

DS11

DS12

RS-

DS13

DS14

DS15

SERD

VCC

SERCK

VCC

5VA

SHFTCNTN

VB1

SDAT

VO1

GND

VCC

SDAT

DACL

SERCK

GND

DACL

VO2

VB2

WRF

SERCK

GND

VCC

5VA

VB3

+12VA

VO3

VO1

DACV1

VO4

VB4

-12VA

VB1

GND

DS[0..15]

GND

LDN

DFF

CLK

U2A

74109

CLK

74161

ENP

ENT

CLK

LOAD

CLR

RCO

NOT

100K

NOR2

74165

SER

CLK

INH

SH/LD

AND3

OR2

DLAT

138

G2A

G2B

AD1866

7 12

DGND AGND

CLK

VBL

VOL

NRL

NRR

VOR

VBR

AD1866

7 12

DGND AGND

CLK

VBL

VOL

NRL

NRR

VOR

VBR

10K

OR2

DLAT

OR5

NOT

U4A

OP497

74165

SER

CLK

INH

SH/LD

U2A

74LS74

CLK

DFF

CLK

10K

DFF3

CLK

NOT

NAND2

DFF3

CLK

U2A

74109

CLK

A14

CLK

RS-

IS-

R/W

STRB-

DACV1

DS[0..15]

SDAT

SERCK

PAGE REGISTER UP TO 16 BITS

NOTE:THE CRITICAL DECODE AND MEMORY

ACCESS TIME IS DURING READ,

THE REQUIRED ACCESS TIME IS

18 NS. FROM DS- LOW.

AS ILLUSTRATED THERE IS ~ 100NS.

TO ACCOMPLISH THE DECODING

FROM PAGE REG WRITE TO

MEMORY READ OR WRITE.

DECODING WILL HAVE TO BE

CAREFULLY DONE ON MEMORIES

WITH A SINGLE CHIP SELECT.

NOTE: POS139 IS A STANDARD 139 WITH INVERTED
OUTPUTS

RAM INTERFACE

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Tuesday, November 19, 2002

Title

Size

Document Number

Rev

Date:

Sheet

VCC

D10

D11

MPG0

D12

MPG1

D13

CS1

D14

CS2

D15

CS3

CS4

A10

A11

A12

A13

WE-

A14

PGR-

MPG0

A10

CS5

MPG1

A11

CS6

D10

A12

CS7

DS-

D11

A13

GND

CS8

CS1

D12

A14

D13

WE-

D14

W/R

D15

DS-

D10

D11

WE-

D12

W/R

D13

D14

D15

WE-

PGR-

D10

A13

D11

IS-

PGR-

D12

R/W

D13

D14

D15

A10

A11

A12

A13

A14

MPG0

MPG1

DS-

CS2

WE-

W/R

RS-

CLK

D[0..15]

A[0..14]

D[0..15]

A[0..14]

VCC

GND

IS-

R/W

U2A

POS139

74LS377

CLK

74LS377

CLK

MCM6226

A10

A11

A12

A13

A14

A15

A16

CE1

CE2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

MCM6226

A10

A11

A12

A13

A14

A15

A16

CE1

CE2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

22K

NOT

U2B

POS139

MCM6226

A10

A11

A12

A13

A14

A15

A16

CE1

CE2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CP2N11

14 20

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

129

130

59 61 71 92 104 113 120

62 93 103 121

132

100

3 8

131

101

102

VCC

GND GND

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

VCC

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

~RAMSLCT

~PERIPHSLCT

R/~W

~STROBE

~WRITEENBL

DATA12

DATA13

DATA14

DATA15

GND

GND GND GND GND GND GND GND

VCC

VCC VCC VCC VCC

CLOCKIN

VCC

~RESET

VCC

GND

~RS

W/~R

POSLIM1

NEGLIM1

AXISOUT1

PWMMAG1

PWMSIGN1

AXISIN1

~HOSTINTRPT

SRLRCV

SRLXMT

I/OINTRPT

SRLENABLE

ANALOG1

ANALOG2

ANALOG3

ANALOG4

ANALOG5

ANALOG6

ANALOG7

ANALOG8

ANALOGVCC

ANALOGREFHIGH

ANALOGREFLOW

ANALOGGND

GND GND

GND

N/C

QUADA1

~INDEX1

~HOME1

QUADB1

VCC

PWMMAG2

PWMMAG3

PWMSIGN2

HALL1A

HALL1B

HALL1C

PRLENABLE

SYNCH

OR3

MCM6226

A10

A11

A12

A13

A14

A15

A16

CE1

CE2

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

THE LOGIC LABELED U2 MAY BE IMPLEMENTED IN

A CPLD. THE LOWER 8 ADDRESS BITS, A0-A8, MAY BE

AND 256 USER OUTPUTS.

DECODED TO PROVIDE 256 16 BIT USER INPUTS

USER INPUTS

USER OUTPUTS

USER I/O

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Tuesday, November 19, 2002

Title

Size

Document Number

Rev

Date:

Sheet

UIO0

UIO1

UO0-0

UIO2

UO0-1

UIO3

UO0-2

UIO4

UO0-3

UIO

UIO5

UO0-4

UIO6

UO0-5

UIO7

UO0-6

UO0-7

WE-

UIO0

A10

A11

D10

A12

D11

A13

D12

A14

D13

D14

D15

UO0-8

A12

A12n

UO0-9

UIO

D10

UO0-10

IS-

D11

UO0-11

WE-

D12

UO0-12

W/R

D13

UO0-13

D14

UO0-14

D15

UO0-15

WE-

UIO0

A12n

UIOn

IS-

W/R

UI0n

UIO0

UI0-0

UI0-1

UI0-2

UI0-3

UI0-4

UI0-5

UI0-6

UI0-7

UI0-8

UI0-9

D10

UI0-10

D11

UI0-11

D12

UI0-12

RS-

D13

UI0-13

D14

UI0-14

CLK

D15

UI0-15

UI0n

D[0..15]

A[0..14]

GND

VCC

IS-

UI0n

OR2

OR3

244

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

138

G2A

G2B

22K

NOT

NOR2

74LS377

CLK

74LS377

CLK

244

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

CP2N11

14 20

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

129

130

59 61 71 92 104 113 120

62 93 103 121

132

100

3 8

131

101

102

VCC

GND GND

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

VCC

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

~RAMSLCT

~PERIPHSLCT

R/~W

~STROBE

~WRITEENBL

DATA12

DATA13

DATA14

DATA15

GND

GND GND GND GND GND GND GND

VCC

VCC VCC VCC VCC

CLOCKIN

VCC

~RESET

VCC

GND

~RS

W/~R

POSLIM1

NEGLIM1

AXISOUT1

PWMMAG1

PWMSIGN1

AXISIN1

~HOSTINTRPT

SRLRCV

SRLXMT

I/OINTRPT

SRLENABLE

ANALOG1

ANALOG2

ANALOG3

ANALOG4

ANALOG5

ANALOG6

ANALOG7

ANALOG8

ANALOGVCC

ANALOGREFHIGH

ANALOGREFLOW

ANALOGGND

GND GND

GND

N/C

QUADA1

~INDEX1

~HOME1

QUADB1

VCC

PWMMAG2

PWMMAG3

PWMSIGN2

HALL1A

HALL1B

HALL1C

PRLENABLE

SYNCH

NOTE:FS INPUTS ARE +- 10V

DACRD- WILL LOAD THE COUNTER TO 255.

12.8 USEC. AFTER THE LAST DACRD-

THE COUNTER WILL REACH 0 AND START THE

NEXT CONVERSION. THE INPUT WILL

BE CONVERTED IN 35 USEC. READY FOR

THE NEXT READ 50 USEC LATER.

BE IMPLEMENTEDIN A PLD.

NOTE:THE LOGIC LABELED U2 MAY

NOTE:SIGN EXTENTION FOR 2'S COMPLEMENT

12 BIT A/D IN

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Tuesday, November 19, 2002

Title

Size

Document Number

Rev

Date:

Sheet

VCC

POS1

POS2

POS3

POS4

CVT-

DACRD-

A11

-5VA

CVT-

ENCNT-

CLK

DACRD-

ENCNT-

DACRD-

DS[0..15]

VCC

DS7

DS4

DS8

DS1

A15

DS5

DS14

A13

A12

DS8

DS5

DS10

A10

DS3

GND

A11

DS3

DS15

STRB-

DS6

DS12

DS0

DS13

VCC

AGND

DS10

DS1

DS4

W/R

DS13

DS11

RS-

A14

DS9

GND

DS15

DS0

DS6

DS11

DS7

DS11

GND

DS[0..15]

DS2

CLK

DS14

DS12

DS9

DS2

A[0..15]

CLK

IS-

VCC

GND

74ALS169

CLK

LOAD

U/D

ENT

ENP

RCO

OR4

CP2N11

14 20

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

129

130

59 61 71 92 104 113 120

62 93 103 121

132

100

3 8

131

101

102

VCC

GND GND

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

VCC

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

~RAMSLCT

~PERIPHSLCT

R/~W

~STROBE

~WRITEENBL

DATA12

DATA13

DATA14

DATA15

GND

GND GND GND GND GND GND GND

VCC

VCC VCC VCC VCC

CLOCKIN

VCC

~RESET

VCC

GND

~RS

W/~R

POSLIM1

NEGLIM1

AXISOUT1

PWMMAG1

PWMSIGN1

AXISIN1

~HOSTINTRPT

SRLRCV

SRLXMT

I/OINTRPT

SRLENABLE

ANALOG1

ANALOG2

ANALOG3

ANALOG4

ANALOG5

ANALOG6

ANALOG7

ANALOG8

ANALOGVCC

ANALOGREFHIGH

ANALOGREFLOW

ANALOGGND

GND GND

GND

N/C

QUADA1

~INDEX1

~HOME1

QUADB1

VCC

PWMMAG2

PWMMAG3

PWMSIGN2

HALL1A

HALL1B

HALL1C

PRLENABLE

SYNCH

22K

74ALS169

CLK

LOAD

U/D

ENT

ENP

RCO

NOT

DFF2

CLK

NOT

AD7874

VIN1

VIN2

VIN3

VIN4

CONVST

CLK

REFIN

REFOUT

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

VDD

VSS

AGND

DGND

INT

74LS244

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

NOTE:FS INPUTS ARE +- 10V

38.4 USEC. AFTER THE DACRD-

THE COUNTER WILL REACH 0 AND START THE

NEXT CONVERSION. THE INPUT WILL

BE CONVERTED IN 10 USEC. READY FOR

THE NEXT READ AFTER 50 USEC.

BE IMPLEMENTEDIN A PLD.

NOTE:THE LOGIC LABELED U2 MAY

DACRD- WILL LOAD THE COUNTER TO 700.

SEE ANALOG DEVICES SPECIFICATIONS FOR

ADITIONAL INFORMATION AND POWER BYPASSING.

16 BIT A/D INPUT

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Tuesday, November 19, 2002

Title

Size

Document Number

Rev

Date:

Sheet

+5A

VCC

DS0

DS1

DS2

DS3

AIN1

DS4

DS5

DS6

DS7

DS8

A10

DS9

A11

DS10

A12

DS11

A13

DS12

A14

DS13

A15

CVT-

DS14

DS15

GND

IS-

STRB-

DACRD-

W/R

A11n

DACRD-

GND

A11

A11n

AGND

RS-

CLK

GND

ENCNT-

GND

CLK

DACRD-

CLK

GND

ENCNT-

DACRD-

DS[0..15]

VCC

CVT-

A[0..15]

VCC

74ALS169

CLK

LOAD

U/D

ENT

ENP

RCO

OR4

2.2UF

33.2

374

CLK

CP2N11

14 20

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

129

130

59 61 71 92 104 113 120

62 93 103 121

132

100

3 8

131

101

102

VCC

GND GND

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

VCC

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

~RAMSLCT

~PERIPHSLCT

R/~W

~STROBE

~WRITEENBL

DATA12

DATA13

DATA14

DATA15

GND

GND GND GND GND GND GND GND

VCC

VCC VCC VCC VCC

CLOCKIN

VCC

~RESET

VCC

GND

~RS

W/~R

POSLIM1

NEGLIM1

AXISOUT1

PWMMAG1

PWMSIGN1

AXISIN1

~HOSTINTRPT

SRLRCV

SRLXMT

I/OINTRPT

SRLENABLE

ANALOG1

ANALOG2

ANALOG3

ANALOG4

ANALOG5

ANALOG6

ANALOG7

ANALOG8

ANALOGVCC

ANALOGREFHIGH

ANALOGREFLOW

ANALOGGND

GND GND

GND

N/C

QUADA1

~INDEX1

~HOME1

QUADB1

VCC

PWMMAG2

PWMMAG3

PWMSIGN2

HALL1A

HALL1B

HALL1C

PRLENABLE

SYNCH

74ALS169

CLK

LOAD

U/D

ENT

ENP

RCO

200

AD976

2 5 14

D15

D14

D13

D12

D11

D10

AGND1 AGND2 DGND

VCC

VANA

BUSY

VIN

REF

CAP

R/C

BYTE

2.2UF

NOT

374

CLK

DFF2

CLK

22K

NOT

74ALS169

CLK

LOAD

U/D

ENT

ENP

RCO

EXTERNAL GATING LOGIC INDEX

PERFORMANCE MOTION DEVICES

55 OLD BEDFORD RD

LINCOLN, MA 01773

Tuesday, November 19, 2002

Title

Size

Document Number

Rev

Date:

Sheet

QUADA1

GND

VCC

HOME1

INDX1

INDEX1

QUADB1

QUADA1

QUADB1

22K

OR3

CP24N11

14 20

110

111

112

114

115

116

117

118

119

122

123

124

125

126

127

128

129

130

59 61 71 92 104 113 120

62 93 103 121

132

100

3 8

131

101

102

VCC

GND GND

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

VCC

ADDR0

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

~RAMSLCT

~PERIPHSLCT

R/~W

~STROBE

~WRITEENBL

DATA12

DATA13

DATA14

DATA15

GND

GND GND GND GND GND GND GND

VCC

VCC VCC VCC VCC

CLOCKIN

VCC

~RESET

VCC

GND

~RS

W/~R

POSLIM1

NEGLIM1

AXISOUT1

PWMMAG1

PWMSIGN1

AXISIN1

~HOSTINTRPT

SRLRCV

SRLXMT

I/OINTRPT

SRLENABLE

ANALOG1

ANALOG2

ANALOG3

ANALOG4

ANALOG5

ANALOG6

ANALOG7

ANALOG8

ANALOGVCC

ANALOGREFHIGH

ANALOGREFLOW

ANALOGGND

GND GND

GND

N/C

QUADA1

~INDEX1

~HOME1

QUADB1

VCC

PWMMAG2

PWMMAG3

PWMSIGN2

HALL1A

HALL1B

HALL1C

PRLENABLE

SYNCH

Электронный компонент: MC3410

Document Outline