PLCDA03
thru
PLCDA24
1
05076.R 7 4/05
www.protekdevices.com
ULTRA LOW CAPACITANCE TVS ARRAY
Only One Name Means ProTek'TionTM
APPLICATIONS
Ethernet - 10/100 Base T
FireWire, SCSI & USB
Audio/Video Inputs
xDSL Interfaces
Cellular Phone Terminals
IEC COMPATIBILITY (EN61000-4)
61000-4-2 (ESD): Air - 15kV, Contact - 8kV
61000-4-4 (EFT): 40A - 5/50ns
61000-4-5 (Surge): 24A, 8/20s - Level 2(Line-Gnd) & Level 3(Line-Line)
FEATURES
500 Watts Peak Pulse Power per Line (tp=8/20s)
Bidirectional Configuration
Available in Multiple Voltage Types Ranging From 3V to 24V
Protects Two (2) Lines
ESD Protection > 40 kilovolts
ULTRA LOW CAPACITANCE: 5pF
RoHS Compliant in Lead-Free Versions
MECHANICAL CHARACTERISTICS
Molded JEDEC SO-8 Package
Weight 70 milligrams (Approximate)
Available in Tin-Lead or Lead-Free Pure-Tin Plating(Annealed)
Solder Reflow Temperature:
Tin-Lead - Sn/Pb, 85/15: 240-245C
Pure-Tin - Sn, 100: 260-270C
Flammability Rating UL 94V-0
12mm Tape and Reel Per EIA Standard 481
Marking: Logo, Marking Code, Date Code & Pin One Defined By Dot on Top of Package
05076
PIN CONFIGURATION
SO-8
1
2
4
8
3
5
6
7
2
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DEVICE CHARACTERISTICS
0.1 1 10 100 1,000 10,000
t
d
- Pulse Duration - s
500W 8/20s Waveform
10
100
1,000
10,000
P
PP
- Peak Pulse Power - Watts
FIGURE 1
PEAK PULSE POWER VS PULSE TIME
MAXIMUM RATINGS @ 25C Unless Otherwise Specified
Operating Temperature
SYMBOL
VALUE
-55C to 150C
C
C
-55C to 150C
UNITS
T
J
T
STG
PARAMETER
Storage Temperature
Peak Pulse Power (t
p
= 8/20s) - See Figure 1
P
PP
500
Watts
Note 1: Devices are designed to be used in parallel (See Circuit Diagram). For other applications, contact the factory. Do not apply surge in the
"forward" direction of the TVS.
Note 1: Do not surge from pins 8 to 1, 2 to 7, 6 to 3 and 4 to 5. PIV typically greater than 100V for each rectifier die. Electrical characteristics apply
to pins 1 to 8, 7 to 2, 3 to 6 and 5 to 4.
ELECTRICAL CHARACTERISTICS PER LINE @ 25C Unless Otherwise Specified
PART
NUMBER
(See Note 1)
DEVICE
MARKING
MINIMUM
BREAKDOWN
VOLTAGE
@ 1mA
V
(BR)
VOLTS
MAXIMUM
CLAMPING
VOLTAGE
(See Fig. 2)
@ I
P
= 1A
V
C
VOLTS
MAXIMUM
CLAMPING
VOLTAGE
(See Fig. 2)
@8/20s
V
C
@ I
PP
MAXIMUM
CAPACITANCE
(See Note 2)
@0V, 1 MHz
C
pF
PLCDA03
PLCDA05
PLCDA08
PLCDA12
PLCDA15
PLCDA24
SGA
SGB
SGF
SGC
SGD
SGE
4.5
6.0
8.5
13.3
16.7
26.7
7.0
9.8
13.4
19.0
24.0
43.0
10.9V @ 43.0A
13.5V @ 42.0A
16.0V @ 34.0A
25.9V @ 21.0A
30.0V @ 17.0A
49.0V @ 12.0A
5
5
5
5
5
5
MAXIMUM
LEAKAGE
CURRENT
@V
WM
I
D
A
125
20
10
1
1
1
RATED
STAND-OFF
VOLTAGE
V
WM
VOLTS
3.3
5.0
8.0
12.0
15.0
24.0
0 5 10 15 20 25 30
t - Time - s
0
20
40
60
80
100
120
I
PP
- Peak Pulse Current - % of I
PP
TEST
WAVEFORM
PARAMETERS
t
f
= 8s
t
d
= 20s
t
f
Peak Value I
PP
e
-t
t
d
= t
I
PP
/2
FIGURE 2
PULSE WAVE FORM
3
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GRAPHS
0 25 50 75 100 125 150
T
L
- Lead Temperature - C
20
40
60
80
100
% Of Rated Power
Peak Pulse Power
8/20s
Average Power
FIGURE 3
POWER DERATING CURVE
0
FIGURE 4
OVERSHOOT & CLAMPING VOLTAGE FOR PLCDA05
ESD Test Pulse: 25 kilovolt, 1/30ns (waveshape)
5 Volts per Division
0
10
20
30
40
FIGURE 7
RETURN LOSS - PLCDA05
100 MHz per Division
10 db per Division
-50 db
-20 db
Ref 0 db
20 db
FIGURE 6
INSERTION LOSS - PLCDA05
100 MHz per Division
10 db per Division
-50 db
-20 db
Ref 0 db
20 db
0 2 4 6 8 10 12
I
PP
- Peak Pulse Current - Amps
V
C
- Clamping Voltage - Volts
0
10
20
30
FIGURE 5
TYPICAL CLAMPING VOLTAGE VS PEAK PULSE CURRENT FOR PLCDA15
4
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APPLICATION NOTE
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Circuit board layout is critical for Electromagnetic
Compatibility (EMC) protection. The following
guidelines are recommended:
The protection device should be placed near the
input terminals or connectors, the device will
divert the transient current immediately before it
can be coupled into the nearby traces.
The path length between the TVS device and
the protected line should be minimized.
All conductive loops including power and ground
loops should be minimized.
The transient current return path to ground
should be kept as short as possible to reduce
parasitic inductance.
Ground planes should be used whenever
possible. For multilayer PCBs, use ground vias.
The PLCDA Series are low capacitance, bidirectional TVS arrays that are designed to protect I/O or high speed data lines from the damaging effects
of ESD or EFT. This product series has a surge capability of 500 Watts P
PP
per line for an 8/20s waveshape and offers ESD protection > 40kv.
BIDIRECTIONAL COMMON-MODE CONFIGURATION (Figure 1)
Ideal for use in USB applications, the PLCDA Series provides up to two (2) lines of protection in a common-mode configuration as depicted in Figure 1.
Circuit connectivity is as follows:
Pins 1 & 2 and 3 & 4 are connected to Ground
Pins 5 and 6 are connected to I/O Line D+
Pins 7 and 8 are connected to I/O Line D-
Figure 1. Typical Common-Mode USB Protection
Circuit
1
2
3
4
5
6
7
8
D+
D-
GND
USB
IC
5
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PACKAGE OUTLINE & DIMENSIONS
TAPE & REEL/BULK ORDERING NOMENCLATURE
1. Surface mount product is taped and reeled in accordance
with EIA-481.
2. Suffix-T7 = 7 Inch Reel - 1,000 pieces per 12mm tape,
i.e.,
PLCDA05-T7.
3. Suffix-T13 = 13 Inch Reel - 2,500 pieces per 12mm tape,
i.e.,
PLCDA05-T13.
4. Suffix - LF = Lead-Free, Pure-Tin Plating,
i.e.,
PLCDA05-LF-T7.
5. No Suffix = Product Shipped in Tubes of 98 pcs per Tube.
A
B
C
D
F
G
J
K
P
R
4.80
3.80
1.35
0.35
0.40
1.27 BSC
0.18
0.10
5.80
0.25
5.00
4.00
1.75
0.49
1.250
1.27 BSC
0.25
0.25
6.20
0.50
0.189
0.150
0.054
0.014
0.016
0.05 BSC
0.007
0.004
0.229
0.010
0.196
0.157
0.068
0.019
0.049
0.05 BSC
0.009
0.008
0.244
0.019
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
PACKAGE DIMENSIONS
NOTES
1. - T - = Seating Plane and Datum Surface.
2. Dimensions "A" and "B" are Datum.
3. Dimensions "A" and "B" do not include mold protrusion.
4. Maximum mold protrusion is 0.015" (0.380 mm) per side.
5. Dimensioning and tolerances per ANSI Y14.5M, 1982.
6. Dimensions are exclusive of mold flash and metal burrs.
-A-
8
5
1
4
-B - P
G
D
-T-
C
K
J
R x 45
0 - 10
F
4 PL
0.010 (0.25 MM) M
M
B
+
8 PL
0.010 (0.25 MM) M
S
B
+
S
A
T
PACKAGE OUTLINE
SO-8
0.050 0.005
0.030 0.005
0.245 MIN
0.160 0.005
0.045 0.005
MOUNTING PAD
Outline & Dimensions: Rev 1 - 11/01, 06009
COPYRIGHT ProTek Devices 2005
SPECIFICATIONS: ProTek reserves the right to change the electrical and or mechanical characteristics described herein without notice (except JEDEC).
DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and
specifications is the buyer's and that in furnishing engineering and technical assistance, ProTek assumes no responsibility with respect to the selection or
specifications of such products.
ProTek Devices
2929 South Fair Lane, Tempe, AZ 85282
Tel: 602-431-8101 Fax: 602-431-2288
E-Mail:
sales@protekdevices.com
Web Site:
www.protekdevices.com
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