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Электронный компонент: P4C1024L-70SI

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151
P4C1024L
P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
Means Quality, Service and Speed
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (
CE
1
low and
CE
2
high) and output enabling (
OE
) while write enable
(
WE
) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
The P4C1024L is packaged in a 32-pin 445 mil SOP
as well as a 600 mil PDIP.
The P4C1024L is a 1,048,576-bit low power CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V
10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS
is utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
--32-Pin 600 mil DIP
--32-Pin 445 mil SOP
V
CC
Current (Commercial/Industrial)
-- Operating: 70mA/85mA
-- CMOS Standby: 100
A/100
A
Access Times
--55/70 (Commercial or Industrial)
Single 5 Volts
10% Power Supply
Easy Memory Expansion Using CE
1,
CE
2
and
OE Inputs
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1Q97
INPUT
DATA
CONTROL
262,144-
BIT
MEMORY
ARRAY
COLUMN
I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
CE
1






ROW SELECT
A
A

A
A
(8)
(9)
CE2
OE
CONTROL
CIRCUIT
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
GND
WE
A11
OE
I/O7
I/O6
I/O5
NC
A13
VCC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
15
16
17
18
I/O3
I/O4
CE
1
A9
A8
CE2
A15
DIP (P600), SOP (S12)
TOP VIEW
152
P4C1024L
GND
V
IN
V
CC
Ind'l.
Com'l.
I
LO
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Temperature Range (Ambient)
Supply Voltage
4.5V
V
CC
5.5V
Industrial (-40
C to 85
C)
4.5
V
CC
5.5V
Commercial (0
C to 70
C)
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage with Respect to GND
-0.5
7.0
V
V
TERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
V
CC
+ 0.5
V
T
A
Operating Ambient Temperature
-55
125
C
S
TG
-65
150
C
I
OUT
Output Current into Low Outputs
25
mA
I
LAT
Latch-up Current
>200
mA
Storage Temperature
Symbol
Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
SB
I
SB1
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
V
CC
Current
TTL Standby Current
(TTL Input Levels)
Output Leakage Current
Input Leakage Current
I
OH
= 1mA, V
CC
= 4.5V
I
OL
= 2.1mA
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
V
CC
-0.2V, CE
2
0.2V
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
= V
IH
or CE
2
= V
IL
GND
V
OUT
V
CC
Ind'l.
CE
1
V
IH
or CE
2
V
IL
Com'l.
Test Conditions
Min
Max
Unit
2.4
2.2
-0.5
-5
-2
-5
-2
V
V
V
V
A
A
mA
A
0.4
V
CC
+ 0.3
0.8
+5
+2
+5
+2
3
100
153
P4C1024L
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE
2
V
IH
(min),
CE
1
and
WE
V
IL
(max),
OE
is high. Switching
inputs are 0V and 3V.
**As above but @ f=1 MHz and V
IL
/ V
IH
= 0V/ V
CC
.
CAPACITANCES
(V
CC
= 5.0V, T
A
= 25
C, f = 1.0 MHz)
POWER DISSIPATION CHARACTERISTICS VS. SPEED
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
Test Conditions
Max
Unit
C
IN
C
OUT
Input Capacitance
Output Capacitance
V
IN
= 0V
V
OUT
= 0V
7
9
pF
pF
Symbol
Parameter
-55
-70
Unit
I
CC
Dynamic Operating Current
Commercial
Industrial
70
85
70
85
15
25
15
25
mA
mA
-55
-70
Temperature
Range
Symbol
Parameter
-55
Min
Max
-70
Min
Max
Unit
t
RC
55
ns
t
AA
Address Access Time
55
70
ns
t
AC
Chip Enable Access
Time
55
70
ns
t
OH
Output Hold from
Address Change
5
5
ns
t
LZ
Chip Enable to
Output in Low Z
10
10
ns
t
HZ
Chip Disable to
Output in High Z
20
25
ns
t
OE
Output Enable Low
to Data Valid
30
35
ns
t
OLZ
Output Enable Low
to Low Z
5
5
ns
t
OHZ
Output Enable High
to High Z
20
25
ns
t
PU
Chip Enable to
Power Up Time
0
0
ns
t
PD
Chip Disable to
Power Down Time
55
70
ns
Read Cycle Time
70
*
**
154
P4C1024L
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
1
and
OE
is LOW, and CE
2
is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
1
transition LOW or CE
2
transition HIGH.
READ CYCLE NO. 1 (
OE
OE
OE
OE
OE
CONTROLLED)
(1)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CE
CE
CE
CE
CE
CONTROLLED)
ADDRESS
OE
tRC
(5)
DATA OUT
tOH
CE
tOLZ
tAC
tLZ
tOHZ
tHZ
CE2
tAA
tOE
4. Transition is measured
200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
tAC
CE
1
DATA OUT
tRC
tLZ
DATA VALID
ICC
ISB
tPU
HIGH IMPEDANCE
tPD
tHZ
CURRENT
VCC SUPPLY
CE
2
tAA
ADDRESS
DATA OUT
tRC
tOH
DATA VALID
PREVIOUS DATA VALID
(5)
155
P4C1024L
-55
Notes:
6.
CE
1
and
WE
are LOW and CE
2
is HIGH for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show twz and tow.
8. If
CE
1
goes HIGH or CE
2
goes LOW simultaneously with
WE
HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED)
(6)
Symbol
Parameter
Max
-70
Max
Unit
Min
Min
t
WC
t
CW
t
AS
t
WP
t
AH
t
DH
t
WZ
t
OW
Write Cycle Time
55
70
ns
Chip Enable Time
to End of Write
50
60
ns
Address Valid to
End of Write
50
60
ns
Address Set-up
Time
0
0
ns
Write Pulse Width
40
50
ns
Address Hold
Time
0
0
ns
Data Valid to End
of Write
25
30
ns
Data Hold Time
0
0
ns
Write Enable to
Output in High Z
25
30
ns
Output Active from
End of Write
5
5
ns
t
AW
t
DW
ADDRESS
CE
1
tWC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
DATA UNDEFINED
(9)
(4)
t
CW
tAW
tWP
tDW
tAH
tDH
tOW
tAS
tWZ
(4,7)
(7)
CE
2