ChipFind - документация

Электронный компонент:

Скачать:  PDF   ZIP
P4C116
47
P4C116
ULTRA HIGH SPEED 2K x 8
STATIC CMOS RAMS
DESCRIPTION
The P4C116 is a 16,384-bit ultra high-speed static RAMs
organized as 2K x 8. The CMOS memories require no
clocks or refreshing and have equal access and cycle
times. Inputs are fully TTL-compatible. The RAMs oper-
ate from a single 5V
10% tolerance power supply. Cur-
rent drain is typically 10
A from a 2.0V supply.
Access times as fast as 10 nanoseconds are available,
Means Quality, Service and Speed
1Q97
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 633
mW active, 193 mW standby.
The P4C116 is available in 24-pin 300 mil DIP, SOJ and
SOIC packages providing excellent board level densities.
The P4C116 is also available in 24-pin rectangular and
28-pin square LCC packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
A
OE
INPUT
DATA
CONTROL
ROW
SELECT
16,384-BIT
MEMORY
ARRAY
COLUMN I/O
A
A
A
I/O
1
I/O
8
COLUMN
SELECT
WE
CE
(6)
(5)
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
10/12/15/20/25/35 ns (Commercial)
15/20/25/35 ns (Military)
Low Power Operation
633/715 mW Active -- 15, 20
550/633 mW Active -- 25, 35
193/220 mW Standby (TTL Input)
Output Enable Control Function
Single 5V
10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Produced with PACE II Technology
TM
Standard Pinout (JEDEC Approved)
24-Pin 300 mil DIP, SOIC, SOJ
24-Pin Rectangular LCC (300 x 400 mils)
28-Pin Square LCC (450 x 450 mils)
See Selection Guide Page for LCC
A8
A4
A0
A1
A2
A3
A5
A6
A10
A9
VCC
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
DIP (P4 , D4), SOJ (J3 ), SOIC (S4 )
TOP VIEW
10
15
11
14
12
13
GND
A7
WE
OE
CE
I/O1
I/O2
I/O3
I/O8
I/O7
I/O6
I/O5
I/O4
DIP (P4, D4), SOJ (J4), SOIC (S4)
TOP VIEW
P4C116
48
CE
V
IH
, V
CC
= Max., f = Max., Outputs Open
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
Symbol
Parameter
Conditions Typ. Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Output Capacitance V
OUT
= 0V
7
pF
Grade
(2)
Ambient Temp
Gnd
Vcc
Commercial
0
C to 70
C
0V 5.0V
10%
RECOMMENDED OPERATING CONDITIONS
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25
C, f = 1.0MHz)
Symbol
V
IH
V
IL
V
HC
V
CD
V
OL
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
V
CC
= Min., I
IN
= 18 mA
I
OL
= +8 mA, V
CC
= Min.
Test Conditions
P4C116
Min
Max
2.2
0.5
(3)
V
CC
0.2
0.5
(3)
V
CC
+0.5
0.8
V
CC
+0.5
0.2
1.2
0.4
Unit
V
V
V
V
V
V
V
LC
V
OH
Output High Voltage
(TTL Load)
I
OH
= 4 mA, V
CC
= Min.
2.4
V
5
+5
A
CE
V
HC
, V
CC
= Max., f = 0, Outputs Open
V
IN
V
LC
or V
IN
V
HC
___
I
LI
Input Leakage Current
V
CC
= Max., V
IN
= GND to V
CC
I
LO
Output Leakage Current
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
5
+5
A
I
CC
Dynamic Operating
Current 10, 12
V
CC
= Max., f = Max., Outputs Open
130
mA
I
CC
Dynamic Operating
Current 15, 20
V
CC
= Max., f = Max., Outputs Open
___
115
mA
I
CC
Dynamic Operating
Current 25, 35
V
CC
= Max., f = Max., Outputs Open
___
100
mA
I
SB
Standby Power Supply
Current (TTL Input Levels)
___
35
mA
I
SBI
Standby Power Supply
Current (CMOS Input Levels)
17
mA
P4C116
49
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than 3.0V and
100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition
LOW.
8. Transition is measured
200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
OLZ
ADDRESS
OE
t
RC
DATA OUT
(9)
t
AA
t
OE
t
OH
CE
t
LZ
t
AC
t
HZ
t
OHZ
t
(8)
(8)
(8)
(8)
TIMING WAVEFORM OF READ CYCLE NO. 1 (
OE
OE
OE
OE
OE
CONTROLLED)
(5)
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Output Enable Low to Data Valid
Chip Enable to Power Up Time
Chip Disable to Power Down
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Low Z
Output Enable High to High Z
10
Min Max
12
Min Max
15
Min Max
20
Min Max
25
Min Max
35
Min Max
Unit
15
15
15
2
2
7
10
0
8
0
15
20
2
2
0
0
20
20
8
10
9
20
25
2
3
0
0
25
25
10
15
12
20
35
2
3
0
0
35
35
15
20
15
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
2
2
0
0
10
10
5
10
12
2
2
0
0
12
12
6
12
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
I
CC
Symbol
Parameter
Temperature
Range
Dynamic Operating Current*
Commercial
Military
10
N/A
12
20
25
35
Unit
mA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A
170
160
155
150
180
170
160
155
150
140
15
6
7
8
6
P4C116
50
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALID
PREVIOUS DATA VALID
(9)
RC
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)
(5,7)
DATA VALID
t
CE
DATA OUT
AC
t
RC
t
LZ
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
(8)
(8)
t
HZ
SUPPLY
CC
CURRENT
V
P4C116
51
AC CHARACTERISTICS--WRITE CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED)
(10,11)
ADDRESS
CE
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
DATA UNDEFINED
(13)
(8)
t
CW
t
AW
t
WP
t
DW
t
WR
t
AH
t
DH
t
OW
t
AS
t
WZ
(8,12)
(12)
t
t
WE
ADDRESS
CE
DATA IN
t
WC
DATA VALID
(13)
t
AS
t
CW
t
AW
t
WP
DW
AH
WR
t
DH
t
DATA OUT
HIGH IMPEDANCE
(11)
Notes:
10.
CE
and
WE
must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
12. If CE goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
t
WC
Sym.
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
10
12
15
20
25
35
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
15
12
12
0
12
0
10
0
0
8
20
15
15
0
15
0
12
0
0
10
25
18
18
0
18
0
15
0
0
15
35
25
25
0
20
0
20
0
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CE
CE
CE
CE
CONTROLLED)
(10)
10
8
8
0
8
0
7
0
0
6
12
10
10
0
10
0
8
0
0
7