7
P93U422
FEATURES
Universal 256 x 4 Static RAM
One part, the 93U422, replaces the following
bipolar and CMOS parts:
93422A
93422
93L422A
93L422
Fast Access Time
35 ns (Commercial)
35 ns (Military)
Standard 400 mil DIP and Chip carrier packages
DESCRIPTION
The P93U422 is a 1,024-bit high-speed Static RAM with
a 256 x 4 organization. The P93U422 is a universal
device designed to replace the entire 93 and 93L 256 x 4
static RAM families. The memory requires no clocks or
refreshing and has equal access and cycle times. Inputs
and outputs are fully TTL compatible. Operation is from a
single 5 Volt supply. Easy memory expansion is provided
by an active LOW chip select one (
CS
1
) and active HIGH
P93U422
HIGH SPEED 256 x 4
STATIC CMOS RAM
Means Quality, Service and Speed
1Q97
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS
CMOS for Low Power
440 mW (Commercial)
495 mW (Military)
5V Power Supply
10% for both commercial
and military temperature ranges
Separate I/O
Fully static operation with equal access and
cycle times
Resistant to single event upset and latchup due
to advanced process and design improvements
chip select two (CS
2
) as well as 3-state outputs.
In addition to high performance, the device features
latch-up protection, single event and upset protection.
The P93U422 is offered in several packages: 22-pin 400
mil DIP (plastic and ceramic), 24-pin 300 mil SOIC, 24-
pin LCC and 24-pin CERPACK. Devices are offered in
both commercial and military temperature ranges.
21
17
20
19
18
16
4
5
6
7
8
9
3
1
2
24
23
22
15
14
13
12
11
10
A1 A2 A3
A4
VCC
A
0
A5
A6
A7
GND
NC
D0
D1
D2
O1
O0
CS2
D3
O3
INDEX
WE
O2
CS1
OE
NC
COLUMN
DECODER
SENSE AMPS
32 X 32
ARRAY
CS
1
CS
2
WE
OE
O
0
O
1
O
2
O
3
A
5
A
6
A
7
A
2
A
3
A
4
A
1
A
0
D
1
D
2
D
3
D
0
DATA INPUT
CONTROL
ROW
DECODER
1
2
3
4
5
6
7
8
9
10
11
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
A5
GND
A3
A2
A1
A0
A6
A7
D0
O0
D1
WE
CS2
O3
VCC
OE
D3
O2
D2
O1
A4
CS
1
1
2
3
4
5
6
7
8
9
10
11
A5
GND
A3
A2
A1
A0
A6
A7
D0
O0
D1
WE
CS2
O3
VCC
OE
D3
O2
D2
O1
A4
CS
1
12
22
21
20
19
18
17
16
15
14
13
23
24
NC
NC
SOIC (S4)
TOP VIEW
DIP (P3-1, D3-1)
TOP VIEW
LCC (L4)
TOP VIEW
8
P93U422
T
A
= 125C
T
A
= 0C
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability
Symbol
Parameter
Conditions Typ. Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Output Capacitance V
OUT
= 0V
7
pF
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25
C, f = 1.0MHz)
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
20
mA
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. For test purposes, not more than one output at a time should be shorted.
Short circuit test duration should not exceed 30 seconds.
4. This parameter is sampled and not 100% tested.
Grade
(2)
Commercial
Military
Ambient Temp
0C to 70C
55C to 125C
Gnd
0V
Vcc
5.0V
10%
5.0V
10%
0V
Symbol
V
OH
V
OL
V
IH
V
IL
I
IL
I
IH
I
SC
Parameter
Output High Voltage
Output Low Voltage
Input High Level
Input Low Level
Input Low Current
Input High Current
Output Short Circuit Current
(3)
Test Conditions
V
CC
= Min., V
IN
= V
IH
or V
IL
, I
OH
= 5.2 mA
V
CC
= Min., V
IN
= V
IH
or V
IL
, I
OL
= 8.0 mA
V
IN
= 0.40 V
V
CC
= Max, V
IN
= 4.5V
V
CC
= Max., V
OUT
= 0.0V
I
CEX
Output Leakage Current
V
CL
Input Clamp Voltage
I
IN
= 10mA
V
OUT
= 2.4V, V
CC
= Max.
T
A
= 75C
T
A
= 55C
P93U422
Min.
2.4
2.1
Max.
0.45
0.8
300
40
70
70
70
80
90
1.5
Unit
V
V
V
V
A
A
mA
mA
V
Power Supply Current
50
50
A
All Inputs = GND
V
CC
= Max.
I
CC
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
V
OUT
= 0.5V, V
CC
= Max.
9
P93U422
t
S
(DI)
t
PLZ
(
WE
)
(8)
t
PHZ
(
WE
)
(8)
TRUTH TABLE
recovery times by eliminating the "write recovery glitch."
Reading is performed with chip selct one (
CS
1
) LOW, chip
select two (CS
2
) HIGH, write enable (
WE
) HIGH and
output enable (
OE
) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O
0
through O
3
). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(
CS
1
) is HIGH, or during the write operation when write
enable (
WE
) is LOW.
An active LOW write enable (
WE
) controls the writing/
reading operation of the memory. When chip select one
(
CS
1
) and write enable (
WE
) are LOW and chip select
two (CS
2
) is HIGH, the information on data inputs (D
0
through D
3
) is written into the addressed memory word
and preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
FUNCTIONAL DESCRIPTION
SWITCHING CHARACTERISTICS (5,6)
Over Operating Range (Commercial and Military)
Mode
CS
2
CS
CS
CS
CS
CS
1
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Output
Standby
L
X
X
X
High Z
Standby
X
H
X
X
High Z
D
OUT
Disabled
H
L
X
H
High Z
Read
H
L
H
L
D
OUT
Write
H
L
L
X
High Z
Notes:
H = HIGH
L = Low
X = Don't Care
HIGH Z = Implies outputs are disabled or off. This
condition is defined as high impedance state
for the P93U422.
Unit
ns
Parameters
t
PLH(A)
(7)
t
PLH(A)
(7)
t
PZH
(
CS
1,
CS
2
)
(8)
t
PZL
(
CS
1,
CS
2
)
(8)
t
PZH
(
WE
)
(8)
t
PZL
(
WE
)
(8)
t
PZH
(
OE
)
(8)
t
PZL
(
OE
)
(8)
t
S
(A)
t
h
(DI)
t
S
(
CS
1,
CS
2
)
t
h
(
CS
1,
CS
2
)
t
pw
(
WE
)
t
PHZ
(
CS
1,
CS
2
)
(8)
t
PLZ
(
CS
1,
CS
2
)
(8)
t
PHZ
(
OE
)
(8)
t
PLZ
(
OE
)
(8)
Description
Delay from Address to Output (Address Access Time) (See Fig. 2)
Delay from Chip Select to Active Output and Correct Data (See Fig. 2)
Delay from Write Enable to Active Output and Correct Data (Write Recovery)
(See Fig. 1)
Delay from Output Enable to Active Output and Correct Data (See Fig. 2)
Setup Time Address (Prior to Initiation of Write) (See Fig. 1)
Hold Time Address (After Termination of Write) (See Fig. 1)
Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1)
Hold Time Data Input (After Termination of Write) (See Fig. 1)
Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1)
Hold Time Chip Select (After Termination of Write) (See Fig. 1)
Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1)
Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2)
Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1)
Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2)
P93U422
5
5
5
5
5
5
20
Max.
Min.
35
25
25
25
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
h
(A)
10
P93U422
Notes:
5) Test conditions assume signal transition times of 10 ns or less.
6) Extended temperature operation guaranteed with 400 linear feet per minute of air flow.
7) t
PLH
(A)
and t
PHL
(A)
are tested with S
1
closed and C
L
= 15 pF with both input and output timing referenced to 1.5V
8) t
PZH
(
WE
), t
PZH
(
CS
1
, CS
2
) and t
PZH
(
OE
) are measured with S
1
open, C
L
= 15 pF and with both the input and output timing
referenced to 1.5V. t
PZL
(
WE
), t
PZL
(
CS
1
, CS
2
) and t
PZL
(
OE
) are measured with S
1
closed, C
L
= 15pF and with both the input and
output timing referenced to 1.5V.
t
PHZ
(
WE
), t
PHZ
(
CS
1
, CS
2
) and t
PHZ
(
OE
) are measured with S
1
open, C
L
< 5pF and are measured between the 1.5V level
on the input to the V
OH
-500mV level on the output.
t
PLZ
(
WE
), t
PLZ
(
CS
1
, CS
2
) and t
PLZ
(
OE
) are measured with S
1
closed, C
L
< 5pF and are measured between the 1.5V level
on the input to the V
OL
+500mV level on the output.
11
P93U422
CHIP
SELECT
12
P93U422
SELECTION GUIDE
The P93U422 is available in the following temperature range, speed, and package options.
Temperature
Range
Package
Speed (ns)
CERDIP
LCC
CERDIP
LCC
35
Commercial
Temperature
Plastic DIP
Plastic SOIC
Military Pro-
cessed*
Military
Temperature
-35PC
-35SC
-35DM
-35LM
-35DMB
-35LMB
ORDERING INFORMATION
*Military temperature range with MIL-STD-883, Class B processing.
Device Type
Package
Processing
P93U422
x
x
xx
Speed
35 ns Commercial
35 ns Military
256 x 4 SRAM
C 0
C to +70
C
M 55
C to +125
C
MB MIL-STD-883, Class B
D CERDIP (400 mil)
L Ceramic LCC (400 mil square)
P Plastic DIP (400 mil)
S Plastic SOIC (300 mil)
F CERPACK
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