57490-580-00 A

FibreFIT490

Features

Compliant with the following Fibre Channel (FC)
technology:

Third Generation Fibre Channel Physical and
Signaling Interface (FC-PH-3) Rev. 9.4

Fibre Channel-Arbitrated Loop-2 (FC-AL-2)
Rev. 7

Fibre Channel-Fabric Loop Attachment
Technical Report (FC-FLA) Rev. 2.7

Fibre Channel Backbone (FC-BB) Rev. 4.6

Fibre Channel-Methodologies for
Interconnects (FC-MI) Rev. 0.2

Fibre Channel-Generic Services-3 (FC-GS-3)
Rev. 6.4

Embedded microcontroller to automate Fibre
Channel operations

200 MB/sec, full-duplex Fibre Channel data
transfer rate

On-chip 8B/10B encode and decode

On-chip 1 and 2 Gbit serial transceivers

32 on-chip, full-frame buffers

Data protection with frame buffer CRC checking on
transmit and receive

Two 32-bit, unidirectional DMA busses supporting
transfers greater than 266 MB/sec each

Microprocessor interface support for Intel and
Motorola processors

Product Description

The FibreFIT490 is part of the QLogic family of

high-performance, low-cost, single-chip Fibre Channel
controllers. The FibreFIT product provides an efficient,
easy to use Fibre Channel port to makers of bridge/router
products. The FibreFIT490 supports both loop and
point-to-point topology. One major concern with any
network is the gathering of statistics and error information.
The FibreFIT490 contains several counters that log specific
events. This information can be processed by external
firmware to meet many different reporting and/or recovery
schemes. The FibreFIT490 block diagram is shown in
figure 1.

INTERNAL

MICROCONTROLLER

FibreFIT FABRIC INTERFACE CONTROLLER

PROGRAM MEMORY

(SRAM)

MICROPROCESSOR

INTERFACE

EXTERNAL

FIBRE CHANNEL LOOP OR

POINT-TO-POINT

INTERAL

1 AND 2 Gbit

TRANSCEIVERS

INTERNAL FRAME CONTROLLER

TX FRAME

CONTROLLER

DMA

CONTROLLER

EXTERNAL DMA

DEVICE/POS-PSY

MICROPROCESSOR

FIBRE CHANNEL

CONTROLLER

TRANSLATED LOOP

TABLE

RX FRAME

CONTROLLER

INTERNAL FRAME CONTROLLER

Figure 1. FibreFIT490 Block Diagram

QLogic Corporation

FibreFIT490 Fibre Channel Controller

Data Sheet

FibreFIT490

57490-580-00 A

QLogic Corporation

Product Architecture

Fibre Channel Controller

The Fibre Channel controller supports the following:

Fibre Channel data rates of 106.25 MB/sec and
212.25 MB/sec

Embedded 1 and 2 Gbit copper transceivers

Full duplex frame transmit and receive

Point-to-point operation

Arbitrated loop operation

Nonzero login credit

Class F frame priority support

Full frame pass-through mode (transmit and
receive)

CRC checking and generation

The Fibre Channel controller implements the FC-AL-2

protocol, including the FC-1 and FC-2 layers of the
signaling interface. The FC-0 layer is implemented by
internal serial link transmitter and receiver modules that
connect to the Fibre Channel controller through two 10-bit
interfaces.

The Fibre Channel controller includes an 8B/10B

encoder and decoder, an elasticity buffer for clock skew
management, and an FC-AL state machine.

The Fibre Channel controller transmits and receives at

the full Fibre Channel rate of 212.5 MB/sec with
full-duplex transfers.

As specified in the FC-AL protocol, the Fibre Channel

controller uses the alternate buffer-to-buffer credit model
to pace frames. The Fibre Channel controller receive path
validates frames received from the Fibre Channel based on
user-configurable criteria. The transmit path transmits
frames from the external DMA device to the Fibre Channel.
The Fibre Channel controller automatically handles frame
delimiters and frame control.

Microcontroller

The FibreFIT490 microcontroller supports the

following:

30 MIPS minimum (two-clock instruction cycle
except for branch)

64 single-word instructions

16-bit wide instructions

Eight-bit wide data path

4K instruction locations

32 general purpose registers

64 dual-port mailboxes

Five-level deep hardware stack

Direct, indirect, absolute, and immediate
addressing modes

Two hardware interrupts, one with four-bit
auto-interrupt vectors and status

Full chip access through the microprocessor bus

The microcontroller allows users to automate the

FC-AL protocol. The microcontroller's Harvard
architecture improves performance and flexibility by
separating instruction and data memory. Its pipelined
architecture overlaps instruction fetch and result storage
with instruction decode and execution cycles to provide
two-clock instruction execution and four-clock branch
execution. The microcontroller supports direct, indirect,
absolute, and immediate addressing modes. The
microcontroller has a 16-byte register file, 32 mailbox
registers, a five-level deep stack, an integer ALU, and other
special purpose registers. The microcontroller has access
to its internal registers, the FC-AL command FIFO, the
internal frame buffers, and all registers within the
FibreFIT490. This access provides flexibility in
automating the FibreFIT490 to respond to received frames.

The microcontroller supports two types of interrupt

schemes: firmware and hardware. The firmware interrupt
scheme allows an external microprocessor to initiate an
operation within the microcontroller without stopping the
microcontroller's current operation. The firmware
interrupt vector can be modified by the microprocessor
while a microcontroller program is running. Hardware
interrupts come directly from the Fibre Channel module.
The microcontroller can be configured either to deliver
these interrupts to the microprocessor or to intercept these
interrupts and act on them as part of command automation.

DMA Interface Controller

The FibreFIT490 DMA interface controller (DMA

controller) supports the following:

Packet over SONET-physical layer (POS-PHYTM)
Level 3 32-bit support

16 transmit and 16 receive full-frame buffers

Two 32-bit, unidirectional data busses running at
greater than 266.67 MB/sec each

Data protection with 32-bit buffer CRC checking
on each channel

Indication of priority frame reception

The DMA controller is an intelligent, high-speed

interface controller. It provides an interface between the
Fibre Channel controller and the external bus. Users select
either a generic DMA bus or the POS-PHY Level 3
interface at power-up reset. The DMA controller also
provides multichannel access to or from 32 internal
full-frame buffers. Frames received for transmission on the
outbound fibre are placed into one of the transmit buffers.
Each frame is tracked by the AL_PA, and in-order delivery
is guaranteed. Frames received from the inbound fibre are
placed in one of the receive buffers. Each frame is delivered
to the external interface in the order it was received.
Optionally, up to four transmit buffers can be allocated to

57490-580-00 A

FibreFIT490

QLogic Corporation

the microcontroller for additional code storage. Additional
buffers can also be allocated to the microcontroller for
storing temporary variables.

Microprocessor Interface

The FibreFIT490 samples the configuration pins during

power-up reset to configure the microprocessor operating
mode.

The FibreFIT490 connects to a microprocessor as

follows:

Multiplexed and nonmultiplexed address/data:
11-bit address bus and 16-bit data bus

Programmable byte ordering: big endian and little
endian

Support for numerous microprocessors, including:

Intel 80186, 80188, 80196

Motorola 68000, 68300, 68020, 68008,
MPC8240

The flexible FibreFIT490 microprocessor interface can

be configured for processors that support a ready signal.
Alternately, the microprocessor interface can be configured
in a fixed-timing mode for processors that do not support
a ready signal. In fixed timing mode, performance-critical
register access is accomplished in 50 ns.

Электронный компонент: FibreFIT490