83140-580-02 B
ISP1040C
1
Features
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PCI Local Bus Specification revision 2.1 compliant
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Compliance with ANSI SCSI standard
X3.131-1994
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Compliance with ANSI X3T10/855D SCSI-3
parallel interface (SPI) standard
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Compliance with ANSI X3T10/1071D Fast-20
standard
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Compliance with PCI Bus Power Management
Interface Specification Revision 1.0 (PC97)
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Onboard RISC processor to execute operations at
the I/O control block level from the host memory
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Supports fast, wide, and Ultra (Fast-20) SCSI data
transfer rates
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SCSI initiator and target modes of operation
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32-bit, intelligent bus master, DMA PCI bus
interface
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Supports PCI dual-address cycle (64-bit
addressing)
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SCSI operations executed from start to finish
without host intervention
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Simultaneous, multiple logical threads
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JTAG boundary scan support
Product Description
The ISP1040C is a single-chip, highly integrated, bus
master, SCSI I/O processor for use in SCSI initiator-type
applications. The device interfaces the PCI bus to a wide,
Ultra SCSI bus and contains an onboard RISC processor.
The ISP1040C is a fully autonomous device, capable of
managing multiple I/O operations and associated data
transfers from initiation to completion without host CPU
intervention. The ISP1040C provides power management
feature support in accordance with the PCI Bus Power
Management Specification while retaining full pin
compatibility with the QLogic ISP1040B. The ISP1040C
block diagram is illustrated in figure 1.
I/O BUS
Figure 1. ISP1040C Block Diagram
DMA BUS
SXP SCSI ENGINE
PCI INTERFACE
HOST MEMORY
HOST SOFTWARE
DRIVER
REQUEST
QUEUE
RESPONSE
QUEUE
32-BIT
PCI
BUS
IOCBS
FIFO
WCS
SEQUENCERS
CONTROL
DATA FIFO
64 BYTE
COMMAND FIFO
DMA
CONTROL
MAILBOX
REGISTERS
RISC
REGISTER
FILE
ALU
BOOT
CODE
MEMORY
INTERFACE
8/16-BIT
DATA 16
ADDRESS 16
ISP1040C
COMMAND
BUFFER
MESSAGE
BUFFER
SXP CODE
REGISTERS
PARALLEL
SCSI BUS
CTRL/CONFIG
REGISTERS
EXTERNAL
CODE/DATA
MEMORY
128 BYTE
FLASH
BIOS
NVRAM
QLogic Corporation
ISP1040C Intelligent SCSI Processor
Data Sheet
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ISP1040C
83140-580-02 B
QLogic Corporation
ISP Initiator and Target Firmware
The ISP1040C firmware implements a cooperative,
multitasking host adapter that provides the host system with
complete SCSI command and data transport capabilities,
thus freeing the host system from the demands of the SCSI
bus protocol. The ISP1040C firmware provides two
interfaces to the host system: the command interface and
the SCSI transport interface. The single-threaded command
interface facilitates debugging, configuration, and error
recovery. The multithreaded SCSI transport interface
maximizes use of the SCSI and host buses. The ISP1040C
switches dynamically between initiator and target modes.
Software Drivers
BIOS firmware is available for the ISP1040C. Software
drivers are available for the following operating systems:
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AIX
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I
2
O
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DOS/Windows
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Novell NetWare
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OS/2
s
SCO UNIX
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UnixWare
s
Windows 95
s
Windows NT
I/O Subsystem Organization
To maximize I/O throughput and improve host and
SCSI bus utilization, the ISP1040C incorporates a
high-speed, proprietary RISC processor; an intelligent
SCSI bus controller (SCSI executive processor [SXP]); and
a host bus, dual-channel DMA controller. The SCSI bus
controller and the host bus DMA controller operate
independently and concurrently under control of the
onboard RISC processor for maximum system
performance. The ISP1040C RISC interface requires
external program data memory.
The complete I/O subsystem solution using the
ISP1040C and associated supporting memory devices is
shown in figure 2.
Interfaces
The ISP1040C supports the following interfaces:
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PCI bus
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RISC processor
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SCSI executive processor
Pins that support these interfaces and other chip
operations are shown in figure 3.
ISP1040C
SCSI
16
SCSI
TARGETS
TARGET
TARGET
PCI
I/F
SCSI
I/F
RISC
CODE/DATA
MEMORY
PCI
BUS
PCI
HOST
MEMORY
IOCB
DATA
32
Figure 2. I/O Subsystem Design Using the ISP1040C
83140-580-02 B
ISP1040C
3
QLogic Corporation
PCI Bus Interface
The ISP1040C PCI bus interface supports the
following:
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32-bit, intelligent bus master, burst DMA host
interface for fetching I/O control blocks and data
transfers
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16-bit slave mode for communication with host
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Two channel DMA controller
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128-byte data DMA FIFO and 64-byte command
DMA FIFO with threshold control
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Pipelined DMA registers for efficient scatter/gather
operations
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Support for subsystem ID
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Supports PCI dual-address cycle (64-bit
addressing)
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Support for PCI cache commands
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3.3 V and 5.0 V tolerant PCI I/O buffers
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Support for flash BIOS PROM
The ISP1040C is designed to interface directly to the
PCI local bus and operate as a 32-bit DMA master. This
function is accomplished through the PCI bus interface unit
(PBIU) containing an onboard DMA controller. The PBIU
generates and samples PCI bus control signals, generates
host memory addresses, and facilitates data transfers
between host memory and the onboard DMA FIFO. The
PBIU also allows the host to access the ISP1040C internal
registers and communicate with the onboard RISC
processor through the PCI bus target mode operation.
Figure 3. ISP1040C Functional Signal Grouping
EXTBOOT
RISC
INTERFACE
VDD
VSS
POWER
AND GROUND
MISC
CONTROL
BSY
CD
DIFFM
SCSI
INTERFACE
ISP1040C
RISCSTB/JTAG
ESC1-0
RADDR15-0
IF/VDET
ACK
ATN
IO
MSG
REQ
RST
SD15-0
SDP1-0
SEL
TRIG/60MHZ
TSTOUT/TDO
FRAME
STOP
TRDY
DEVSEL
PERR
IDSEL
SERR
IRDY
RESET
CLK
RISCOE
WE
RDATA15-0
TESTMODE0/TDI
RESET
CBE3-0
PAR
INTA
NVDATI
NVCS
NVDATO/SUBID
NVCLK/3V
NVRAM
CONTROL
PDATA7-0
POD
BSYLED
GPIO3-0
RDPAR
DIFFS
EARB
ESD
EIG
ETG
EBSY
ESEL
ERST
SCSI
DIFFERENTIAL
INTERFACE
PCI INTERFACE
AD31-0
BCLK
BGNT
BREQ
FLASH BIOS PROM
FROE
FRWE
TESTMODE1/TMS
TESTMODE2/TCK
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ISP1040C
83140-580-02 B
QLogic Corporation
The ISP1040C onboard DMA controller consists of two
independent DMA channels that initiate transactions on the
PCI bus and transfer data between the memory and DMA
FIFO. The two DMA channels are the command DMA
channel and the data DMA channel. The command DMA
channel is used mainly by the RISC processor for small
transfers such as fetching commands from and writing
status information to the host memory over the PCI bus.
The data DMA channel transfers data between the SCSI
bus and the PCI bus.
The PBIU internally arbitrates between the data DMA
channel and the command DMA channel and alternately
services them. Each DMA channel has a set of DMA
registers that are programmed for transfers by the RISC
processor.
RISC Processor Interface
The ISP1040C RISC processor interface supports the
following:
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Programmable cycle time for external memory
access
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Internal 16-bit wide data paths
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Execution of multiple I/O control blocks from the
host memory
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Management of onboard host bus DMA controller
and SCSI bus controller
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Reduced host intervention and interrupt overhead
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Capacity to generate one interrupt per I/O operation
The onboard RISC processor enables the ISP1040C to
handle complete I/O transactions with no intervention from
the host. The ISP1040C RISC processor controls the chip
interfaces; executes simultaneous, multiple input/output
control blocks (IOCBs); and maintains the required thread
information for each transfer.
SCSI Executive Processor Interface
The ISP1040C SXP interface supports the following:
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8- or 16-bit data transfers
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Ultra SCSI (Fast-20) synchronous data transfer
rates up to 40 Mbytes/sec
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Asynchronous SCSI data transfer rates up to
12 Mbytes/sec
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Programmable SCSI processor
Specialized instruction set with 16-bit
microword
384-bit by 16-bit internal RAM control store
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32-bit, configurable SCSI transfer counter
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Command, status, message in, and message out
buffers
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Device information storage area
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On-chip, single-ended SCSI transceivers (48-mA
drivers)
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Programmable active negation
The SXP provides an autonomous, intelligent SCSI
interface capable of handling complete SCSI operations.
The SXP interrupts the RISC processor only to handle
higher level functions such as threaded operations or error
handling.
Packaging
The ISP1040C is available in a 208-pin plastic quad flat
pack (PQFP).
AIX is a trademark of IBM Corporation.
DOS, OS/2, Windows NT, and Windows 95 are trademarks or registered trademarks of Microsoft Corp.
Novell and NetWare are registered trademarks of Novell, Inc.
SCO UNIX is a registered trademark of Santa Cruz Operations.
UNIX is a trademark of AT&T Bell Laboratories.
All other brand and product names are trademarks or registered trademarks of their respective holders.
July 29, 1997 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200
Specifications are subject to change without notice.
QLogic is a trademark of QLogic Corporation.
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