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6,000 Usable PLD Gates with 82 I/Os
300 MHz 16-bit Counters,
400 MHz Datapaths
0.35
m four-layer metal non-volatile CMOS
process for smallest die sizes
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100% routable with 100% utilization and
complete pin-out stability
Variable-grain logic cells provide high
performance and 100% utilization
Comprehensive design tools include high
quality Verilog/VHDL synthesis
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Interfaces with both 3.3 V and 5.0 V devices
PCI compliant with 3.3 V and 5.0 V buses
for -1/-2/-3/-4 speed grades
Full JTAG boundary scan
I/O Cells with individually controlled
Registered Input Path and Output Enables
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74 bidirectional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
Four High Drive input-only pins
Four High Drive input-only/distributed
network pins
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Two array clock/control networks available
to the logic cell flip-flop clock, set and reset
inputs -- each driven by an input-only pin
Two global clock/control networks available
to the logic cell; F1, clock, set and reset
inputs and the data input, I/O register clock,
reset and enable inputs as well as the output
enable control -- each driven by an input-
only or I/O pin, or any logic cell output or
I/O cell feedback
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Input + logic cell + output total delays
under 6 ns
Data path speeds over 400 MHz
Counter speeds over 300 MHz
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The QL3006 is a 6,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3
FPGAs are fabricated on a 0.35
m four-layer metal process using QuickLogic
's patented
ViaLink
technology to provide a unique combination of high performance, high density, low
cost, and extreme ease-of-use.
The QL3006 contains 160 logic cells. With a maximum of 82 I/Os, the QL3006 is available in
68-pin PLCC, 84-pin PLCC, and 100-pin TQFP packages.
Software support for the complete pASIC 3 family, including the QL3006, is available through
three basic packages. The turnkey QuickWorks
package provides the most complete FPGA
software solution from design entry to logic synthesis, to place and route, to simulation. The
QuickTools
TM
for Workstations package provides a solution for designers who use Cadence
,
Exemplar
TM
, Mentor
, Synopsys
, Synplicity
, Viewlogic
TM
, Aldec
TM
,
or other third-party tools
for design entry, synthesis, or simulation.
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Setup Time
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1.7
1.7
1.7
1.7
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Hold Time
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0.0
t
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Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
t
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Clock High Time
1.2
1.2
1.2
1.2
1.2
t
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Clock Low Time
1.2
1.2
1.2
1.2
1.2
t
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Set Delay
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1.3
1.5
1.8
2.8
t
RESET
Reset Delay
0.8
1.1
1.3
1.6
2.6
t
SW
Set Width
1.9
1.9
1.9
1.9
1.9
t
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Reset Width
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1.8
1.8
1.8
1.8
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High Drive Input Delay
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1.9
2.4
2.9
4.4
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High Drive Input, Inverting Delay
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1.7
1.9
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2.5
3.0
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t
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Input Register Set-Up Time
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3.1
3.1
3.1
3.1
3.1
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t
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Input Register Hold Time
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0.0
0.0
0.0
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t
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Input Register Clock To Q
0.7
0.8
1.0
1.1
1.6
2.1
3.6
t
lRST
Input Register Reset Delay
0.6
0.7
0.9
1.0
1.5
2.0
3.5
t
lESU
Input Register clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
2.3
t
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Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
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Array Clock Delay
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1.3
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t
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Global Clock Pin Delay
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0.7
0.7
0.7
0.7
0.7
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GCKB
Global Clock Buffer Delay
0.8
0.8
0.9
0.9
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Input Delay (bidirectional pad)
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3.1
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t
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Input Register Set-Up Time
3.1
3.1
3.1
3.1
3.1
3.1
t
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Input Register Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
t
lOCLK
Input Register Clock To Q
0.7
1.0
1.2
1.5
2.5
3.0
t
lORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
t
lESU
Input Register clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
t
lEH
Input Register Clock Enable Hold Time
0.0
0.0
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Output Delay Low to High
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2.5
3.1
3.6
4.7
t
OUTHL
Output Delay High to Low
2.2
2.6
3.2
3.7
4.8
t
PZH
Output Delay Tri-state to High
1.2
1.7
2.2
2.8
3.9
t
PZL
Output Delay Tri-state to Low
1.6
2.0
2.6
3.1
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Output Delay High to Tri-State
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Output Delay Low to Tri-State
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1
1
t
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