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Preliminary

Figure 1: QL5632 Diagram

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32-bit / 33 MHz PCI Master/Target

Zero-wait state PCI Master provides
132 MBps transfer rates

Zero-wait-state PCI Target Write/One-wait-
state PCI Target Read interface

Supports all PCI commands, including
configuration and MWI

Supports fully-customizable byte enable for
master channels

Target interface supports retry, disconnect
with/without data transfer, and target abort

Fully programmable back-end interface

Independent PCI bus (33 MHz) and local bus
(up to 160 MHz) clocks

Fully customizable PCI Configuration Space

Configurable FIFOs with depths up to 256
words

Reference design with driver code (Win
95/98/Win 2000/NT4.0) available

PCI v2.3 compliant

Supports Type 0 Configuration Cycles in
Target mode

3.3 V PCI signaling

2.5 V Supply Voltage

280-pin PBGA

208-pin PQTP

Supports Extendable PCI functionality

Unlimited/Continuous Burst Transfers
supported

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Support for PCI host-bridge function

Support for Configuration Space from
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Multi-Function, Expanded Capabilities, &
Expansion ROM capable

PCI v2.3 Power Management Spec
compatible

PCI v2.3 Vital Product Data (VPD)
configuration support

Programmable Interrupt Generator

O support with local processor

Mailbox register support

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772 Logic Cells

41,472 RAM bits

Up to 115 I/O pins

All back-end interface and glue-logic can be
implemented on chip

Six 32-bit busses interface between the PCI
Controller and the Programmable Logic

Eighteen 2,304 bit Dual Port High
Performance SRAM Blocks

1,889 flip-flops available

PCI Bus

PCI Bus 33 MHz/32 bits (data and

address)

Target
Controller

160 MHz
FIFOs

Config
space

DMA
Controller

Master
Controller

High Speed
Logic Cells

High
Speed
Data
Path

Programmable
Logic

32 bit Interface

115 User I/O

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Preliminary

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The QL5632 device in the QuickLogic

QuickPCI ESP (Embedded Standard Product) family

provides a complete and customizable PCI interface solution combined with programmable
logic. This device eliminates any need for the designer to worry about PCI bus compliance,
yet allows for the maximum 32-bit PCI bus bandwidth (132 MBps).

The programmable logic portion of the device contains 772 QuickLogic Logic Cells and
18 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in
many width/depth combinations. They can also be combined with logic cells to form FIFOs,
or be initialized via Serial EEPROM on power-up and used as ROMs.

The QL5632 device meets PCI 2.3 electrical and timing specifications and has been fully
hardware-tested. This device also supports the Win'98 and PC'98 standards. The QL5632
device features 2.5 V operation with multi-volt compatible I/Os. The device can easily
operate in 3 V embedded systems and is fully compatible with 3.3 V applications.

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The PCI Controller is a 32-bit/33 MHz PCI 2.3 Compliant Master/Target Controller
capable of infinite length Master Write and Read transactions at zero wait states
(132 MBps).

The Master will never insert wait states during transfers, so data is supplied or received by
FIFOs that can be configured in the programmable region of the device. The Master is
capable of initiating any type of PCI commands, including configuration cycles and Memory
Write and Invalidate (MWI). This enables the QL5632 device to act as a PCI host. The Master
Controller will most often be operated by a DMA Controller in the programmable region of
the device. DMA Controller reference design is available and will be included in the
Quick

Works

9.3 design software.

The Target interface offers full PCI Configuration Space and flexible target addressing. It
supports zero-wait-state target Write and one-wait-state target Read operations. It also
supports retry, disconnect with/without data transfer, and target abort requested by the back
end. Any number of 32-bit BARs may be configured as either memory or I/O space. All
required and optional PCI 2.3 Configuration Space registers can be implemented within the
programmable region of the device. A reference design of a Target Configuration and
Addressing module is available and will be included in the Quick

Works 9.3 design software.

The interface ports are divided into a set of ports for master transactions and a set for target
transactions. The Master DMA controller and Target Configuration Space and Address
Decoding are done in the programmable logic region of the device. These functions are not
timing critical, so leaving these elements in the programmable region allows the greatest
degree of flexibility to the designer. Reference DMA controller, Configuration Space, and
Address Decoding blocks are readily available so that the design cycle can be minimized.

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Preliminary

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The configuration space is completely customizable in the programmable region of the
device.

PCI address and command decoding is performed by logic in the programmable section of
the device. This allows support for any size of memory or I/O space for back end logic. It
also allows the user to implement any subset of the PCI commands supported by the
QL5632. In the reference design, QuickLogic provides a reference Address
Register/Counter and Command Decode block.

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The customizable DMA controller included with the QuickWorks design software contains
the following features:

Configurable DMA count size for Reads and Writes (up to 30 bits)

Configurable DMA burst size for PCI (including unlimited/continuous burst)

Customizable PCI command to use by core

Customizable Byte Enable signal

Programmable Arbitration between DMA Read & Write transactions

DMA Registers may be mapped to any area of Target Memory Space, including:

Read Address (32-bit register)

Write Address (32-bit register)

Read Length (16-bit register) / Write Length (16-bit register)

Control and Status (32-bit register, includes 8 bit Burst Length)

DMA Registers are available to the local design or the PCI bus

Programmable Interrupt Control to signal end of transfer or other event

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Preliminary

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FIFOs may be created with the RAM/FIFO wizard in the QuickWorks tools.

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shows

the graphical interface used to create these FIFOs. FIFOs may be designed up to
1,889 words deep. The 18 RAM cells available in the QL5632 allow for up to:

9 FIFOs at 128 words deep (36 wide)

4 FIFOs at 256 words deep (36 wide)

2 FIFOs at 512 words deep (36 wide)

1 FIFO at 1,024 words deep (36 wide)

Figure 2: Graphical Interface to create FIFO

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shows the interface symbol you have to use in your schematic design in order to

attach the local interface programmable logic design to the PCI core. If you are designing
with a top-level Verilog or VHDL file you must use a structural instantiation of this
PCI32_25um block instead of a graphical symbol.

Электронный компонент: QL5632-BPQ208C

Document Outline