This product conforms to specifications per the terms of the Ramtron
Ramtron International Corporation
standard warranty. Production processing does not necessarily in-
1850 Ramtron Drive, Colorado Springs, CO 80921
clude testing of all parameters.
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
Rev 2.2
June 2002
1 of 12
FM1608
64Kb Bytewide FRAM Memory
Features
64K bit Ferroelectric Nonvolatile RAM
Organized as 8,192 x 8 bits
High Endurance 1 Trillion (10
12
) Read/Writes
10 year Data Retention
NoDelayTM Writes
Advanced High-Reliability Ferroelectric Process
Superior to BBSRAM Modules
No battery concerns
Monolithic reliability
True surface mount solution, no rework steps
Superior for moisture, shock, and vibration
Resistant to negative voltage undershoots
SRAM & EEPROM Compatible
JEDEC 8Kx8 SRAM & EEPROM pinout
120 ns Access Time
180 ns Cycle Time
Low Power Operation
15 mA Active Current
20
A Standby Current
Industry Standard Configuration
Industrial Temperature -40
C to +85
C
28-pin SOIC or DIP
Description
The FM1608 is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile but operates in other respects as a RAM.
It provides data retention for 10 years while
eliminating the reliability concerns, functional
disadvantages and system design complexities of
battery-backed SRAM. Its fast write and high write
endurance make it superior to other types of
nonvolatile memory.
In-system operation of the FM1608 is very similar to
other RAM based devices. Minimum read- and write-
cycle times are equal. The FRAM memory, however,
is nonvolatile due to its unique ferroelectric memory
process. Unlike BBSRAM, the FM1608 is a truly
monolithic nonvolatile memory. It provides the same
functional benefits of a fast write without the serious
disadvantages associated with modules and batteries
or hybrid memory solutions.
These capabilities make the FM1608 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in a bytewide environment. The
availability of a true surface-mount package improves
the manufacturability of new designs, while the DIP
package facilitates simple design retrofits. The
FM1608 offers guaranteed operation over an
industrial temperature range of -40C to +85C.
Pin Configuration
Ordering Information
FM1608-120-P 120 ns access, 28-pin plastic DIP
FM1608-120-S 120 ns access, 28-pin SOIC
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
CE
A10
OE
A11
A9
A8
NC
WE
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FM1608
Rev. 2.2
June 2002
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Address
Latch
A0-A12
CE
Control
Logic
WE
Row
Decoder
Block Decoder
Column Decoder
A0-A7
A8-A9
A10-A12
I/O Latch
Bus Driver
OE
8,192 x 8 FRAM Array
DQ0-7
Figure 1. Block Diagram
Pin Description
Pin Name
I/O
Pin Description
A0-A12
Input
Address: The 13 address inputs select one of 8,192 bytes in the FRAM array. The
address value will be latched on the falling edge of /CE.
DQ0-7
I/O
Data: 8-bit bi-directional data bus for accessing the FRAM array.
/CE
Input
Chip Enable: /CE selects the device when low. Asserting /CE low causes the address
to be latched internally. Address changes that occur after /CE goes low will be
ignored until the next falling edge occurs.
/OE
Input
Output Enable: Asserting /OE low causes the FM1608 to drive the data bus when
valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated.
/WE
Input
Write Enable: Asserting /WE low causes the FM1608 to write the contents of the
data bus to the address location latched by the falling edge of /CE.
VDD
Supply
Supply Voltage: 5V
VSS Supply
Ground.
Functional Truth Table
/CE /WE
Function
H X
Standby/Precharge
X
Latch Address (and Begin Write if /WE=low)
L H
Read
L
Write
Note: The /OE pin controls only the DQ output buffers.
FM1608
Rev. 2.2
June 2002
3 of 12
Overview
The FM1608 is a bytewide FRAM memory. The
memory array is logically organized as 8,192 x 8 and
is accessed using an industry standard parallel
interface. The FM1608 is inherently nonvolatile via
its unique ferroelectric process. All data written to the
part is immediately nonvolatile with no delay.
Functional operation of the FRAM memory is the
same as SRAM type devices, except the FM1608
requires a falling edge of /CE to start each memory
cycle.
Memory Architecture
Users access 8,192 memory locations each with 8
data bits through a parallel interface. The 13-bit
address specifies each of the 8,192 bytes uniquely.
Internally, the memory array is organized into 8
blocks of 1Kb each. The 3 most-significant address
inputs decode one of 8 blocks. This block
segmentation has no effect on operation, however the
user may wish to group data into blocks by its
endurance requirements as explained in a later
section.
The cycle time is the same for read and write memory
operations. This simplifies memory controller logic
and timing circuits. Likewise the access time is the
same for read and write memory operations. When
/CE is deasserted high, a precharge operation begins,
and is required of every memory cycle. Thus unlike
SRAM, the access and cycle times are not equal.
Writes occur immediately at the end of the access
with no delay. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed.
Note that the FM1608 has no special power-down
demands. It will not block user access, and it contains
no power-management circuits other than a simple
internal power-on reset. It is the user's responsibility
to ensure that VDD is within datasheet tolerances and
to ensure the proper voltage level and timing
relationship between VDD and /CE in power-up and
power-down events to prevent incorrect operation.
Memory Operation
The FM1608 is designed to operate in a manner very
similar to other bytewide memory products. For users
familiar with BBSRAM, the performance is
comparable but the bytewide interface operates in a
slightly different manner as described below. For
users familiar with EEPROM, the obvious differences
result from the higher write performance
of FRAM technology including NoDelay writes and
much higher write endurance.
Read Operation
A read operation begins on the falling edge of /CE.
At this time, the address bits are latched and a
memory cycle is initiated. Once started, a complete
memory cycle must be completed internally
regardless of the state of /CE. Data becomes available
on the bus after the access time has been satisfied.
After the address has been latched, the address value
may change upon satisfying the hold time parameter.
Unlike an SRAM, changing address values will have
no effect on the memory operation after the address is
latched.
The FM1608 will drive the data bus when /OE is
asserted low. If /OE is asserted after the memory
access time has been satisfied, the data bus will be
driven with valid data. If /OE is asserted prior to
completion of the memory access, the data bus will
not be driven until valid data is available. This feature
minimizes supply current in the system by eliminating
transients caused by invalid data being driven onto
the bus. When /OE is inactive the data bus will
remain tri-stated.
Write Operation
Writes occur in the FM1608 within the same time
interval as reads. The FM1608 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the part begins the
memory cycle as a write. The FM1608 will not drive
the data bus regardless of the state of /OE.
In a /WE-controlled write, the memory cycle begins
on the falling edge of /CE. The /WE signal falls after
the falling edge of /CE. Therefore the memory cycle
begins as a read. The data bus will be driven
according to the state of /OE until /WE falls. The
timing of both /CE- and /WE-controlled write cycles
is shown in the electrical specifications.
Write access to the array begins asynchronously after
the memory cycle is initiated. The write access
terminates on the rising edge of /WE or /CE,
whichever is first. Data set-up time, as shown in the
electrical specifications, indicates the interval during
which data cannot change prior to the end of the write
access.
FM1608
Rev. 2.2
June 2002
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Unlike other truly nonvolatile memory technologies,
there is no write delay with FRAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Therefore, any operation including read or
write can occur immediately following a write. Data
polling, a technique used with EEPROMs to
determine if a write is complete, is unnecessary.
Precharge Operation
The precharge operation is an internal condition that
prepares the memory for a new access. All memory
cycles consist of a memory access and a precharge.
The precharge is initiated by deasserting the /CE pin
high. It must remain high for at least the minimum
precharge time t
PC
.
The user dictates the beginning of this operation since
a precharge will not begin until /CE rises. However
the device has a maximum /CE low time specification
that must be satisfied.
Endurance
The FM1608 internally operates with a read and
restore mechanism. Therefore, each read and write
cycle involves a change of state. The memory
architecture is based on an array of rows and
columns. Each read or write access causes an
endurance cycle for an entire row. In the FM1608, a
row is 32 bits wide. Every 4-byte boundary marks
the beginning of a new row. Endurance can be
optimized by ensuring frequently accessed data is
located in different rows. Regardless, FRAM offers
substantially higher write endurance than other
nonvolatile memories. The rated endurance limit of
10
12
cycles will allow 3000 accesses per second to the
same row for 10 years.
Applications
As the first truly nonvolatile RAM, the FM1608 fits
into many diverse applications. Clearly, its monolithic
nature and high performance make it superior to
battery-backed SRAM in most every application. This
applications guide is intended to facilitate the
transition from BBSRAM to FRAM. It is divided into
two parts. First is a treatment of the advantages of
FRAM memory compared with battery-backed
SRAM. Second is a design guide, which highlights
the simple design considerations that should be
reviewed in both retrofit and new design situations.
FRAM Advantages
Although battery-backed SRAM is a mature and
established solution, it has numerous weaknesses.
These stem directly or indirectly from the presence of
the battery. FRAM uses an inherently nonvolatile
storage mechanism that requires no battery. It
therefore eliminates these weaknesses. The major
considerations in upgrading to FRAM follow:
Construction Issues
1. Cost
The cost of both the component and the
manufacturing overhead of battery-backed SRAM is
high. FRAM, with its monolithic construction is
inherently a lower cost solution. In addition, there is
no `built-in' rework step required for battery
attachment when using surface mount parts.
Therefore assembly is streamlined and more cost
effective. In the case of DIP battery-backed modules,
the user is constrained to through-hole assembly
techniques and a board wash using no water.
2. Humidity
A typical battery-backed SRAM module is qualified
at 60 C, 90% Rh, no bias, and no pressure. This is
because the multi-component assemblies are
vulnerable to moisture, not to mention dirt. FRAM is
qualified using HAST highly accelerated stress test.
This requires 120 C at 85% Rh, 24.4 psia at 5.5V
bias.
3. System reliability
Data integrity must be in question when using a
battery-backed SRAM. They are inherently
vulnerable to shock and vibration. If the battery
contact comes loose, data will be lost. In addition a
negative voltage, even a momentary undershoot, on
any pin of a battery-backed SRAM can cause data
loss. The negative voltage causes current to be drawn
directly from the battery. These momentary short
circuits can greatly weaken a battery and reduce its
capacity over time. In general, there is no way to
monitor the lost battery capacity. Should an
undershoot occur in a battery backed system during a
power down, data can be lost immediately.
4. Space
Certain disadvantages of battery-backed, such as
susceptibility to shock, can be reduced by using the
old fashioned DIP module. However, this alternative
takes up board space, add height, and dictates
through-hole assembly. FRAM offers a true surface-
mount solution that uses 25% of the board space.
FM1608
Rev. 2.2
June 2002
5 of 12
No multi-piece assemblies no connectors, and no
modules. A real nonvolatile RAM is finally
available!
Direct Battery Issues
5. Field
maintenance
Batteries, no matter how mature, are a built-in
maintenance problem. They eventually must be
replaced. Despite long life projections, it is
impossible to know if any individual battery will last
considering all of the factors that can degrade them.
6. Environmental
Lithium batteries are widely regarded as an
environmental problem. They are a potential fire
hazard and proper disposal can be a burden. In
addition, shipping of lithium batteries may be
restricted.
7. Style!
Backing up an SRAM with a battery is an old-
fashioned approach. In many cases, such modules are
the only through-hole component in sight. FRAM is
the latest memory technology and it is changing the
way systems are designed.
FRAM is nonvolatile and writes fast -- no battery
required!
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