This product conforms to specifications per the terms of the Ramtron
Ramtron International Corporation
standard warranty. Production processing does not necessarily in-
1850 Ramtron Drive, Colorado Springs, CO 80921
clude testing of all parameters.
(800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058
www.ramtron.com
Rev 2.0
July 2003
Page 1 of 13
FM24CL64
64Kb Serial 3V FRAM Memory
Features
64K bit Ferroelectric Nonvolatile RAM
Organized as 8,192 x 8 bits
Unlimited Read/Write Cycles
10 year Data Retention
NoDelayTM Writes
Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
Up to 1 MHz maximum bus frequency
Direct hardware replacement for EEPROM
Supports legacy timing for 100 kHz & 400 kHz
Low Power Operation
True 2.7V-3.6V Operation
75
A Active Current (100 kHz)
1
A Standby Current
Industry Standard Configuration
Industrial Temperature -40
C to +85
C
8-pin SOIC
Description
The FM24CL64 is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM24CL64 performs write operations at bus
speed. No write delays are incurred. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers write
endurance orders of magnitude higher than
EEPROM. Also, FRAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.
These capabilities make the FM24CL64 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24CL64 provides substantial benefits to users
of serial EEPROM, yet these benefits are available in
a hardware drop-in replacement. The FM24CL64 is
provided in industry standard 8-pin surface mount
package using a familiar two-wire protocol. It is
guaranteed over an industrial temperature range of
-40C to +85C.
Pin Configuration
A0
A1
A2
VSS
VDD
WP
SCL
SDA
1
2
3
4
8
7
6
5
Pin Names
Function
A0-A2 Device
Select
Address
SDA Serial
Data/address
SCL Serial
Clock
WP Write
Protect
VSS Ground
VDD Supply
Voltage
Ordering Information
FM24CL64-S 8-pin
SOIC
FM24CL64
Rev 2.0
July 2003
Page 2 of 14
Address
Latch
`
2,048 x 32
FRAM Array
Data Latch
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A0-A2
Figure 1. FM24CL64 Block Diagram
Pin Description
Pin Name
Type
Pin Description
A0-A2
Input
Address 0-2. These pins are used to select one of up to 8 devices of the same type on
the same two-wire bus. To select the device, the address value on the three pins must
match the corresponding bits contained in the device address. The address pins are
pulled down internally.
SDA
I/O
Serial Data Address. This is a bi-directional line for the two-wire interface. It is
open-drain and is intended to be wire-OR'd with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. A pull-up resistor is required.
SCL
Input
Serial Clock. The serial clock line for the two-wire interface. Data is clocked out of
the part on the falling edge, and in on the rising edge. The SCL input also
incorporates a Schmitt trigger input for noise immunity.
WP
Input
Write Protect. When tied to VDD, addresses in the entire memory map will be write-
protected. When WP is connected to ground, all addresses may be written. This pin
is pulled down internally.
VDD
Supply
Supply Voltage: 2.7V to 3.6V
VSS Supply
Ground
FM24CL64
Rev 2.0
July 2003
Page 3 of 13
Overview
The FM24CL64 is a serial FRAM memory. The
memory array is logically organized as a 8,192 x 8 bit
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24CL64 and a serial
EEPROM with the same pinout relates to its superior
write performance.
Memory Architecture
When accessing the FM24CL64, the user addresses
8,192 locations each with 8 data bits. These data bits
are shifted serially. The 8,192 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish other non-memory devices),
and an extended 16-bit address. Only the lower 13
bits are used by the decoder for accessing the
memory. The upper three address bits should be set
to 0 for compatibility with larger devices in the
future.
The access time for memory operation is essentially
zero beyond the time needed for the serial protocol.
That is, the memory is read or written at the speed of
the two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a
new bus transaction can be shifted into the part, a
write operation will be complete. This is explained in
more detail in the interface section below.
Users expect several obvious system benefits from
the FM24CL64 due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that it is the user's responsibility to ensure that
VDD is within data sheet tolerances to prevent
incorrect operation.
Two-wire Interface
The FM24CL64 employs a bi-directional two-wire
bus protocol using few pins or board space. Figure 2
illustrates a typical system configuration using the
FM24CL64 in a microcontroller-based system. The
industry standard two-wire bus is familiar to many
users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24CL64 always is a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including start, stop, data bit, or acknowledge. Figure
3 illustrates the signal conditions that specify the four
states. Detailed timing diagrams are in the electrical
specifications.
Microcontroller
SDA
SCL
FM24CL64
A0 A1 A2
SDA
SCL
FM24CL64
A0 A1 A2
VDD
Rmin = 1.1 K
Rmax = tR/Cbus
Figure 2. Typical System Configuration
FM24CL64
Rev 2.0
July 2003
Page 4 of 13
Stop
(Master)
Start
(Master)
7
Data bits
(Transmitter)
6
0
Data bit
(Transmitter)
Acknowledge
(Receiver)
SCL
SDA
Figure 3. Data Transfer Protocol
Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24CL64 should end
with a stop condition. If an operation is in progress
when a stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a stop condition.
Start Condition
A start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All commands should be preceded by a start
condition. An operation in progress can be aborted by
asserting a start condition at any time. Aborting an
operation using the start condition will ready the
FM24CL64 for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The acknowledge takes place after the 8
th
data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the no-acknowledge ceases the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24CL64
will continue to place data onto the bus as long as
the receiver sends acknowledges (and clocks). When
a read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24CL64 to attempt to drive the
bus on the next clock while the master is sending a
new command such as stop.
Slave Address
The first byte that the FM24CL64 expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the device select address bits, and a bit that specifies
if the transaction is a read or a write.
Bits 7-4 are the device type and should be set to
1010b for the FM24CL64. These bits allow other
types of function types to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
address select bits. They must match the
corresponding value on the external address pins to
select the device. Up to eight, FM24CL64s can
reside on the same two-wire bus by assigning a
different address to each. Bit 0 is the read/write bit.
A 0 indicates a write operation.
FM24CL64
Rev 2.0
July 2003
Page 5 of 13
1
0
1
0
A2 A1 A0 R/W
Slave
ID
Device
Select
7
6
5
4
3
2
1
0
Figure 4. Slave Address
Addressing Overview
After the FM24CL64 (as receiver) acknowledges the
device address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB. Since the
device uses only 13 address bits, the value of the
upper three bits are don't care. Following the MSB is
the LSB with the remaining eight address bits. The
address value is latched internally. Each access
causes the latched address value to be incremented
automatically. The current address is the value that is
held in the latch -- either a newly written value or the
address following the last access. The current address
will be held for as long as power remains or until a
new value is written. Reads always use the current
address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24CL64 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (1FFFh) is reached, the address latch will
roll over to 0000h. There is no limit to the number of
bytes that can be accessed with a single read or write
operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24CL64 can begin. For a read operation the
FM24CL64 will place 8 data bits on the bus then wait
for an acknowledge from the master. If the
acknowledge occurs, the FM24CL64 will transfer the
next sequential byte. If the acknowledge is not sent,
the FM24CL64 will end the read operation. For a
write operation, the FM24CL64 will accept 8 data
bits from the master then send an acknowledge. All
data transfer occurs MSB (most significant bit) first.
Memory Operation
The FM24CL64 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24CL64 and a similar
configuration EEPROM during writes. The
complete operation for both writes and reads is
explained below.
Write Operation
All writes begin with a device address, then a
memory address. The bus master indicates a write
operation by setting the LSB of the device address
to a 0. After addressing, the bus master sends each
byte of data to the memory and the memory
generates an acknowledge condition. Any number of
sequential bytes may be written. If the end of the
address range is reached internally, the address
counter will wrap from 1FFFh to 0000h.
Unlike other nonvolatile memory technologies,
there is no effective write delay with FRAM. Since
the read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a ready condition.
Internally, an actual memory write occurs after the
8
th
data bit is transferred. It will be complete before
the acknowledge is sent. Therefore, if the user
desires to abort a write without altering the memory
contents, this should be done using start or stop
condition prior to the 8
th
data bit. The FM24CL64
uses no page buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL64 will not acknowledge data bytes that are
written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature. WP is pulled
down internally.
Figure 5 below illustrates both a single-byte and
multiple-write.
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