RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Contents

-------------------------------------------------------------------------------------

page

- Features

----------------------------------------------------------------------------------------------

- Block Diagram

------------------------------------------------------------------------------------

- Pin Configuration

------------------------------------------------------------------------------- 5

- PQFP and LQFP Pin-Out Table

--------------------------------------------------------- 7

- Pin Description

----------------------------------------------------------------------------------- 8

- Basic Application System Block

--------------------------------------------------------13

- Oscillator Characteristics

------------------------------------------------------------------14

- Read/Write timing Diagram

--------------------------------------------------------------16

- Execution Unit

-----------------------------------------------------------------------------------18

General Register

---------------------------------------------------------------------------18

Segment Register

---------------------------------------------------------------------------18

Instruction Pointer and Status Flags Register

----------------------------------19

Address Generation

-----------------------------------------------------------------------20

- Peripheral Control Block Register

----------------------------------------------------21

- System Clock Block

---------------------------------------------------------------------------23

- Reset

--------------------------------------------------------------------------------------------------24

- Bus Interface Unit

-----------------------------------------------------------------------------26

Memory and I/O Interface

-------------------------------------------------------------26

Data Bus

---------------------------------------------------------------------------------------26

Wait States

------------------------------------------------------------------------------------27

Bus Hold

---------------------------------------------------------------------------------------28

- Chip Select Unit

---------------------------------------------------------------------------------30

U
C
S

-------------------------------------------------------------------------------------------30

LCS

-------------------------------------------------------------------------------------------31

MCSx

-----------------------------------------------------------------------------------------32

PCSx

------------------------------------------------------------------------------------------33

- Interrupt Controller Unit

------------------------------------------------------------------36

Master Mode and Slave Mode

--------------------------------------------------------36

Interrupt Vector, Type and Priority

-------------------------------------------------37

Interrupt Request

--------------------------------------------------------------------------38

Interrupt Acknowledge

------------------------------------------------------------------38

Programming the Registers

------------------------------------------------------------39

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

- DMA Unit

------------------------------------------------------------------------------------------52

DMA Operation

--------------------------------------------------------------------------52

External Request

-------------------------------------------------------------------------57

- Timer Control Unit

----------------------------------------------------------------------------59

= Watchdog Timer

------------------------------------------------------------------------63

Timer/Counter Unit Output Mode

------------------------------------------------64

- Asynchronous Serial Port

------------------------------------------------------------------65

- Synchronous Serial Port

--------------------------------------------------------------------69

= Synchronous Serial Port Operation

------------------------------------------71

- PIO Unit

--------------------------------------------------------------------------------------------73

PIO Multi-Function Pin list Table

-------------------------------------------------73

- PSRAM Control Unit

------------------------------------------------------------------------76

- Instruction Set Opcodes and Clock Cycle

-----------------------------------------77

R8800LV Execution Timings

-------------------------------------------------------81

- DC Characteristics

----------------------------------------------------------------------------82

- AC Characteristics

----------------------------------------------------------------------------84

- Package Information

-------------------------------------------------------------------------93

- Revision History

--------------------------------------------------------------------------------95

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

16-Bit Microcontroller with 16-bit external data bus

Features

RISC architecture

Five-stages pipeline

Static Design & Synthesizable design

Bus interface

- Multiplexed address and Data bus which

is compatible with 80C186 microprocessor

- Supports nonmultiplexed address bus [A19 : A0]

- 1M byte memory address space

- 64K byte I/O space

Software is compatible with the 80C186

microprocessor

Support one Asynchronous serial channel & one

Synchronous serial channel

Supports 32 PIO pins

PSRAM (Pseudo static RAM) interface with

auto-refresh control

Three independent 16-bit timers and Timer 1 can

be programmed as a watchdog timer

The Interrupt controller with five maskable

external interrupts and one nonmaskable external

interrupt

Two independent DMA channels

Programmable chip-select logic for Memory

or I/O bus cycle decoder

Programmable wait-state generator

Support CPU ID

Block Diagram

n
o
u s

I
n
t e r f a c e

o
n
t r o l

U
n
i t

n
t
o
-

r
i
a l

i
o
n

4
b
i t s )

i
o
n
g
i
s t e r

S
i
g n a l

o
n

1
V
2

1
/
I R Q

E
C
T

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

R8800LV PQFP and LQFP Pin-Out table

Pin name

LQFP Pin No.

PQFP Pin No.

Pin name

LQFP Pin No.

PQFP Pin No.

AD0

A11

AD8

A10

AD1

AD9

AD2

AD10

AD3

AD11

AD4

AD12

AD5

VCC

GND

AD13

AD6

GND

VCC

WHB

AD14

WLB

AD7

HLDA

AD15

HOLD

S6/

UZI

/PI O29

SRDY/PI O6

UZI

/PI O26

NMI

TXD/PI O27

DT/

/PI O4

RXD/PI O28

D
E
N

/PI O5

SDATA/PI O21

100

MCS

/PI O14

SDEN1/PI O23

MCS

/PI O15

SDEN0/PI O22

I NT4/ PI O30

SCLK/PI O20

I NT3/

INTA

/I RQ

B
H
E

A
D
EN

I NT2/

INTA

/PI O31

I NT1/

S
E
LECT

I NT0

ALE

UCS

C
N
CE

ARDY

LCS

C
N
CE

2
S

PCS

/A2/PI O2

PCS

/A1/PI O3

0
S

VCC

GND

PCS

/PI O19

PCS

/PI O18

GND

VCC

PCS

/PI O17

CLKOUTA

PCS

/PI O16

CLKOUTB

VCC

GND

MCS

/PI O24

A19/PI O9

/PI O25

A18/PI O8

GND

VCC

RST

A17/PI O7

TMRI N1/PI O0

A16

TMROUT1/PI O1

A15

TMROUT0/PI O10

A14

TMRI N0/PI O11

A13

DRQ1/PI O13

A12

DRQ0/PI O12

100

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Pin Description

Pin No.(PQFP)

Symbol

Type

Description

15, 21, 38, 61, 67, 92

VCC

Input

System power: +3.3 volt power supply.

12, 18, 41, 64, 70, 89

GND

Input

System ground.

RST

Input*

Reset input. When

is asserted, the CPU immediately

terminate all operation, clears the internal registers & logic,
and the address transfers to the reset address FFFF0h.

Input

Input to the oscillator amplifier.

Output

Output from the inverting oscillator amplifier.

CLKOUTA

Output

Clock output A. The CLKOUTA operation is the same as
crystal input frequency (X1). CLKOUTA remains active during
reset and bus hold conditions.

CLKOUTB

Output

Clock output B. The CLKOUTB operation is the same as
crystal input frequency (X1). CLKOUTB remains active
during reset and bus hold conditions.

Synchronous Serial Port Interface

1
2

SDEN1/PIO23
SDEN0/PIO22

Output/Input

Serial data enables. Active-high. These pins enable data
transfers of the synchronous serial interface. SDEN1 for port1,
SDEN0 for port0.

SCLK/PIO20

Output/Input

Synchronous serial data clock. This pin provides the shift clock
to an external device. SCLK=X1/2, 4, 8 or 16 depending on
register setting. This pin held high during the UART inactive.

100

SDATA/PIO21

Input/Output

Synchronous serial data. This pin provides the shift data to or
receives a serial data from an external device.

Asynchronous Serial Port Interface

TXD/PIO27

Output/Input

Transmit data. This pin transmits asynchronous serial data
from the UART of the microcontroller.

RXD

Input

Receive data. This pin receives asynchronous serial data.

Bus Interface

Bus high enable/address enable. During a memory access, the

and (AD0 or A0) encodings indicate what type of the

bus cycle.

is asserted during T1 and keeps the asserted

to T3 and Tw. This pin is floating during bus hold and reset.

B
H
E

and (AD0 or A0) Encodings

AD0 or A0

Type of Bus Cycle

0
0
1
1

0
1
0
1

Word transfer
High byte transfer (D15-D8)
Low byte transfer (D7-D0)
Refresh

B
H
E

A
D
EN

Output/Input

The address portion of the AD bus can be enabled or disabled
by DA bit in the LMCS and UMCS register during LCS or
UCS bus cycle access, if

is held high during

power-on reset. The

B
H
E

A
D
EN

with a internal weak pull-

up register, so no external pull-up register is required. The AD
bus always drives both address and data during LCS or UCS
bus cycle access, if the

B
H
E

A
D
EN

pin with external pull-

low resister during reset.

Output

Write strobe. This pin indicates that the data on the bus is to be
written into a memory or an I/O device.

is active during

T2, T3 and Tw of any write cycle, floats during a bus hold or

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

reset.

Output

Read Strobe. Active low signal which indicates that the
microcontroller is performing a memory or I/O read cycle.

floats during bus hold or reset.

ALE

Output

Address latch enable. Active high. This pin indicates that an
address output on the AD bus. Address is guaranteed to be
valid on the trailing edge of ALE. This pin is tri-stated during
ONCE mode and is never floating during a bus hold or reset.

ARDY

Input

Asynchronous ready. This pin performs the microcontroller
that the address memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that is
asynchronous to CLKOUTA and is active high. The falling
edge of ARDY must be synchronized to CLKOUTA. Tie
ARDY high, the microcontroller is always asserted in the ready
condition. If the ARDY is not used, tie this pin low to yield
control to SRDY.
Both SRDY and ARDY should be tied to high if the system
need not assert wait state by externality.
Bus cycle status. These pins are encoded to indicate the bus
status.

can be used as memory or I/O indicator.

can be

used as DT/

indicator. These pins are floating during hold

and reset.

Bus Cycle Encoding Description

Bus Cycle

10
11

2
S

1
S

0
S

Output

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
Passive

19
20
22

23-37

39, 40

A19/PIO9
A18/PIO8
A17/PIO7

A16-A2

A1 , A0

Output/Input

Address bus. Non-multiplex memory or I/O address. The A bus
is one-half of a CLKOUTA period earlier than the AD bus.
These pins are high-impedance during bus hold or reset.

78,80,82,84,86,88

91,94

79,81,83,85,87,90

93,95

AD0-AD7

AD8-AD15

Input/Output

The multiplexed address and data bus for memory or I/O
accessing. The address is present during the t1 clock phase, and
the data bus phase is in t2-t4 cycle.
The address phase of the AD bus can be disabled when the

pin with external pull-Low resister during reset.

The AD bus is in high-impedance state during bus hold or reset
condition and this bus also be used to load system
configuration information (with pull-up or pull-Low resister)
into the F6h register when the reset input from low go high.

WHB

Output

Write high byte. This pin indicates the high byte data (AD15-
AD8) on the bus is to be written to a memory or I/O device.
This pin is floating during reset or bus hold.

WLB

Output

Write low byte. This pin indicates the low byte data (AD7-
AD0) on the bus is to be written to a memory or I/O device.
This pin is floating during reset or bus hold.

HLDA

Output

Bus hold acknowledge. Active high. The microcontroller will

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

issue a HLDA in response to a HOLD request by external bus
master at the end of T4 or Ti. When the microcontroller is in
hold status (HLDA is high), the AD15-AD0, A19-A0,

, DT/ ,

and

are

floating, and the

and

will be drive high. After HOLD is detected

as being low, the microcontroller will lower HLDA.

HOLD

Input

Bus Hold request. Active high. This pin indicates that another
bus master is requesting the local bus.

SRDY/PIO6

Input/Output

Synchronous ready. This pin performs the microcontroller that
the address memory space or I/O device will complete a data
transfer. The SRDY pin accepts a falling edge that is
asynchronous to CLKOUTA and is active high. SRDY is
accomplished by elimination of the one-half clock period
required to internally synchronize ARDY. Tie SRDY high the
microcontroller is always assert in the ready condition. If the
SRDY is not used, tie this pin low to yield control to ARDY.

Both SRDY and ARDY should be tied to high if the
system need not assert wait state by externality.

DT/

/PIO4

Output/Input

Data transmit or receive. This pin indicates the direction of
data flow through an external data-bus transceiver. DT/

low,

the microcontroller receives data. When DT/R is asserted high,
the microcontroller writes data to the data bus.

D
E
N

/PIO5

Output/Input

Data enable. This pin is provided as a data bus transceiver
output enable.

is asserted during memory and I/O access.

is drived high when DT/

changes state. It is floating

during bus hold or reset condition.

S6/

/PIO29 Output/Input

Bus cycle status bit6/clock divided by 2. For S6 feature, this
pin is low to indicate a microcontroller-initiated bus cycle or
high to indicate a DMA-initiated bus cycle during T2, T3, Tw
and T4. For

feature. The internal clock of

microcontroller is the external clock be divided by 2.
(CLKOUTA, CLKOUTB=X1/2), if this pin held low during
power-on reset. The pin is sampled on the rising edge of

RST

UZI

/PIO26

Output/Input

Upper zero indicate. This pin is the logical OR of the inverted
A19-A16. It asserts in the T1 and is held throughout the cycle.

Chip Select Unit Interface

50
51
68
69

MCS

/PIO14

MCS

/PIO15

MCS

/PIO24

/PIO25

Output/Input

Midrange memory chip selects. For

feature, these pins

are active low when enable the MMCS(A6h) register to access
a memory. The address ranges are programmable.

are held high during bus hold. When

programming LMCS(A6h) register, pin69 is as a

pin to

auto refresh the PSRAM.

UCS

O
N
CE

Output/Input

Upper memory chip select/ONCE mode request 1. For
feature, this pin acts low when system accesses the defined
portion memory block of the upper 512K bytes (80000h-
FFFFFh) memory region.

default acted address region is

from F0000h to FFFFFh after power-on reset. The address
range acting

is programmed by software. For

feature. If

and

are sampled low on the

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

rising edge of

. The microcontroller enters ONCE mode.

In ONCE mode, all pins are high-impedance. This pin
incorporates weakly pull-up resistor.

LCS

O
N
CE

Output/Input

Lower memory chip select/ONCE mode request 0. For
feature, this pin acts low when the microcontroller accesses the
defined portion memory block of the lower 512K (00000h-
7FFFFh) memory region. The address range acting

programmed by software.
For

feature, see

description. This pin

incorporates weakly pull-up register.

59
60

PCS

/A2/PIO2

PCS

/A1/PIO3

Output/Input

Peripheral chip selects/latched address bit. For

feature,

these pins act low when the microcontroller accesses the fifth
or sixth region of the peripheral memory (I/O or memory
space). The base address of

is programmable. These pins

assert with the AD address bus and are not float during bus
hold.
For latched address bit feature. These pins output the latched
address A2, A1 when cleared the EX bit in the

and

auxiliary register. The A2, A1 retains previous latched

data during bus hold.

62
63
65
66

PCS

/PIO19

PCS

/PIO18

PCS

/PIO17

PCS

/PIO16

Output/Input

Peripheral chip selects. These pins act low when the
microcontroller accesses the defined memory area of the
peripheral memory block (I/O or memory address). For I/O
accessed, the base address can be programmed in the region
00000h to 0FFFFh.
For memory address access, the base address can be located in
the 1M byte memory address region. These pins assert with the
multiplexed AD address bus and are not float during bus hold.

Interrupt Control Unit Interface

NMI

Input

Nonmaskable Interrupt. The NMI is the highest priority
hardware interrupt and is nonmaskable. When this pin is
asserted (NMI transition from low to high), the microcontroller
always transfers the address bus to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt
vector table. The NMI pin must be asserted for at least one
CLKOUTA period to guarantee that the interrupt is recognized.

INT4/PIO30

Input/Output

Maskable interrupt request 4. Act high. This pin indicates that
an interrupt request has occurred. The microcontroller will
jump to the INT4 address vector to execute the service routine
if the INT4 is enable. The interrupt input can be configured to
be either edge- or level-triggered. The requesting device must
holt the INT4 until the request is acknowledged to guarantee
interrupt recognition.

INT3/

/IRQ Input/Output

Maskable interrupt request 3/interrupt acknowledge 1/slave
interrupt request. For INT3 feature, except the difference
interrupt line and interrupt address vector, the function of INT3
is the same as INT4.
For

feature, in cascade mode or special fully-nested

mode, this pin corresponds the INT1.
For IRQ feature, when the microcontroller is as a slave device,
this pin issues an interrupt request to the master interrupt
controller.

INT2/

/PIO31 Input/Output

Maskable interrupt request 2/interrupt acknowledge 0. For
INT2 feature, except the difference interrupt line and interrupt

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

address vector, the function of INT2 is the same as INT4.
For

feature, in cascade mode or special fully-nested

mode, this pin corresponds the INT0.

INT1/

S
E
LECT

Input/Output

Maskable interrupt request 1/slave select. For INT1 feature,
except the difference interrupt line and interrupt address vector,
the function of INT1 is the same as INT4.
For

feature, when the microcontroller is as a slave

device, this pin is drived from the master interrupt controller
decoding. This pin acts to indicate that an interrupt appears on
the address and data bus.
The INT0 must act before

acts when the interrupt

type appears on the bus.

INT0

Input

Maskable interrupt request 0. Except the interrupt line and
interrupt address vector, the function of INT0 is the same as
INT4.

Timer Control Unit Interface

72
75

TMRIN1/PIO0

TMRIN0/PIO11

Input/Output

Timer input. These pins can be as clock or control signal input,
which depend upon the programmed timer mode. After
internally synchronizing low to high transitions on TMRIN, the
timer controller increments. These pins must be pull-up if not
being used.

73
74

TMROUT1/PIO1

TMROUT0/PIO10

Output/Input

Timer output. Depending on timer mode select these pins
provide single pulse or continuous waveform. The duty cycle
of the waveform can be programmable. These pins are floated
during a bus hold or reset.

DMA Unit Interface

76
77

DRQ1/PIO13
DRQ0/PIO12

Input/Output

DMA request. These pins are asserted high by an external
device when the device is ready for DMA channel 1 or channel
0 to perform a transfer. These pins are level-triggered and
internally synchronized. The DRQ signals must remain act
until finish serviced and are not latched.

Notes:

1.When enable the PIO Data register, there are 32 MUX definition pins can be as a PIO pin. For example, the DRD1/PIO13

(pin76) can be as a PIO13 when enable the PIO Data register.

2.The PIO status during Power-On reset : PIO1, PIO10, PIO22, PIO23 are input with pull-down, PIO4 to PIO9 are

normal operation and the others are input with pull-up.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Execution Unit

General Register

The R8800LV has eight 16-bit general registers. And the AX,BX,CX,DX can be subdivided into two 8-bit register

(AH,AL,BH,

BL,CH,CL,DH,DL). Tthe functions of these registers are described as follows.

AX : Word Divide , Word Multiply, Word I/O operation.

AH : Byte Divide , Byte Multiply, Byte I/O , Decimal Arithmetic, Translate operation.

AL : Byte Divide , Byte Multiply operation.

BX : Translate operation.

CX : Loops, String operation

CL : Variable Shift and Rotate operation.

DX : Word Divide , Word Multiply, Indirect I/O operation

SP : Stack operations (POP, POPA, POPF, PUSH, PUSHA, PUSHF)

BP : General-purpose register which can be used to determine offset address of operands in Memory.

SI : String operations

DI : String operations

Segment Register

R8800LV has four 16-bit segment registers, CS, DS, SS, ES. The segment registers contain the base addresses (starting

location) of these memory segments, and they are immediately addressable for code (CS), data (DS & ES), and stack (SS)

memory.

a
t
o r

g
i
s t e r

o
o
p / R e p e a t / S h i f t
o
i
n t e r

t
i
o n I n d e x

i
n
t e r

I
n
d e x

o
u
p

L

REGISTERS

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

CS (Code Segment) : The CS register points to the current code segment, which contains instruction to be fetched. The

default location memory space for all instruction is 64K. The initial value of CS register is 0FFFFh.

DS (Data Segment) : The DS register points to the current data segment, which generally contains program variables. The

DS register initialize to 0000H.

SS (Stack Segment ) : The SS register points to the current stack segment, which is for all stack operations, such as pushes

and pops. The stack segment is used for temporary space. The SS register initialize to 0000H.

ES (Extra Segment) : The ES register points to the current extra segment which is typically for data storage, such as large

string operations and large data structures. The DS register initialize to 0000H.

Instruction Pointer and Status Flags Register

IP (Instruction Pointer) : The IP is a 16-bit register and it contains the offset of the next instruction to be fetched. Software

can not to direct access the IP register and this register is updated by the Bus Interface Unit. It can change, be saved or be

restored as a result of program execution. The IP register initialize to 0000H and the CS:IP starting execution address is at

0FFFF0H.

These flags reflect the status after the Execution Unit is executed.

Bit 15-12 : Reserved

Bit 11: OF, Overflow Flag. An arithmetic overflow has occurred, this flag will be set.

Bit 10 : DF, Direction Flag. If this flag is set, the string instructions are increment address process. If DF is cleared, the string

instructions are decrement address process. Refer the STD and CLD instructions for how to set and clear the DF flag.

g
m
e n t

g
m
e n t
e
g
m e n t

e
g
m e n t

R
E
G I S T E R S

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 9 : IF, Interrupt-Enable Flag. Refer the STI and CLI instructions for how to set and clear the IF flag.

Set to 1 : The CPU enables the maskable interrupt request.

Set to 0 : The CPU disables the maskable interrupt request.

Bit 8: TF, Trace Flag. Set to enable single-step mode for debugging; Clear to disable the single-step mode. If an application

program sets the TF flag using POPF or IRET instruction, a debug exception is generated after the instruction (The

CPU automatically generates an interrupt after each instruction) that follows the POPF or IRET instruction.

Bit 7: SF, Sign Flag. If this flag is set, the high-order bit of the result of an operation is 1

indicating it is negative.

Bit 6: ZF, Zero Flag. The result of operation is zero, this flag is set.

Bit 5: Reserved

Bit 4: AF, Auxiliary Flag. If this flag is set, there has been a carry from the low nibble to the high or a borrow from the high

nibble to the low nibble of the AL general-purpose register. Used in BCD operation.

Bit 3: Reserved.

Bit 2: PF, Parity Flag. The result of low-order 8 bits operation has even parity, this flag is set.

Bit 1: Reserved

Bit 0: CF, Carry Flag. If CF is set, there has been a carry out or a borrow into the high-order bit of the instruction result.

Address generation

The Execution Unit generates a 20-bit physical address to Bus Interface Unit by the Address Generation. Memory is organized

in sets of segments. Each segment contains a 16 bits value. Memory is addressed using a two-component address that consists

of a 16-bit segment and 16-bit offset. The Physical Address Generation figure describes how the logical address transfers to the

physical address.

A
d d r e s s

B
a s e

f
t
4 b i t s

Address Generation

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Peripheral Control Block Register

The peripheral control block can be mapped into either memory or I/O space which is to program the FEh register. And it

starts at FF00h in I/O space when reset the microprocessor.

The following table is the definition of all the peripheral Control Block Register , and the detail description will arrange on

the relation Block Unit.

Offset

(HEX)

Page

Offset

(HEX)

Page

Peripheral Control Block Relocation Register

Timer 2 Mode / Control Register

Reset Configuration Register

Timer 2 Maxcount Compare A Register

Processor Release Level Register

Timer 2 Count Register

PDCON Register

Timer 1 Mode / Control Register

Enable RCU Register

Timer 1 Maxcount Compare B Register

Clock Prescaler Register

Timer 1 Maxcount Compare A Register

Memory Partition Register

Timer 1 Count Register

DA DMA 1 Control Register

Timer 0 Mode / Control Register

DMA 1 Transfer Count Register

Timer 0 Maxcount Compare B Register

DMA 1 Destination Address High Register

Timer 0 Maxcount Compare A Register

DMA 1 Destination Address Low Register

Timer 0 Count Register

DMA 1 Source Address High Register

Serial Port Interrupt Control Register

DMA 1 Source Address Low Register

Watchdog Timer Control Register

CA DMA 0 Control Register

INT4 Control Register

DMA 0 Transfer Count Register

INT3 Control Register

DMA 0 Destination Address High Register

INT2 Control Register

DMA 0 Destination Address Low Register

INT1 Control Register

DMA 0 Source Address High Register

INT0 Control Register

DMA 0 Source Address Low Register

DMA 1 Interrupt Control Register

PCS

and

MCS

Auxiliary Register

DMA 0 Interrupt Control Register

Midrange Memory Chip Select Register

Timer Interrupt Control Register

Peripheral Chip Select Register

Interrupt Status Register

Low Memory Chip Select Register

Interrupt Request Register

Upper Memory Chip Select Register

In-service Register

Serial Port Baud Rate Divisor Register

Priority Mask Register

Serial Port Receive Register

Interrupt Mask Register

Serial Port Transmit Register

Poll Status Register

Serial Port Status Register

Poll Register

Serial Port Control Register

End-of-Interrupt

PIO Data 1 Register

Interrupt Vector Register

PIO Direction 1 Register

Synchronous Serial Receive Register

PIO Mode 1 Register

Synchronous Serial Transmit 0 Register

PIO Data 0 Register

Synchronous Serial Transmit 1 Register

PIO Direction 0 Register

Synchronous Serial Enable Register

PIO Mode 0 Register

Synchronous Serial Status Register

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

The peripheral control block is mapped into either memory or I/O space by programming this register. When the other chip

selects (

PCSx

MCSx

) are programmed to zero wait states and ignore the external ready, the

PCSx

MCSx

can overlap

the control block.

Bit 15: Reserved

Bit 14: S/

, Slave/Master Configures the interrupt controller

set 0 : Master mode, set 1: Slaved mode

Bit 13 : Reserved

Bit 12: M/

, Memory/IO space. At reset, this bit is set to 0 and the PCB map start at FF00h in I/O space.

set 1- The peripheral control block (PCB) is located in memory space.

set 0- The PCB is located in I/O space.

Bit 11-0 : R19-R8 , Relocation Address Bits

The upper address bits of the PCB base address. The lower eight bits default to 00h. When the PCB is mapped to I/O

space, the R19-R16 must be programmed to 0000b.

Read only register that specifies the processor release version and RDC identify number

Bit 15-8 : Processor version

01h : version A , 02h : version B, 03h : version C, 04h : version D

Bit 7-0 : RDC identify number - D9h

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

System Clock Block

Bit 15: PSEN , Enable Power-save Mode. This bit is cleared by hardware when an external interrupt occurs. This bit does not

be changed when software interrupts (INT instruction) and exceptions occurs.

Set 1: enable power-save mode and divides the internal operating clock by the value in F2-F0.

Bit14-12: Reserved

Bit 11: CBF, CLKOUTB Output Frequency selection.

Set 1: CLKOUTB output frequency is same as crystal input frequency.

Set 0 : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor

internal clock.

Bit 10 : CBD, CLKOUTB Drive Disable

Set 1: Disable the CLKOUTB. This pin will be three-state.

Set 0 : Enable the CLKOUTB.

Bit 9: CAF, CLKOUTA Output Frequency selection.

Set 1: CLKOUTA output frequency is same as crystal input frequency.

Set 0 : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor

internal clock .

Bit 8: CAD, CLKOUTA Drive Disable.

Set 1: Disable the CLKOUTA. This pin will be three-state.

L
K
/ 1 2 8 )

.
9
)
.
1
1 )

.
8
)
.
1
0 )

h
.
2 - F 0 h . 0 )

.
1
5 )

S
e
l e c t
V
2

o
c
e s s o r I n t e r n a l C l o c k

Clock

i
s
a b l e

S
e
l e c t

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Set 0 : Enable the CLKOUTA.

Bit 7-3 : Reserved

Bit 2-0: F2- F0, Clock Divisor Select.

F2, F1, F0 ----- Divider Factor

0, 0, 0 ---- Divide by 1

0, 0, 1 ---- Divide by 2

0, 1, 0 ---- Divide by 4

0, 1, 1 ---- Divide by 8

1, 0, 0 ---- Divide by 16

1, 0, 1 ---- Divide by 32

1, 1, 0 ---- Divide by 64

1, 1, 1 ---- Divide by 128

Reset

Processor initialization is accomplished with activation of the

RST

pin. To reset the processor, this pin should be held low

for at least seven oscillator periods. The Reset Status Figure shows the status of the

RST

pin and others relation pins.

When

RST

from low go high , the state of input pin (with weakly pull-up or pull-down) will be latched , and each pin will

perform the individual function. The AD15-AD0 will be latched into the register F6h.

UCS

O
N
CE

LCS

O
N
CE

will

enter ONCE mode (All of the pins will floating except X1 , X2) when with pull-low resisters. The input clock will divide by

2 when S6/

C
L
KDIV

with pull-low resister. The AD15-AD0 bus will not drive the address phase during

UCS

LCS

cycle

B
H
E

A
D
EN

with pull-low resister

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bus Interface Unit

The bus interface unit drives address, data, status and control information to define a bus cycle. The bus A19-A0 are non-

multiplex memory or I/O address. The AD15-AD0 are multiplexed address and data bus for memory or I/O accessing. The

2
S

1
S

are encoded to indicate the bus status, which is described in the Pin Description table in page 5. The Basic

Application System Block (page 10) and Read/Write Timing Diagram (page 12) describe the basic bus operation.

Memory and I/O interface

The memory space consists of 1M bytes (512k 16-bit port) and the I/O space consists of 64k bytes (32k 16-bit port). Memory

devices exchange information with the CPU during memory read, memory write and instruction fetch bus cycles. I/O read

and I/O write bus cycles use a separate I/O address space. Only IN/OUT instruction can access I/O address space, and

information must be transferred between the peripheral device and the AX register. The first 256 bytes of I/O space can be

accessed directly by the I/O instructions. The entire 64k bytes I/O address space can be accessed indirectly, through the DX

Data Bus

The memory address space data bus is physically implemented by dividing the address space into two banks of up to 512k

bytes. Each one bank connects to the lower half of the data bus and contains the even-addressed bytes (A0=0). The other

e
s

n
d
I / O S p a c e

us Models

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

bank connects to the upper half of the data bus and contains odd-addressed bytes (A0=1). A0 and BHE determine whether

one bank or both banks participate in the data transfer.

Wait States

Wait states extend the data phase of the bus cycle. The ARDY or SRDY input with low level will insert wait states. If R2 bit=0,

The user also can inserts wait state by programmed the internal chip select registers.

The R2 bit of UMCS ( offset 0A0h) default is low, so each one of the ARDY or SRDY should in ready

state (with pull high resistor) when at power on reset or external reset.

The wait state counter value is decided by the R3, R1,R0 bits in each chip select register. There are five group R3,R1,R0 bits in

the registers offset A0h, A2h, A4h, A6h, A8h. Each group is independent.

Bus Hold

When the bus hold requested ( HOLD pin active high) by the another bus master, the microprocessor will issue a HLDA

a
t
e

n

c o n t r o l

s
t
e
b l o c k D i a g r a m

eady is active High

t
i
n U M C S d e f a u l t i s " 0 " , s o C P U i s r e q u i r e d

a
l
r e a d y a t p o w e r - o n r e s e t .

a
i
t s t a t e c o u n t e r v a l u e i s l o c a t e d a t

o
l
r e g i s t e r s i n c h i p s e l e c t u n i t .

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Chip Select Unit

The Chip Select Unit provides 12 programmable chip select pins to access a specific memory or peripheral device.

The chip selects are programmed through five peripheral control registers (A0h, A2h, A4h, A6h, A8h). And all of the

chip selects can be insert wait states by programmed the peripheral control register.

U
C
S

The

UCS

default to active on reset for program code access. The memory active range is upper 512k (80000h FFFFFh),

which is programmable. And the default memory active range of

UCS

is 64k ( F0000h FFFFFh).

The

UCS

active to drive low four CLKOUTA oscillators if no wait state inserts. There are three wait-states insert to

UCS

active cycle on reset.

Bit 15 : Reserved

Bit 14-12 : LB2-LB0, Memory block size selection for

UCS

chip select pin.

The

UCS

chip select pin active region can be configured by the LB2-LB0.

The default memory block size is from F0000h to FFFFFh.

LB2, LB1, LB0 ---- Memory Block size , Start address, End Address

1 , 1 , 1 ---- 64k , F0000h , FFFFFh

1 , 1 , 0 ---- 128k , E0000h , FFFFFh

1 , 0 , 0 ---- 256k , C0000h , FFFFFh

0 , 0 , 0 ---- 512k , 80000h , FFFFFh

Bit 11-8 : Reserved

Bit 7 : DA , Disable Address. If the

B
H
E

A
D
EN

pin is held high on the rising edge of

RST

, then the DA bit is valid to

enable/disable the address phase of the AD bus. If the

B
H
E

A
D
EN

pin is held low on the rising edge of

RST

, the

AD bus always drive the address and data.

Set 1 : Disable the address phase of the AD15 AD0 bus cycle when

UCS

is asserted.

Set 0 : Enable the address phase of the AD15 AD0 bus cycle when

UCS

is asserted.

Bit 6-3: Reserved

Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for

UCS

chip select.

Set 1: external ready is ignored.

Set 0: external ready is required.

Bit 1-0 : R1-R0, Wait-State value. When R2 is set to 0, it can inserted wait-state into an access to the

UCS

memory area.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(R1,R0) = (0,0) -- 0 wait-state ; (R1,R0) = (0,1) -- 1 wait-state

(R1,R0) = (1,0) -- 2 wait-state ; (R1,R0) = (1,1) -- 3 wait-state

LCS

The lower 512k bytes (00000h-9FFFFh) memory region chip selects. The memory active range is programmable, which

has no default size on reset. So the A2h register must be programmed first before to access the target memory range. The

LCS

pin is not active on reset, but any read or write access to the A2h register activates this pin.

Bit 15: Reserved

Bit 14-12 : UB2-UB0, Memory block size selection for

LCS

chip select pin

The

LCS

chip select pin active region can be configured by the UB2-UB0.

The

LCS

pin is not active on reset, but any read or write access to the A2h (LMCS) register activates this pin.

UB2, UB1, UB0 ---- Memory Block size , Start address, End Address

0 , 0 , 0 ---- 64k , 00000h , 0FFFFh

0 , 0 , 1 ---- 128k , 00000h , 1FFFFh

0 , 1 , 1 ---- 256k , 00000h , 3FFFFh

1 , 1 , 1 ---- 512k , 00000h , 7FFFFh

Bit 11-8 : Reserved

Bit 7 : DA , Disable Address. If the

B
H
E

A
D
EN

pin is held high on the rising edge of

RST

, then the DA bit is valid to

enable/disable the address phase of the AD bus. If the

B
H
E

A
D
EN

pin is held high on the rising edge of

RST

, the

AD bus always drive the address and data.

Set 1 : Disable the address phase of the AD15 AD0 bus cycle when

LCS

is asserted.

Set 0 : Enable the address phase of the AD15 AD0 bus cycle when

LCS

is asserted.

Bit 6 : PSE, PSRAM Mode Enable. This bit is used to enable PSRAM support for the

LCS

chip select memory space. The

refresh control unit registers E0h,E2h,E4h must be configured for auto refresh before PSRAM support is enabled.

PSE set to 1: PSRAM support is enable

PSE set to 0: PSRAM support is disable

Bit 5-3: Reserved

Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for

LCS

chip select.

Set 1: external ready is ignored.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Set 0: external ready is required.

Bit 1-0 : R1-R0, Wait-State value. When R2 is set to 0, it can inserted wait-state into an access to the

LCS

memory area.

(R1,R0) = (0,0) -- 0 wait-state ; (R1,R0) = (0,1) -- 1 wait-state

(R1,R0) = (1,0) -- 2 wait-state ; (R1,R0) = (1,1) -- 3 wait-state

MCSx

The memory block of

MCS4

MCS0

can be located anywhere within the 1M bytes memory space, exclusive of the

areas associated with the

UCS

and

LCS

chip selects. The maximum

MCSx

active memory range is 512k bytes.

The MCS chip selects are programmed through two registers A6h and A8h, and these select pins are not active on reset. Both

A6h and A8h registers must be accessed with a read or write to activate

MCS4

MCS0

. There aren't default value on A6h

and A8h registers, so the A6h and A8h must be programmed first before

MCS4

MCS0

active.

Bit 15-7 : BA19-BA13, Base Address. The BA19-BA13 correspond to bits 19-13 of the 1M bytes (20-bits) programmable

base address of the

MCS

chip select block. The bits 12 to 0 of the base address are always 0.

The base address can be set to any integer multiple of the size of the memory block size selected in these bits. For

example, if the midrange block is 32Kbytes, only the bits BA19 to BA15 can be programmed. So the block address

could be locate at 20000h or 38000h but not in 22000h.

The base address of the

MCS

chip select can be set to 00000h only if the

LCS

chip select is not active. And the

MCS

chip select address range is not allowed to overlap the

LCS

chip select address range.

The

MCS

chip select address range also is not allowed to overlap the

UCS

chip select address range.

Bit 8-3 : Reserved

Bit 2: R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the

MCS

chip selects. The R1,R0

bits of this register determine the number of wait state to insert.

set to 1: external ready is ignored

set to 0: external ready is required

Bit 1-0 : R1-R0, Wait-State value. The R1,R0 determines the number of wait states inserted into a

MCS

access.

(R1,R0) : (1,1) 3 wait states , (1,0) 2 wait states, (0,1) 1 wait states , (0,0) 0 wait states

A13

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15: Reserved

Bit 14-8: M6-M0,

MCS

Block Size. These bits determines the total block size for the

MCS3

MCS0

chip selects. Each

individual chip select is active for one quarter of the total block size. For example, if the block size is 32K bytes

and the base address is located at 20000h. The individual active memory address range of

MCS3

MCS0

20000h to 21FFF,

MCS1

-22000 to 23FFFh, MCS2- 24000h to 25FFFh, MCS3- 26000h to 27FFFh.

MCS

total block size is defined by M6-M0,

M6-M0 , Total block size, MCSx address active range

0000001b , 8k , 2k

0000010b , 16k , 4k

0000100b , 32k , 8k

0001000b , 64k , 16k

0010000b , 128k , 32k

0100000b , 256k , 64k

1000000b , 512k , 128k

Bit 7 : EX, Pin Selector. This bit configures the multiplex output which the

PCS6

PCS5

pins as chip selects or A2-A1.

Set 1 :

PCS6

PCS5

are configured as peripheral chip select pins.

Set 0:

PCS6

is configured as address bit A2,

PCS5

is configured as A1.

Bit 6: MS, Memory or I/O space Selector.

Set 1: The

PCSx

pins are active for memory bus cycle.

Set 0: The

PCSx

pins are active for I/O bus cycle.

Bit 5-3 : Reserved

Bit 2 : R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS5,PCS6 chip selects. The

R1,R0 bits of this register determine the number of wait state to insert.

set to 1: external ready is ignored

set to 0: external ready is required

Bit 1-0 : R1-R0, Wait-State value. The R1,R0 determines the number of wait states inserted into a

PCS5

PCS6

access.

(R1,R0) : (1,1) 3 wait states , (1,0) 2 wait states, (0,1) 1 wait states , (0,0) 0 wait states

PCSx

The peripheral or memory chip selects which are programmed through A4h and A8h register to define these pins.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

The base address memory block can be located anywhere within the 1M bytes memory space, exclusive of the areas associated

with the

MCS4

LCS

and

MCS

chip elects. If the chip selects are mapped to I/O space, the access range is 64k bytes. PCS6

PCS5 can be configured from 0 wait-state to 3 wait-states.

PCS3

PCS0

can be configured from 0 wait-state to 15 wait-

states.

Bit 15-7 : BA19-BA11, Base Address. BA19-BA11 correspond to bit 19-11 of the 1M bytes (20-bits) programmable base

address of the

PCS

chip select block.

When the

PCS

chip selects are mapped to I/O space, BA19-BA16 must be wrote to 0000b because the I/O address

bus in only 64K bytes (16-bits) wide.

PCSx

address range:

PCS0

: Base Address - Base Address + FFh

PCS1

: Base Address + 100h - Base Address + 1FFh

PCS2

: Base Address + 200h - Base Address + 2FFh

PCS3

: Base Address + 300h - Base Address + 3FFh

PCS5

: Base Address + 500h - Base Address + 5FFh

PCS6

: Base Address + 600h - Base Address + 6FFh

Bit 6-4: Reserved

Bit 3: R3; Bit 1-0: R1,R0 ,Wait-State Value. The R3,R1,R0 determines the number of wait-states inserted into a

PCS3

PCS0

access.

R3, R1, R0 -- Wait States

0, 0, 0 -- 0

0, 0, 1 -- 1

0, 1, 0 -- 2

0, 1, 1 -- 3

1, 0, 0 -- 5

1, 0, 1 -- 7

1, 1, 0 -- 9

1, 1, 1 -- 15

Bit 2 : R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the

PCS3

PCS0

chip selects.

The R3,R1,R0 bits determine the number of wait state to insert.

set to 1: external ready is ignored

A11

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Interrupt Controller Unit

There are twelve interrupt requests source connect to the controller: five maskable interrupt pins ( INT0 INT4); one non-

maskable interrupt pin (NMI) ; Six internal unit request source ( Timer 0, 1,2 ;DMA 0,1 ; Asynchronous serial unit).

Master Mode and Slave Mode

The interrupt controller can be programmed as a master or slave mode. (program FEh , bit 14). The master mode has two

connections : Fully Nested Mode connection or Cascade Mode connection.

l
a
v e M o d e S e l e c t

/
2

t

R E Q .

E
Q
.

e
r
r u p t R E Q .
e
r
r u p t R E Q .

n
o
u s S e r i a l P o r t

o
n

p
t
T y p e

p
t
R E Q .
i
c
e

e
d
g e

d
g
e t o D M A ,

r
i
a l p o r t U n i t

A
d d r e s s / D a t a B u s

t

Control Unit Block Diagram

e
e

de Connections

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Interrupt Vector, Type and Priority

The following table shows the interrupt vector addresses, type and the priority. The maskable interrupt priority can be changed

by programmed the priority register. The Vector addresses for each interrupt are fixed.

Interrupt source

Interrupt

Type

Vector

Address

EOI

Type

Priority

Note

Divide Error Exception

00h

Trace interrupt

01h

04h

1-1

NMI

02h

08h

1-2

Breakpoint Interrupt

03h

0Ch

INTO Detected Over Flow Exception 04h

10h

Array Bounds Exception

05h

14h

Mode Connection

S
0
S
0

p
t
S o u r c e s

p
t
S o u r c e s
p
t
S o u r c e s

p
t
S o u r c e s

nection

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Undefined Opcode Exception

06h

18h

ESC Opcode Exception

07h

1Ch

Timer 0

08h

20h

2-1

*/**

Reserved

09h

DMA 0

0Ah

28h

DMA 1

0Bh

2Ch

INT0

0Ch

30h

INT1

0Dh

34h

INT2

0Eh

38h

INT3

0Fh

3Ch

INT4

10h

40h

Watchdog Timer

11h

44h

Timer 1

12h

48h

2-2

*/**

Timer 2

13h

4Ch

2-3

*/**

Asynchronous Serial port

14h

50h

Reserved

15h-1Fh

Note * : When the interrupt occurs in the same time, the priority is (1-1 > 1-2) ; (2-1> 2-2 > 2-3)

Note **: The interrupt types of these sources are programmable in slave mode.

Interrupt Request

When an interrupt is request, the internal interrupt controller verifies the interrupt is enable (The IF flag is enable, no MSK bit

set ) and that there are no higher priority interrupt requests being serviced or pending. If the interrupt is granted , the interrupt

controller uses the interrupt type to access a vector from the interrupt vector table.

If the external INT is active (level-trigger) to request the interrupt controller service, and the INT pins must hold till the

microcontroller enter the interrupt service routine. There is no interrupt-acknowledge output when running in fully nested

mode, so it should use PIO pin to simulate the interrupt-acknowledge pin if necessary.

Interrupt Acknowledge

The processor requires the interrupt type as an index into the interrupt table. The internal interrupt can provide the interrupt

type or an external controller can provide the interrupt type.

The internal interrupt controller provides the interrupt type to processor without external bus cycles generation. When an

external interrupt controller is supplying the interrupt type, the processor generates two acknowledge bus cycles, and the

interrupt type is written to the AD7-AD0 lines by the external interrupt controller.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 2-0 : PR2-PR0, Priority. These bits determine the priority of the serial port relative to the other interrupt signals.

The priority selection:

PR2, PR1, PR0 -- Priority

0 , 0 , 0 -- 0 ( High)

0 , 0 , 1 -- 1

0 , 1 , 0 -- 2

0 , 1 , 1 -- 3

1 , 0 , 0 -- 4

1 , 0 , 1 -- 5

1 , 1 , 0 -- 6

1 , 1 , 1 -- 7 ( Low )

(Master Mode)

Bit 15- 8, bit 6-5 : Reserved

Bit 7 : ETM, Edge trigger mode enable. When this bit set to 1 and Bit 4 set to 0, the Interrupt is triggered by low go high edge.

The low go high edge will be latched ( one level ) till this interrupt is been serviced.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT4

Set 0: Enable the INT4 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of 42h

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(Master Mode)

Bit 15- 8, bit 6-5 : Reserved

Bit 7:ETM, Edge trigger mode enable. When this bit set to 1 and Bit 4 set to 0, the Interrupt is triggered by low go high edge

The low go high edge will be latched ( one level ) till this interrupt is been serviced.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT3

Set 0: Enable the INT3 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of 42h

(Master Mode)

Bit 15-8, bit 6- 5 : Reserved

Bit 7 : ETM, Edge trigger mode enable. When this bit set to 1 and Bit 4 set to 0, the Interrupt is triggered by low go high edge.

The low go high edge will be latched ( one level ) till this interrupt is been serviced.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT2

Set 0: Enable the INT2 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(Master Mode)

Bit 15-8 : Reserved

Bit 7 : ETM, Edge trigger mode enable. When this bit set to 1 and Bit 4 set to 0, the Interrupt is triggered by low go high edge.

The low go high edge will be latched ( one level ) till this interrupt is been serviced.

Bit 6: SFNM, Special Fully Nested Mode.

Set 1: Enable the special fully nested mode of INT1

Bit 5: C, Cascade Mode, Set this bit to 1 to enable cascade mode.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT1

Set 0: Enable the INT1 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Slave Mode), Timer 2 interrupt control register , reset value is 0000h

Bit 15- 4 : Reserved

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the Timer 2

Set 0: Enable the Timer 2 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode)

Bit 15-8 : Reserved

Bit 7 : ETM, Edge trigger mode enable. When this bit set to 1 and Bit 4 set to 0, the Interrupt is triggered by low go high edge.

The low go high edge will be latched ( one level ) till this interrupt is been serviced.

Bit 6: SFNM, Special Fully Nested Mode.

Set 1: Enable the special fully nested mode of INT0.

Bit 5: C, Cascade Mode, Set this bit to 1 to enable cascade mode.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT0

Set 0: Enable the INT0 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Slave Mode), Timer 1 interrupt control register , reset value is 0000h

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the timer 1

Set 0: Enable the timer 1 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the DMA 1 controller

Set 0: Enable the DMA 1 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Slave Mode), DMA 1 interrupt control register , reset value is 0000h

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the DMA 1 controller

Set 0: Enable the DMA 1 controller interrupt.

Bit 2-0: PR, Interrupt Priority

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the DMA 0 controller

Set 0: Enable the DMA 0 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Slave Mode), reset value is 0000h

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the DMA 0 controller

Set 0: Enable the DMA 0 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the Timer controller

Set 0: Enable the Timer controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(Slave Mode), Timer 0 interrupt control register , reset value is 0000h

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the Timer 0 controller

Set 0: Enable the Timer 0 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode),

Reset value undifine

Bit 15 : DHLT, DMA Halt.

Set 1: halts any DMA activity. When non-maskable interrupts occur.

Set 0: When an IRET instruction is excuted.

Bit 14-3 : Reserved.

Bit 2-0 : TMR2-TMR0,

Set 1: indicates the corresponding timer has an interrupt request pending.

(Slave Mode), Reset value is 0000h

Bit 15 : DHLT, DMA Halt.

Set 1: halts any DMA activity. When non-maskable interrupts occur.

Set 0: When an IRET instruction is executed.

Bit 14-3 : Reserved.

Bit 2-0 : TMR2-TMR0,

Set 1: indicates the corresponding timer has an interrupt request pending.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(Master Mode)

The Interrupt Request register is a read-only register. For internal interrupts (SPI, WD, D1, D0, and TMR), the corresponding

bit is set to 1 when the device requests an interrupt. The bit is reset during the internally generated interrupt acknowledge. For

INT4-INT0 external interrupts, the corresponding bit (I4-I0) reflects the current value of the external signal.

Bit 15-11 : Reserved.

Bit 10 : SPI, Serial Port Interrupt Request. Indicates the interrupt state of the serial port.

Bit 9 : WD, Watchdog Timer Interrupt Request.

Set 1: The Watchdog Timer has an interrupt pending.

Bit 8-4 : I4-I0, Interrupt Requests.

Set 1: The corresponding INT pin has an interrupt pending.

Bit 3-2 : D1-D0, DMA Channel Interrupt Request.

Set 1: The corresponding DMA channel has an interrupt pending.

Bit 1: Reserved.

Bit 0 : TMR, Timer Interrupt Request.

Set 1: The timer control unit has an interrupt pending.

(Slave Mode)

The Interrupt Request register is a read-only register. For internal interrupts (D1, D0, TMR2, TMR1, and TMR0), the

corresponding bit is set to 1 when the device requests an interrupt. The bit is reset during the internally generated interrupt

acknowledge.

Bit 15-6 : Reserved.

Bit 5-4 : TMR2/TMR1, Timer2/Timer1 Interrupt Request.

Set 1: Indicates the state of any interrupt requests form the associated timer.

Bit 3-2 : D1-D0, DMA Channel Interrupt Request.

Set 1: Indicates the corresponding DMA channel has an interrupt pending.

Bit 1 : Reserved.

Bit 0 : TMR0, Timer 0 Interrupt Request.

Set 1: Indicates the state of an interrupt request from Timer 0.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(Master Mode)

The bits in the INSERV register are set by the interrupt controller when the interrupt is taken. Each bit in the register is cleared

by writing the corresponding interrupt type to the EOI register.

Bit 15-11 : Reserved.

Bit 10 : SPI, Serial Port Interrupt In-Service.

Set 1: the serial port interrupt is currently being serviced.

Bit 9 : WD, Watchdog Timer Interrupt In-Service.

Set 1: the watchdog timer interrupt is currently being serviced.

Bit 8-4 : I4-I0, Interrupt In-Service.

Set 1: the corresponding INT interrupt is currently being serviced.

Bit 3-2 : D1-D0, DMA Channel Interrupt In-Service.

Set 1: the corresponding DMA channel interrupt is currently being serviced.

Bit 1 : Reserved.

Bit 0 : TMR, Timer Interrupt In-Service.

Set 1: the timer interrupt is currently being serviced.

(Slave Mode)

The bits in the In-Service register are set by the interrupt controller when the interrupt is taken. The in-

service bits are

cleared by writing to the EOI register.

Bit 15-6 : Reserved.

Bit 5-4 : TMR2-TMR1, Timer2/Timer1 Interrupt In-Service.

Set 1: the corresponding timer interrupt is currently being serviced.

Bit 3-2 : D1-D0, DMA Channel Interrupt In-Service.

Set 1: the corresponding DMA Channel is currently being serviced.

Bit 1 : Reserved.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 0 : TMR0, Timer 0 Interrupt In-Service.

Set 1: the Timer 0 interrupt is currently being serviced.

(Master Mode)

Determining the minimum priority level at which maskable interrupts can generate an interrupt.

Bit 15-3 : Reserved.

Bit 2-0 : PRM2-PRM0, Priority Field Mask. Determining the minimum priority that is required in order for a maskable

interrupt source to generate an interrupt.

Priority

PR2-PR0

(High) 0

000

001

010

011

100

101

110

(Low) 7

111

(Slave Mode)

Determining the minimum priority level at which maskable interrupts can generate an interrupt.

Bit 15-3 : Reserved.

Bit 2-0 : PRM2-PRM0, Priority Field Mask. Determining the minimum priority that is required in order for a maskable

interrupt source to generate an interrupt.

Priority

PR2-PR0

(High) 0

000

001

010

011

100

101

110

(Low) 7

111

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(Master Mode)

Bit 15-11 : Reserved.

Bit 10 : SPI, Serial Port Interrupt Mask. The state of the mask bit of the asynchronous serial port interrupt.

Bit 9 : WD, Virtual Watchdog Timer Interrupt Mask. The state of the mask bit of the Watchdog Timer interrupt.

Bit 8-4 : I4-I0, Interrupt Masks. Indicates the state of the mask bit of the corresponding interrupt.

Bit 3-2 : D1-D0, DMA Channel Interrupt Masks. Indicates the state of the mask bit of the corresponding DMA Channel

interrupt.

Bit 1: Reserved.

Bit 0 : TMR, Timer Interrupt Mask. The state of the mask bit of the timer control unit .

(Slave Mode)

Bit 15-6 : Reserved.

Bit 5-4 : TMR2-TMR1, Timer 2/Timer1 Interrupt Mask. The state of the mask bit of the Timer Interrupt Control register.

Set 1: Timer2 or Time1 has its interrupt requests masked

Bit 3-2 : D1-D0, DMA Channel Interrupt Mask. The state of the mask bits of the corresponding DMA control register.

Bit 1 : Reserved.

Bit 0 : TMR0, Timer 0 Interrupt Mask. The state of the mask bit of the Timer Interrupt Control Register

(Master mode)

The Poll Status (POLLST) register mirrors the current state of the Poll register. the POLLST register can be read without

affecting the current interrupt request.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15 : IREQ, Interrupt Request.

Set 1: if an interrupt is pending. The S4-S0 field contains valid data.

Bit 14-5 : Reserved.

Bit 4-0 : S4-S0, Poll Status. Indicates the interrupt type of the highest priority pending interrupt.

(Master mode)

When the Poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll register.

Bit 15 : IREQ, Interrupt Request.

Set 1: if an interrupt is pending. The S4-S0 field contains valid data.

Bit 14-5 : Reserved.

Bit 4-0 : S4-S0, Poll Status. Indicates the interrupt type of the highest priority pending interrupt.

(Master Mode)

Bit 15 : NSPEC, Non-Specific EOI.

Set 1: indicates non-specific EOI.

Set 0: indicates the specific EOI interrupt type in S4-S0.

Bit 14-5 : Reserved.

Bit 4-0: S4-S0, Source EOI Type. Specifies the EOI type of the interrupt that is currently being processed.

(Slave Mode)

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15-3 : Reserved.

Bit 2-0 : L2-L0, Interrupt Type. Encoded value indicating the priority of the IS(interrupt service) bit to reset. Writes to these

bits cause an EOI to be issued for the interrupt type in slave mode.

(

Slave Mode)

Bit 15-8 : Reserved

Bit 7-3 : T4-T0, Interrupt Type.

The following interrupt type of slave mode can be programmed.

Timer 2 interrupt controller : (T4,T3,T2,T1,T0, 1, 0, 1)b

Timer 1 interrupt controller : (T4,T3,T2,T1,T0, 1, 0, 0)b

DMA 1 interrupt controller : (T4,T3,T2,T1,T0, 0, 1, 1)b

DMA 0 interrupt controller : (T4,T3,T2,T1,T0, 0, 1, 0)b

Timer 0 interrupt controller : (T4,T3,T2,T1,T0, 0, 0, 0)b

Bit 2-0 :Reserved

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

DMA Unit

The DMA controller provides the data transfer between the memory and peripherals without the intervention of the CPU.

There are two DMA channels in the DMA unit. Each channel can accept DMA request from one of two source :

external pin (DRQ0 for channel 0 or DRQ1 for channel 1) or Timer 2 overflow. The data transfer from source to destination

can be memory to memory or memory, to I/O, or I/O to I/O, or I/O to memory. Either bytes or words can be transferred to or

from even or odd addresses and two bus cycles are necessary (read from source and write to destination) for each data transfer.

DMA Operation

Every DMA transfer consists of two bus cycles (figure of Typical DMA Transfer) and the two bus cycles can not be separated

by a bus hold request, a refresh request or another DMA request. The registers ( CAh, C8h, C6h, C4h, C2h, C0h, DAh, D8h,

D6h, D4h, D2h, D0h) are used to configure and operate the two DMA channels.

n
t
r o l

d
d
e r / S u b t r a c t o r

s
f
e r C o u n t e r C h a n n e l 0

D
e
s t i n a t i o n A d d r e s s C h a n n e l 0

S
o
u r c e A d d r e s s C h a n n e l 0

s
f
e r C o u n t e r C h a n n e l 1

D
e
s t i n a t i o n A d d r e s s C h a n n e l 1

S
o
u r c e A d d r e s s C h a n n e l 1

t
i
o n

p
t
R e q u e s t

h
a
n n e l 0
h
a
n n e l 1

C
o
n t r o l R e g i s t e r 1 , D A h

C
o
n t r o l R e g i s t e r 0 , C A h

A
d d r e s s / D a t a B u s

R
e q u e s t

h
a
n n e l 0

h
a
n n e l 1

it

Block

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 3-0: DDA19-DDA16, High DMA 0 Destination Address. These bits are map to A19- A16 during a DMA transfer when

the destination address is in memory space or I/O space. If the destination address is in I/O space (64Kbytes), these

bits must be programmed to 0000b.

Bit 15-0: DDA15-DDA0, Low DMA 0 Destination Address. These bits are mapped to A15- A0 during a DMA transfer.

The value of (DDA19-DDA0)b will increment or decrement by 2 after each DMA transfer.

Bit 15-4: Reserved

Bit 3-0: DSA19-DSA16, High DMA 0 Source Address. These bits are mapped to A19- A16 during a DMA transfer when the

source address is in memory space or I/O space. If the source address is in I/O space (64Kbytes), these bits must be

programmed to 0000b.

Bit 15-0: DSA15-DSA0, Low DMA 0 Source Address. These bits are mapped to A15- A0 during a DMA transfer.

The value of (DSA19-DSA0)b will increment or decrement by 2 after each DMA transfer.

DDA0

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15:

, Destination Address Space Select.

Set 1: The destination address is in memory space.

Set 0: The destination address is in I/O space.

Bit 14: DDEC, Destination Decrement.

Set 1: The destination address is automatically decrement after each transfer.

The

/W (bit 0) bit determines the decrement value which is by 1 or 2 When both DDEC and DINC bits are

set to 1, the address remains constant

Set 0 : Disable the decrement function.

Bit 13: DINC, Destination Increment.

Set 1: The destination address is automatically increment after each transfer.

The

/W (bit 0) bit determines the increment value which is by 1 or 2

Set 0 : Disable the decrement function.

Bit 12: SM/

, Source Address Space Select.

Set 1: The Source address is in memory space.

Set 0: The Source address is in I/O space

Bit 11: SDEC, Source Decrement.

Set 1: The Source address is automatically decrement after each transfer.

The

/W (bit 0) bit determines the decrement value which is by 1 or 2 When both SDEC and SINC bits are set

to 1, the address remains constant

Set 0 : Disable the decrement function.

Bit 10: SINC, Source Increment.

Set 1: The Source address is automatically increment after each transfer.

The

/W (bit 0) bit determines the increment value which is by 1 or 2

Set 0 : Disable the decrement function

Bit 9 : TC, Terminal Count.

Set 1: The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0.

Set 0: The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0.

Unsynchronized DMA transfer is always terminated when the DMA transfer count register reaches 0,

regardless the setting of this bit.

Bit 8 : INT, Interrupt.

Set 1: DMA unit generates an interrupt request when complete the transfer count .

The TC bit must set to 1 to generate an interrupt.

Bit 7-6: SYN1-SYN0, Synchronization Type Selection.

SYN1 , SYN0 -- Synchronization Type

0 , 0 -- Unsynchronized

0 , 1 -- Source synchronized

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

1 , 0 -- Destination synchronized

1 , 1 -- Reserved

Bit 5: P , Priority.

Set 1: It selects high priority for this channel when both DMA 0 and DMA 1 are transfer in same time.

Bit 4: TDRQ, Timer Enable/Disable Request

Set 1: Enable the DMA requests from timer 2.

Set 0: Disable the DMA requests from timer 2.

Bit 3: Reserved

Bit 2: CHG, Changed Start Bit. This bit must set to 1 when will modify the ST bit.

Bit 1: ST, Start/Stop DMA channel.

Set 1: Start the DMA channel

Set 0: Stop the DMA channel

Bit 0 :

/W, Byte/Word Select.

Set 1: The address is incremented or decremented by 2 after each transfer.

Set 0 :The address is incremented or decremented by 1 after each transfer.

Bit 15-0: TC15-TC0, DMA 1 transfer Count. The value of this register is decremented by 1 after each transfer.

Bit 15-4: Reserved

Bit 3-0: DDA19-DDA16, High DMA 1 Destination Address. These bits are map to A19- A16 during a DMA transfer when

the destination address is in memory space or I/O space. If the destination address is in I/O space (64Kbytes), these

bits must be programmed to 0000b.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15-0: DDA15-DDA0, Low DMA 1 Destination Address. These bits are mapped to A15- A0 during a DMA transfer.

The value of (DDA19-DDA0)b will increment or decrement by 2 after each DMA transfer.

Bit 15-4: Reserved

Bit 3-0: DSA19-DSA16, High DMA 1 Source Address. These bits are mapped to A19- A16 during a DMA transfer when the

source address is in memory space or I/O space. If the source address is in I/O space (64Kbytes), these bits must be

programmed to 0000b.

Bit 15-0: DSA15-DSA0, Low DMA 1 Source Address. These bits are map to A15- A0 during a DMA transfer.

The value of (DSA19-DSA0)b will increment or decrement by 2 after each DMA transfer.

External Requests

External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling edge of CLKOUTA. It takes a

minimum of four clocks before the DMA cycle is initiated by the Bus Interface. The DMA request is cleared four clocks

before the end of the DMA cycle. And no DMA acknowledge is provided, since the chip-selects (MCSx, PCSx) can be

programmed to be active for a given block of memory or I/O space, and the DMA source and destination address registers can

be programmed to point to the same given block.

DMA transfer can be either source or destination synchronized, and it can also be unsynchronized. The Source-Synchronized

Transfer figure shows the typical source-synchronized transfer which provides the source device at least three clock cycles

from the time it is acknowledged to deassert its DRQ line.

DDA0

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

The Destination-Synchronized Transfer figure shows the typical destination-synchronized transfer which differs from a source-

synchronized transfer in that two idle states are added to the end of the deposit cycle. The two idle states extend the DMA

cycle to allow the destination device to deassert its DRQ pin four clocks before the end of the cycle. If the two idle states were

not inserted, the destination device would not have time to deassert its DRQ signal.

1
)

2
)

c
l
e

y
c
l e

Synchronized Transfers

Current source synchronized transfer will not be immediately

followed by another DMA transfer.

Current source synchronized transfer will be immediately

followed by antoher DMA transfer.

chronized Transfers

t

destination synchronized transfer will not be immediately

wed by another DMA transfer.

t

destination synchronized transfer will be immediately

wed by another DMA transfer.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Timer Control Unit

There are three 16-bit programmable timers in the R8800LV. The timer operation is independent of the CPU. The three timers

can be programmed as a timer element or as a counter element. Timers 0 and 1 are each connect to two external pins (TMRIN0,

TMROUT0, TMRIN1, TMROUT1) which can be used to count or time external events, or they can be used to generate a

variable-duty-cycle waveforms. Timer 2 is not connected any external pins. It can be used as a prescale to timer 0 and timer 1

or as a DMA request source.

These bits definition for timer 0 are same as the bits of register 5Eh for timer 1.

l
o
c k

t

R e g i s t e r

a
r
e R e g i s t e r

a
x
c o u n t C o m p a r e R e g i s t e r

M
a
x c o u n t C o m p a r e R e g i s t e r

t

R e g i s t e r

s
t
r
o
l R e g i s t e r

r
o
l R e g i s t e r

/
D
a t a B u s

Unit Block

r
o
l R e g i s t e r

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15 0: TC15-TC0, Timer 0 Count Value. This register contains the current count of timer 0. The count is incremented by

one every four internal processor clocks or by prescaled the timer 2, or by one every four external clock which is

configured the external clock select bit to refer the TMRIN1 signal.

Bit 15-0 : TC15 TC0, Timer 0 Compare A Value.

Bit 15-0 : TC15 TC0, Timer 0 Compare B Value.

Bit 15: EN, Enable Bit.

Set 1: The timer 1 is enable.

Set 0: The timer 1 is inhibited from counting.

The

INH

bit must be set 1 during writing the EN bit, and the

INH

bit and EN bit must be in the same write.

Bit 14:

INH

, Inhibit Bit. This bit is allows selective updating the EN bit. The

INH

bit must be set 1 during writing the EN

bit, and both the

INH

bit and EN bit must be in the same write. This bit is not stored and is always read as 0.

Bit 13: INT, Interrupt Bit.

Set 1: A interrupt request is generated when the count register equals a maximum count. If the timer is configured in

dual max-count mode, an interrupt is generated each time the count reaches max-count A or max-count B

Set 0: Timer 1 will not issue interrupt request.

Bit 12: RIU, Register in Use Bit.

Set 1: The Maxcount Compare B register of timer 1 is being used

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Set 0: The Maxcount Compare A register of timer 1 is being used

Bit 11-6 : Reserved.

Bit 5: MC, Maximum Count Bit. When the timer reaches its maximum count, the MC bit will set to 1 by H/W. In dual

maxcount mode, this bit is set each time either Maxcount Compare A or Maxcount Compare B register is reached. This

bit is set regardless of the EN bit (66h.15).

Bit 4: RTG, Re-trigger Bit. This bit define the control function by the input signal of TMRIN1 pin. When EXT=1 (5Eh.2),

this bit is ignored.

Set 1: Timer1 Count Register (58h) counts internal events; Reset the counting on every TMRIN1 input signal from low

go high (rising edge trigger).

Set 0: Low input holds the timer 1 Count Register (58h) value; High input enables the counting which counts internal

events.

The definition of setting the (EXT , RTG )

( 0 , 0 ) Timer1 counts the internal events. if the TMRIN1 pin remains high.

( 0 , 1 ) -- Timer1 counts the internal events; count register reset on every rising transition on the TMRIN1 pin

( 1 , x ) -- TMRIN1 pin input acts as clock source and timer1 count register increase one every four external clock.

Bit 3: P, Prescaler Bit. This bit and EXT(5Eh.2) define the timer 1 clock source.

The definition of setting the (EXT , P )

( 0 , 0 ) Timer1 Count Register increase one every four internal processor clock.

( 0 , 1 ) Timer1 count register increase one which prescal by timer 2.

( 1 , x ) -- TMRIN1 pin input acts as clock source and Timer1 Count Register increase one every four external clock.

Bit 2: EXT, External Clock Bit.

Set 1: Timer 1 clock source from external

Set 0: Timer 1 clock source from internal

Bit 1 : ALT, Alternate Compare Bit. This bit controls whether the timer runs in single or dual maximum count mode.

Set 1: Specify dual maximum count mode. In this mode the timer counts to Maxcount Compare A, then resets the

count register to 0. Then the timer counts to Maxcount Compare B, then resets the count register to 0 again,

and starts over with Maxcount Compare A.

Set 0: Specify single maximum count mode. In this mode the timer will count to the valve contained in Maxcount

Compare A and reset to 0, and then the timer counts to Maxcount Compare A again. Maxcount Compare B is

not used in this mode.

Bit 0: CONT, Continuous Mode Bit.

Set 1: The timer to run continuously.

Set 0: The timer will halt after each counting to the maximum count and the EN bit will be cleared.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15 0: TC15-TC0, Timer 1 Count Value. This register contains the current count of timer 1. The count is incremented by

one every four internal processor clocks or by prescaled the timer 2, or by one every four external clock which is

configured the external clock select bit to refer the TMRIN1 signal.

Bit 15-0 : TC15 TC0, Timer 1 Compare A Value.

Bit 15-0 : TC15 TC0, Timer 1 Compare B Value.

Bit 15: EN, Enable Bit.

Set 1: The timer 2 is enable.

Set 0: The timer 2 is inhibited from counting.

The

INH

bit must be set 1 during writing the EN bit, and the

INH

bit and EN bit must be in the same write.

Bit 14:

INH

, Inhibit Bit. This bit is allows selective updating the EN bit. The

INH

bit must be set 1 during writing the EN

bit, and both the

INH

bit and EN bit must be in the same write. This bit is not stored and is always read as 0.

Bit 13: INT, Interrupt Bit.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Set 1: A interrupt request is generated when the count register equals a maximum count.

Set 0: Timer 2 will not issue interrupt request.

Bit 12-6 : Reserved.

Bit 5: MC, Maximum Count Bit. When the timer reaches its maximum count, the MC bit will set to 1 by H/W. This bit is set

regardless of the EN bit (66h.15).

Bit 4-1: Reserved.

Bit 0: COUNT, Continuous Mode Bit.

Set 1: Timer is continuously running when timer reaches the maximum count.

Set 0: The EN bit (66h.15) is cleared and the timer is hold after each timer count reaches the maximum count.

Bit 15 0: TC15-TC0, Timer 2 Count Value. This register contains the current count of timer 2. The count is incremented by

one every four internal processor clocks.

Bit 15-0 : TC15 TC0, Timer 2 Compare A Value.

Watchdog Timer

Timer 1 can also be configure as a watchdog timer. Software must fist programmed the Timer 1 Mode/Control (5Eh), Count

(58h), and Max Count (5Ah, 5Ch) registers and then program the Watchdog Timer Interrupt Control Register ( 42h) to enable

the watchdog timer interrupt , The Timer 1 Count Register must be reloaded at intervals less than the Timer 1 Maxcount value

to assure the watchdog interrupt is not occurred.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the watchdog timer

Set 0: Enable the watchdog timer interrupt.

Bit 2- 0: PR, Priority.

The priority selection:

PR2, PR1, PR0 -- Priority

0 , 0 , 0 -- 0 (High)

0 , 0 , 1 -- 1

0 , 1 , 0 -- 2

0 , 1 , 1 -- 3

1 , 0 , 0 -- 4

1 , 0 , 1 -- 5

1 , 1 , 0 -- 6

1 , 1 , 1 -- 7 (Low )

Timer/Counter Unit Output Mode

Timers 0 and 1 can use one maximum count value or two maximum count value. Timer 2 can use only one maximum count

value. Timer 0 and timer1 can be configured to single or dual Maximum Compare count mode, the TMROUT0 or TMROUT1

signals can be used to generated waveform of various duty cycle.

t

A

t

B

i
m
u m

d
e

a
x
i m u m
d
e

t

A

M
i c r o p r o c e s s o r c l o c k

ounter Unit Output Modes

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Asynchronous Serial Port

R8800LV asynchronous serial port provides the TXD, RXD pins for the full duplex bi-directional data transfer and without

handshaking signals. The UART port supports : 8-bit or 7-bit data transfer; odd parity, even parity, or no parity; 1 or 2 stop bits.

DMA transfers through the serial port are not supported

The receive/transmit clock is based on the microprocessor clock. The serial port can be used in power-saved mode, but the

transfer rate must be adjusted to correctly reflect the new internal operating frequency. Software is programmed through the

80h, 82h, 84h, 86h, 88h registers to configure the asynchronous serial port.

Bit 15-12: Reserved

Bit 11: TXIE, Transmit Holding Register Empty Interrupt Enable.

This bit is set 1 to enable serial port to generates an interrupt request when the transmit holding register is empty.

Bit 9: LOOP, Loopback.

Set 1: The serial port in the loopback mode. In this mode, the transmit shift register is connect to the transmit shift

Bit 8: BRK, Send Break.

h
)

6
h
)
(
8
0 h )

8
2
h )

(
8
8 h )

/
D
a t a B u s

k

Diagram

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

It should to check the TEMT bit (82h.6) is a 1 before setting the BRK bit.

Set 1: The serial port send a frame of continues level output on the TXD pin and the output level depends on the

BRAVAL bit status, when any data is written to transmit data register.

Bit 7: BRKVAL, Break Value.

Set 1: TXD pin continuous drive high level signal during send break operation.

Set 0: TXD pin continuous drive low level signal during send break operation.

Bit 6-5: PMODE, Parity Mode. Parity generation and checking during transmission and reception.

Parity mode selection by (Bit 6 , Bit 5) : ( 0 , x) No parity bit in frame , ( 1 , 0) Odd number of 1s in frame.

( 1 , 1 ) Even number of 1s in frame.

Bit 4: WLGN, Word Length.

Set 1: The serial port sends and receives 8 bits of data per frame.

Set 0: The serial port sends and receives 7 bits of data per frame.

Bit 3: STP, Stop Bits.

Set 1: Two stop bits are used to signify the end of a frame.

Set 0: One stop bit are used to signify the end of a frame.

Bit 2: TMODE, Transmit Mode.

Set 1: Enable the transmit section of the serial port.

Set 0: Disable the transmit section of the serial port.

Bit 1: RSIE, Receive Status interrupt Enable.

Set 1: Enable the receive section of serial port to generate an interrupt

Set 0: Disable the receive section of serial port to generate an interrupt

Bit 0: RMODE, Receive Mode.

Set 1: Enable the receive section of the serial port.

Set 0: Disable the receive section of the serial port.

Bit 15-7 : Reserved

Bit 6: TEMT, Transmitter Empty. Read only bit. This bit is set by H/W when the the transmit shift register is empty. It can

not disable the transmit function when the bit is 0.

Bit 5: THRE, Transmit Holding Register Empty. Read only bit. When this bit is 1, the transmit holding buffer contains

invalid data and the transmit data register (84h) can be written a new data. When this bit is 0, it indicate that transmit

holding buffer contains valid data that not yet been copied to transmit shift register and the transmit data register (84h)

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

can not be written a new data.

When the transmit interrupt is enabled, a serial port interrupt is generated when this bit is 1. The THRE bit is

automatically cleared by H/W during copy data to transmit holding buffer.

Bit 4: RDR, Receive Data Ready. Read only bit. When the receive data register is ready to read, this bit is 1. When the bit is

0, the receive data register dose not contain valid data. This bit will be cleared by H/W when reading the receive data

Bit 3: BRKI, Break Interrupt. It indicates that a break has been receive when this bit is set 1 and it will generate a serial pot

interrupt request if the RISE bit (80h.1) is enabled. This bit is set by H/W and should be cleared by software.

Bit 2: FER, Framing Error. This bit is set to indicate that a framing error occurred during reception of data and it will

generate a serial pot interrupt request if the RISE bit (80h.1) is enabled. This bit is set by H/W and should be cleared by

software.

Bit 1: PER, Parity Error. This bit is set to indicate that a party error occurred during reception of data and it will generate a

serial pot interrupt request if the RISE bit (80h.1) is enabled. This bit is set by H/W and should be cleared by software.

Bit 0: OER, Overrun Error. This bit is set to indicate that a overrun error occurred during reception of data and it will

generate a serial port interrupt request if the RISE bit (80h.1) is enabled. This bit is set by H/W and should be cleared

by software.

Bit 15-8: Reserved

Bit 7-0 : TDATA, Transmit Data. Software writes this register with data to be transmitted on the serial port.

The THRE bit (82h.5) should be read as a 1 before writing this register to avoid overwriting data to this register.

When writing data to this register, the THRE bit will be cleared by H/W in the same time.

Bit 15-8: Reserved

Bit 7-0: RDATA, Received DATA. The PDR bit (82h.4) should be read as 1 beforeread the RDATA register to avoid reading

invalid data.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Synchronous Serial Port

There are four pins for synchronous serial port interface, which is half duplex, bi-directional data transfer. The synchronous

serial interface operates in a master/slave configuration, and the synchronous serial port of R8800LV as a master mode. The

SCLK frequency is affected by the reduced microprocessor clock frequency when in power-save mode. Software is

programmed the 10h, 12h, 14h,16h, 18h to configured the synchronous serial port interface.

Read only register that indicates the state of the SSI port.

Bit 15-3 : Reserved.

Bit 2 : RE/TE, Receive/Transmit Error Detect.

Set 1: Either a read of Synchronous Serial Receive register or a write to one transmit registers while the SSI is busy

(PB=1).

Set 0: SDEN output is inactive.

Bit 1: DR/TR, Data Receive/Transmit Complete.

Set 1: End of the transfer of data bit 7 (SCLK rising edge) during a transmit or receive operation.

Set 0: When the SSR register is read, when one of the SSD0 or SSD1 registers is written, when the SSS register is read,

or when both SDEN0 and SDEN1 become inactive.

Bit 0: PB, SSI port Busy.

Set 1: a transmit or receive operation is in progress.

Set 0: the port is ready to transmit or receive data.

This read/write register controls the operation of the SDEN0-SDEN1 outputs the transfer rate of the SSI port.

Bit 15-3 : Reserved.

Bit 3-2 : SCLKDIV, SCLK Divide.

SCLKDIV

SCLK Frequency Divider

00b

Processor clock/2

01b

Processor clock/4

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

10b

Processor clock/8

11b

Processor clock/16

Bit 1 : DE1, SDEN1 Enable.

Set 1: SDEN1 pin is held High.

Set 0: SDEN1 pint is Low.

Bit 0 : DE0, SDEN0 Enable.

Set 1: SDEN0 pin is held High.

Set 0: SDEN0 pint is Low.

Synchronous Serial Transmit 1 Register. The register contains data to be transfer from the processor to the peripheral on a

write operation.

Bit 15-8 : Reserved.

Bit 7-0: SD, Send Data. Data to transmit over the SDATA pin.

Synchronous Serial Transmit 0 Register. The register contains data to be transfer from the processor to the peripheral on a

write operation.

Bit 15-8 : Reserved.

Bit 7-0: SD, Send Data. Data to transmit over the SDATA pin.

Th Synchronous Serial Receive Register contains the data transferred from the peripheral to the processor on a read

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

PIO Unit

R8800LV provides 32 programmable I/O signals, which are multi-function pins with others normal function signals. Software

is programmed through the registers ( 7Ah, 78h, 76h, 74h, 72h, 70h) to configure the multi-function pins for PIO or normal

function.

PIO multi-function Pin list table

PIO No.

Pin No.

Multi Function

Reset status/PIO internal resister

TMRIN1

Input with 10k pull-up

TMROUT1

Input with 10k pull-down

PCS

/A2

Input with 10k pull-up

PCS

/A1

Input with 10k pull-up

DT/

Normal operation/ Input with 10k pull-up

DEN

Normal operation/ Input with 10k pull-up

SRDY

Normal operation/ Input with 10k pull-down

A17

Normal operation/ Input with 10k pull-up

A18

Normal operation/ Input with 10k pull-up

A19

Normal operation/ Input with 10k pull-up

TMROUT0

Input with 10k pull-down

TMRIN0

Input with 10k pull-up

DRQ0

Input with 10k pull-up

DRQ1

Input with 10k pull-up

MCS

Input with 10k pull-up

MCS

Input with 10k pull-up

PCS

Input with 10k pull-up

PCS

Input with 10k pull-up

e
r
n a l
e
r
n a l

w
n

n
o
r m a l f u n c t i o n

a
t
a I n

c
e
s s o r

o
n

u
n
c t i o n

I
n / O u t

Operation Diagram

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

PCS

Input with 10k pull-up

PCS

Input with 10k pull-up

SCLK

Input with 10k pull-up

100

SDATA

Input with 10k pull-up

SDEN0

Input with 10k pull-down

SDEN1

Input with 10k pull-down

MCS

Input with 10k pull-up

MCS

R
F
SH

Input with 10k pull-up

UZI

Input with 10k pull-up

TXD

Input with 10k pull-up

RXD

Input with 10k pull-up

S6/

C
L
KDIV

Input with 10k pull-up

INT4

Input with 10k pull-up

INT2

Input with 10k pull-up

Bit 15- 0 : PDATA31-PDATA16, PIO Data Bits.

These bits PDATA31- PDATA16 map to the PIO31 PIO16 which indicate the driven level when the PIO pin as an

output or reflects the external level when the PIO pin as an input .

Bit 15-0 : PDIR 31- PDIR16, PIO Direction Register.

Set 1: Configure the PIO pin as an input.

Set 0: Configure the PIO pin as an output or as normal pin function.

31 - 16)

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15-0: PMODE31-PMODE16, PIO Mode Bit.

The definition of PIO pins are configured by the combination of PIO Mode and PIO Direction. And the PIO pin is

programmed individual.

The definition (PIO Mode, PIO Direction) for PIO pin function:

( 0 , 0 ) Normal operation , ( 0 , 1 ) PIO input with pullup/pulldown

( 1 , 0 ) PIO output , ( 1 , 1 ) -- PIO input without pullup/pulldown

Bit 15-0 : PDATA15- PDATA0 : PIO Data Bus.

These bits PDATA15- PDATA0 map to the PIO15 PIO0 which indicate the driven level when the PIO pin as an

output or reflects the external level when the PIO pin as an input.

Bit 15-0 : PDIR 15- PDIR0, PIO Direction Register.

Set 1: Configure the PIO pin as an input.

Set 0: Configure the PIO pin as an output or as normal pin function.

Bit 15-0: PMODE15-PMODE0, PIO Mode Bit.

15 - 0)

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

PSRAM Control Unit

The PSRAM interface is provided by the R8800LV and the refresh control unit automatically generates refresh bus cycles. The

refresh control unit uses the internal microprocessor clock as a operating source clock. if the power-saved mode is enabled, the

refresh control unit must be programmed to reflect the new clock rate. Software programs the registers (E0, E2, E4) to control

the refresh control unit operation.

Bit 15-9: M6-M0, Refresh Base. M6-M0 map to A19-A13 of the 20-bit memory refresh address.

Bit 8-0 : Reserved.

Bit 15-9 : Reserved

Bit 8-0: RC8-RC0, Refresh Counter Reload Value.

Bit 15: E, Enable RCU.

Set 1: Enable the refresh counter unit

Set 0 : Disable the refresh counter unit.

Bit 14-9 : Reserved

Bit 8-0: T8-T0, Refresh Count. Read only bits and these bits present value of the down counter which triggers refresh

requests.

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

INSTUCTION SET OPCODES AND CLOCK CYCLES

Function

Format

Clocks

Notes

DATA TRANSFER INSTRUCTIONS
MOV = Move
register to register/memory

1000100w

mod reg r/m

1/1

1000101w

mod reg r/m

1/6

immediate to register/memory

1100011w

mod 000 r/m

data

data if w=1

1/1

immediate to register

1011w reg

data

data if w=1

memory to accumulator

1010000w

addr-low

addr-high

accumulator to memory

1010001w

addr-low

addr-high

10001110

mod 0 reg r/m

3/8

segment register to register/memory

10001100

mod 0 reg r/m

2/2

PUSH

Push

memory

11111111

mod 110 r/m

01010 reg

segment register

000reg110

immediate

011010s0

data

data if s=0

POP = Pop
memory

10001111

mod 000 r/m

01011 reg

segment register

000 reg 111 (reg01)

PUSHA = Push all

01100000

POPA = Pop all

01100001

XCHG = Exchange
register/memory

1000011w

mod reg r/m

3/8

10010 reg

XTAL = Translate byte to AL

11010111

IN = Input from
fixed port

1110010w

port

variable port

1110110w

OUT = Output from
fixed port

1110010w

port

variable port

1110110w

LEA = Load EA to register

10001101

mod reg r/m

LDS = Load pointer to DS

11000101

mod reg r/m

(mod

11)

LES = Load pointer to ES

11000100

mod reg r/m

(mod

11)

ENTER = Build stack frame

11001000

data-low

data-high

L = 0

L = 1

L > 1

11+10(L-1)

LEAVE = Tear down stack frame

11001001

LAHF = Load AH with flags

10011111

SAHF = Store AH into flags

10011110

PUSHF = Push flags

10011100

POPF = Pop flags

10011101

ARITHMETIC INSTRUCTIONS
ADD = Add
reg/memory with register to either

000000dw

mod reg r/m

1/7

immediate to register/memory

100000sw

mod 000 r/m

data

data if sw=01

1/8

immediate to accumulator

0000010w

data

data if w=1

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Function

Format

Clocks

Notes

ADC = Add with carry
reg/memory with register to either

000100dw

mod reg r/m

1/7

immediate to register/memory

100000sw

mod 010 r/m

data

data if sw=01

1/8

immediate to accumulator

0001010w

data

data if w=1

INC = Increment
register/memory

1111111w

mod 000 r/m

1/8

01000 reg

SUB = Subtract
reg/memory with register to either

001010dw

mod reg r/m

1/7

immediate from register/memory

100000sw

mod 101 r/m

data

data if sw=01

1/8

immediate from accumulator

0001110w

data

data if w=1

SBB = Subtract with borrow
reg/memory with register to either

000110dw

mod reg r/m

1/7

immediate from register/memory

100000sw

mod 011 r/m

1/8

immediate from accumulator

0001110w

data

data if w=1

DEC = Decrement
register/memory

1111111w

mod 001 r/m

1/8

01001 reg

NEG = Change sign
register/memory

1111011w

mod reg r/m

1/8

CMP = Compare
register/memory with register

0011101w

mod reg r/m

1/7

0011100w

mod reg r/m

1/7

immediate with register/memory

100000sw

mod 111 r/m

data

data if sw=01

1/7

immediate with accumulator

0011110w

data

data if w=1

MUL = multiply (unsigned)

1111011w

mod 100 r/m

memory-byte

memory-word

IMUL = Integer multiply (signed)

1111011w

mod 101 r/m

memory-byte

memory-word

011010s1

mod reg r/m

data

data if s=0

23/28

DIV = Divide (unsigned)

1111011W

mod 110 r/m

memory-byte

memory-word

IDIV = Integer divide (signed)

1111011w

mod 111 r/m

memory-byte

memory-word

AAS = ASCII adjust for subtraction

00111111

DAS = Decimal adjust for subtraction

00101111

AAA = ASCII adjust for addition

00110111

DAA = Decimal adjust for addition

00100111

AAD = ASCII adjust for divide

11010101

00001010

AAM = ASCII adjust for multiply

11010100

00001010

CBW = Corrvert byte to word

10011000

CWD = Convert word to double-word

10011001

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Function

Format

Clocks

Notes

BIT MANIPULATION INSTRUCTUIONS
NOT = Invert register/memory

1111011w

mod 010 r/m

1/7

AND = And
reg/memory and register to either

001000dw

mod reg r/m

1/7

immediate to register/memory

1000000w

mod 100 r/m

data

data if w=1

1/8

immediate to accumulator

0010010w

data

data if w=1

OR = Or
reg/memory and register to either

000010dw

mod reg r/m

1/7

immediate to register/memory

1000000w

mod 001 r/m

data

data if w=1

1/8

immediate to accumulator

0000110w

data

data if w=1

XOR = Exclusive or
reg/memory and register to either

001100dw

mod reg r/m

1/7

immediate to register/memory

1000000w

mod 110 r/m

data

data if w=1

1/8

immediate to accumulator

0011010w

data

data if w=1

TEST = And function to flags , no result
register/memory and register

1000010w

mod reg r/m

1/7

immediate data and register/memory

1111011w

mod 000 r/m

data

data if w=1

1/8

immediate data and accumulator

1010100w

data

data if w=1

Sifts/Rotates
register/memory by 1

1101000w

mod TTT r/m

2/8

1101001w

mod TTT r/m

1+n / 7+n

1100000w

mod TTT r/m

count

1+n / 7+n

STRING MANIPULATION INSTRUCTIONS
MOVS = Move byte/word

1010010w

INS = Input byte/word from DX port

0110110w

OUTS = Output byte/word to DX port

0110111w

CMPS = Compare byte/word

1010011w

SCAS = Scan byte/word

101011w

LODS = Load byte/word to AL/AX

1010110w

STOS = Store byte/word from AL/AX

1010101w

Repeated by count in CX:

MOVS = Move byte/word

11110010

1010010w

4+9n

INS = Input byte/word from DX port

11110010

0110110w

5+9n

OUTS = Output byte/word to DX port

11110010

0110111w

5+9n

CMPS = Compare byte/word

1111011z

1010011w

4+18n

SCAS = Scan byte/word

1111001z

1010111w

4+13n

LODS = Load byte/word to AL/AX

11110010

0101001w

3+9n

STOS = Store byte/word from AL/AX

11110100

0101001w

4+3n

PROGRAM TRANSFER INSTRUCTIONS
Conditional Transfers --

-- jump if:

JE/JZ = equal/zero

01110100

disp

1/9

JL/JNGE = less/not greater or equal

01111100

disp

1/9

JLE/JNG = less or equal/not greater

01111110

disp

1/9

JC/JB/JNAE = carry/below/not above or equal

01110010

disp

1/9

JBE/JNA = below or equal/not above

01110110

disp

1/9

JP/JPE = parity/parity even

01111010

disp

1/9

JO = overflow

01110000

disp

1/9

JS = sign

01111000

disp

1/9

JNE/JNZ = not equal/not zero

01110101

disp

1/9

JNL/JGE = not less/greater or equal

01111101

disp

1/9

JNLE/JG = not less or equal/greater

01111111

disp

1/9

JNC/JNB/JAE = not carry/not below

01110011

disp

1/9

/above or equal
JNBE/JA = not below or equal/above

01110111

disp

1/9

JNP/JPO = not parity/parity odd

01111011

disp

1/9

JNO = not overflow

01110001

disp

1/9

JNS = not sign

01111001

disp

1/9

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Function

Format

Clocks

Notes

Unconditional Transfers

CALL = Call procedure
direct within segment

11101000

disp-low

disp-high

reg/memory indirect within segment

11111111

mod 010 r/m

12/17

indirect intersegment

11111111

mod 011 r/m

(mod11)

direct intersegment

10011010

segment offset

selector

RET = Retum from procedure
within segment

11000011

within segment adding immed to SP

11000010

data-low

data-high

intersegment

11001011

instersegment adding immed to SP

1001010

data-low

data-high

JMP = Unconditional jump
short/long

11101011

disp-low

9/9

direct within segment

11101001

disp-low

disp-high

reg/memory indirect within segment

11111111

mod 100 r/m

11/16

indirect intersegment

11111111

mod 101 r/m

(mod ?11)

direct intersegment

11101010

segment offset

selector

Iteration Control
LOOP = Loop CX times

11100010

disp

7/16

LOOPZ/LOOPE = Loop while zero/equal

11100001

disp

7/16

LOOPNZ/LOOPNE = Loop while not zero/equal 11100000

disp

7/16

JCXZ = Jump if CX = zero

11100011

disp

7/15

Interrupt
INT = Interrupt
Type specified

11001101

type

Type 3

11001100

INTO = Interrupt on overflow

11001110

43/4

BOUND = Detect value out of range

01100010

mod reg r/m

21-60

IRET = Interrupt return

11001111

PROCESSOR CONTROL INSTRUCTIONS
CLC = clear carry

11111000

CMC = Complement carry

11110101

STC = Set carry

11111001

CLD = Clear direction

11111100

STD = Set direction

11111101

CLI = Clear interrupt

11111010

STI = Set interrupt

11111011

HLT = Halt

11110100

WAIT = Wait

10011011

LOCK = Bus lock prefix

11110000

ESC = Math coprocessor escape

11011MMM mod PPP r/m

NOP = No operation

10010000

SEGMENT OVERRIDE PREFIX
CS

00101110

00110110

00111110

00100110

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

R8800LV Execution Timings

The above instruction timing represent the minimum execution time in clock cycles for each instruction. The timings given
are based on the following assumptions:
1. The opcode, along with and data or displacement required for execution, has been prefetched and resides in the instruction
queue at the time is needed.
2. No wait states or bus HOLDs occur.
3. All word -data is located on even-address boundaries.
4. One RISC micro operation(uOP) maps one cycle(according the pipeline stages described below) , except the following
case:

4.1 Memory read uOP need 6 cycles for bus.

4.2 Memory push uOP need 1 cycle if it has no previous Memory push uOP, and 5 cycles if it has previous Memory push or
Memory Write uOP.

4.3 MUL uOP and DIV of ALU function uOP for 8 bits operation need both 8 cycles, for 16 bits operation need both 16
cycles.
4.4 All jumps, calls, ret and loopXX instructions required to fetch the next instruction for the destination
address(Unconditional Fetch uOP) will need 9 cycles.

Note: op_r: operand read stage, EA: Calculate Effective Address stage, Idle: Bus Idle stage, T0..T3: Bus T0..T3 stage,

Access: Access data from cache memory stage.

Pipeline Stages for single micro operation(one cycle):

Fetch Decode op_r ALU WB

(For ALU function uOP)

Fetch Decode EA Access WB

(For Memory function uOP)

Pipeline stages for Memory read uOP(6 cycles):

Fetch Decode EA Access Idle T0 T1 T2 T3 WB

Bus Cycle

Pipeline stages for Memory push uOP after Memory push uOP (another 5 cycles):

Fetch Decode EA

Access

Idle T0 T1 T2

WB (1

Memory push uOP)

uOP) Fetch Decode EA

Access

Idle T0 T1 T2 T3 WB

pipeline stall

Pipeline stages for unconditional fetch:

Fetch Decode EA

Access

Idle T0

T1 T2

Fetch

(Fetch uOP)

(next uOP) Fetch

Decode

Access

Idle T0 T1 T2 T3 WB

will be flushed

These 9 cycles caused branch penalty

Fetch

Decode

following stages..

(New uOP)

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

DC Characteristics

Absolute Maximum Rating

Symbol

Rating

Commercial

Unit

Note

Vterm

Terminal Voltage
with Respect
To GND

-0.5 to Vcc+0.5
V

Operating
Temperature

0 to +70

Centigrade

Power Dissipation

1.5

Recommended DC Operating Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

Vcc

Supply Voltage

3.0

3.3

3.6

GND

Ground

Vih

Input High Voltage(1)

2.0

---

Vcc+0.5

Vih1

Input High Voltage(RES)

2.5

Vcc+0.5

Vih2

Input High Voltage (X1)

2.5

Vcc+0.5

Vil

Input Low voltage

-0.5

0.8

Note 1:

RST

,X1 pins not included

DC Electrical Characteristics

Symbol

Parameter

Test Condition

Min

Max

Unit

Ili

Input Leakage Current
(for 32 Pio Pins)

Vcc=Vmax
Vin=GND to
Vcc

300

Ili

Input Leakage
Current (Others)

Vcc=Vmax
Vin=GND to
Vcc

Ilo

Output Leakage
Current

Vcc=Vmax
Vin=GND to
Vcc

300

VOL

Output Low Voltage

Iol=2mA,
Vcc=Min.

_____

0.4

VOH

Output High Voltagr

Ioh=-2.4mA,
Vcc=Min.

2.4

____

Note1:Vmax=3.6V Vmin=3.0V

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

No.

Description

MIN

MAX

Unit

CLKOUTA high to A Address Valid

A address valid to

low

1.5T-12

S6 active delay

S6 inactive delay

AD address Valid Delay

Address Hold

Data in setup

Data in Hold

ALE active delay

ALE inactive delay

Address Valid after ALE inactive

1/2T-10

ALE width

T-10

active delay

Pulse Width

2T-15

inactive delay

CLKOUTA HIGH to

LCS

UCS

valid

UCS,LCS inactive delay

PCS

MCS

active delay

PCS

MCS

inactive delay

D
E
N

active delay

D
E
N

inactive delay

DTR active delay

DTR inactive delay

Status active delay

Status inactive delay

UZI

active delay

UZI

inactive delay

1. T means a clock period time

2. All timing parameters are measured at 1.5V with 50 PF loading on CLKOUTA

. All output test conditions are with CL=50 pF

RDC

RISC DSP Controller

R8800LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

No.

Description

MIN

MAX

Unit

CLKOUTA high to A Address Valid

A address valid to

low

1.5T-12

S6 active delay

S6 inactive delay

AD address Valid Delay

Address Hold

ALE active delay

ALE width

T-10

ALE inactive delay

Address valid after ALE inactive

1/2T-10

active delay

pulse width

2T-15

inactive delay

WHB

WLB

active delay

WHB

WLB

inactive delay

BHE active delay

BHE inactive delay

CLKOUTA high to

UCS

LCS

valid

UCS

LCS

inactive delay

PCS

MCS

active delay

PCS

MCS

inactive delay

D
E
N

active delay

D
E
N

inactive delay

D
T
R

active delay

D
T
R

inactive delay

Status active delay

Status inactive delay

UZI

active delay

UZI

inactive delay

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: R8800LV

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: R8800LV