RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Contents

-----------------------------------------------------------------------------------

page

1. Features ---------------------------------------------------------------------------4
2. Block Diagram ------------------------------------------------------------------4
3. Pin Configuration --------------------------------------------------------------5
4. Pin Description ------------------------------------------------------------------8
5. Basic Application System Block -------------------------------------------- 14
6. Oscillator Characteristics --------------------------------------------------- 15
7. Read/Write timing Diagram ------------------------------------------------- 16
8. Execution Unit --------------------------------------------------------------- 18
8.1

General Register

---------------------------------------------------------- 18

8.2

Segment Register

--------------------------------------------------------- 18

8.3

Instruction Pointer and Status Flags Register ---------------------------

8.4

Address Generation

------------------------------------------------------ 20

9. Peripheral Control Block Register ---------------------------------------- 21
10. System Clock Block --------------------------------------------------------- 23
11. Reset --------------------------------------------------------------------------- 24
12. Bus Interface Unit ------------------------------------------------------------ 26
12.1

Memory and I/O Interface -------------------------------------------------

12.2

Data Bus

----------------------------------------------------------------- 26

12.3

Wait States---------------------------------------------------------------------

12.4

Bus Hold -----------------------------------------------------------------------

13. Chip Select Unit ------------------------------------------------------------- 30
13.1

UCS

---------------------------------------------------------------------------

13.2

LCS

---------------------------------------------------------------------------

13.3

MCSx

-------------------------------------------------------------------------

13.4

PCSx

------------------------------------------------------------------------

14. Interrupt Controller Unit ------------------------------------------------- 37
14.1

Master Mode and Slave Mode

----------------------------------------- 37

14.2

Interrupt Vector, Type -----------------------------------------------------

14.3

Interrupt Request

------------------------------------------------------- 39

14.4

Interrupt Acknowledge

------------------------------------------------ 39

14.5

Programming Register -----------------------------------------------------

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

15. DMA Unit --------------------------------------------------------------------- 53
15.1

DMA Operation --------------------------------------------------------------

15.2

External Request -------------------------------------------------------------

15.3 Serial Port DMA/Transfer-------------------------------------------- 59
16. Timer Control Unit --------------------------------------------------------- 61
16.1

Timer/Counter Unit Output Mode

---------------------------------- 65

17. Watchdog Timer ------------------------------------------------------------ 66
18. Asynchronous Serial Port ------------------------------------------------- 69
18.1 Serial Port Flow Control ------------------------------------------- 69
18.1.1 DCE/DTE Protocol ----------------------------------------- 69
18.1.2 CTS/RTR Protocol ------------------------------------------ 70
18.2 DMA Transfer to/form a serial port function ----------------- 70
18.3 The Asynchronous Modes description -------------------------- 71
19. PIO Unit ---------------------------------------------------------------------- 76
19.1

PIO Multi-Function Pin list Table

----------------------------------- 76

20. PSRAM Control Unit ------------------------------------------------------ 79
21. Instruction Set Opcodes and Clock Cycle ----------------------------- 80
21.1

R8830LV Execution Timings

----------------------------------------- 84

22. DC Characteristics ---------------------------------------------------------- 85
23. AC Characteristics ---------------------------------------------------------- 87
24. Package Information ------------------------------------------------------- 96
25. Revision History ------------------------------------------------------------- 98

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

16-Bit Microcontroller with 8-bit external data bus

1. Features

RISC architecture

Static Design & Synthesizable design

Bus interface

- Multiplexed address and Data bus which

compatible with 80C188 microprocessor

- Supports nonmultiplexed address bus [A19 : A0]

- 1M byte memory address space

- 64K byte I/O space

Software compatible with the 80C186

Support two Asynchronous serial channel with

hardware handshaking signals.

Support serial port with DMA transfers

Supports 32 PIO pins

PSRAM (Pseudo static RAM) interface with

auto-refresh control

Three independent 16-bit timers and one

independent watchdog timer

The Interrupt controller with seven maskable

external interrupts and one nonmaskable

external interrupt

Two independent DMA channels

Programmable chip-select logic for Memory

or I/O bus cycle decoder

Programmable wait-state generator

2. Block Diagram

DMA

Unit

PSRAM

Control

Unit

Chip

Select

Unit

Refresh

Control

Unit

Bus

Interface

Unit

PIO

Unit

Timer Control

Unit

Interrupt

Control Unit

Clock and

Power

Management

Asynchro-

nous Serial

Port0

Instruction

Queue (64bits)

Instruction

Decoder

Register

File

General,

Segment,

Eflag Register

ALU

(Special,

Logic,

Adder,

BSF)

Micro

ROM

EA / LA

Address

Control Signal

Execution

Unit

CLKOUTA

CLKOUTB INT6-INT4

INT0

TMRIN0

TMROUT0

TMRIN1

TMROUT1

DRQ0

DRQ1

TXD0

RXD0

A19~A0

AD7~AD0

AO15~AO8

VCC

GND

LCS/ONCE0

MCS3/RFSH

UCS/ONCE1

PCS5/A1

PCS6/A2

ARDY

SRDY

S2~S0

DT/R

DEN

HOLD

HLDA

S6/CLKDIV2

UZI

ALE

Asynchro-

nous Serial

Port1

RTS0/RTR0

CTS0/ENRX0

TXD1

RXD1

RTS1/RTR1

CTS1/ENRX1

RFSH2/ADEN

INT3/INTA1/IRQ

INT2/INTA0

INT1/SELECT

NMI

RST

MCS2-MCS0

PCS3-PCS0

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

3. Pin Configuration

(PQFP)

100

R8830LV

Microcontroller

RXD0/PIO23

TXD0/PIO22

ALE

ARDY

GND

VCC

CLKOUTA

CLKOUTB

GND

A19/PIO9

A18/PIO8

VCC

A17/PIO7

A16

A15

A14

A13

A12

A11

A10

VCC

GND

HLDA

HOLD

SRDY/PIO6

NMI

INT4/PIO30

INT0

VCC

GND

VCC

GND

TMRIN1/PIO0

TMROUT1/PIO1

TMROUT0/PIO10

TMRIN0/PIO11

DRQ1/INT5/PIO13

DRQ0/INT6/PIO12

AD0

AO8

AD1

AO9

AD2

AO10

AD3

A011

AD4

AO12

AD5

GND

AO13

AD6

VCC

AO14

AD7

AO15

TXD1/PIO27

RXD1/PIO28

INT3/INTA1/IRQ

UCS/ONCE1

LCS/ONCE0

S6/CLKDIV2/PIO29

DT/R/PIO4

DEN/PIO5

MCS0/PIO14

MCS1/PIO15

INT2/INTA0/PIO31

PCS6/A2/PIO2

PCS5/A1/PIO3

PCS1/PIO17

PCS0/PIO16

MCS2/PIO24

MCS3/RFSH/PIO25

RST

UZI/PIO26

INT1/SELECT

PCS2/CTS1/ENRX1/PIO18

PCS3/RTS1/RTR1/PIO19

RTS0/RTR0/PIO20

CTS0/ENRX0/PIO21

RFSH2/ADEN

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(LQFP)

R8830LV

AD0

AO8

AD1

AO9

AD2

AO10

AD3

AO11

AD4

AO12

AD5

GND

AO13

AD6

VCC

AO14

AD7

AO15

S6/CLKDIV2/PIO29

UZI/PIO26

TXD1/PIO27

RXD1/PIO28

RXD0/PIO23

TXD0/PIO22

ALE

ARDY

GND

VCC

CLKOUTA

CLKOUTB

GND

A19/PIO9

A18/PIO8

VCC

A17/PIO7

A16

A15

A14

A13

A12

A11

A10

VCC

GND

HOLD

HLDA

SRDY/PIO6

NMI

INT4/PIO30

INT0

VCC

GND

VCC

GND

TMRIN1/PIO0

TMROUT0/PIO10

TMRIN0/PIO11

TMROUT1/PIO1

DRQ1/INT5/PIO13

DRQ0/INT6/PIO12

DT/R/PIO4

INT3/INTA1/IRQ

INT2/INTA0/PIO31

INT1/SELECT

LCS/ONCE0

PCS6/A2/PIO2

PCS5/A1/PIO3

PCS1/PIO17

PCS0/PIO16

RST

100

DEN/PIO5

MCS3/RFSH/PIO25

CTS0/ENRX0/PIO21

RTS0/RTR0/PIO20

GND

PCS3/RTS1/RTR1/PIO19

PCS2/CTS1/ENRX1/PIO18

RFSH2/ADEN

MCS0/PIO14

MCS1/PIO15

UCS/ONCE1

MCS2/PIO24

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

R8830LV Pin OUT Table

Pin name

LQFP Pin No.

PQFP Pin No.

Pin name

LQFP Pin No.

PQFP Pin No.

AD0 1

A11

AO8 2

A10

AD1 3

AO9 4

AD2 5

AO10 6

AD3 7

AO11 8

AD4 9

AO12 10

AD5 11

VCC

GND 12

AO13 13

AD6 14

GND

VCC 15

GND

AO14 16

66 43

AD7 17

HLDA

AO15 18

HOLD

S6/

CLKDIV

/PI O29

19 96

SRDY/PI

UZI

/PI O26

20 97

NMI

TXD1/PI O27

DT/

/PI O4

71 48

RXD1/PI O28

DEN

/PI O5

72 49

CTS

ENRX

/PIO21

23 100

MCS

/PI O14

73 50

RXD0/PI O23

MCS

/PI O15

74 51

TXD0/PI O22

I NT4/ PI O30

RTS /

RTR

/PIO20

26 3 I NT3/

INTA /I RQ

76 53

RFSH

/ ADEN

27 4 I NT2/

INTA

/PI O31

77 54

28 5 I NT1/

SELECT

78 55

29 6

NT0

ALE 30

7 UCS/

ONCE

80 57

ARDY 31 8

LCS/

ONCE

81 58

32 9

PCS

/A2/PI O2

82 59

33 10

PCS

/A1/PI O3

83 60

34 11

VCC

GND 35

12 3

PCS /

RTS /

RTR

/PI O19

85 62

X1 36

PCS /

CTS

ENRX

/PI O18

86 63

X2 37

GND

VCC 38

PCS

/PI O17

88 65

CLKOUTA 39 16

PCS

/PI O16

89 66

CLKOUTB 40 17

VCC

90 67

GND 41

MCS

/PI O24

91 68

A19/PI O9

MCS

/ RFSH /PI O25

92 69

A18/PI O8

GND

VCC 44

RST

94 71

A17/PI O7

TMRI N1/PI O0

A16 46

23 TMROUT1/PI

A15 47

TMROUT0/PI

O10

A14

TMRI N0/PI O11

A13 49

DRQ1/INT6/PI

O13

A12 50

DRQ0/INT5/PI

O12

100

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

4. Pin Description

Pin

No.(PQFP)

Symbol Type

Description

15, 21, 38,

61, 67, 92

VCC Input

System power: +5 volt power supply.

12, 18, 41, 42

64, 70, 89

GND Input

System ground.

RST

Input*

Reset input. When RST is asserted, the CPU immediately
terminate all operation, clears the internal registers & logic,
and the address transfers to the reset address FFFF0h.

13 X1

Input

Input to the oscillator amplifier.

14 X2

Output

Output from the inverting oscillator amplifier.

16 CLKOUTA

Output

Clock output A. The CLKOUTA operation is the same as
crystal input frequency (X1). CLKOUTA remains active during
reset and bus hold conditions.

17 CLKOUTB

Output

Clock output B. The CLKOUTB operation is the same as
crystal input frequency (X1). CLKOUTB remains active
during reset and bus hold conditions.

Asynchronous Serial Port Interface

1 RXD0/PIO23

Input/Output

Receive data for asynchronous serial port 0. This pin receives
asynchronous serial data.

2 TXD0/PIO22

Output/Input

Tranmit data for asynchronous serial port 0. This pin
transmits asynchronous serial data from the UART of the
microcontrolles.

RTS /

RTR /PIO20

Output/Input

Ready to Send/Ready to Receive signal for asynchronous
serial port 0. when the

RTS bit in AUXCON register is set

and FC bit in the serial port 0 register is set the

RTS signal

is enabled. Other the

RTS bit is cleared and FC bit is set

the

RTR signal is enabled.

100

CTS /

ENRX /PIO21

Input/Output

Clear to Send/Enable Receiver Request signal for
asyncgronous serial port 0. when

ENRX bit in the

AUXCON register is cleared and the FC bit in the serial port
0 control register is set the

CTS signal is enabled.

Otherwise when

ENRX bit is set and the FC bit is set the

ENRX signal is enabled.

98 TXD1/PIO27

Output/Input

Tranmit data for asynchronous serial port 0. This pin
transmits asynchronous serial data from the UART of the
microcontrolles.

99 RXD1/PIO28

Input/Output

Receive data for asynchronous serial port 0. This pin receives
asynchronous serial data.

PCS /

RTS /

RTR

Output/Input

Ready to Send/Ready to Receive signal for asynchronous
serial port 1. when the

RTS bit in AUXCON register is set

and FC bit in the serial port 1 register is set the

RTS signal

is enabled. otherwise the

RTS bit is cleared and FC bit is set

the

RTR signal is enabled.

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

PCS /

CTS /

ENRX

Output/Input

Clear to Send/Enable Receiver Request signal for
asynchronous serial port 0. when

ENRX

bit in the

AUXCON register is cleared and the FC bit in the serial port
0 control register is set the

CTS signal is enabled. otherwise

when

ENRX

bit is set and the FC bit is set the

ENRX

signal is enabled.

Bus Interface

RFSH / ADEN

Output/Input

For

RFSH feature, this pin actice low to indicate a DRAM

refresh bus cycle.
For ADEN feature, when this pin is held high on power-on
reset the address portion of the AD bus can be disabled or
enabled by DA bit in the LMCS and UMCS register during
LCS or UCS bus cycle access. The

RFSH / ADEN with a

internal weak pull-up resister, so no external pull-up resister is
reqired. The AD bus always drives both address and data
during LCS or UCS bus cycle access, if the

RFSH / ADEN pin with external pull-Low resister during

reset.

Output

Write strobe. This pin indicates that the data on the bus is to be
written into a memory or an I/O device. WR is active during
T2, T3 and Tw of any write cycle, floats during a bus hold or
reset.

Output

Read Strobe. Active low signal which indicates that the
microcontroller is performing a memory or I/O read cycle.

RD floats during bus hold or reset.

7 ALE

Output

Address latch enable. Active high. This pin indicates that an
address output on the AD bus. Address is guaranteed to be
valid on the trailing edge of ALE. This pin is tri-stated during
ONCE mode and is never floating during a bus hold or reset.

8 ARDY

Input

Asynchronous ready. This pin performs the microcontroller
that the address memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that is
asynchronous to CLKOUTA and is active high. The falling
edge of ARDY must be synchronized to CLKOUTA. Tie
ARDY high, the microcontroller is always asserted in the ready
condition. If the ARDY is not used, tie this pin low to yield
control to SRDY.
Both SRDY and ARDY should be tied to high if the system
need not assert wait state by externality.
Bus cycle status. These pins are encoded to indicate the bus
status. 2

S can be used as memory or I/O indicator. 1

S can

be used as DT/ R indicator. These pins are floating during
hold and reset.

Bus Cycle Encoding Description

10
11

Output

Bus Cycle

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
Passive

19
20
22

23-37

39, 40

A19/PIO9
A18/PIO8
A17/PIO7

A16-A2

A1 , A0

Output/Input

Address bus. Non-multiplex memory or I/O address. The A bus
is one-half of a CLKOUTA period earlier than the AD bus.
These pins are high-impedance during bus hold or reset.

78,80,82,84,

86,

88,91,94

AD0-AD7 Input/Output

The multiplexed address and data bus for memory or I/O
accessing. The address is present during the t1 clock phase, and
the data bus phase is in t2-t4 cycle.
The address phase of the AD bus can be disabled when the

BHE / ADEN pin with external pull-Low resister during reset.

The AD bus is in high-impedance state during bus hold or
reset condition and this bus also be used to load system
configuration information (with pull-up or pull-Low resister)
into the RESCON(F6h) register when the reset input from low
go high.

79,81,83,85,8

7,90

93,95

AO8-AO15 Output

Address Only Bus, In the multiplexed address bus, the AO15
AO8 combine with the AD7 AD0 to form a 16 bit address
bus. These pins are floating during a bus hold or reset.

Output

Write Byte. This pin active low to indicate a write cycle on the
bus. It is floating during reset.

44 HLDA

Output

Bus hold acknowledge. Active high. The microcontroller will
issue a HLDA in response to a HOLD request by external bus
master at the end of T4 or Ti. When the microcontroller is in
hold status (HLDA is high), the AD15-D0, A19-A0, WR ,

RD , DEN , 0

S - 1

S , 6

S , BHE , DT/ R , WHB and WLB are

floating, and the UCS , LCS ,

PCS -

PCS ,

MCS -

MCS

and

PCS -

PCS will be drive high. After HOLD is detected

as being low, the microcontroller will lower HLDA.

45 HOLD

Input

Bus hold request. Active high. This pin indicates that another
bus master is requesting the local bus.

46 SRDY/PIO6

Input/Output

Synchronous ready. This pin performs the microcontroller that
the address memory space or I/O device will complete a data
transfer. The SRDY pin accepts a falling edge that is
asynchronous to CLKOUTA and is active high. SRDY is
accomplished by elimination of the one-half clock period
required to internally synchronize ARDY. Tie SRDY high the
microcontroller is always assert in the ready condition. If the
SRDY is not used, tie this pin low to yield control to ARDY.

Both SRDY and ARDY should be tied to high if the
system need not assert wait state by externality.

DT/ R /PIO4

Output/Input

Data transmit or receive. This pin indicates the direction of
data flow through an external data-bus transceiver. DT/ R low,
the microcontroller receives data. When DT/R is asserted high,
the microcontroller writes data to the data bus.

DEN /PIO5

Output/Input Data enable. This pin is provided as a data bus transceiver

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

output enable. DEN is asserted during memory and I/O access.

DEN is drived high when DT/ R changes state. It is floating

during bus hold or reset condition.

S6/

CLKDIV /PIO29

Output/Input

Bus cycle status bit6/clock divided by 2. For S6 feature, this
pin is low to indicate a microcontroller-initiated bus cycle or
high to indicate a DMA-initiated bus cycle during T2, T3, Tw
and T4. For

CLKDIV feature. The internal clock of

microcontroller is the external clock be divided by 2.
(CLKOUTA, CLKOUTB=X1/2), if this pin held low during
power-on reset. The pin is sampled on the rising edge of

RST .

UZI /PIO26

Output/Input

Upper zero indicate. This pin is the logical OR of the inverted
A19-A16. It asserts in the T1 and is held throughout the cycle.

Chip Select Unit Interface

50
51
68
69

MCS /PIO14

MCS /PIO15

MCS /PIO24

MCS / RFSH /PIO25

Output/Input

Midrange memory chip selects. For MCS feature, these pins
are active low when enable the MMCS(A6h) register to access
a memory. The address ranges are programmable.

MCS -

MCS are held high during bus hold. When

programming LMCS(A2h) register, pin69 is as a RFSH pin to
auto refresh the PSRAM.

UCS /

ONCE

Output/Input

Upper memory chip select/ONCE mode request 1. For UCS
feature, this pin acts low when system accesses the defined
portion memory block of the upper 512K bytes
(80000h-FFFFFh) memory region. UCS default acted
address region is from F0000h to FFFFFh after power-on reset.
The address range acting UCS is programmed by software.
For

ONCE feature. If

ONCE and

ONCE are sampled

low on the rising edge of RST . The microcontroller enters
ONCE mode. In ONCE mode, all pins are high-impedance.
This pin incorporates weakly pull-up resistor.

LCS /

ONCE

Output/Input

Lower memory chip select/ONCE mode request 0. For LCS
feature, this pin acts low when the microcontroller accesses the
defined portion memory block of the lower 512K
(00000h-7FFFFh) memory region. The address range acting

LCS is programmed by software.

For

ONCE feature, see UCS /

ONCE description. This pin

incorporates weakly pull-up register.

59
60

PCS /A2/PIO2

PCS /A1/PIO3

Output/Input

Peripheral chip selects/latched address bit. For PCS feature,
these pins act low when the microcontroller accesses the fifth
or sixth region of the peripheral memory (I/O or memory
space). The base address of PCS is programmable. These pins
assert with the AD address bus and are not float during bus
hold.
For latched address bit feature. These pins output the latched
address A2, A1 when cleared the EX bit in the MCS and

PCS auxiliary register. The A2, A1 retains previous latched

data during bus hold.

62
63
65

PCS /

RTS /

RTR /PIO19

PCS /

CTS /

ENRX PIO18

PCS /PIO17

Output/Input

Peripheral chip selects. These pins act low when the
microcontroller accesses the defined memory area of the
peripheral memory block (I/O or memory address). For I/O

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

PCS /PIO16

accessed, the base address can be programmed in the region
00000h to 0FFFFh.
For memory address access, the base address can be located in
the 1M byte memory address region. These pins assert with the
multiplexed AD address bus and are not float during bus hold.

Interrupt Control Unit Interface

47 NMI

Input

Nonmaskable Interrupt. The NMI is the highest priority
hardware interrupt and is nonmaskable. When this pin is
asserted (NMI transition from low to high), the microcontroller
always transfers the address bus to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt
vector table. The NMI pin must be asserted for at least one
CLKOUTA period to guarantee that the interrupt is recognized.

52 INT4/PIO30

Input/Output

Maskable interrupt request 4. Act high. This pin indicates that
an interrupt request has occurred. The microcontroller will
jump to the INT4 address vector to execute the service routine
if the INT4 is enable. The interrupt input can be configured to
be either edge- or level-triggered. The requesting device must
holt the INT4 until the request is acknowledged to guarantee
interrupt recognition.

INT3/

INTA /IRQ

Input/Output

Maskable interrupt request 3/interrupt acknowledge 1/slave
interrupt request. For INT3 feature, except the difference
interrupt line and interrupt address vector, the function of INT3
is the same as INT4.
For

INTA feature, in cascade mode or special fully-nested

mode, this pin corresponds the INT1.
For IRQ feature, when the microcontroller is as a slave device,
this pin issues an interrupt request to the master interrupt
controller.

INT2/

INTA /PIO31

Input/Output

Maskable interrupt request 2/interrupt acknowledge 0. For
INT2 feature, except the difference interrupt line and interrupt
address vector, the function of INT2 is the same as INT4.
For

INTA feature, in cascade mode or special fully-nested

mode, this pin corresponds the INT0.

INT1/ SELECT

Input/Output

Maskable interrupt request 1/slave select. For INT1 feature,
except the difference interrupt line and interrupt address vector,
the function of INT1 is the same as INT4.
For SELECT feature, when the microcontroller is as a slave
device, this pin is drived from the master interrupt controller
decoding. This pin acts to indicate that an interrupt appears on
the address and data bus.
The INT0 must act before SELECT acts when the interrupt
type appears on the bus.

56 INT0

Input/Output

Maskable interrupt request 0. Except the interrupt line and
interrupt address vector, the function of INT0 is the same as
INT4.

Timer Control Unit Interface

72
75

TMRIN1/PIO0

TMRIN0/PIO11

Input/Output

Timer input. These pins can be as clock or control signal input,
which depend upon the programmed timer mode. After
internally synchronizing low to high transitions on TMRIN, the
timer controller increments. These pins must be pull-up if not
being used.

73
74

TMROUT1/PIO1

TMROUT0/PIO10

Output/Input

Timer output. Depending on timer mode select these pins
provide single pulse or continuous waveform. The duty cycle

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

of the waveform can be programmable. These pins are floated
during a bus hold or reset.

DMA Unit Interface

76
77

DRQ1/INT6/PIO13
DRQ0/INT5/PIO12

Input/Output

DMA request. These pins are asserted high by an external
device when the device is ready for DMA channel 1 or channel
0 to perform a transfer. These pins are level-triggered and
internally synchronized. The DRQ signals must remain act
until finish serviced and are not latched.
For INT6/INT5 function: When the DMA function is not being
used, INT6/INT5 can be used as an additional external
interrupt request. And they share the corresponding interrupt
type and register control bits. The INT6/5 are edge-triggered
only and must be hold until the interrupt is acknowledged.

Notes:

1.When enable the PIO Data register, there are 32 MUX definition pins can be as a PIO pin. For example, the DRD1/PIO13

(pin76) can be as a PIO13 when enable the PIO Data register.

2.The PIO status during Power-On reset : PIO1, PIO10, PIO22, PIO23 are input with pull-down, PIO4 to PIO9 are

normal operation and the others are input with pull-up.

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

5. Basic Application System Block

RS232

Level

Converter

Serial port0

Timer0-1

INT

DMA

PIO

AD7-AD0

A19-A0

Data(8)

Address

UCS

Flash ROM

Data(8)

Address

SRAM

Data

Address

Peripheral

PCS

R8830LV

LCS

BASIC APPLICATION SYSTEM BLOCK (A)

RST

VCC

100K

1uF

Serial port1

RS232

Level

Converter

Serial port0

Timer0-1

INT

DMA

PIO

D7-D0

A19-A0

Data(8)

Address

UCS

Flash ROM

Data(8)

Address

SRAM

Data

Address

Peripheral

PCS

R8830LV

LCS

BASIC APPLICATION SYSTEM BLOCK (B)

RST

VCC

100K

1uF

DIR

Transciver

Latch

DEN

DT/R

AD7-AD0

ALE

AO15-AO8

A19-A16

Serial port1

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

6. Oscillator Characteristics

For fundamental -mode crystal:

Reference

Frequency

10.8288M Hz 19.66M Hz

30M Hz

33M Hz

40M Hz

None None None None None

10Pf 10Pf None None None

10Pf 10Pf 10Pf 10Pf 10Pf

None None None None None

For third-overtone mode crystal:

Reference

Frequency

22.1184M Hz 28.322M Hz 33.177M Hz

40M Hz

44.1M Hz

1M 1.5M 1.5M 1.5M 1.5M

15Pf 15Pf 15Pf 15Pf 15Pf

30Pf 30Pf 30Pf 30Pf 30Pf

220Pf 220Pf 220Pf 120Pf

10uL 4.7uL 2.7uL 2.7uL

R8830LV

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

8. Execution Unit

8.1 General Register

The R8830LV has eight 16-bit general registers. And the AX,BX,CX,DX can be subdivided into two 8-bit register

(AH,AL,BH,

BL,CH,CL,DH,DL). Tthe functions of these registers are described as follows.

AX : Word Divide , Word Multiply, Word I/O operation.

AH : Byte Divide , Byte Multiply, Byte I/O , Decimal Arithmetic, Translate operation.

AL : Byte Divide , Byte Multiply operation.

BX : Translate operation.

CX : Loops, String operation

CL : Variable Shift and Rotate operation.

DX : Word Divide , Word Multiply, Indirect I/O operation

SP : Stack operations (POP, POPA, POPF, PUSH, PUSHA, PUSHF)

BP : General-purpose register which can be used to determine offset address of operands in Memory.

SI : String operations

DI : String operations

8.2 Segment Register

R8830LV has four 16-bit segment registers, CS, DS, SS, ES. The segment registers contain the base addresses (starting

location) of these memory segments, and they are immediately addressable for code (CS), data (DS & ES), and stack (SS)

memory.

Accumulator

Base Register

Count/Loop/Repeat/Shift

Data

Stack Pointer

Destination Index

Base Pointer

Source Index

Data

Group

Index Group

and

Pointer

GENERAL REGISTERS

High

Low

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RISC DSP Controller

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RDC Semiconductor Co.

Rev:1.4

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CS (Code Segment) : The CS register points to the current code segment, which contains instruction to be fetched. The

default location memory space for all instruction is 64K. The initial value of CS register is 0FFFFh.

DS (Data Segment) : The DS register points to the current data segment, which generally contains program variables. The

DS register initialize to 0000H.

SS (Stack Segment ) : The SS register points to the current stack segment, which is for all stack operations, such as pushes

and pops. The stack segment is used for temporary space. The SS register initialize to 0000H.

ES (Extra Segment) : The ES register points to the current extra segment which is typically for data storage, such as large

string operations and large data structures. The DS register initialize to 0000H.

8.3 Instruction Pointer and Status Flags Register

IP (Instruction Pointer) : The IP is a 16-bit register and it contains the offset of the next instruction to be fetched. Software

can not to direct access the IP register and this register is updated by the Bus Interface Unit. It can change, be saved or be

restored as a result of program execution. The IP register initialize to 0000H and the CS:IP starting execution address is at

0FFFF0H.

These flags reflect the status after the Execution Unit is executed.

Bit 15-12 : Reserved

Bit 11: OF, Overflow Flag. An arithmetic overflow has occurred, this flag will be set.

Bit 10 : DF, Direction Flag. If this flag is set, the string instructions are increment address process. If DF is cleared, the string

instructions are decrement address process. Refer the STD and CLD instructions for how to set and clear the DF flag.

Code Segment

Data Segment

Stack Segment

Extra Segment

SEGMENT REGISTERS

Processor Status Flags Registers

FLAGS

Reset Value : 0000h

Res

Reserved

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RISC DSP Controller

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Rev:1.4

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Bit 9 : IF, Interrupt-Enable Flag. Refer the STI and CLI instructions for how to set and clear the IF flag.

Set to 1 : The CPU enables the maskable interrupt request.

Set to 0 : The CPU disables the maskable interrupt request.

Bit 8: TF, Trace Flag. Set to enable single-step mode for debugging; Clear to disable the single-step mode. If an application

program sets the TF flag using POPF or IRET instruction, a debug exception is generated after the instruction (The

CPU automatically generates an interrupt after each instruction) that follows the POPF or IRET instruction.

Bit 7: SF, Sign Flag. If this flag is set, the high-order bit of the result of an operation is 1

indicating it is negative.

Bit 6: ZF, Zero Flag. The result of operation is zero, this flag is set.

Bit 5: Reserved

Bit 4: AF, Auxiliary Flag. If this flag is set, there has been a carry from the low nibble to the high or a borrow from the high

nibble to the low nibble of the AL general-purpose register. Used in BCD operation.

Bit 3: Reserved.

Bit 2: PF, Parity Flag. The result of low-order 8 bits operation has even parity, this flag is set.

Bit 1: Reserved

Bit 0: CF, Carry Flag. If CF is set, there has been a carry out or a borrow into the high-order bit of the instruction result.

8.4 Address generation

The Execution Unit generates a 20-bit physical address to Bus Interface Unit by the Address Generation. Memory is organized

in sets of segments. Each segment contains a 16 bits value. Memory is addressed using a two-component address that consists

of a 16-bit segment and 16-bit offset. The Physical Address Generation figure describes how the logical address transfers to the

physical address.

TO Memory

Physical Address

Segment Base

Offset

Logical

Address

Shift left 4 bits

Physical Address Generation

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

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9. Peripheral Control Block Register

The peripheral control block can be mapped into either memory or I/O space which is to program the FEh register. And it

starts at FF00h in I/O space when reset the microprocessor.

The following table is the definition of all the peripheral Control Block Register , and the detail description will arrange on

the relation Block Unit.

Offset

(HEX)

Page

Offset

(HEX)

Page

FE Peripheral Control Block Relocation Register

70 PIO Mode 0 Register

F6 Reset Configuration Register

66 Timer 2 Mode / Control Register

F4 Processor Release Level Register

62 Timer 2 Maxcount Compare A Register

F2 Serial Port Flow Control Register

60 Timer 2 Count Register

F0 System configuration register

5E Timer 1 Mode / Control Register

E6 Watchdog timer control register

5C Timer 1 Maxcount Compare B Register

E4 Enable RCU Register

5A Timer 1 Maxcount Compare A Register

E2 Clock Prescaler Register

58 Timer 1 Count Register

E0 Memory Partition Register

56 Timer 0 Mode / Control Register

DA DMA 1 Control Register

54 Timer 0 Maxcount Compare B Register

D8 DMA 1 Transfer Count Register

52 Timer 0 Maxcount Compare A Register

D6 DMA 1 Destination Address High Register

50 Timer 0 Count Register

D4 DMA 1 Destination Address Low Register

44 Serial Port 0 interrupt control register

D2 DMA 1 Source Address High Register

42 Serial port 1 interrupt control register

D0 DMA 1 Source Address Low Register

40 INT4 Control Register

CA DMA 0 Control Register

3E INT3 Control Register

C8 DMA 0 Transfer Count Register

3C INT2 Control Register

C6 DMA 0 Destination Address High Register

3A INT1 Control Register

C4 DMA 0 Destination Address Low Register

38 INT0 Control Register

C2 DMA 0 Source Address High Register

36 DMA 1/INT6 Interrupt Control Register

C0 DMA 0 Source Address Low Register

34 DMA 0/INT5 Interrupt Control Register

PCS and MCS Auxiliary Register

32 Timer Interrupt Control Register

A6 Midrange Memory Chip Select Register

30 Interrupt Status Register

A4 Peripheral Chip Select Register

2E Interrupt Request Register

A2 Low Memory Chip Select Register

2C Interrupt In-service Register

A0 Upper Memory Chip Select Register

2A InterruptPriority Mask Register

88 Serial Port 0 Baud Rate Divisor Register

28 Interrupt Mask Register

86 Serial Port 0 Receive Register

26 Interrupt Poll Status Register

84 Serial Port 0 Transmit Register

24 Interrupt Poll Register

82 Serial Port 0 Status Register

22 Interrupt End-of-Interrupt

80 Serial Port 0 Control Register

20 Interrupt Vector Register

7A PIO Data 1 Register

18 Serial port 1 baud rate divisor

78 PIO Direction 1 Register

16 Serial port 1 receive register

76 PIO Mode 1 Register

14 Serial port 1 transmit register

74 PIO Data 0 Register

12 Serial port 1 status register

72 PIO Direction 0 Register

10 Serial port 1 control register

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

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The peripheral control block is mapped into either memory or I/O space by programming this register. When the other chip

selects ( PCSx or MCSx ) are programmed to zero wait states and ignore the external ready, the PCSx or MCSx can overlap

the control block.

Bit 15: Reserved

Bit 14: S/ M , Slave/Master Configures the interrupt controller

set 0 : Master mode, set 1: Slaved mode

Bit 13 : Reserved

Bit 12: M/ IO , Memory/IO space. At reset, this bit is set to 0 and the PCB map start at FF00h in I/O space.

set 1- The peripheral control block (PCB) is located in memory space.

set 0- The PCB is located in I/O space.

Bit 11-0 : R19-R8 , Relocation Address Bits

The upper address bits of the PCB base address. The lower eight bits default to 00h. When the PCB is mapped to I/O

space, the R19-R16 must be programmed to 0000b.

Read only register that specifies the processor release version and RDC identify number

Bit 15-8 : Processor version

01h : version A , 02h : version B, 03h : version C, 04h : version D

Bit 7-0 : RDC identify number - D9h

Peripheral Control Block Relocation Register:

Offset : FEh

Reset Value : 20FFh

Res

R19 - R8

M/IO

S/M

Processor Release Level Register

Offset : F4h

Reset Value : D9h

PRL

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

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10. System Clock Block

Bit 15: PSEN , Enable Power-save Mode. This bit is cleared by hardware when an external interrupt occurs. This bit does not

be changed when software interrupts (INT instruction) and exceptions occurs.

Set 1: enable power-save mode and divides the internal operating clock by the value in F2-F0.

Bit14 : MCSBIT,

MCS control bit. Set to 0: The

MCS operate normally. Set to 1:

MCS is active over the entire

MCSx range

Bit13-12: Reserved

Bit 11: CBF, CLKOUTB Output Frequency selection.

Set 1: CLKOUTB output frequency is same as crystal input frequency.

Set 0 : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor

internal clock.

Bit 10 : CBD, CLKOUTB Drive Disable

Set 1: Disable the CLKOUTB. This pin will be three-state.

Set 0 : Enable the CLKOUTB.

Bit 9: CAF, CLKOUTA Output Frequency selection.

Set 1: CLKOUTA output frequency is same as crystal input frequency.

Set 0 : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor

CLKIN

CLKIN/2

CLOCK

Divisior

(CLK/2-CLK/128)

MUX

CAF(F0h.9)

MUX

CBF(F0h.11)

CAD(F0h.8)

CBD(F0h.10)

F2-F0(F0h.2-F0h.0)

PSEN(F0h.15)

CLK

CLKIN

CLKIN/2 Select

S6/CLKDIV2

CLKOUTA

CLKOUTB

Microprocessor Internal Clock

System Clock

enable/disable

Divisor Select

Power-Save Control Register

Offset : F0h

Reset Value : 0000h

MCSBIT

PSEN

CAD

CAF

CBD

CBF

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

internal clock .

Bit 8: CAD, CLKOUTA Drive Disable.

Set 1: Disable the CLKOUTA. This pin will be three-state.

Set 0 : Enable the CLKOUTA.

Bit 7-3 : Reserved

Bit 2-0: F2- F0, Clock Divisor Select.

F2, F1, F0 ----- Divider Factor

0, 0, 0 ---- Divide by 1

0, 0, 1 ---- Divide by 2

0, 1, 0 ---- Divide by 4

0, 1, 1 ---- Divide by 8

1, 0, 0 ---- Divide by 16

1, 0, 1 ---- Divide by 32

1, 1, 0 ---- Divide by 64

1, 1, 1 ---- Divide by 128

11. Reset

Processor initialization is accomplished with activation of the RST pin. To reset the processor, this pin should be held low

for at least seven oscillator periods. The Reset Status Figure shows the status of the RST pin and others relation pins.

When RST from low go high , the state of input pin (with weakly pull-up or pull-down) will be latched , and each pin will

perform the individual function. The AO15-AO8,AD7-AD0 will be latched into the register F6h. UCS /

ONCE ,

LCS /

ONCE will enter ONCE mode (All of the pins will floating except X1 , X2) when with pull-low resisters. The input

clock will divide by 2 when S6/

CLKDIV with pull-low resister. TheAO15-AO8, AD7-AD0 bus will not drive the address

phase during UCS , LCS cycle if BHE / ADEN with pull-low resister

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15- 0 : RC ,Reset Configuration AD15 AD0.

The AO15 to AO8, AD7 to AD0 must with weakly pull-up or pull-down resistors to correspond the contents when AO15 to

AO8,AD7-AD0 be latched into this register during the RST pin from low go high. And the value of the reset configuration

register provides the system information when software read this register. This register is read only and the contents remain

valid until the next processor reset.

Reset Configuration Register

Offset : F6h

Reset Value : AD15-AD0

CLKOUTA

A19-A0

AD7-AD0

ALE

BHE

DEN

S2-S0

ffff0

min 7T

UCS

Reset Status

(float)

(input)

(float)

DT/R

(input)

RST

(input)

AO15-AO8

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

12. Bus Interface Unit

The bus interface unit drives address, data, status and control information to define a bus cycle. The bus A19-A0 are

non-multiplex memory or I/O address. The AD15-AD0 are multiplexed address and data bus for memory or I/O accessing.

The 2

S - 1

S are encoded to indicate the bus status, which is described in the Pin Description table in page 5. The Basic

Application System Block (page 10) and Read/Write Timing Diagram (page 12) describe the basic bus operation.

12.1 Memory and I/O interface

The memory space consists of 1M bytes (512k 16-bit port) and the I/O space consists of 64k bytes (32k 16-bit port). Memory

devices exchange information with the CPU during memory read, memory write and instruction fetch bus cycles. I/O read

and I/O write bus cycles use a separate I/O address space. Only IN/OUT instruction can access I/O address space, and

information must be transferred between the peripheral device and the AX register. The first 256 bytes of I/O space can be

accessed directly by the I/O instructions. The entire 64k bytes I/O address space can be accessed indirectly, through the DX

12.2 Data Bus

The memory address space data bus is physically implemented by dividing the address space into two banks of up to 512k

bytes. Each one bank connects to the lower half of the data bus and contains the even-addressed bytes (A0=0). The other

Memory

Space

FFFFFH

1M Bytes

I/O

Space

0FFFFH

64K Bytes

Memory and I/O Space

FFFFF

FFFFD

FFFFE

FFFFC

512K Bytes

A19:1

D15:8

BHE

D7:0

Physical Data Bus Models

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

bank connects to the upper half of the data bus and contains odd-addressed bytes (A0=1). A0 and BHE determine whether

one bank or both banks participate in the data transfer.

12.3 Wait States

Wait states extend the data phase of the bus cycle. The ARDY or SRDY input with low level will insert wait states. If R2 bit=0,

The user also can inserts wait state by programmed the internal chip select registers.

The R2 bit of UMCS ( offset 0A0h) default is low, so each one of the ARDY or SRDY should in ready

state (with pull high resistor) when at power on reset or external reset.

The wait state counter value is decided by the R3,R1,R0 bits in each chip select register. There are five group R3,R1,R0 bits in

the registers offset A0h, A2h, A4h, A6h, A8h. Each group is independent.

12.4 Bus Hold

When the bus hold requested ( HOLD pin active high) by the another bus master, the microprocessor will issue a HLDA

Wait State

Counter

Rising

Edge

R2 bit in control

registers

Bus

Ready

CLKOUTA

ARDY

SRDY

Wait-state block Diagram

Bus Ready is active High

R2 bit in UMCS default is"0", so CPU is required

external ready at power-on reset.

The wait state counter value is located at

control registers in chip select unit.

Falling

Edge

CLKOUTA

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Rev:1.4

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in response to a HOLD request at the end of T4 or Ti. When the microprocessor is in hold status (HLDA is high), the

AD15-AD0, A19-A0, WR , RD , DEN , 1

S - 0

S , 6

S , BHE , DT/ R , WHB and WLB are floating, and the UCS , LCS ,

PCS -

PCS ,

MCS -

MCS and

PCS -

PCS will be drive high. After HOLD is detected as being low, the

microprocessor will lower the HLDA.

CLKOUTA

HOLD

HLDA

A19:A0

DEN

S2:S0

AD15:AD0

DT/R

WLB

BUS HOLD ENTER WAVEFORM

Case 1

Case 2

Floating

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RISC DSP Controller

R8830LV

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Rev:1.4

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12.5 Bus Width

The R8830LV default is 16 bits bus access. And the bus can be programmed as 8-bits or 16-bits access during memory or I/O

access is located in the LCS or MCSx or PCSx address space. The UCS code- fetched selection is 16 bits bus width,

which can not be changed by programmed the register.

Bit 15-7: Reserved.

Bit 6: ENRX1, Enable the Receiver Request of Serial port 1.

Set 1: The

CTS /

ENRX pin is configured as

ENRX

Set 0: The

CTS /

ENRX pin is configured as

CTS

Bit 5: RTS1, Enable Request to Send of Serial port 1.

Set 1: The

RTR /

RTS pin is configured as

RTS

Set 0: The

RTR /

RTS pin is configured as

RTR

Bit 4: ENRX0, Enable the Receiver Request of Serial port 0.

Set 1: The

CTS /

ENRX pin is configured as

ENRX

Set 0: The

CTS /

ENRX pin is configured as

CTS

Bit 3: RTS0, Enable Request to Send of Serial port 0.

Set 1: The

RTR /

RTS pin is configured as

RTS

Set 0: The

RTR /

RTS pin is configured as

RTR

Bit 2: LSIZ, LCS Data Bus Size selection. This bit can not be changed while executing from LCS space or while the

Peripheral Control Block is overlaid with PCS space.

Set 1: 8 bits data bus access when the memory access located in the LCS memory space.

Set 0: 16 bits data bus access when the memory access located in the LCS memory space.

Bit 1: MSIZ, MCSx , PCSx Memory Data Bus Size selection. This bit can not be changed while executing from the

associated or while the Peripheral Control Block is overlaid on this address space.

Set 1: 8 bits data bus access when the memory access locate in the selection memory space.

Set 0 : 16 bits data bus access when the memory access locate in the selection memory space.

Bit 0: IOSIZ, I/O Space Data Bus Size selection. This bit determines the width of the data bus for all I/O space accesses.

Set 1: 8 bits data bus access.

Set 0 : 16 bits data bus access.

Auxiliary configuration Register

Offset : F2h

Reset Value : 0000h

Reserved

ENRX1

RTS1

ENRX0

RTS0 LSIZ MSIZ IOSIZ

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

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13. Chip Select Unit

The Chip Select Unit provides 12 programmable chip select pins to access a specific memory or peripheral device.

The chip selects are programmed through five peripheral control registers (A0h, A2h, A4h, A6h, A8h). And all of the

chip selects can be insert wait states by programmed the peripheral control register.

13.1

UCS

The UCS default to active on reset for program code access. The memory active range is upper 512k (80000h FFFFFh),

which is programmable. And the default memory active range of UCS is 64k ( F0000h FFFFFh).

The UCS active to drive low four CLKOUTA oscillators if no wait state inserts. There are three wait-states insert to UCS

active cycle on reset.

Bit 15 : Reserved

Bit 14-12 : LB2-LB0, Memory block size selection for UCS chip select pin.

The UCS chip select pin active region can be configured by the LB2-LB0.

The default memory block size is from F0000h to FFFFFh.

LB2, LB1, LB0 ---- Memory Block size , Start address, End Address

1 , 1 , 1 ---- 64k , F0000h , FFFFFh

1 , 1 , 0 ---- 128k , E0000h , FFFFFh

1 , 0 , 0 ---- 256k , C0000h , FFFFFh

0 , 0 , 0 ---- 512k , 80000h , FFFFFh

Bit 11-8 : Reserved

Bit 7 : DA , Disable Address. If the BHE / ADEN pin is held high on the rising edge of RST , then the DA bit is valid to

enable/disable the address phase of the AD bus. If the BHE / ADEN pin is held high on the rising edge of RST , the

AD bus always drive the address and data.

Set 1 : Disable the address phase of the AD15 AD0 bus cycle when UCS is asserted.

Set 0 : Enable the address phase of the AD15 AD0 bus cycle when UCS is asserted.

Bit 6-3: Reserved

Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for UCS chip select.

Set 1: external ready is ignored.

Set 0: external ready is required.

Bit 1-0 : R1-R0, Wait-State value. When R2 is set to 0, it can inserted wait-state into an access to the UCS memory area.

Upper Memory Chip Select Register

Offset : A0h

Reset Value :F03Bh

LB2 - LB0

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RISC DSP Controller

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RDC Semiconductor Co.

Rev:1.4

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(R1,R0) = (0,0) -- 0 wait-state ; (R1,R0) = (0,1) -- 1 wait-state

(R1,R0) = (1,0) -- 2 wait-state ; (R1,R0) = (1,1) -- 3 wait-state

13.2

LCS

The lower 512k bytes (00000h-7FFFFh) memory region chip selects. The memory active range is programmable, which

has no default size on reset. So the A2h register must be programmed first before to access the target memory range. The LCS

pin is not active on reset, but any read or write access to the A2h register activates this pin.

Bit 15: Reserved

Bit 14-12 : UB2-UB0, Memory block size selection for LCS chip select pin

The LCS chip select pin active region can be configured by the UB2-UB0.

The LCS pin is not active on reset, but any read or write access to the A2h (LMCS) register activates this pin.

UB2, UB1, UB0 ---- Memory Block size , Start address, End Address

0 , 0 , 0 ---- 64k , 00000h , 0FFFFh

0 , 0 , 1 ---- 128k , 00000h , 1FFFFh

0 , 1 , 1 ---- 256k , 00000h , 3FFFFh

1 , 1 , 1 ---- 512k , 00000h , 7FFFFh

Bit 11-8 : Reserved

Bit 7 : DA , Disable Address. If the BHE / ADEN pin is held high on the rising edge of RST , then the DA bit is valid to

enable/disable the address phase of the AD bus. If the BHE / ADEN pin is held low on the rising edge of RST , the

AD bus always drive the address and data.

Set 1 : Disable the address phase of the AD15 AD0 bus cycle when LCS is asserted.

Set 0 : Enable the address phase of the AD15 AD0 bus cycle when LCS is asserted.

Bit 6 : PSE, PSRAM Mode Enable. This bit is used to enable PSRAM support for the LCS chip select memory space. The

refresh control unit registers E0h,E2h,E4h must be configured for auto refresh before PSRAM support is enabled.

PSE set to 1: PSRAM support is enable

PSE set to 0: PSRAM support is disable

Bit 5-3: Reserved

Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for LCS chip select.

Set 1: external ready is ignored.

Low Memory Chip Select Register

Offset : A2h

Reset Value :

UB2 - UB0

PSE

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RDC Semiconductor Co.

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Set 0: external ready is required.

Bit 1-0 : R1-R0, Wait-State value. When R2 is set to 0, it can inserted wait-state into an access to the LCS memory area.

(R1,R0) = (0,0) -- 0 wait-state ; (R1,R0) = (0,1) -- 1 wait-state

(R1,R0) = (1,0) -- 2 wait-state ; (R1,R0) = (1,1) -- 3 wait-state

13.3

MCSx

The memory block of MCS4 - MCS0 can be located anywhere within the 1M bytes memory space, exclusive of the

areas associated with the UCS and LCS chip selects. The maximum MCSx active memory range is 512k bytes.

The MCSx chip selects are programmed through two registers A6h and A8h, and these select pins are not active on reset.

Both A6h and A8h registers must be accessed with a read or write to activate MCS4 - MCS0 . There aren't default value on

A6h and A8h registers, so the A6h and A8h must be programmed first before MCS4 - MCS0 active.

Bit 15-7 : BA19-BA13, Base Address. The BA19-BA13 correspond to bits 19-13 of the 1M bytes (20-bits) programmable

base address of the MCS chip select block. The bits 12 to 0 of the base address are always 0.

The base address can be set to any integer multiple of the size of the memory block size selected in these bits. For

example, if the midrange block is 32Kbytes, only the bits BA19 to BA15 can be programmed. So the block address

could be locate at 20000h or 38000h but not in 22000h.

The base address of the MCS chip select can be set to 00000h only if the LCS chip select is not active. And the

MCS chip select address range is not allowed to overlap the LCS chip select address range.

The MCS chip select address range also is not allowed to overlap the UCS chip select address range.

Bit 8-3 : Reserved

Bit 2: R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the MCS chip selects. The R1,R0

bits of this register determine the number of wait state to insert.

set to 1: external ready is ignored

set to 0: external ready is required

Bit 1-0 : R1-R0, Wait-State value. The R1,R0 determines the number of wait states inserted into a MCS access.

(R1,R0) : (1,1) 3 wait states , (1,0) 2 wait states, (0,1) 1 wait states , (0,0) 0 wait states

Midranage Memory Chip Select Register

Offset : A6h

Reset Value :

BA19 - BA13

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RISC DSP Controller

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Rev:1.4

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Bit 15: Reserved

Bit 14-8: M6-M0, MCS Block Size. These bits determines the total block size for the MCS3 - MCS0 chip selects. Each

individual chip select is active for one quarter of the total block size. For example, if the block size is 32K bytes

and the base address is located at 20000h. The individual active memory address range of MCS3 to MCS0 is

MCS0 20000h to 21FFF, MCS1 -22000 to 23FFFh, MCS2 - 24000h to 25FFFh, MCS3 - 26000h to 27FFFh.

MCSx total block size is defined by M6-M0,

M6-M0 , Total block size, MCSx address active range

0000001b , 8k , 2k

0000010b , 16k , 4k

0000100b , 32k , 8k

0001000b , 64k , 16k

0010000b , 128k , 32k

0100000b , 256k , 64k

1000000b , 512k , 128k

Bit 7 : EX, Pin Selector. This bit configures the multiplex output which the PCS6 - PCS5 pins as chip selects or A2-A1.

Set 1 : PCS6 , PCS5 are configured as peripheral chip select pins.

Set 0: PCS6 is configured as address bit A2, PCS5 is configured as A1.

Bit 6: MS, Memory or I/O space Selector.

Set 1: The PCSx pins are active for memory bus cycle.

Set 0: The PCSx pins are active for I/O bus cycle.

Bit 5-3 : Reserved

Bit 2 : R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS5,PCS6 chip selects. The

R1,R0 bits of this register determine the number of wait state to insert.

set to 1: external ready is ignored

set to 0: external ready is required

Bit 1-0 : R1-R0, Wait-State value. The R1,R0 determines the number of wait states inserted into a PCS5 - PCS6 access.

(R1,R0) : (1,1) 3 wait states , (1,0) 2 wait states, (0,1) 1 wait states , (0,0) 0 wait states

13.4

PCSx

The peripheral or memory chip selects which are programmed through A4h and A8h register to define these pins.

Offset : A8h

Reset Value :

M6 - M0

PCS and MCS Auxiliary Register

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RISC DSP Controller

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The base address memory block can be located anywhere within the 1M bytes memory space, exclusive of the areas associated

with the MCS4 , LCS and MCS chip elects. If the chip selects are mapped to I/O space, the access range is 64k bytes.

PCS6 PCS5 can be configured from 0 wait-state to 3 wait-states.

PCS3 PCS0 can be configured from 0 wait-state to 15

wait-states.

Bit 15-7 : BA19-BA11, Base Address. BA19-BA11 correspond to bit 19-11 of the 1M bytes (20-bits) programmable base

address of the PCS chip select block.

When the PCS chip selects are mapped to I/O space, BA19-BA16 must be wrote to 0000b because the I/O address

bus in only 64K bytes (16-bits) wide.

PCSx address range:

PCS0 : Base Address - Base Address+255

PCS1 : Base Address+256 - Base Address+511

PCS2 : Base Address+512 - Base Address+767

PCS3 : Base Address+768 - Base Address+1023

PCS5 : Base Address+1280 - Base Address+1535

PCS6 : Base Address+1536 - Base Address+1791

Bit 6-4: Reserved

Bit 3: R3; Bit 1-0: R1,R0 ,Wait-State Value. The R3,R1,R0 determines the number of wait-states inserted into a PCS3 -

PCS0 access.

R3, R1, R0 -- Wait States

0, 0, 0 -- 0

0, 0, 1 -- 1

0, 1, 0 -- 2

0, 1, 1 -- 3

1, 0, 0 -- 5

1, 0, 1 -- 7

1, 1, 0 -- 9

1, 1, 1 -- 15

Bit 2 : R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS3 - PCS0 chip selects.

The R3,R1,R0 bits determine the number of wait state to insert.

set to 1: external ready is ignored

Peripheral Chip Select Register

Offset : A4h

Reset Value :

BA19 - BA11

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RISC DSP Controller

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14. Interrupt Controller Unit

There are 16 interrupt requests source connect to the controller: 7 maskable interrupt pins ( INT0 INT6); 2 non-maskable

interrupts (NMI pin , WDT) ; 7 internal unit request source ( Timer 0, 1,2 ;DMA 0,1 ; Asynchronous serial port 0, 1).

14.1 Master Mode and Slave Mode

The interrupt controller can be programmed as a master or slave mode. (program FEh , bit 14). The master mode has two

connections : Fully Nested Mode connection or Cascade Mode connection.

R8830LV

Interrupt Source

INT0

INT1

INT2

INT3

INT4

Interrupt Source

Fully Nested Mode Connections

INT5

INT6

Interrupt Source

Interrupt

Control

Logic

Master/Slave Mode Select

(FEH.14)

Timer0/1/2

Interrupt REQ.

Timer0 REQ.

INT0

Timer1 REQ.

Timer2 REQ.

DMA0 Interrupt REQ.

DMA1 Interrupt REQ.

INT2

INT3

INT4

Asynchronous Serial Port 0

Execation

Unit

Interrupt Type

Interrupt REQ.

In-Service

Register

EOI

Register

Acknowledge

Acknowledge to DMA,

Timer,Serial port Unit

Internal Address/Data Bus

16 Bit

Interrupt Control Unit Block Diagram

Asynchronous Serial Port 1

INT5

INT6

NMI

Watchdog Timer

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14.2 Interrupt Vector, Type and Priority

The following table shows the interrupt vector addresses, type and the priority. The maskable interrupt priority can be changed

by programmed the priority register. The Vector addresses for each interrupt are fixed.

Interrupt source

Interrupt

Type

Vector

Address

EOI

Type

Priority Note

Divide Error Exception

00h

Trace interrupt

01h

04h

1-1

NMI 02h

08h

1-2

Breakpoint Interrupt

03h

0Ch

Slave Mode Connection

INT0

INTA0

IRQ

8259

R8830LV

Cascade

Address Dccode

Select

Cascade Mode Connection

INT0

INTA0

INT1

INTA1

8259

IR7

8259

IR7

CAS3-CAS0

R8830LV

8259

CAS3-CAS0

8259

CAS3-CAS0

INT

INTA

INT

INTA

Interrupt Sources

INT4

INT5

INT6

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INTO Detected Over Flow Exception 04h

10h

Array Bounds Exception

05h

14h

Undefined Opcode Exception

06h

18h

ESC Opcode Exception

07h

1Ch

Timer 0

08h

20h

2-1

*/**

Reserved 09h

DMA 0/INT5

0Ah

28h

DMA 1/INT6

0Bh

2Ch

INT0 0Ch

30h

INT1 0Dh

34h

INT2 0Eh

38h

INT3 0Fh

3Ch

INT4 10h

40h

Asynchronous Serial port 1

11h

44h

Timer 1

12h

48h

2-2

*/**

Timer 2

13h

4Ch

2-3

*/**

Asynchronous Serial port 0

14h

50h

Reserved 15h-1Fh

Note * : When the interrupt occurs in the same time, the priority is (1-1 > 1-2) ; (2-1> 2-2 > 2-3)

Note **: The interrupt types of these sources are programmable in slave mode.

14.3 Interrupt Request

When an interrupt is request, the internal interrupt controller verifies the interrupt is enable (The IF flag is enable, no MSK bit

set ) and that there are no higher priority interrupt requests being serviced or pending. If the interrupt is granted , the interrupt

controller uses the interrupt type to access a vector from the interrupt vector table.

If the external INT is active (level-trigger) to request the interrupt controller service, and the INT pins must hold till the

microcontroller enter the interrupt service routine. There is no interrupt-acknowledge output when running in fully nested

mode, so it should use PIO pin to simulate the interrupt-acknowledge pin if necessary.

14.4 Interrupt Acknowledge

The processor requires the interrupt type as an index into the interrupt table. The internal interrupt can provide the interrupt

type or an external controller can provide the interrupt type.

The internal interrupt controller provides the interrupt type to processor without external bus cycles generation. When an

external interrupt controller is supplying the interrupt type, the processor generates two acknowledge bus cycles, and the

interrupt type is written to the AD7-AD0 lines by the external interrupt controller.

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RISC DSP Controller

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Rev:1.4

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14.5 Programming the Registers

Software is programmed through the registers ( Master mode: 44h, 42h, 40h, 3Eh, 3Ch, 3Ah, 38h, 36h, 34h, 32h, 30h, 2Eh,

2Ch, 2Ah, 28h, 26h, 24h, 22h; Slave Mode: 3Ah, 38h, 36h, 34h, 32h, 30h, 2Eh, 2Ch, 2Ah, 28h,22h, 20h ) to define the

interrupt controller operation.

(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK, Mask.

Set 1: Mask the interrupt source of the asynchronous serial port 0.

Set 0: Enable the serial port 0 interrupt.

Bit 2-0 : PR2-PR0, Priority. These bits determine the priority of the serial port relative to the other interrupt signals.

CLKOUTA

ADDRESS[19:0]

AD15:AD0

ALE

BHE

DEN

S2:S0

INTERRUPT ACKNOWLEDGE CYCLE

(CASECADE OR SLAVE MODE)

INTR ACK

ADDRESS

DT/R

Interrupt

TYPE

INTA0,INTA1

Serial Port 0 Interrupt Control Register

Offset : 44h

Reset Value : 000Fh

Reserved

MSK

PR2

PR1

PR0

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The priority selection:

PR2, PR1, PR0 -- Priority

0 , 0 , 0 -- 0 ( High)

0 , 0 , 1 -- 1

0 , 1 , 0 -- 2

0 , 1 , 1 -- 3

1 , 0 , 0 -- 4

1 , 0 , 1 -- 5

1 , 1 , 0 -- 6

1 , 1 , 1 -- 7 ( Low )

(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK, Mask.

Set 1: Mask the interrupt source of the asynchronous serial port 1.

Set 0: Enable the serial port 1 interrupt.

Bit 2-0 : PR2-PR0, Priority. These bits determine the priority of the serial port relative to the other interrupt signals.

The priority selection:

PR2, PR1, PR0 -- Priority

0 , 0 , 0 -- 0 ( High)

0 , 0 , 1 -- 1

0 , 1 , 0 -- 2

0 , 1 , 1 -- 3

1 , 0 , 0 -- 4

1 , 0 , 1 -- 5

1 , 1 , 0 -- 6

1 , 1 , 1 -- 7 ( Low )

Serial Port 1 Interrupt Control Register

Offset : 42h

Reset Value : 000Fh

Reserved

MSK

PR2

PR1

PR0

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(Master Mode)

Bit 15- 8, bit 6-5 : Reserved

Bit 7: ETM, Edge trigger enable. When this bit set to 1 and Bit 4 set to 0, interrupt is triggered by low go high edge.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT4

Set 0: Enable the INT4 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of 44h

(Master Mode)

Bit 15- 8, bit 6- 5 : Reserved

Bit 7: ETM, Edge trigger enable. When this bit set to 1 and Bit 4 set to 0, interrupt is triggered by low go high edge.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT3

Set 0: Enable the INT3 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of 44h

INT4 Control Register

Offset : 40h

Reset Value : 000Fh

Reserved

MSK

PR2

PR1

PR0

LTM

ETM

INT3 Control Register

Offset : 3Eh

Reset Value : 000Fh

Reserved

MSK

PR2

PR1

PR0

LTM

ETM

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(Master Mode)

Bit 15- 8, bit 6-5 : Reserved

Bit 7: ETM, Edge trigger enable. When this bit set to 1 and Bit 4 set to 0, interrupt is triggered by low go high edge.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT2

Set 0: Enable the INT2 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode)

Bit 15-8 : Reserved

Bit 7: ETM, Edge trigger enable. When this bit set to 1 and Bit 4 set to 0, interrupt is triggered by low go high edge.

Bit 6: SFNM, Special Fully Nested Mode.

Set 1: Enable the special fully nested mode of INT1

Bit 5: C, Cascade Mode. Set this bit to 1 to enable the cascade mode for INT1 or INT0.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT1

Set 0: Enable the INT1 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

INT2 Control Register

Offset : 3Ch

Reset Value : 000Fh

Reserved

MSK

PR2

PR1

PR0

LTM

ETM

INT1 Control Register

Offset : 3Ah

Reset Value : 000Fh

Reserved

MSK

PR2

PR1

PR0

LTM

SFNM

ETM

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(Slave Mode) , This register is for timer 2 interrupt control, reset value is 0000h

Bit 15- 4 : Reserved

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the Timer 2

Set 0: Enable the Timer 2 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode)

Bit 15-8 : Reserved

Bit 7: ETM, Edge trigger enable. When this bit set to 1 and Bit 4 set to 0, interrupt is triggered by low go high edge.

Bit 6: SFNM, Special Fully Nested Mode.

Set 1: Enable the special fully nested mode of INT0.

Bit 5: C, Cascade Mode. Set this bit to 1 to enable the cascade mode for INT1 or INT0.

Bit 4: LTM, Level-Triggered Mode.

Set 1: Interrupt is triggered by high active level

Set 0 : Interrupt is triggered by low go high edge.

Bit 3 : MSK, Mask.

Set 1: Mask the interrupt source of the INT0

Set 0: Enable the INT0 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Slave Mode),For Timer 1 interrupt control register, reset value is 0000h

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the timer 1

Set 0: Enable the timer 1 interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

INT0 Control Register

Offset : 38h

Reset Value : 000Fh

Reserved

MSK

PR2

PR1

PR0

LTM

SFNM

ETM

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(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the DMA 1 controller

Set 0: Enable the DMA 1 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Slave Mode), reset value is 0000h

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the DMA 1 controller

Set 0: Enable the DMA 1 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the DMA 0 controller

Set 0: Enable the DMA 0 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Slave Mode), reset value is 0000h

DMA 1/INT6 Interrupt Control Register

Offset : 36h

Reset Value : 000Fh

MSK

PR2

PR1

PR0

DMA 0/INT5 Interrupt Control Register

Offset : 34h

Reset Value : 000Fh

MSK

PR2

PR1

PR0

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Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the DMA 0 controller

Set 0: Enable the DMA 1 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode)

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the timer controller

Set 0: Enable the timer controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Slave Mode), reset value is 0000h

Bit 15-4 : Reserved

Bit 3: MSK , Mask.

Set 1: Mask the interrupt source of the timer 0 controller

Set 0: Enable the timer 0 controller interrupt.

Bit 2-0: PR, Interrupt Priority

These bits setting for priority selection is same as bit 2-0 of the register 44h

(Master Mode), Reset value undefine

Bit 15 : DHLT, DMA Halt.

Set 1: halts any DMA activity. When non-maskable interrupts occur.

Timer Interrupt Control Register

Offset : 32h

Reset Value : 000Fh

MSK

PR2

PR1

PR0

Interrupt Status Register

Offset : 30h

Reset Value :

Reserved

TMR2 TMR1 TMR0

DHLT

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Set 0: When an IRET instruction is executed.

Bit 14-3 : Reserved.

Bit 2-0 : TMR2-TMR0,

Set 1: indicates the corresponding timer has an interrupt request pending.

(Slave Mode), Reset value is 0000h

Bit 15 : DHLT, DMA Halt.

Set 1: halts any DMA activity. When non-maskable interrupts occur.

Set 0: When an IRET instruction is executed.

Bit 14-3 : Reserved.

Bit 2-0 : TMR2-TMR0,

Set 1: indicates the corresponding timer has an interrupt request pending.

(Master Mode)

The Interrupt Request register is a read-only register. For internal interrupts (SP0, SP1, D1/I6, D0/I5, and TMR), the

corresponding bit is set to 1 when the device requests an interrupt. The bit is reset during the internally generated interrupt

acknowledge. For INT4-INT0 external interrupts, the corresponding bit (I4-I0) reflects the current value of the external signal.

Bit 15-11 : Reserved.

Bit 10 : SP0, Serial Port 0 Interrupt Request. Indicates the interrupt state of the serial port 0.

Bit 9 : SP1, Serial Port 1 Interrupt Request. Indicates the interrupt state of the serial port 1.

Bit 8-4 : I4-I0, Interrupt Requests.

Set 1: The corresponding INT pin has an interrupt pending.

Bit 3-2 : D1/I6-D0/I5, DMA Channel or INT Interrupt Request.

Set 1: The corresponding DMA channel or INT has an interrupt pending.

Bit 1: Reserved.

Bit 0 : TMR, Timer Interrupt Request.

Set 1: The timer control unit has an interrupt pending.

Interrupt Request Register

Offset : 2Eh

Reset Value :

Reserved

D0/I5

Res

TMR

D1/I6

SP1

SP0

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(Slave Mode)

The Interrupt Request register is a read-only register. For internal interrupts (D1/I6, D0/I5, TMR2, TMR1, and TMR0), the

corresponding bit is set to 1 when the device requests an interrupt. The bit is reset during the internally generated interrupt

acknowledge.

Bit 15-6 : Reserved.

Bit 5-4 : TMR2/TMR1, Timer2/Timer1 Interrupt Request.

Set 1: Indicates the state of any interrupt requests form the associated timer.

Bit 3-2 : D1/I6-D0/I5, DMA Channel or INT Interrupt Request.

Set 1: Indicates the corresponding DMA channel or INT has an interrupt pending.

Bit 1 : Reserved.

Bit 0 : TMR0, Timer 0 Interrupt Request.

Set 1: Indicates the state of an interrupt request from Timer 0.

(Master Mode)

The bits in the INSERV register are set by the interrupt controller when the interrupt is taken. Each bit in the register is cleared

by writing the corresponding interrupt type to the EOI register.

Bit 15-11 : Reserved.

Bit 10 : SP0, Serial Port 0 Interrupt In-Service.

Set 1: the serial port 0 interrupt is currently being serviced.

Bit 9 : SP1, Serial Port 1 Interrupt In-Service.

Set 1: the serial port 1 interrupt is currently being serviced.

Bit 8-4 : I4-I0, Interrupt In-Service.

Set 1: the corresponding INT interrupt is currently being serviced.

Bit 3-2 : D1/I6-D0/I5, DMA Channel or INT Interrupt In-Service.

Set 1: the corresponding DMA channel or INT interrupt is currently being serviced.

Bit 1 : Reserved.

Interrupt Request Register

Offset : 2Eh

Reset Value : 0000h

Reserved

D0/I5

Res TMR0

D1/I6

TMR1

TMR2

In - Service Register

Offset : 2Ch

Reset Value : 0000h

Reserved

D0/I5

Res

TMR

D1/I6

SP1

SP0

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Bit 0 : TMR, Timer Interrupt In-Service.

Set 1: the timer interrupt is currently being serviced.

(Slave Mode)

The bits in the In-Service register are set by the interrupt controller when the interrupt is taken. The in-

service bits are

cleared by writing to the EOI register.

Bit 15-6 : Reserved.

Bit 5-4 : TMR2-TMR1, Timer2/Timer1 Interrupt In-Service.

Set 1: the corresponding timer interrupt is currently being serviced.

Bit 3-2 : D1/I6-D0/I5, DMA Channel or INT Interrupt In-Service.

Set 1: the corresponding DMA Channel or INT Interrupt is currently being serviced.

Bit 1 : Reserved.

Bit 0 : TMR0, Timer 0 Interrupt In-Service.

Set 1: the Timer 0 interrupt is currently being serviced.

(Master Mode)

Determining the minimum priority level at which maskable interrupts can generate an interrupt.

Bit 15-3 : Reserved.

Bit 2-0 : PRM2-PRM0, Priority Field Mask. Determining the minimum priority that is required in order for a maskable

interrupt source to generate an interrupt.

Priority PR2-PR0

(High) 0

000

1 001
2 010
3 011
4 100
5 101
6 110

Priority Mask Register

Offset : 2Ah

Reset Value : 0007h

PRM2 PRM1 PRM0

In - Service Register

Offset : 2Ch

Reset Value : 0000h

Reserved

Res TMR0

TMR1

TMR2

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Rev:1.4

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(Low) 7

111

(Slave Mode)

Determining the minimum priority level at which maskable interrupts can generate an interrupt.

Bit 15-3 : Reserved.

Bit 2-0 : PRM2-PRM0, Priority Field Mask. Determining the minimum priority that is required in order for a maskable

interrupt source to generate an interrupt.

Priority PR2-PR0

(High) 0

000

1 001
2 010
3 011
4 100
5 101
6 110

(Low) 7

111

(Master Mode)

Bit 15-11 : Reserved.

Bit 10 : SP0, Serial Port 0 Interrupt Mask. The state of the mask bit of the asynchronous serial port 0 interrupt.

Bit 9 : SP1, Serial Port 1 Interrupt Mask. The state of the mask bit of the asynchronous serial port 1 interrupt.

Bit 8-4 : I4-I0, Interrupt Masks. Indicates the state of the mask bit of the corresponding interrupt.

Bit 3-2 : D1/I6-D0/I5, DMA Channel or INT Interrupt Masks.

Indicates the state of the mask bit of the corresponding DMA Channel or INT interrupt.

Bit 1: Reserved.

Bit 0 : TMR, Timer Interrupt Mask. The state of the mask bit of the timer control unit .

(Slave Mode)

Bit 15-6 : Reserved.

Interrupt Mask Register

Offset : 28h

Reset Value : 07FDh

D0/I5

Res

TMR

D1/I6

SP1

SP0

Reserved

Interrupt Request Register

Offset : 28h

Reset Value : 003Dh

Reserved

D0/I5

Res TMR0

D1/I6

TMR1

TMR2

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Bit 5-4 : TMR2-TMR1, Timer 2/Timer1 Interrupt Mask. The state of the mask bit of the Timer Interrupt Control register.

Set 1: Timer2 or Time1 has its interrupt requests masked

Bit 3-2 : D1/I6-D0/I5, DMA Channel or INT Interrupt Mask.

Indicating the state of the mask bits of the corresponding DMA or INT6/INT5 control register.

Bit 1 : Reserved.

Bit 0 : TMR0, Timer 0 Interrupt Mask. The state of the mask bit of the Timer Interrupt Control Register

(Master Mode)

The Poll Status (POLLST) register mirrors the current state of the Poll register. the POLLST register can be read without

affecting the current interrupt request.

Bit 15 : IREQ, Interrupt Request.

Set 1: if an interrupt is pending. The S4-S0 field contains valid data.

Bit 14-5 : Reserved.

Bit 4-0 : S4-S0, Poll Status. Indicates the interrupt type of the highest priority pending interrupt.

(Master Mode)

When the Poll register is read, the current interrupt is acknowledged and the next interrupt takes its place in the Poll register.

Bit 15 : IREQ, Interrupt Request.

Set 1: if an interrupt is pending. The S4-S0 field contains valid data.

Bit 14-5 : Reserved.

Bit 4-0 : S4-S0, Poll Status. Indicates the interrupt type of the highest priority pending interrupt.

Poll Status Register

Offset : 26h

Reset Value :

S4 - S0

Reserved

IREQ

Poll Register

Offset : 24h

Reset Value :

S4 - S0

Reserved

IREQ

End - Of - Interrupt

Offset : 22h

Reset Value :

S4 - S0

NSPEC

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(Master Mode)

Bit 15 : NSPEC, Non-Specific EOI.

Set 1: indicates non-specific EOI.

Set 0: indicates the specific EOI interrupt type in S4-S0.

Bit 14-5 : Reserved.

Bit 4-0: S4-S0, Source EOI Type. Specifies the EOI type of the interrupt that is currently being processed.

(Slave Mode)

Bit 15-3 : Reserved.

Bit 2-0 : L2-L0, Interrupt Type. Encoded value indicating the priority of the IS(interrupt service) bit to reset. Writes to these

bits cause an EOI to be issued for the interrupt type in slave mode.

(

Slave Mode)

Bit 15-8 : Reserved

Bit 7-3 : T4-T0, Interrupt Type.

The following interrupt type of slave mode can be programmed.

Timer 2 interrupt controller : (T4,T3,T2,T1,T0, 1, 0, 1)b

Timer 1 interrupt controller : (T4,T3,T2,T1,T0, 1, 0, 0)b

DMA 1 interrupt controller : (T4,T3,T2,T1,T0, 0, 1, 1)b

DMA 0 interrupt controller : (T4,T3,T2,T1,T0, 0, 1, 0)b

Timer 0 interrupt controller : (T4,T3,T2,T1,T0, 0, 0, 0)b

Bit 2-0 :Reserved

Interrupt Vector Register

Offset : 20h

Reset Value :

T4 - T0

End - Of - Interrupt

Offset : 22h

Reset Value : 0000h

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

15 DMA Unit

The DMA controller provides the data transfer between the memory and peripherals without the intervention of the CPU.

There are two DMA channels in the DMA unit. Each channel can accept DMA request from one of three sources:

external pin (DRQ0 for channel 0 or DRQ1 for channel 1) or serial port (port 0 or port 1) or Timer 2 overflow. The data

transfer from source to destination can be memory to memory ,or memory to I/O, or I/O to I/O, or I/O to memory. Either bytes

or words can be transferred to or from even or odd addresses and two bus cycles are necessary (read from source and write to

destination) for each data transfer.

15.1 DMA Operation

Every DMA transfer consists of two bus cycles (figure of Typical DMA Transfer) and the two bus cycles can not be separated

by a bus hold request, a refresh request or another DMA request. The registers ( CAh, C8h, C6h, C4h, C2h, C0h, DAh, D8h,

D6h, D4h, D2h, D0h) are used to configure and operate the two DMA channels.

DMA

Control

Logic

Adder Control

Logic

20-bit Adder/Subtractor

C8h-Transfer Counter Channel 0

C6h,C4h-Destination Address Channel 0

C2h,C0h-Source Address Channel 0

D8h-Transfer Counter Channel 1

D6h,D4h-Destination Address Channel 1

D2h,D0h-Source Address Channel 1

Request

Arbitration

Logic

INT

Interrupt Request

CAh.8-Channel 0

CAh.8-Channel 1

Channel Control Register1,DAh

Channel Control Register0,CAh

Internal Address/Data Bus

Timer 2 Request

DRQ0

DRQ1

TDRQ

CAH.4-Channel 0

DAH.4-Channel 1

20 bit

16 bit

DMA Unit Block

Serial Port0

Serial Port1

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

The definition of Bits 15-0 for DMA0 are same as the Bits 15-0 of register DAh for DMA1.

Bit 15-0: TC15-TC0, DMA 0 transfer Count. The value of this register is decremented by 1 after each transfer.

Bit 15-4: Reserved

CLKOUTA

ALE

A19-A0

AD15-AD0

Address

Data

Address

Data

Typical DMA Trarsfer

DMA Transfer Count Register

Offset : C8h (DMA0)

Reset Value :

TC15 - TC0

DMA Destination Address High Register

Offset : C6h (DMA0)

Reset Value :

Reserved

DDA19 - DDA16

DMA Control Registers

Offset : CAh (DMA0)

Reset Value : FFF9h

SINC

SDEC

DINC

DDEC

CHG

Res

TDRQ

SYN0

SYN1

INT

B/W

SM/IO

DM/IO

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

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Bit 3-0: DDA19-DDA16, High DMA 0 Destination Address. These bits are map to A19- A16 during a DMA transfer when

the destination address is in memory space or I/O space. If the destination address is in I/O space (64Kbytes), these

bits must be programmed to 0000b.

Bit 15-0: DDA15-DDA0, Low DMA 0 Destination Address. These bits are mapped to A15- A0 during a DMA transfer.

The value of (DDA19-DDA0)b will increment or decrement by 2 after each DMA transfer.

Bit 15-4: Reserved

Bit 3-0: DSA19-DSA16, High DMA 0 Source Address. These bits are mapped to A19- A16 during a DMA transfer when the

source address is in memory space or I/O space. If the source address is in I/O space (64Kbytes), these bits must be

programmed to 0000b.

Bit 15-0: DSA15-DSA0, Low DMA 0 Source Address. These bits are mapped to A15- A0 during a DMA transfer.

The value of (DSA19-DSA0)b will increment or decrement by 2 after each DMA transfer.

DMA Destination Address Low Register

Offset : C4h (DMA0)

Reset Value :

DDA15 - DDA0

DMA Source Address High Register

Offset : C2h (DMA0)

Reset Value :

DSA19 - DSA16

DMA Source Address Low Register

Offset : C0h (DMA0)

Reset Value :

DSA15 - DSA0

DMA Control Registers

Offset : DAh (DMA1)

Reset Value : FFF9h

SINC

SDEC

DINC

DDEC

CHG

Res

TDRQ

SYN0

SYN1

INT

B/W

SM/IO

DM/IO

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15: DM / IO , Destination Address Space Select.

Set 1: The destination address is in memory space.

Set 0: The destination address is in I/O space.

Bit 14: DDEC, Destination Decrement.

Set 1: The destination address is automatically decrement after each transfer.

The B /W (bit 0) bit determines the decrement value which is by 1 or 2 When both DDEC and DINC bits are

set to 1, the address remains constant

Set 0 : Disable the decrement function.

Bit 13: DINC, Destination Increment.

Set 1: The destination address is automatically increment after each transfer.

The B /W (bit 0) bit determines the increment value which is by 1 or 2

Set 0 : Disable the decrement function.

Bit 12: SM/ IO , Source Address Space Select.

Set 1: The Source address is in memory space.

Set 0: The Source address is in I/O space

Bit 11: SDEC, Source Decrement.

Set 1: The Source address is automatically decrement after each transfer.

The B /W (bit 0) bit determines the decrement value which is by 1 or 2 When both SDEC and SINC bits are set

to 1, the address remains constant

Set 0 : Disable the decrement function.

Bit 10: SINC, Source Increment.

Set 1: The Source address is automatically increment after each transfer.

The B /W (bit 0) bit determines the increment value which is by 1 or 2

Set 0 : Disable the decrement function

Bit 9 : TC, Terminal Count.

Set 1: The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0.

Set 0: The synchronized DMA transfer is terminated when the DMA transfer count register reaches 0.

Unsynchronized DMA transfer is always terminated when the DMA transfer count register reaches 0,

regardless the setting of this bit.

Bit 8 : INT, Interrupt.

Set 1: DMA unit generates an interrupt request when complete the transfer count .

The TC bit must set to 1 to generate an interrupt.

Bit 7-6: SYN1-SYN0, Synchronization Type Selection.

SYN1 , SYN0 -- Synchronization Type

0 , 0 -- Unsynchronized

0 , 1 -- Source synchronized

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

1 , 0 -- Destination synchronized

1 , 1 -- Reserved

Bit 5: P , Priority.

Set 1: It selects high priority for this channel when both DMA 0 and DMA 1 are transfer in same time.

Bit 4: TDRQ, Timer Enable/Disable Request

Set 1: Enable the DMA requests from timer 2.

Set 0: Disable the DMA requests from timer 2.

Bit 3: Reserved

Bit 2: CHG, Changed Start Bit. This bit must set to 1 when will modify the ST bit.

Bit 1: ST, Start/Stop DMA channel.

Set 1: Start the DMA channel

Set 0: Stop the DMA channel

Bit 0 : B /W, Byte/Word Select.
Set 1: The address is incremented or decremented by 2 after each transfer.

Set 0 :The address is incremented or decremented by 1 after each transfer.

Bit 15-0: TC15-TC0, DMA 1 transfer Count. The value of this register is decremented by 1 after each transfer.

Bit 15-4: Reserved

Bit 3-0: DDA19-DDA16, High DMA 1 Destination Address. These bits are map to A19- A16 during a DMA transfer when

the destination address is in memory space or I/O space. If the destination address is in I/O space (64Kbytes), these

bits must be programmed to 0000b.

DMA Transfer Count Register

Offset : D8h (DMA1)

Reset Value :

TC15 - TC0

DMA Destination Address High Register

Offset : D6h (DMA1)

Reset Value :

Reserved

DDA19 - DDA16

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

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Bit 15-0: DDA15-DDA0, Low DMA 1 Destination Address. These bits are mapped to A15- A0 during a DMA transfer.

The value of (DDA19-DDA0)b will increment or decrement by 2 after each DMA transfer.

Bit 15-4: Reserved

Bit 3-0: DSA19-DSA16, High DMA 1 Source Address. These bits are mapped to A19- A16 during a DMA transfer when the

source address is in memory space or I/O space. If the source address is in I/O space (64Kbytes), these bits must be

programmed to 0000b.

Bit 15-0: DSA15-DSA0, Low DMA 1 Source Address. These bits are map to A15- A0 during a DMA transfer.

The value of (DSA19-DSA0)b will increment or decrement by 2 after each DMA transfer.

15.2 External Requests

External DMA requests are asserted on the DRQ pins. The DRQ pins are sampled on the falling edge of CLKOUTA. It takes a

minimum of four clocks before the DMA cycle is initiated by the Bus Interface. The DMA request is cleared four clocks

before the end of the DMA cycle. And no DMA acknowledge is provided, since the chip-selects (MCSx, PCSx) can be

programmed to be active for a given block of memory or I/O space, and the DMA source and destination address registers can

be programmed to point to the same given block.

DMA transfer can be either source or destination synchronized, and it can also be unsynchronized. The Source-Synchronized

Transfer figure shows the typical source-synchronized transfer which provides the source device at least three clock cycles

from the time it is acknowledged to deassert its DRQ line.

DMA Destination Address Low Register

Offset : D4h (DMA1)

Reset Value :

DDA15 - DDA0

DMA Source Address Low Register

Offset : D0h (DMA1)

Reset Value :

DSA15 - DSA0

DMA Source Address High Register

Offset : D2h (DMA1)

Reset Value :

DSA19 - DSA16

Reserved

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

The Destination-Synchronized Transfer figure shows the typical destination-synchronized transfer which differs from a

source-synchronized transfer in that two idle states are added to the end of the deposit cycle. The two idle states extend the

DMA cycle to allow the destination device to deassert its DRQ pin four clocks before the end of the cycle. If the two idle states

were not inserted, the destination device would not have time to deassert its DRQ signal.

CLKOUTA

DRQ(Case1)

DRQ(Case2)

Fetch Cycle

Source-Synchronized Transfers

NOTES:
Case1 : Current source synchronized transfer will not be immediately
followed by another DMA transfer.
Case2 : Current source synchronized transfer will be immediately
followed by antoher DMA transfer.

CLKOUTA

DRQ(Case1)

DRQ(Case2)

Fetch Cycle

Destination-Synchronized Transfers

NETES:
Case1 : Current destination synchronized transfer will not be immediately
followed by another DMA transfer.
Case2 : Current destination synchronized transfer will be immediately
followed by another DMA transfer.

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

15.3 Serial Port/DMA Transfer

The serial port data can be DMA transfer to or from memory( or IO) space. And the B /W bit of DMA control Register must

be set 1 for byte transfer. The map address of Transmit Data Register is written to the DMA Destination Address Register and

the memory (or I/O) address is written to the DMA Source Address Register, when transmit data. The map address of Receive

Data Register is written to the DMA Source Address Register and the memory (or I/O) address is written to the DMA

Destination Address Register, when receive data.

The software is programmed through the Serial Port Control Register to perform the serial port/ DMA transfer.

When a DMA channel is in use by a serial port, the corresponding external DMA request signal is deactivated. For DMA to the

serial port, the DMA channel should be configured as destination synchronized. For DMA from the serial port, the DMA

channel should be configured as source synchronized.

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

16. Timer Control Unit

There are three 16-bit programmable timers in the R8830LV. The timer operation is independent of the CPU. The three timers

can be programmed as a timer element or as a counter element. Timers 0 and 1 are each connect to two external pins (TMRIN0,

TMROUT0, TMRIN1, TMROUT1) which can be used to count or time external events, or they can be used to generate a

variable-duty-cycle waveforms. Timer 2 is not connected any external pins. It can be used as a prescale to timer 0 and timer 1

or as a DMA request source.

These bits definition for timer 0 are same as the bits of register 5Eh for timer 1.

Offset : 50h

Reset Value :

Timer 0 Count Register

TC15 - TC0

Counter

Element

Control

Logic

Microprocessor Clock

50h,Timer 0 Count Register

58h,Timer 1 Compare Register

52h,54h,Timer0 Maxcount Compare Register

5Ah,5Ch,Timer 1 Maxcount Compare Register

62h,Timer 2 Count Register

60h,Timer 2 count Register

Interrupt Request

5Eh,Timer 1 Control Register

56h,Timer 0 Control Register

Internal Address/Data Bus

TMROUT1

TMROUT2

16 bit

Timer / Counter Unit Block

16 bit

DMA Request

66h,Timer 2 Control Register

TMRIN1 TMRIN0

(Timer2)

(Timer0,1,2)

Offset : 56h

Reset Value : 0000h

Timer 0 Mode / Control Register

CONT

ALT

EXT

RTG

RIU

INT

INH

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15 0: TC15-TC0, Timer 0 Count Value. This register contains the current count of timer 0. The count is incremented by

one every four internal processor clocks or by prescaled the timer 2, or by one every four external clock which is

configured the external clock select bit to refer the TMRIN1 signal.

Bit 15-0 : TC15 TC0, Timer 0 Compare A Value.

Bit 15-0 : TC15 TC0, Timer 0 Compare B Value.

Bit 15: EN, Enable Bit.

Set 1: The timer 1 is enable.

Set 0: The timer 1 is inhibited from counting.

The INH bit must be set 1 during writing the EN bit, and the INH bit and EN bit must be in the same write.

Bit 14: INH , Inhibit Bit. This bit is allows selective updating the EN bit. The INH bit must be set 1 during writing the EN

bit, and both the INH bit and EN bit must be in the same write. This bit is not stored and is always read as 0.

Bit 13: INT, Interrupt Bit.

Set 1: A interrupt request is generated when the count register equals a maximum count. If the timer is configured in

dual max-count mode, an interrupt is generated each time the count reaches max-count A or max-count B

Set 0: Timer 1 will not issue interrupt request.

Bit 12: RIU, Register in Use Bit.

Set 1: The Maxcount Compare B register of timer 1 is being used

Offset : 52h

Reset Value :

Timer 0 Maxcount Compare A Register

TC15 - TC0

Offset : 54h

Reset Value :

Timer 0 Maxcount Compare B Register

TC15 - TC0

Offset : 5Eh

Reset Value : 0000h

Timer 1 Mode / Control Register

CONT

ALT

EXT

RTG

RIU

INT

INH

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Set 0: The Maxcount Compare A register of timer 1 is being used

Bit 11-6 : Reserved.

Bit 5: MC, Maximum Count Bit. When the timer reaches its maximum count, the MC bit will set to 1 by H/W. In dual

maxcount mode, this bit is set each time either Maxcount Compare A or Maxcount Compare B register is reached. This

bit is set regardless of the EN bit (66h.15).

Bit 4: RTG, Re-trigger Bit. This bit define the control function by the input signal of TMRIN1 pin. When EXT=1 (5Eh.2),

this bit is ignored.

Set 1: Timer1 Count Register (58h) counts internal events; Reset the counting on every TMRIN1 input signal from low

go high (rising edge trigger).

Set 0: Low input holds the timer 1 Count Register (58h) value; High input enables the counting which counts internal

events.

The definition of setting the (EXT , RTG )

( 0 , 0 ) Timer1 counts the internal events. if the TMRIN1 pin remains high.

( 0 , 1 ) -- Timer1 counts the internal events; count register reset on every rising transition on the TMRIN1 pin

( 1 , x ) -- TMRIN1 pin input acts as clock source and timer1 count register increase one every four external clock.

Bit 3: P, Prescaler Bit. This bit and EXT(5Eh.2) define the timer 1 clock source.

The definition of setting the (EXT , P )

( 0 , 0 ) Timer1 Count Register increase one every four internal processor clock.

( 0 , 1 ) Timer1 count register increase one which prescal by timer 2.

( 1 , x ) -- TMRIN1 pin input acts as clock source and Timer1 Count Register increase one every four external clock.

Bit 2: EXT, External Clock Bit.

Set 1: Timer 1 clock source from external

Set 0: Timer 1 clock source from internal

Bit 1 : ALT, Alternate Compare Bit. This bit controls whether the timer runs in single or dual maximum count mode.

Set 1: Specify dual maximum count mode. In this mode the timer counts to Maxcount Compare A, then resets the

count register to 0. Then the timer counts to Maxcount Compare B, then resets the count register to 0 again,

and starts over with Maxcount Compare A.

Set 0: Specify single maximum count mode. In this mode the timer will count to the valve contained in Maxcount

Compare A and reset to 0, and then the timer counts to Maxcount Compare A again. Maxcount Compare B is

not used in this mode.

Bit 0: CONT, Continuous Mode Bit.

Set 1: The timer to run continuously.

Set 0: The timer will halt after each counting to the maximum count and the EN bit will be cleared.

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 15 0: TC15-TC0, Timer 1 Count Value. This register contains the current count of timer 1. The count is incremented by

one every four internal processor clocks or by prescaled the timer 2, or by one every four external clock which is

configured the external clock select bit to refer the TMRIN1 signal.

3Bit 15-0 : TC15 TC0, Timer 1 Compare A Value.

Bit 15-0 : TC15 TC0, Timer 1 Compare B Value.

Bit 15: EN, Enable Bit.

Set 1: The timer 2 is enable.

Set 0: The timer 2 is inhibited from counting.

The INH bit must be set 1 during writing the EN bit, and the INH bit and EN bit must be in the same write.

Bit 14: INH , Inhibit Bit. This bit is allows selective updating the EN bit. The INH bit must be set 1 during writing the EN

bit, and both the INH bit and EN bit must be in the same write. This bit is not stored and is always read as 0.

Bit 13: INT, Interrupt Bit.

Offset : 58h

Reset Value :

Timer 1 Count Register

TC15 - TC0

Offset : 5Ah

Reset Value :

Timer 1 Maxcount Compare A Register

TC15 - TC0

Offset : 66h

Reset Value : 0000h

Timer 2 Mode / Control Register

CONT

INT

INH

Offset : 5Ch

Reset Value :

Timer 1 Maxcount Compare B Register

TC15 - TC0

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Set 1: A interrupt request is generated when the count register equals a maximum count.

Set 0: Timer 2 will not issue interrupt request.

Bit 12-6 : Reserved.

Bit 5: MC, Maximum Count Bit. When the timer reaches its maximum count, the MC bit will set to 1 by H/W. This bit is set

regardless of the EN bit (66h.15).

Bit 4-1: Reserved.

Bit 0: COUNT, Continuous Mode Bit.

Set 1: Timer is continuously running when timer reaches the maximum count.

Set 0: The EN bit (66h.15) is cleared and the timer is hold after each timer count reaches the maximum count.

Bit 15 0: TC15-TC0, Timer 2 Count Value. This register contains the current count of timer 2. The count is incremented by

one every four internal processor clocks.

Bit 15-0 : TC15 TC0, Timer 2 Compare A Value.

16.1 Timer/Counter Unit Output Mode

Timers 0 and 1 can use one maximum count value or two maximum count value. Timer 2 can use only one maximum count

value. Timer 0 and timer1 can be configured to single or dual Maximum Compare count mode, the TMROUT0 or TMROUT1

signals can be used to generated waveform of various duty cycle.

Offset : 60h

Reset Value :

Timer 2 Count Register

TC15 - TC0

Offset : 62h

Reset Value :

Timer 2 Maxcount Compare A Register

TC15 - TC0

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

17. Watchdog Timer

R8830LV has one independent watchdog timer, which is programmable. The watchdog timer is active after reset and the

timeout count with a maximum count value. The keyed sequence ( 3333h, CCCCh ) must be written to the register (E6h) first

then writing new configuration to the Watchdog Timer Control Register. It is a single write so every one writing to Watchdog

Timer Control Register must follow the rule.

To read the Watchdog Timer Control Register, the keyed sequence (5555h, AAAAh) must be written to the register (E6h) first.

The current count should be reset before modifying the Watchdog Timer timeout period to ensure that an immediate timeout

dose not occur.

Bit 15: ENA, Enable Watchdog Timer.

Set 1 : Enable Watchdog Timer.

Set 0 : Disable Watchdog Timer.

Bit 14: WRST, Watchdog Reset.

Set 1: WDT generates a system reset when WDT timeout count is reached.

Set 0 : WDT generates a NMI interrupt when WDT timeout count is reached if the NMIFLAG bit is 0. If the NMIFLAG

bit is 1, the WDT will generate a system reset when timeout.

Bit 13: RSTFLAG, Reset Flag. When watchdog timer reset event has occurred, hardware will set this bit to 1. This bit will be

cleared by any keyed sequence write to this register or external reset. This bit is 0 after an external reset or 1 after

watchdog timer reset.

Bit 12: NMIFLAG, NMI Flag. After WDT generates a NMI interrupt, this bit will be set to 1 by H/W. This bit will be cleared

by any keyed sequence write to this register.

Bit 11-8 : Reserved.

Bit 7-0 : COUNT, Timeout Count. The COUNT setting determines the duration of the watchdog timer timeout interval.

a. The duration equation : Duration =

Exponent

/ Frequency

b. The Exponent of the COUNT setting:

(Bit 7, Bit 6, Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, Bit 0) = ( Exponent)

( 0 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = (N/A)

( x , x , x , x, x , x , x , x ) = ( 10 )

(x , x , x , x, x , x , 1 , 0 ) = ( 20 )

(x , x , x , x, x , 1 , 0 , 0 ) = ( 21 )

Watchdog Timer Control Register

Offset : E6h

Reset Value : C080h

NMIFLAG

RSTFLAG

WRST

ENA

COUNT

Res

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RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

(x , x , x , x, 1 , 0 , 0 , 0 ) = ( 22 )

(x , x , x , 1, 0 , 0 , 0 , 0 ) = ( 23 )

(x , x , 1 , 0, 0 , 0 , 0 , 0 ) = ( 24 )

( x , 1 , 0 , 0, 0 , 0 , 0 , 0 ) = ( 25 )

( 1 , 0 , 0 , 0, 0 , 0 , 0 , 0 ) = ( 26 )

c. Watchdog timer Duration reference table:

Frequency\Exponent 10 20 21 22

25 26

20 MHz

51 us 52 ms 104 ms 209 ms 419 ms 838 ms 1.67 s 3.35 s

25 MHz

40 us 41 ms 83 ms 167 ms 335 ms 671 ms 1.34 s 2.68 s

33 MHz

30 us 31 ms 62 ms 125 ms 251 ms 503 ms 1.00 s 2.01 s

40 MHz

25 us 26 ms 52 ms 104 ms 209 ms 419 ms 838 ms 1.67 s

50 MHz

20.5 us 21 ms 41.9 ms 83.9ms 167.8 ms 335.5 ms 671 ms 1.34 s

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

18. Asynchronous Serial Port

R8830LV has two asynchronous serial ports, which provide the TXD, RXD pins for the full duplex bi-directional data transfer

and with handshaking signals CTS , ENRX , RTS , RTR . The serial ports support : 9-bit, 8-bit or 7-bit data transfer; odd

parity, even parity, or no parity; 1 stop bits; Error detection; DMA transfers through the serial port; Multi-drop protocol (9-bit)

support; Double buffers for transmit and receive.

The receive/transmit clock is based on the microprocessor clock. The serial port can be used in power-saved mode, but the

transfer rate must be adjusted to correctly reflect the new internal operating frequency. Software is programmed through the

registers ,(80h, 82h, 84h, 86h, 88h for port 0), ( 10h,12h,14h,16h,18h for port 1) to configure the asynchronous serial port.

18.1 Serial Port Flow Control

The two serial ports provided with two data pins (RXD and TXD) and two flow control signals ( RTS , RTR ). Hardware flow

control is enabled when the FC bit in the Serial Port control Register is set. And the flow control signals are configured by

software to support several different protocols.

18.1.1 DCE/DTE Protocol

The R8830LV can be as a DCE (Data Communication Equipment) or as a DTE ( Data Terminal Equipment). This protocol

provides flow control where one serial port is receiving data and other serial port is sending data. To implement the DCE

device, the ENRX bit should be set and the RTS bit should be cleared for the associated serial port. To implement the DTE

device, the ENRX bit should be cleared and the RTS bit should be set for the associated serial port. The ENRX bit and RTS

bit are in the register F2h.

The DCE/DTE protocol is asymmetric interface since the DTE device can not signal the DCE device that is ready to receive

Transmit

Data Register(84h),(14h)

Transmit

Hold Register

Transmit

Shift Regoster

Receive

Data Register(86h),(16h)

Receive

Buffer

Receive Shift

Register

TXD

Control

Logic

Control Register(80h),(10h)

Status Register(82h),(12h)

Baud Rate

Divisor Register(88h),(18h)

Interrupt Request

RXD

Internal Address/Data Bus

Serial Port Block Diagram

16 bit

8 bit

16 bit

8 bit

RTS

RTR

CTS

ENRX

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

data, and the DCE can not send the request to send signal.

The DCE/DTE protocol communication step:

a. DTE send data to DCE

b. RTS signal is asserted by DTE when data is available.

c. The RTS signal is interpreted by the DCE device as a request to enable its receiver.

d. The DCE asserts the RTR signal to response that DCE is ready to receive data.

18.1.2 CTS/RTR Protocol

The serial port can be programmed as a CTS/RTS protocol by clearing both ENRX bit and RTS bit. This protocol is a

symmetric interface, which provides flow control when both ports are sending and receiving data.

18.2 DMA Transfer to/from a serial port function

DMA transfers to the serial port function as destination-synchronized DMA transfers. A new transfer is requested when the

Transmit Holding Register is empty. When the port is configured for DMA transmits, the corresponding transmit interrupt is

disabled regardless of the TXIE bit setting.

DMA transfers from the serial port function as source-synchronized DMA transfers. A new transfer is requested when the

Receive Buffer contains valid data. When the port is configured for DMA receives, the corresponding receive interrupt is

disabled regardless of the RXIE bit setting.

The DMA request is generated internally when a DMA channel is being used for serial port transfers. And the DRQ0 or

DRQ1 are not active when a serial port DMA transfers.

Hardware handshaking may be used in conjunction with serial port DMA transfers.

DCE

DTE

ENRX

RTS

RTR

CTS

DCE/DTE Protocol Connection

RTS:Request to send

CTS:Clear to send

RTR:Ready to receive

ENRX:Enable receiver request

RTR

CTS

CTS/RTR Protocol Connection

CTS:Clear to send

RTR:Ready to receive

CTS

RTR

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

18.3 The Asynchronous Modes description

There are 4 modes operation in the asynchronous serial port.

Mode1: Mode 1 is the 8-bit asynchronous communications mode. Each frame consists of a start bit, eight data bits and a stop

bit. when parity is used, the eighth data bit becomes the parity bit.

Mode 2: Mode 2 is used together with Mode 3 for multiprocessor communications over a common serial link. In mode 2, the

RX machine will not complete a reception unless the ninth data bit is a one. Any character received with the ninth bit equal to

zero is ignored. No flags are set, no interrupts occur and no data is transferred to Receive Data Register. In mode 3, characters

are received regardless of the state of the ninth data bit.

Mode 3: Mode 3 is the 9-bit asynchronous communications mode. Mode 3 is the same as mode 1 except that a frame

contains nine data bits. The ninth data bit becomes the parity bit when the parity feature is enabled.

Mode 4: Mode 4 is the 7-bit asynchronous communications mode. Each frame consists of a start bit, seven data bits and a

stop bit. Parity bit is not available in mode 4.

Bit 15-13: DMA, DMA Control Field. These bits configure the serial port for use with DMA transfers.

DMA control bits

(Bit 15, bit 14, bit 13)b --- Receive --- Transmit

( 0, 0, 0 ) --- No DMA --- No DMA

( 0, 0, 1 ) --- DMA 0 --- DMA 1

( 0, 1, 0 ) --- DMA 1 --- DMA 0

( 0, 1, 1 ) --- N/A --- N/A

( 1, 0, 0 ) --- DMA 0 --- No DMA

( 1, 0, 1 ) --- DMA 1 --- No DMA

( 1, 1, 0 ) --- No DMA --- DMA 0

( 1, 1, 1 ) --- No DMA --- DMA 1

Bit 12: RSIE, Receive Status Interrupt Enable. An exception occurs during data reception or error detection occur will

generate an interrupt.

Set 1: Enable the serial port 0 to generate an interrupt request.

Bit 11: BRK, Send Break.

Set this bit to 1 , the TXD pin always drives low.

Serial Port 0 Contrl Register

Offset : 80h

Reset Value : 0000h

DMA

RISE BRK

TB8

TXIE RXIE

TMODE

RMODD

EVN

MODE

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Long Break : The TXD is driven low for grater than (2M+3) bit times;

Short break : The TXD is driven low for grater than M bit times;

* M= start bit + data bits number + parity bit + stop bit

Bit 10 : TB8, Transmit Bit 8. This bit is transmitted as ninth data bit in mode 2 and mode 3. This bit is cleared after every

transmission.

Bit 9: FC, Flow Control Enable.

Set 1: Enable the hardware flow control for serial port 0.

Set 0 : Disable the hardware flow control for serial port 0.

Bit 8 : TXIE, Transmitter Ready Interrupt Enable. When the Transmit Holding Register is empty ( THRE bit in Status

Set 1: Enable the Interrupt.

Set 0 : Disable the interrupt.

Bit 7: RXIE, Receive Data Ready Interrupt Enable. When the receiver buffer contains valid data ( RDR bit in Status

Set 1: Enable the Interrupt.

Set 0 : Disable the interrupt.

Bit 6 : TMODE, Transmit Mode.

Set 1: Enable the TX machines.

Set 0: Disable the TX machines.

Bit 5: RMODE, Received Mode.

Set 1: Enable the RX machines.

Set 0: Disable the RX machines.

Bit 4: EVN, Even Parity. This bit is valid only when the PE bit is set.

Set 1: the even parity checking is enforced (even number of 1s in frame).

Set 0: odd parity checking is enforced (odd number of 1s in frame).

Bit 3: PE, Parity Enable.

Set 1 : Enable the parity checking.

Set 0 : Disable the parity checking.

Bit 2-0: MODE, Mode of Operation.

( bit 2, bit 1, bit 0) MODE

Data Bits

Parity Bits

Stop Bits

( 0 , 0 , 1)

Mode 1

7 or 8

1 or 0

( 0 , 1 , 0)

Mode 2

N/A

( 0 , 1 , 1)

Mode 3

8 or 9

1 or 0

( 1 , 0 , 0)

Mode 4

N/A

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

The Serial Port 0 Status Register provides information about the current status of the serial port 0.

Bit 15-11: Reserved.

Bit 10: BRK1, Long Break Detected. This bit should be reset by software.

When a long break is detected, this bit will be set high.

Bit 9 : BRK0, Short Break Detected. This bit should be reset by software.

When a short break is detected, this bit will be set high

Bit 8: RB8,Received Bit 8. This bit should be reset by software.

This bit contains the ninth data bit received in mode 2 and mode 3.

Bit 7: RDR, Received Data Ready. Read only.

The Received Data Register contains valid data, this bit is set high. This bit can only be reset by reading the Serial

Port 0 Receive Register.

Bit 6: THRE, Transmit Hold Register Empty. Read only.

When the Transmit Hold Register is ready to accept data, this bit will be set. This bit will be reset when writing data

to the Transmit Hold Register.

Bit 5: FER, Framing Error detected. This bit should be reset by software.

This bit is set when a framing error is detected.

Bit 4: OER, Overrun Error Detected. This bit should be reset by software.

This bit is set when an overrun error is detected.

Bit 3: PER, Parity Error Detected. This bit should be reset by software.

This bit is set when a parity error ( for mode 1 and mode 3) is detected.

Bit 2: TEMT, Transmitter Empty. This bit is read only.

When the Transmit Shift Register is empty, this bit will be set.

Bit 1: HS0, Handshake Signal 0. This bit is read only.

This bit reflects the inverted value of the external

CTS pin.

Bit 0 : Reserved.

Bit 15-8: Reserved

Serial Port 0 Status Register

Offset : 82h

Reset Value :

BRK1

TEMT HS0

Res

Reserved

BRK0 RB8

RDR THRE FER

OER

PER

Serial Port 0 Transmit Register

Offset : 84h

Reset Value :

Reserved

TDATA

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Bit 7-0 : TDATA, Transmit Data. Software writes this register with data to be transmitted on the serial port 0.

Bit 15-8: Reserved

Bit 7-0: RDATA, Received DATA. The RDR bit should be read as 1 before read the RDATA register to avoid reading

invalid data.

Bit 15-0: BAUDDIV, Baud Rate Divisor.

The general formula for baud rate divisor is Baud Rate = Microprocessor Clock / (16 x BAUDDIV)

For example, The Microprocessor clock is 22.1184MHz and the BAUDDIV=12 (Decimal), the baud rate of serial

port is 115.2k.

These bits definition are same as the bits definition of Register 80h

These bits definition are same as the bits definition of Register 82h

Serial Port 0 Receive Register

Offset : 86h

Reset Value :

RDATA

Reserved

Serial Port 0 Baud Rate Divisor Register

Offset : 88h

Reset Value : 0000h

BAUDDIV

Serial Port 1 Contrl Register

Offset : 10h

Reset Value : 0000h

DMA

RISE BRK

TB8

TXIE RXIE

TMODE

RMODD

EVN

MODE

Serial Port 1 Status Register

Offset : 12h

Reset Value :

BRK1

TEMT HS0

Res

Reserved

BRK0 RB8

RDR THRE FER

OER

PER

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

These bits definition are same as the bits definition of Register 84h

These bits definition are same as the bits definition of Register 86h

These bits definition are same as the bits definition of Register 88h

Serial Port 1 Transmit Register

Offset : 14h

Reset Value :

Reserved

TDATA

Serial Port 1 Receive Register

Offset : 16h

Reset Value :

RDATA

Reserved

Serial Port 1 Baud Rate Divisor Register

Offset : 18h

Reset Value : 0000h

BAVDDIV

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

19. PIO Unit

R8830LV provides 32 programmable I/O signals, which are multi-function pins with others normal function signals. Software

is programmed through the registers ( 7Ah, 78h, 76h, 74h, 72h, 70h) to configure the multi-function pins for PIO or normal

function.

19.1 PIO multi-function Pin list table

PIO No.

Pin No.

Multi Function

Reset status/PIO internal resister

TMRIN1

Input with 10k pull-up

TMROUT1

Input with 10k pull-down

2 59 PCS6 /A2

Input with 10k pull-up

3 60 PCS5 /A1

Input with 10k pull-up

4 48

DT/ R

Normal operation/ Input with 10k pull-up

5 49

DEN

Normal operation/ Input with 10k pull-up

SRDY

Normal operation/ Input with 10k pull-down

A17

Normal operation/ Input with 10k pull-up

A18

Normal operation/ Input with 10k pull-up

A19

Normal operation/ Input with 10k pull-up

TMROUT0

Input with 10k pull-down

TMRIN0

Input with 10k pull-up

DRQ0/INT5

Input with 10k pull-up

DRQ1/INT6

Input with 10k pull-up

14 50

MCS

Input with 10k pull-up

15 51

MCS

Input with 10k pull-up

16 66

PCS

Input with 10k pull-up

17 65

PCS

Input with 10k pull-up

Write

PDATA

VCC

For internal

pull-up

For internal

pull-down

Pin

"0":un-normal function

Normal Data In

Read

PDATA

Microprocessor

Clock

PIO

Direction

PIO

Mode

Normal Function

PIO Data In/Out

PIO pin Operation Diagram

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

18 63 2

PCS /

CTS /

ENRX Input with 10k pull-up

19 62 3

PCS /

RTS /

RTR

Input with 10k pull-up

20 3

RTS /

RTR

Input with 10k pull-up

21 100

CTS /

ENRX

Input with 10k pull-up

TXD0

Input with 10k pull-down

RXD0

Input with 10k pull-down

24 68

MCS

Input with 10k pull-up

25 69

MCS / RFSH

Input with 10k pull-up

26 97

UZI

Input with 10k pull-up

TXD1

Input with 10k pull-up

RXD1

Input with 10k pull-up

29 96 S6/ CLKDIV

Input with 10k pull-up

INT4

Input with 10k pull-up

INT2

Input with 10k pull-up

Bit 15- 0 : PDATA31-PDATA16, PIO Data Bits.

These bits PDATA31- PDATA16 map to the PIO31 PIO16 which indicate the driven level when the PIO pin as an

output or reflects the external level when the PIO pin as an input .

Bit 15-0 : PDIR 31- PDIR16, PIO Direction Register.

Set 1: Configure the PIO pin as an input.

Set 0: Configure the PIO pin as an output or as normal pin function.

Bit 15-0: PMODE31-PMODE16, PIO Mode Bit.

Offset : 7Ah

Reset Value :

PDATA (31 - 16)

PIO Data 1 Register

Offset : 78h

Reset Value : FFFFh

PDIR (31 - 16)

PIO Direction 1 Register

Offset : 76h

Reset Value : 0000h

PMODE (31 - 16)

PIO Mode 1 Register

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

The definition of PIO pins are configured by the combination of PIO Mode and PIO Direction. And the PIO pin is

programmed individual.

The definition (PIO Mode, PIO Direction) for PIO pin function:

( 0 , 0 ) Normal operation , ( 0 , 1 ) PIO input with pull-up/pull-down

( 1 , 0 ) PIO output , ( 1 , 1 ) -- PIO input without pull-up/pull-down

Bit 15-0 : PDATA15- PDATA0 : PIO Data Bus.

These bits PDATA15- PDATA0 map to the PIO15 PIO0 which indicate the driven level when the PIO pin as an

output or reflects the external level when the PIO pin as an input.

Bit 15-0 : PDIR 15- PDIR0, PIO Direction Register.

Set 1: Configure the PIO pin as an input.

Set 0: Configure the PIO pin as an output or as normal pin function.

Bit 15-0: PMODE15-PMODE0, PIO Mode Bit.

Offset : 74h

Reset Value :

PDATA (15 - 0)

PIO Data 0 Register

Offset : 72h

Reset Value : FFFFh

PDIR (15 - 0)

PIO Direction 0 Register

Offset : 70h

Reset Value : 0000h

PMODE (15 - 0)

PIO Mode 0 Register

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

20. PSRAM Control Unit

The PSRAM interface is provided by the R8830LV and the refresh control unit automatically generates refresh bus cycles. The

refresh control unit uses the internal microprocessor clock as a operating source clock. if the power-saved mode is enabled, the

refresh control unit must be programmed to reflect the new clock rate. Software programs the registers (E0, E2, E4) to control

the refresh control unit operation.

Bit 15-9: M6-M0, Refresh Base. M6-M0 map to A19-A13 of the 20-bit memory refresh address.

Bit 8-0 : Reserved.

Bit 15-9 : Reserved

Bit 8-0: RC8-RC0, Refresh Counter Reload Value.

Bit 15: E, Enable RCU.

Set 1: Enable the refresh counter unit

Set 0 : Disable the refresh counter unit.

Bit 14-9 : Reserved

Bit 8-0: T8-T0, Refresh Count. Read only bits and these bits present value of the down counter which triggers refresh

requests.

Memory Partition Register

Offset : E0h

Reset Value : 0000h

M6 - M0

Clock Prescaler Register

Offset : E2h

Reset Value :

RC8 - RC0

Enable RCU Register

Offset : E4h

Reset Value : 0000h

T8 - T0

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

21. INSTUCTION SET OPCODES AND CLOCK CYCLES

Function Format

Clocks

Notes

DATA TRANSFER INSTRUCTIONS

MOV = Move

1000100w

mod reg r/m

1/1

1000101w

mod reg r/m

1/6

immediate to register/memory

1100011w

mod 000 r/m

data

data if w=1

1/1

immediate to register

1011w reg data

data if w=1

memory to accumulator

1010000w

addr-low

addr-high

accumulator to memory

1010001w

addr-low

addr-high

10001110

mod 0 reg r/m

3/8

segment register to register/memory

10001100

mod 0 reg r/m

2/2

PUSH

Push

memory

11111111

mod 110 r/m

01010 reg

segment register

000reg110

immediate

011010s0

data

data if s=0

POP = Pop

memory

10001111

mod 000 r/m

01011 reg

segment register

000 reg 111 (reg01)

PUSHA = Push all

01100000

POPA = Pop all

01100001

XCHG = Exchange

1000011w mod reg r/m

3/8

10010 reg

XTAL = Translate byte to AL

11010111

IN = Input from

fixed port

1110010w port

variable port

1110110w

OUT = Output from

fixed port

1110010w port

variable port

1110110w

LEA = Load EA to register

10001101

mod reg r/m

LDS = Load pointer to DS

11000101

mod reg r/m

(mod

11)

LES = Load pointer to ES

11000100

mod reg r/m

(mod

11)

ENTER = Build stack frame

11001000 data-low

data-high L

L = 0

L = 1

L > 1

11+10(L-1)

LEAVE = Tear down stack frame

11001001

LAHF = Load AH with flags

10011111

SAHF = Store AH into flags

10011110

PUSHF = Push flags

10011100

POPF = Pop flags

10011101

ARITHMETIC INSTRUCTIONS

ADD = Add

reg/memory with register to either

000000dw

mod reg r/m

1/7

immediate to register/memory

100000sw

mod 000 r/m

data

data if sw=01

1/8

immediate to accumulator

0000010w

data

data if w=1

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Function Format

Clocks

Notes

ADC = Add with carry

reg/memory with register to either

000100dw

mod reg r/m

1/7

immediate to register/memory

100000sw

mod 010 r/m

data

data if sw=01

1/8

immediate to accumulator

0001010w

data

data if w=1

INC = Increment

1111111w

mod 000 r/m

1/8

01000 reg

SUB = Subtract

reg/memory with register to either

001010dw

mod reg r/m

1/7

immediate from register/memory

100000sw

mod 101 r/m

data

data if sw=01

1/8

immediate from accumulator

0001110w

data

data if w=1

SBB = Subtract with borrow

reg/memory with register to either

000110dw

mod reg r/m

1/7

immediate from register/memory

100000sw

mod 011 r/m

1/8

immediate from accumulator

0001110w

data

data if w=1

DEC = Decrement

1111111w

mod 001 r/m

1/8

01001 reg

NEG = Change sign

1111011w

mod reg r/m

1/8

CMP = Compare

0011101w

mod reg r/m

1/7

0011100w

mod reg r/m

1/7

immediate with register/memory

100000sw

mod 111 r/m

data

data if sw=01

1/7

immediate with accumulator

0011110w

data

data if w=1

MUL = multiply (unsigned)

1111011w

mod 100 r/m

memory-byte

memory-word

IMUL = Integer multiply (signed)

1111011w

mod 101 r/m

memory-byte

memory-word

mod reg r/m

data

data if s=0

23/28

DIV = Divide (unsigned)

1111011W

mod 110 r/m

memory-byte

memory-word

IDIV = Integer divide (signed)

1111011w

mod 111 r/m

memory-byte

memory-word

AAS = ASCII adjust for subtraction

00111111

DAS = Decimal adjust for subtraction

00101111

AAA = ASCII adjust for addition

00110111

DAA = Decimal adjust for addition

00100111

AAD = ASCII adjust for divide

11010101

00001010

AAM = ASCII adjust for multiply

11010100

00001010

CBW = Corrvert byte to word

10011000

CWD = Convert word to double-word

10011001

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

Function Format

Clocks

Notes

BIT MANIPULATION INSTRUCTUIONS

NOT = Invert register/memory

1111011w

mod 010 r/m

1/7

AND = And

reg/memory and register to either

001000dw

mod reg r/m

1/7

immediate to register/memory

1000000w

mod 100 r/m

data

data if w=1

1/8

immediate to accumulator

0010010w

data

data if w=1

OR = Or

reg/memory and register to either

000010dw

mod reg r/m

1/7

immediate to register/memory

1000000w

mod 001 r/m

data

data if w=1

1/8

immediate to accumulator

0000110w

data

data if w=1

XOR = Exclusive or

reg/memory and register to either

001100dw

mod reg r/m

1/7

immediate to register/memory

1000000w

mod 110 r/m

data

data if w=1

1/8

immediate to accumulator

0011010w

data

data if w=1

TEST = And function to flags , no result

1000010w

mod reg r/m

1/7

immediate data and register/memory

1111011w

mod 000 r/m

data

data if w=1

1/8

immediate data and accumulator

1010100w

data

data if w=1

Sifts/Rotates

1101000w

mod TTT r/m

2/8

1101001w

mod TTT r/m

1+n / 7+n

1100000w

mod TTT r/m

count

1+n / 7+n

STRING MANIPULATION INSTRUCTIONS

MOVS = Move byte/word

1010010w

INS = Input byte/word from DX port

0110110w

OUTS = Output byte/word to DX port

0110111w

CMPS = Compare byte/word

1010011w

SCAS = Scan byte/word

101011w

LODS = Load byte/word to AL/AX

1010110w

STOS = Store byte/word from AL/AX

1010101w

Repeated by count in CX:

MOVS = Move byte/word

11110010

1010010w

4+9n

INS = Input byte/word from DX port

11110010

0110110w

5+9n

OUTS = Output byte/word to DX port

11110010

0110111w

5+9n

CMPS = Compare byte/word

1111011z

1010011w

4+18n

SCAS = Scan byte/word

1111001z

1010111w

4+13n

LODS = Load byte/word to AL/AX

11110010

0101001w

3+9n

STOS = Store byte/word from AL/AX

11110100

0101001w

4+3n

PROGRAM TRANSFER INSTRUCTIONS

Conditional Transfers --

-- jump if:

JE/JZ = equal/zero 01110100

disp

1/9

JL/JNGE = less/not greater or equal

01111100 disp

1/9

JLE/JNG = less or equal/not greater

01111110

disp

1/9

JC/JB/JNAE = carry/below/not above or equal

01110010 disp

1/9

JBE/JNA = below or equal/not above

01110110 disp

1/9

JP/JPE = parity/parity even

01111010 disp

1/9

JO = overflow

01110000 disp

1/9

JS = sign

01111000 disp

1/9

JNE/JNZ = not equal/not zero

01110101 disp

1/9

JNL/JGE = not less/greater or equal

01111101 disp

1/9

JNLE/JG = not less or equal/greater

01111111 disp

1/9

JNC/JNB/JAE = not carry/not below

01110011 disp

1/9

/above or equal

JNBE/JA = not below or equal/above

01110111 disp

1/9

JNP/JPO = not parity/parity odd

01111011 disp

1/9

JNO = not overflow

01110001 disp

1/9

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

JNS = not sign

01111001 disp

1/9

Function Format

Clocks

Notes

Unconditional Transfers

CALL = Call procedure

direct within segment

11101000

disp-low

disp-high

reg/memory indirect within segment

11111111

mod 010 r/m

12/17

indirect intersegment

11111111

mod 011 r/m

(mod11)

direct intersegment

10011010

segment offset

selector

RET = Retum from procedure

within segment

11000011

within segment adding immed to SP

11000010

data-low

data-high

intersegment

11001011

instersegment adding immed to SP

1001010

data-low

data-high

JMP = Unconditional jump

short/long

11101011

disp-low

9/9

direct within segment

11101001

disp-low

disp-high

reg/memory indirect within segment

11111111

mod 100 r/m

11/16

indirect intersegment

11111111

mod 101 r/m

(mod ?11)

direct intersegment

11101010

segment offset

selector

Iteration Control

LOOP = Loop CX times

11100010

disp

7/16

LOOPZ/LOOPE = Loop while zero/equal

11100001

disp

7/16

LOOPNZ/LOOPNE = Loop while not zero/equal 11100000

disp

7/16

JCXZ = Jump if CX = zero

11100011

disp

7/15

Interrupt

INT = Interrupt

Type specified

11001101

type

Type 3

11001100

INTO = Interrupt on overflow

11001110

43/4

BOUND = Detect value out of range

01100010

mod reg r/m

21-60

IRET = Interrupt return

11001111

PROCESSOR CONTROL INSTRUCTIONS

CLC = clear carry

11111000

CMC = Complement carry

11110101

STC = Set carry

11111001

CLD = Clear direction

11111100

STD = Set direction

11111101

CLI = Clear interrupt

11111010

STI = Set interrupt

11111011

HLT = Halt

11110100

WAIT = Wait

10011011

LOCK = Bus lock prefix

11110000

ESC = Math coprocessor escape

11011MMM mod PPP r/m

NOP = No operation

10010000

SEGMENT OVERRIDE PREFIX

CS 00101110

00110110

00111110

00100110

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

21.1

R8830LV Execution Timings

The above instruction timing represent the minimum execution time in clock cycles for each instruction. The timings given
are based on the following assumptions:
1. The opcode, along with and data or displacement required for execution, has been prefetched and resides in the instruction
queue at the time is needed.
2. No wait states or bus HOLDs occur.
3. All word -data is located on even-address boundaries.
4. One RISC micro operation(uOP) maps one cycle(according the pipeline stages described below) , except the following
case:

4.1 Memory read uOP need 6 cycles for bus.

4.2 Memory push uOP need 1 cycle if it has no previous Memory push uOP, and 5 cycles if it has previous Memory push or
Memory Write uOP.

4.3 MUL uOP and DIV of ALU function uOP for 8 bits operation need both 8 cycles, for 16 bits operation need both 16
cycles.
4.4 All jumps, calls, ret and loopXX instructions required to fetch the next instruction for the destination
address(Unconditional Fetch uOP) will need 9 cycles.

Note: op_r: operand read stage, EA: Calculate Effective Address stage, Idle: Bus Idle stage, T0..T3: Bus T0..T3 stage,

Access: Access data from cache memory stage.

Pipeline Stages for single micro operation(one cycle):

Fetch Decode op_r ALU WB

(For ALU function uOP)

Fetch Decode EA Access WB

(For Memory function uOP)

Pipeline stages for Memory read uOP(6 cycles):

Fetch Decode EA Access Idle T0 T1 T2 T3 WB

Bus Cycle

Pipeline stages for Memory push uOP after Memory push uOP (another 5 cycles):

Fetch Decode EA

Access

Idle T0 T1 T2

WB (1

Memory push uOP)

uOP) Fetch Decode EA

Access

Idle T0 T1 T2 T3 WB

pipeline stall

Pipeline stages for unconditional fetch:

Fetch Decode EA

Access

Idle T0

T1 T2

Fetch

(Fetch uOP)

(next uOP) Fetch

Decode

Access

Idle T0 T1 T2 T3 WB

will be flushed

These

cycles

caused

branch

penalty

Fetch

Decode

following stages..

(New uOP)

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

22. DC Characteristics

Absolute Maximum Rating

Symbol Rating

Commercial

Unit Note

Vterm

Terminal Voltage
with Respect
To GND

-0.5 to Vcc+0.5
V

Operating
Temperature

0 to +70

Centigrade

Pt Power

Dissipation

1.5

Recommended DC Operating Conditions

Symbol Parameter

Min. Typ. Max. Unit

Vcc Supply

Voltage

3.0

3.3 3.6 V

GND Ground

Vih Input

High

Voltage(1)

2.0

---

Vcc+0.5

Vih1 Input

High

Voltage(RES)

2.5

Vcc+0.5

Vih2

Input High Voltage (X1)

2.5

Vcc+0.5

Vil

Input Low voltage

-0.5

0.8

Note 1:

RST

,X1 pins not included

DC Electrical Characteristics

Symbol Parameter

Test

Condition

Min

Max Unit

Ili Input

Leakage

Current

(for 32 Pio Pins)

Vcc=Vmax
Vin=GND to
Vcc

300

Ili Input

Leakage

Current (Others)

Vcc=Vmax
Vin=GND to
Vcc

Ilo Output

Leakage

Current

Vcc=Vmax
Vin=GND to
Vcc

300

VOL

Output Low Voltage

Iol=2mA,
Vcc=Min.

_____ 0.4 V

VOH

Output High Voltagr

Ioh=-2.4mA,
Vcc=Min.

2.4 ____

Note1:Vmax=3.6V Vmin=3.0V

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

No. Description

MIN

MAX Unit

CLKOUTA high to A Address Valid

A address valid to RD low

1.5T-12

S6 active delay

S6 inactive delay

AD address Valid Delay

6 Address

Hold

0 12 ns

Data in setup

Data in Hold

ALE active delay

ALE inactive delay

Address Valid after ALE inactive

1/2T-10

12 ALE

width

T-10

active delay

0 15 ns

RD Pulse Width

2T-15

RD inactive delay

0 20 ns

CLKOUTA HIGH to LCS UCS valid

0 20 ns

UCS,LCS inactive delay

PCS , MCS active delay

0 20 ns

PCS , MCS inactive delay

0 20 ns

DEN active delay

0 20 ns

DEN inactive delay

0 20 ns

DTR active delay

DTR inactive delay

Status active delay

Status inactive delay

UZI active delay

0 20 ns

UZI inactive delay

0 20 ns

1. T means a clock period time

2. All timing parameters are measured at 1.5V with 50 PF loading on CLKOUTA

. All output test conditions are with CL=50 pF

RDC

RISC DSP Controller

R8830LV

RDC Semiconductor Co.

Rev:1.4

Subject to change without notice

No. Description

MIN

MAX

Unit

CLKOUTA high to A Address Valid

A address valid to WR low

1.5T-12

S6 active delay

S6 inactive delay

AD address Valid Delay

6 Address

Hold

ALE active delay

8 ALE

width

T-10

ALE inactive delay

Address valid after ALE inactive

1/2T-10

WR active delay

0 15 ns

WR pulse width

2T-15

WR inactive delay

0 15 ns

WHB , WLB active delay

0 20 ns

WHB , WLB inactive delay

0 20 ns

BHE active delay

BHE inactive delay

CLKOUTA high to UCS , LCS valid

0 20 ns

UCS , LCS inactive delay

0 20 ns

PCS , MCS active delay

0 20 ns

PCS , MCS inactive delay

0 20 ns

DEN active delay

0 20 ns

DEN inactive delay

0 20 ns

DTR active delay

0 20 ns

DTR inactive delay

0 20 ns

Status active delay

Status inactive delay

UZI active delay

0 20 ns

UZI inactive delay

0 20 ns

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: R8830LV

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: R8830LV