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Электронный компонент: RTL8201CP

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SINGLE-CHIP/SINGLE-PORT
10/100M FAST ETHERNET PHYCEIVER
(With Auto Crossover)

DATASHEET




Rev. 1.1
26 September 2003
Track ID: JATR-1076-21

RTL8201CP
RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver ii Track ID: JATR-1076-21 Rev. 1.1
COPYRIGHT
2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer's reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date
Summary
1.0 2003/06/09
First
release.
1.1
2003/09/26
Minor cosmetic changes.
Modify LED Pin behavior.
RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver iii Track ID: JATR-1076-21 Rev. 1.1
Table of Contents
1.
GENERAL DESCRIPTION ............................................................................................................................................... 1
2.
FEATURES .......................................................................................................................................................................... 1
3.
BLOCK DIAGRAM............................................................................................................................................................ 2
4.
PIN ASSIGNMENTS........................................................................................................................................................... 3
5.
PIN DESCRIPTION............................................................................................................................................................ 4
5.1.
MII I
NTERFACE
........................................................................................................................................................... 4
5.2.
SNI (S
ERIAL
N
ETWORK
I
NTERFACE
) 10M
BPS
O
NLY
................................................................................................... 5
5.3.
C
LOCK
I
NTERFACE
...................................................................................................................................................... 5
5.4.
10M
BPS
/100M
BPS
N
ETWORK
I
NTERFACE
................................................................................................................... 5
5.5.
D
EVICE
C
ONFIGURATION
I
NTERFACE
.......................................................................................................................... 6
5.6.
LED I
NTERFACE
/PHY A
DDRESS
C
ONFIGURATION
...................................................................................................... 6
5.7.
P
OWER AND
G
ROUND
P
INS
.......................................................................................................................................... 7
5.8.
R
ESET AND
O
THER
P
INS
.............................................................................................................................................. 7
6.
REGISTER DESCRIPTIONS............................................................................................................................................ 8
6.1.
R
EGISTER
0 B
ASIC
M
ODE
C
ONTROL
R
EGISTER
........................................................................................................... 8
6.2.
R
EGISTER
1 B
ASIC
M
ODE
S
TATUS
R
EGISTER
............................................................................................................... 9
6.3.
R
EGISTER
2 PHY I
DENTIFIER
R
EGISTER
1................................................................................................................... 9
6.4.
R
EGISTER
3 PHY I
DENTIFIER
R
EGISTER
2................................................................................................................... 9
6.5.
R
EGISTER
4 A
UTO
-N
EGOTIATION
A
DVERTISEMENT
R
EGISTER
(ANAR) ................................................................... 10
6.6.
R
EGISTER
5 A
UTO
-N
EGOTIATION
L
INK
P
ARTNER
A
BILITY
R
EGISTER
(ANLPAR)..................................................... 10
6.7.
R
EGISTER
6 A
UTO
-N
EGOTIATION
E
XPANSION
R
EGISTER
(ANER) ............................................................................ 11
6.8.
R
EGISTER
16 NW
AY
S
ETUP
R
EGISTER
(NSR)............................................................................................................ 12
6.9.
R
EGISTER
17 L
OOPBACK
, B
YPASS
, R
ECEIVER
E
RROR
M
ASK
R
EGISTER
(LBREMR)................................................ 12
6.10.
R
EGISTER
18 RX_ER C
OUNTER
(REC) .................................................................................................................... 13
6.11.
R
EGISTER
19 SNR D
ISPLAY
R
EGISTER
...................................................................................................................... 13
6.12.
R
EGISTER
25 T
EST
R
EGISTER
.................................................................................................................................... 13
7.
FUNCTIONAL DESCRIPTION ...................................................................................................................................... 14
7.1.
MII
AND
M
ANAGEMENT
I
NTERFACE
......................................................................................................................... 14
7.1.1.
Data Transition .................................................................................................................................................... 14
7.1.2.
Serial Management.............................................................................................................................................. 15
7.2.
A
UTO
-N
EGOTIATION AND
P
ARALLEL
D
ETECTION
...................................................................................................... 16
7.2.1.
Setting the Medium Type and Interface Mode to MAC ........................................................................................ 16
7.2.2.
UTP Mode and MII Interface............................................................................................................................... 16
7.2.3.
UTP Mode and SNI Interface............................................................................................................................... 17
7.2.4.
Fiber Mode and MII Interface ............................................................................................................................. 17
7.3.
F
LOW
C
ONTROL
S
UPPORT
......................................................................................................................................... 17
7.4.
H
ARDWARE
C
ONFIGURATION AND
A
UTO
-N
EGOTIATION
............................................................................................ 18
7.5.
LED
AND
PHY A
DDRESS
C
ONFIGURATION
............................................................................................................... 19
7.6.
S
ERIAL
N
ETWORK
I
NTERFACE
................................................................................................................................... 20
7.7.
P
OWER
D
OWN
, L
INK
D
OWN
, P
OWER
S
AVING
,
AND
I
SOLATION
M
ODES
..................................................................... 20
7.8.
M
EDIA
I
NTERFACE
..................................................................................................................................................... 20
7.8.1.
100Base-TX.......................................................................................................................................................... 20
7.8.2.
100Base-FX Fiber Mode Operation .................................................................................................................... 21
7.8.3.
10Base-T TX/RX................................................................................................................................................... 21
7.9.
R
EPEATER
M
ODE
O
PERATION
.................................................................................................................................... 22
7.10.
R
ESET
,
AND
T
RANSMIT
B
IAS
..................................................................................................................................... 22
7.11.
3.3V P
OWER
S
UPPLY AND
V
OLTAGE
C
ONVERSION
C
IRCUIT
...................................................................................... 22
7.12.
F
AR
E
ND
F
AULT
I
NDICATION
...................................................................................................................................... 22
RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver iv Track ID: JATR-1076-21 Rev. 1.1
8.
CHARACTERISTICS ...................................................................................................................................................... 23
8.1.
DC C
HARACTERISTICS
.............................................................................................................................................. 23
8.1.1.
Absolute Maximum Ratings ................................................................................................................................. 23
8.1.2.
Operating Conditions .......................................................................................................................................... 23
8.1.3.
Power Dissipation................................................................................................................................................ 23
8.1.4.
Input Voltage: Vcc................................................................................................................................................ 23
8.2.
AC C
HARACTERISTICS
.............................................................................................................................................. 24
8.2.1.
MII Transmission Cycle Timing ........................................................................................................................... 24
8.2.2.
MII Reception Cycle Timing ................................................................................................................................ 25
8.2.3.
SNI Transmission Cycle Timing ........................................................................................................................... 27
8.2.4.
SNI Reception Cycle Timing ................................................................................................................................ 28
8.2.5.
MDC/MDIO Timing ............................................................................................................................................. 29
8.3.
C
RYSTAL
C
HARACTERISTICS
..................................................................................................................................... 30
8.4.
T
RANSFORMER
C
HARACTERISTICS
............................................................................................................................ 30
9.
MECHANICAL DIMENSIONS....................................................................................................................................... 31
9.1.
M
ECHANICAL
D
IMENSIONS
N
OTES
............................................................................................................................ 32

List of Tables
Table 1. MII Interface ................................................................................................................................. 4
Table 2. SNI (Serial Network Interface) 10Mbps Only.............................................................................. 5
Table 3. Clock Interface.............................................................................................................................. 5
Table 4. 10Mbps/100Mbps Network Interface ........................................................................................... 5
Table 5. Device Configuration Interface..................................................................................................... 6
Table 6. LED Interface/PHY Address Configuration................................................................................. 6
Table 7. Power and Ground Pins ................................................................................................................ 7
Table 8. Reset and Other Pins..................................................................................................................... 7
Table 9. Register 0 Basic Mode Control Register ...................................................................................... 8
Table 10. Register 1 Basic Mode Status Register......................................................................................... 9
Table 11. Register 2 PHY Identifier Register 1 ............................................................................................ 9
Table 12. Register 3 PHY Identifier Register 2 ............................................................................................ 9
Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR) ................................................. 10
Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR).................................... 10
Table 15. Register 6 Auto-Negotiation Expansion Register (ANER) ........................................................ 11
Table 16. Register 16 NWay Setup Register (NSR)................................................................................... 12
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR).............................. 12
Table 18. Register 18 RX_ER Counter (REC) ........................................................................................... 13
Table 19. Register 19 SNR Display Register.............................................................................................. 13
Table 20. Register 25 Test Register ............................................................................................................ 13
Table 21. Serial Management ..................................................................................................................... 15
Table 22. Setting the Medium Type and Interface Mode to MAC ............................................................. 16
Table 23. UTP Mode and MII Interface ..................................................................................................... 16
Table 24. UTP Mode and SNI Interface ..................................................................................................... 17
Table 25. Fiber Mode and MII Interface..................................................................................................... 17
RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver v Track ID: JATR-1076-21 Rev. 1.1
Table 26. Auto-Negotiation Mode Pin Settings.......................................................................................... 18
Table 27. Power Saving Mode Pin Settings................................................................................................ 20
Table 28. Absolute Maximum Ratings ....................................................................................................... 23
Table 29. Operating Conditions .................................................................................................................. 23
Table 30. Power Dissipation ....................................................................................................................... 23
Table 31. Input Voltage: Vcc...................................................................................................................... 23
Table 32. MII Transmission Cycle Timing................................................................................................. 24
Table 33. MII Reception Cycle Timing...................................................................................................... 25
Table 34. SNI Transmission Cycle Timing ................................................................................................ 27
Table 35. SNI Reception Cycle Timing...................................................................................................... 28
Table 36. MDC/MDIO Timing................................................................................................................... 29
Table 37. Crystal Specifications ................................................................................................................. 30
Table 38. Transformer Specifications......................................................................................................... 30

List of Figures
Figure 1. Block Diagram............................................................................................................................. 2
Figure 2. Pin Assignments .......................................................................................................................... 3
Figure 3. Read Cycle................................................................................................................................. 15
Figure 4. Write Cycle................................................................................................................................ 15
Figure 5. LED and PHY Address Configuration ...................................................................................... 19
Figure 6. LED Definitions ........................................................................................................................ 19
Figure 7. MII Transmission Cycle Timing-1 ............................................................................................ 24
Figure 8. MII Transmission Cycle Timing-2 ............................................................................................ 25
Figure 9. MII Reception Cycle Timing-1 ................................................................................................. 26
Figure 10. MII Reception Cycle Timing-2 ................................................................................................. 26
Figure 11. SNI Transmission Cycle Timing-1............................................................................................ 27
Figure 12. SNI Transmission Cycle Timing-2............................................................................................ 27
Figure 13. SNI Reception Cycle Timing-1 ................................................................................................. 28
Figure 14. SNI Reception Cycle Timing-2 ................................................................................................. 28
Figure 15. MDC/MDIO Timing.................................................................................................................. 29
Figure 16. MDC/MDIO MAC to PHY Transmission Without Collision................................................... 29
Figure 17. MDC/MDIO PHY to MAC Reception Without Error .............................................................. 30