Document Outline

Description
Features
Card Line Up
Card Pin Assignment
Card Pin Explanation
Card Block Diagram
Card Function Explanation
- Register construction
- Host access specifications
- Configuration register specifications
- CIS informations
- Task File register specification
- ATA Command specifications
- Sector Transfer Protocol
Absolute Maximum Ratings
Recommended DC Operating Conditions
Capacitance
System Performance
DC Characteristics-1
DC Characteristics-2
DC Characteristics-3
DC Characteristics-4
AC Characteristics
- Attribute Memory Read AC Characteristics
- Attribute Memory Write AC Characteristics
- I/O Access Read AC Characteristics
- I/O Access Write AC Characteristics
- Common Memory Access Read AC Characteristics
- Common Memory Access Write AC Characteristics
- True IDE Mode Access Read AC Characteristics
- True IDE Mode Access Write AC Characteristics
- Reset Characteristics
- Power on Reset Characteristics
Attention for Card Use
Physical Outline
Caution for Handling Cards

Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
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Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

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contained therein.

HB28H016A8H

FLASH ATA Card

16 MByte

ADE-203-1363B (Z)

Rev. 1.0

Jan. 24, 2003

Description

HB28H016A8H is Flash ATA card. This card complies with PC card ATA standard and is suitable for the
usage of data storage memory medium for PC or any other electric equipment. This card is equipped with
0.18

m CMOS 128 Mega bit Flash memory. This card is suitable for ISA (Industry Standard Architecture)

bus interface standard , and read/write unit is 1 sector (512 bytes) sequential access. By using this card it is
possible to operate good performance for the system which have PC card slots.

Features

PC card ATA standard specification

68 pin two pieces connector and Type II (5 mm)

3.3 V/5 V single power supply operation

ISA standard and Read/Write unit is 512 bytes (sector) seque ntial access

Sector Read/Write transfer rate: 8MB/sec burst

Card density is 16 Mega bytes maximum

This card is equipped 0.18

m CMOS 128 Mega bit Flash memory

3 variations of mode access

Memory card mode

I/O card mode

True IDE mode

Internal self-diagnostic program operates at V

power on

High reliability based on internal ECC (Error Correcting Code) function

Auto Sleep Function

Data write is 300,000 cycles/block.*

Note: 1. One block consists of four sectors (512 byte

4).

HB28H016A8H

Rev. 1, Jan. 2003, page 3 of 65

Card Pin Assignment

Memory card mode

I/O card mode

True IDE mode

Pin No.

Signal name

I/O

Signal name

I/O

Signal name

I/O

1 GND

GND

I/O D3

I/O

I/O D4

I/O

I/O D5

I/O

I/O D6

I/O

I/O D7

I/O

-CE1 I -CE1 I -CE1 I

A10

I A10

9 -OE I

-OE I

-ATASEL

11 A9

I A9

12 A8

I A8

15 -WE

I -WE

RDY/-BSY

O -IREQ O INTRQ O

17 V

22 A7

I A7

23 A6

I A6

24 A5

I A5

25 A4

I A4

26 A3

I A3

27 A2

I A2

28 A1

I A1

29 A0

I A0

I/O D0

I/O

I/O D1

I/O

I/O D2

I/O

O -IOIS16 O -IOIS16 O

HB28H016A8H

Rev. 1, Jan. 2003, page 4 of 65

Memory card mode

I/O card mode

True IDE mode

Pin No.

Signal name

I/O

Signal name

I/O

Signal name

I/O

34 GND

GND

35 GND

GND

36 -CD1 O

-CD1 O

D11

I/O D11

I/O

D12

I/O D12

I/O

D13

I/O D13

I/O

D14

I/O D14

I/O

D15

I/O D15

I/O

42 -CE2 I -CE2 I -CE2 I

-VS1

O -VS1

44 -IORD I -IORD I -IORD I

45 -IOWR I -IOWR I -IOWR I

51 V

56 -CSEL I -CSEL I -CSEL I

-VS2

O -VS2

58 RESET I RESET I -RESET

-WAIT O -WAIT O IORDY O

-INPACK

O -INPACK

61 -REG I -REG I -REG I

BVD2

I/O -SPKR

I/O -DASP

I/O

BVD1

I/O -STSCHG I/O -PDIAG I/O

I/O D8

I/O

I/O D9

I/O

D10

I/O D10

I/O

67 -CD2 O

-CD2 O

68 GND

GND

HB28H016A8H

Rev. 1, Jan. 2003, page 5 of 65

Card Pin Explanation

Signal name

Direction Pin No.

Description

A10 to A0
(PC Card Memory mode)

8, 11, 12, 22, 23,
24, 25, 26, 27,
28, 29

Address bus is A10 to A0. A10 is MSB and A0 is
LSB.

A10 to A0
(PC Card I/O mode)

A2 to A0
(True IDE mode)

27, 28, 29

Address bus is A10 to A0. Only A2 to A0 are used,
A10 to A3 should be grounded by the host.

BVD1
(PC Card Memory mode)

I/O

BVD1 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.

-STSCHG
(PC Card I/O mode)

-STSCHG is used for changing the status of
Configuration and status register in attribute area.

-PDIAG
(True IDE mode)

-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.

BVD2
(PC Card Memory mode)

I/O

BVD2 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.

-SPKR
(PC Card I/O mode)

-SPKR outputs speaker signals. This output line is
constantly driven to a high state since this product
does not support the audio function.

-DASP
(True IDE mode)

-DASP is the Disk Active/Slave Present signal in the
Master/Slave handshake protocol.

-CD1, -CD2
(PC Card Memory mode)

36, 67

-CD1 and -CD2 are the card detection signals. -CD1
and -CD2 are connected to ground in this card, so
host can detect that the card is inserted or not.

-CD1, -CD2
(PC Card I/O mode)

-CD1, -CD2
(True IDE mode)

-CE1, -CE2
(PC Card Memory mode)
Card Enable

7, 42

-CE1 and -CE2 are low active card select signals.
Byte/Word/Odd byte mode are defined by
combination of -CE1, -CE2 and A0.

-CE1, -CE2
(PC Card I/O mode)
Card Enable

-CE1, -CE2
(True IDE mode)

-CE2 is used for select the Alternate Status Register
and the Device Control Register while -CE1 is the
chip select for the other task file registers.

HB28H016A8H

Rev. 1, Jan. 2003, page 6 of 65

Signal name

Direction Pin No.

Description

-CSEL
(PC Card Memory mode)

This signal is not used.

-CSEL
(PC Card I/O mode)

-CSEL
(True IDE mode)

This signal is used to configure this device as a
Master or a Slave when configured in the True IDE
mode. When this pin is grounded, this device is
configured as a Master. When the pin is open, this
device is configured as a Slave.

D15 to D0
(PC Card Memory mode)

I/O

41, 40, 39, 38,
37, 66, 65, 64, 6,
5, 4, 3, 2, 32, 31,
30

Data bus is D15 to D0. D0 is the LSB of the even byte
of the word. D8 is the LSB of the odd byte of the
word.

D15 to D0
(PC Card I/O mode)

D15 to D0
(True IDE mode)

GND
(PC Card Memory mode)

1, 34, 35, 68

Ground

GND
(PC Card I/O mode)

GND
(True IDE mode)

-INPACK
(PC Card Memory mode)

This signal is not used and should not be connected
at the host.

-INPACK
(PC Card I/O mode)
Input Acknowledge

This signal is asserted low by this card when the card
is selected and responding to an I/O read cycle at the
address that is on the address bus during -CE and
-IORD are low. This signal is used for the input data
buffer control.

-INPACK
(True IDE mode)

This signal is not used and should not be connected
at the host.

-IORD
(PC Card Memory mode)

This signal is not used.

-IORD
(PC Card I/O mode)

-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until I/O
card interface setting up.

-IORD
(True IDE mode)

-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until True
IDE interface setting up.

HB28H016A8H

Rev. 1, Jan. 2003, page 7 of 65

Signal name

Direction Pin No.

Description

-IOWR
(PC Card Memory mode)

This signal is not used.

-IOWR
(PC Card I/O mode)

-IOWR is used for control of data write in I/O task file
area. This card does not respond to -IOWR until I/O
card interface setting up.

-IOWR
(True IDE mode)

-IOWR is used for control of data write in I/O task file
area. This card does not respond to -IOWR until True
IDE interface setting up.

-OE
(PC Card Memory mode)

-OE is used for the control of reading register's data in
attribute area or task file area.

-OE
(PC Card I/O mode)

-OE is used for the control of reading register's data in
attribute area.

-ATASEL
(True IDE mode)

To enable True IDE mode this input should be
grounded by the host.

RDY/-BSY
(PC Card Memory mode)

The signal is RDY/-BSY pin. RDY/-BSY pin turns low
level during the card internal initialization operation at
V

applied or reset applied, so next access to the

card should be after the signal turned high level.

-IREQ
(PC Card I/O mode)

This signal is active low -IREQ pin. The signal of low
level indicates that the card is requesting software
service to host, and high level indicates that the card
is not requesting.

INTRQ
(True IDE mode)

This signal is the active high Interrupt Request to the
host.

-REG
(PC Card Memory mode)
Attribute memory select

-REG is used during memory cycles to distinguish
between task file and attribute memory accesses.
High for task file, Low for attribute memory is
accessed.

-REG
(PC Card I/O mode)

-REG is constantly low when task file or attribute
memory is accessed.

-REG
(True IDE mode)

This input signal is not used and should be connected
to VCC.

HB28H016A8H

Rev. 1, Jan. 2003, page 8 of 65

Signal name

Direction Pin No.

Description

RESET
(PC Card Memory mode)

This signal is active high RESET pin. If this signal is
asserted high, the card internal initialization begins to
operate. During the card internal initialization
RDY/-BSY is low. After the card internal initialization
RDY/-BSY is high.

RESET
(PC Card I/O mode)

This signal is active high RESET pin. If this signal is
asserted high, the card internal initialization begins to
operate. In this mode, RDY/-BSY signal can not be
used, so using Status Register the Ready/Busy status
can be confirmed.

-RESET
(True IDE mode)

This signal is active low -RESET pin. If this signal is
asserted low, all the register's in this card are reset.
In this mode, RDY/-BSY signal can not be used, so
using status register the Ready/Busy status can be
confirmed.

(PC Card Memory mode)

17, 51

+5 V, +3.3 V power.

(PC Card I/O mode)

(True IDE mode)

-VS1, -VS2
(PC Card Memory mode)

43, 57

These signals are intended to notify V

requirement

to host. -VS1 is held grounded and -VS2 is
nonconnected in this card.

-VS1, -VS2
(PC Card I/O mode)

-VS1, -VS2
(True IDE mode)

-WAIT
(PC Card Memory mode)

This signal is active low -WAIT pin. In this card this
signal is constantly high level.

-WAIT
(PC Card I/O mode)

IORDY
(True IDE mode)

This output signal may be used as IORDY. In this
card this signal is constantly high impedance.

-WE
(PC Card Memory mode)

-WE is used for the control of writing register's data in
attribute memory area or task file area.

-WE
(PC Card I/O mode)

-WE is used for the control of writing register's data in
attribute memory area.

-WE
(True IDE mode)

This input signal is not used and should be connected
to V

by the host.

HB28H016A8H

Rev. 1, Jan. 2003, page 12 of 65

Host access specifications

1. Attribute access specifications

When CIS-ROM region or Configuration register region is accessed, read and write operations are executed
under the condition of -REG = "L" as follows. That region can be accessed by Byte/Word/Odd-byte modes
which are defined by PC card standard specifications.

Attribute Read Access Mode

Mode

-REG

-CE2

-CE1

-OE

-WE

D8 to D15

D0 to D7

Standby mode

H H

High-Z High-Z

Byte

access

(8-bit) L H L L L H High-Z

even

byte

L H L H L H High-Z

invalid

Word access (16-bit)

L H invalid even

byte

Odd byte access (8-bit)

L H invalid High-Z

Note:

: L or H

Attribute Write Access Mode

Mode

-REG

-CE2

-CE1

-OE

-WE

D8 to D15

D0 to D7

Standby mode

H H

Don't care

Byte access (8-bit)

Don't care

even byte

L H L H H L Don't

care

Don't

care

Word access (16-bit)

Don't care

even byte

Odd byte access (8-bit)

Don't care

Note:

: L or H

Attribute Access Timing Example

Dout

A0 to A10

-REG

-CE2/-CE1

-OE

-WE

D0 to D15

read cycle

write cycle

Din

HB28H016A8H

Rev. 1, Jan. 2003, page 13 of 65

2. Task File register access specifications

There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address

area. Each case of Task File register read and write operations are executed under the condition as follows. That area can

be accessed by Byte/Word/Odd Byte mode which are defined by PC card standard specifications.

(1) I/O address map

Task File Register Read Access Mode (1)

Mode

-REG -CE2 -CE1 A0

-IORD -IOWR -OE

-WE

D8 to D15 D0 to D7

Standby mode

H H

High-Z High-Z

Byte

access

(8-bit) L H L L L H H H High-Z even

byte

L H L H L H H H High-Z odd

byte

Word access (16-bit)

L H H H odd

byte

even

byte

Odd byte access (8-bit) L

L H H H odd

byte

High-Z

Note:

: L or H

Task File Register Write Access Mode (1)

Mode

-REG -CE2 -CE1 A0

-IORD -IOWR -OE

-WE

D8 to D15 D0 to D7

Standby mode

H H

Don't care Don't care

Byte

access

(8-bit) L H L L H L H H Don't

care

even

byte

L H L H H L H H Don't

care

odd

byte

Word access (16-bit)

H L H H odd

byte

even

byte

Odd byte access (8-bit) L

H L H H odd

byte

Don't

care

Note:

: L or H

Task File Register Access Timing Example (1)

Dout

A0 to A10

-REG

-CE2/-CE1

-IORD

- IOWR

D0 to D15

read cycle

write cycle

Din

HB28H016A8H

Rev. 1, Jan. 2003, page 14 of 65

(2) Memory address map

Task File Register Read Access Mode (2)

Mode

-REG -CE2 -CE1 A0

-OE

-WE

-IORD -IOWR D8 to D15 D0 to D7

Standby mode

H H

High-Z High-Z

Byte

access

(8-bit) H H L L L H H H High-Z even

byte

H H L H L H H H High-Z odd

byte

Word access (16-bit)

L H H H odd

byte

even

byte

Odd byte access (8-bit) H

L H H H odd

byte

High-Z

Note:

: L or H

Task File Register Write Access Mode (2)

Mode

-REG -CE2 -CE1 A0

-OE

-WE

-IORD -IOWR D8 to D15 D0 to D7

Standby mode

H H

Don't care Don't care

Byte

access

(8-bit) H H L L H L H H Don't

care

even

byte

H H L H H L H H Don't

care

odd

byte

Word access (16-bit)

H L H H odd

byte

even

byte

Odd byte access (8-bit) H

H L H H odd

byte

Don't

care

Note:

: L or H

Task File Register Access Timing Example (2)

Dout

A0 to A10

-REG

-CE2/-CE1

-OE

-WE

D0 to D15

read cycle

write cycle

Din

HB28H016A8H

Rev. 1, Jan. 2003, page 15 of 65

3. True IDE Mode

The card can be configured in a True IDE

ode of operation. This card is configured in this mode only when the -OE

input signal is asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host.

Only I/O operation to the task file and data register are allowed. If this card is configured during power on
sequence, data register are accessed in word (16-bit).

The card permits 8-bit accesses if the user issues a Set

Feature Command to put the device in 8-bit mode.

True IDE Mode Read I/O Function

Mode

-CE2

-CE1

A0 to A2 -IORD

-IOWR

D8 to D15 D0 to D7

Invalid mode

High-Z High-Z

Standby mode

High-Z High-Z

Data register access

odd byte

even byte

Alternate status access

High-Z

status out

Other task file access

1-7H

High-Z

data

Note:

: L or H

True IDE Mode Write I/O Function

Mode

-CE2

-CE1

A0 to A2 -IORD

-IOWR

D8 to D15 D0 to D7

Invalid mode

don't care don't care

Standby mode

don't care don't care

Data register access

odd byte

even byte

Control register access

don't care control in

Other task file access

1-7H

don't care data

Note:

: L or H

True IDE Mode I/O Access Timing Example

Dout

Din

A0 to A2

-CE

-IORD

-IOWR

-IOIS16

D0 to D15

read cycle

write cycle

HB28H016A8H

Rev. 1, Jan. 2003, page 16 of 65

Configuration register specifications

This card supports four Configuration registers for the purpose of the configuration and observation of this
card. These registers can be used in memory card mode and I/O card mode. In True IDE mode, these
registers can not be used.

1. Configuration Option register (Address 200H)

This register is used for the configuration of the card configuration status and for the issuing soft reset to the
card.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

SRESET LevlREQ INDEX

Note: initial value: 00H

Name R/W

Function

SRESET
(HOST->)

R/W Setting this bit to "1", places the card in the reset state (Card Hard Reset). This

operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to "0",
places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) .
Card configuration status is reset and the card internal initialized operation starts when
Card Hard Reset is executed, so next access to the card should be the same sequence
as the power on sequence.

LevlREQ
(HOST->)

R/W This bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode

interrupt is selected.

INDEX
(HOST->)

R/W This bits is used for select operation mode of the card as follows.

When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose
of Memory card interface recognition.

INDEX bit assignment

INDEX bit

5 4 3 2 1 0 Card mode

Task File register address

Mapping mode

0 0 0 0 0 0 Memory card

0H to FH, 400H to 7FFH

memory mapped

0 0 0 0 0 1 I/O card

xx0H to xxFH

contiguous I/O mapped

0 0 0 0 1 0 I/O card

1F0H to 1F7H, 3F6H to 3F7H

primary I/O mapped

0 0 0 0 1 1 I/O card

170H to 177H, 376H to 377H

secondary I/O mapped

HB28H016A8H

Rev. 1, Jan. 2003, page 17 of 65

2. Configuration and Status register (Address 202H)

This register is used for observing the card state.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

CHGED

SIGCHG

IOIS8

0 0 PWD

INTR

Note: initial value: 00H

Name R/W

Function

CHGED
(CARD->)

This bit indicates that CRDY/-BSY bit on Pin Replacement register is set to "1". When
CHGED bit is set to "1", -STSCHG pin is held "L" at the condition of SIGCHG bit set to
"1" and the card configured for the I/O interface.

SIGCHG
(HOST->)

R/W This bit is set or reset by the host for enabling and disabling the status-change signal (-

STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", -
STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept
"H".

IOIS8
(HOST->)

R/W The host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus

(D7 to D0).

PWD
(HOST->)

R/W When this bit is set to "1", the card enters sleep state (Power Down mode). When this

bit is reset to "0", the card transfers to idle state (active mode). RRDY/-BSY bit on Pin
Replacement Register becomes BUSY when this bit is changed. RRDY/-BSY will not
become Ready until the power state requested has been entered. This card
automatically powers down when it is idle, and powers back up when it receives a
command.

INTR
(CARD->)

This bit indicates the internal state of the interrupt request. This bit state is available
whether I/O card interface has been configured or not. This signal remains true until
the condition which caused the interrupt request has been serviced. If interrupts are
disabled by the -IEN bit in the Device Control Register, this bit is a zero.

HB28H016A8H

Rev. 1, Jan. 2003, page 18 of 65

3. Pin Replacement register (Address 204H)

This register is used for providing the signal state of -IREQ signal when the card configured I/O card interface.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0 0 CRDY/-BSY

0 1 1 RRDY/-BSY

Note: initial value: 0CH

Name R/W

Function

CRDY/-BSY
(HOST->)

R/W This bit is set to "1" when the RRDY/-BSY bit changes state. This bit may also be

written by the host.

RRDY/-BSY
(HOST->)

R/W When read, this bit indicates +READY pin states. When written, this bit is used for

CRDY/-BSY bit masking.

4. Socket and Copy register (Address 206H)

This register is used for identification of the card from the other cards. Host can read and write this register.
This register should be set by host before this card's Configuration Option register set.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

0 0 0 DRV#

0 0 0 0

Note: initial value: 00H

Name R/W

Function

DRV#
(HOST->)

R/W This fields are used for the configuration of the plural cards. When host configures the

plural cards, written the card's copy number in this field. In this way, host can perform
the card's master/slave organization.

HB28H016A8H

Rev. 1, Jan. 2003, page 19 of 65

CIS informations

CIS informations are defined as follows. By reading attribute address from "0000 H", card CIS informations
can be confirmed.

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

000H

01H CISTPL_DEVICE

Device info tuple

Tuple code

002H

04H TPL_LINK

Link length is 4 byte

Link to next tuple

004H DFH

Device

type W

P
S

Device speed Device type = DH: I/O device

WPS = 1: No WP
Device speed = 7: ext speed

Device type, WPS, speed

006H 4AH

EXT

Speed
mantissa

Speed
exponent

400 ns if no wait

Extended speed

008H

01H 1x

2k units

2k byte of address space

Device size

00AH

FFH List end marker

End of device

END marker

00CH

1CH CISTPL_DEVICE_OC

Other conditions device info
tuple

Tuple code

00EH

04H TPL_LINK

Link length is 4 bytes

Link to next tuple

010H 02H EXT

Reserved V

MWAIT 3 V, wait is not used

Other conditions info field

012H D9H

Device

type W

P
S

Device speed Device type = DH: I/O device

WPS = 1: No WP
Device speed = 1: 250 ns

Device type, WPS, speed

014H

01H 1x

2k units

2k byte of address space

Device size

016H

FFH List end marker

End of device

END marker

018H

18H CISTPL_JEDEC_C

JEDEC ID common memory Tuple code

01AH

02H TPL_LINK

Link length is 2 bytes

Link to next tuple

01CH

DFH PCMCIA's manufacturer's JEDEC

ID code

Manufacturer's ID code

JEDEC ID of PC Card ATA

01EH

01H PCMCIA JEDEC device code

2nd byte of JEDEC ID

020H

20H CISTPL_MANFID

Manufacturer's ID code

Tuple code

022H

04H TPL_LINK

Link length is 4 bytes

Link to next tuple

024H

07H Low byte of PCMCIA

manufacturer's code

HITACHI JEDEC
manufacturer's ID

Low byte of manufacturer's
ID code

026H

00H High byte of PCMCIA

manufacturer's code

Code of 0 because other byte
is JEDEC 1 byte
manufacture's ID

High byte of manufacturer's
ID code

028H

00H Low byte of product code

HITACHI code for PC CARD
ATA

Low byte of product code

02AH

00H High byte of product code

High byte of product code

HB28H016A8H

Rev. 1, Jan. 2003, page 20 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

02CH

15H CISTPL_VERS_1

Level 1 version/product info

Tuple code

02EH

15H TPL_LINK

Link length is 15h bytes

Link to next tuple

030H 04H TPPLV1_MAJOR

PCMCIA2.0/JEIDA4.1

Major

version

032H 01H TPPLV1_MINOR

PCMCIA2.0/JEIDA4.1

Minor

version

034H

48H

` H '

Info string 1

036H

49H

` I '

038H

54H

` T '

03AH

41H

` A '

03CH

43H

` C '

03EH

48H

` H '

040H

49H

` I '

042H 00H

Null

terminator

044H

46H

` F '

Info string 2

046H

4CH

` L '

048H

41H

` A '

04AH

53H

` S '

04CH

48H

` H '

04EH 00H

Null

terminator

050H

35H

` 5 '

Vender specific strings

052H

2EH

` . '

054H

30H

` 0 '

056H 00H

Null

terminator

058H

FFH List end marker

End of device

END marker

05AH

21H CISTPL_FUNCID

Function ID tuple

Tuple code

05CH

02H TPL_LINK

Link length is 2 bytes

Link to next tuple

05EH

04H TPLFID_FUNCTION = 04H

Disk function, may be silicon,
may be removable

PC card function code

060H

01H Reserved

R P

R = 0: No BIOS ROM
P = 1: Configure card at
power on

System initialization byte

HB28H016A8H

Rev. 1, Jan. 2003, page 21 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

062H

22H CISTPL_FUNCE

Function extension tuple

Tuple code

064H

02H TPL_LINK

Link length is 2 bytes

Link to next tuple

066H

01H Disk function extension tuple type Disk interface type

Extension tuple type for disk

068H

01H Disk interface type

PC card ATA interface

Interface type

06AH

22H CISTPL_FUNCE

Function extension tuple

Tuple code

06CH

03H TPL_LINK

Link length is 3 bytes

Link to next tuple

06EH

02H Disk function extension tuple type Single drive

Extension tuple type for disk

070H 0CH

Reserved D

S V

, silicon, single drive

V = 0: No V

required

S = 1: Silicon
U = 1: Unique serial #
D = 0: Single drive on card

Basic ATA option
parameters byte 1

072H

0FH R

E N P3 P2 P1 P0

P0: Sleep mode supported
P1: Standby mode
supported
P2: Idle mode suppported
P3: Drive auto power control
N: Some config excludes
3X7
E: Index bit is emulated
I: Twin IOIS16# data reg
only
R: Reserved

Basic ATA option
parameters byte 2

074H

1AH CISTPL_CONFIG

Configuration tuple

Tuple code

076H

05H TPL_LINK

Link length is 5 bytes

Link to next tuple

078H

01H RFS

RMS

RAS

RFS: Reserved
RMS: TPCC_RMSK size - 1 =
0
RAS: TPCC_RADR size - 1 = 1
1 byte register mask
2 byte config base address

Size of fields byte TPCC_SZ

07AH

03H TPCC_LAST

Entry with config index of
03H is final entry in table

Last entry of config registers

07CH

00H TPCC_RADR (LSB)

Configuration registers are
located at 200H in REG
space

Location of config registers

07EH 02H TPCC_RADR

(MSB)

080H

0FH Reserved

S P C I

I: Configuration index
C: Configuration and status
P: Pin replacement
S: Socket and copy

Configuration registers
present mask
TPCC_RMSK

HB28H016A8H

Rev. 1, Jan. 2003, page 22 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

082H

1BH CISTPL_CFTABLE_ENTRY

Configuration table entry
tuple

Tuple code

084H

08H TPL_LINK

Link length is 8 bytes

Link to next tuple

086H

C0H I

D Configuration index

Memory mapped I/O
configuration
I = 1: Interface byte follows
D = 1: Default entry
Configuration index = 0

Configuration table index
byte
TPCE_INDX

088H

40H W

R P B Interface type

W = 0: Wait not used
R = 1: Ready active
P = 0: WP used
B = 0: BVD1 and BVD2 not
used
IF type = 0: Memory
interface

Interface description field
TPCE_IF

08AH

A1H M

IR IO T P

M = 1: Misc info present
MS = 01: Memory space info
single 2-byte length
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: V

only info

Feature selection byte
TPCE_FS

08CH

01H R

DI PI AI SI HV LV NV

Nominal voltage only follows
R: Reserved
DI: Power down current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info

Power parameters for V

08EH

55H X

Mantissa

Exponent

Nominal voltage = 5 V

nominal value

090H

08H Length in 256 bytes pages (LSB) Length of memory space is 2

Memory space description
structures (TPCE_MS)

092H

00H Length in 256 bytes pages (MSB)

094H 20H X R

P R

A T

X = 0: No more misc fields
R: Reserved
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive

Miscellaneous features field
TPCE_MI

HB28H016A8H

Rev. 1, Jan. 2003, page 23 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

096H

1BH CISTPL_CFTABLE_ENTRY

Configuration table entry
tuple

Tuple code

098H

06H TPL_LINK

Link length is 6 bytes

Link to next tuple

09AH

00H I

D Configuration index

Memory mapped I/O
configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 0

Configuration table index
byte
TPCE_INDX

09CH

01H M

IR IO T P

M = 0: No Misc info
MS = 00: No Memory space
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: V

only info

Feature selection byte
TPCE_FS

09EH

21H R

DI PI AI SI HV LV NV

Power parameters for V

0A0H

B5H X

Mantissa

Exponent

Nominal voltage = 3.0 V

nominal value

0A2H 1EH X Extension

0.3 V

Extension byte

0A4H

4DH X

Mantissa

Exponent

Max average current over 10
msec is 45 mA

Max. average current

HB28H016A8H

Rev. 1, Jan. 2003, page 24 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

0A6H

1BH CISTPL_CFTABLE_ ENTRY

Configuration table entry
tuple

Tuple code

0A8H

0AH TPL_LINK

Link length is 10 bytes

Link to next tuple

0AAH C1H I

D Configuration INDEX

Contiguous I/O mapped ATA
registers configuration
I = 1: Interface byte follows
D = 1: Default entry
Configuration index = 1

Configuration table index
byte TPCE_INDX

0ACH 41H W

R P B Interface type

W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
IF type = 1: I/O interface

Interface description field
TPCE_IF

0AEH 99H M

IR IO T P

M = 1: Misc info present
MS = 00: No memory space
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: V

only info

Feature selection byte
TPCE_FS

0B0H

01H R

DI PI AI SI HV LV NV

Nominal voltage only follows
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info

Power parameters for V

0B2H

55H X

Mantissa

Exponent

Nominal voltage = 5 V

nominal value

0B4H

64H R

S E IO AddrLine

S = 1: 16-bit hosts supported
E = 1: 8-bit hosts supported
IO AddrLine: 4 lines
decoded

I/O space description field
TPCE_IO

0B6H

F0H S

P L M V B I

S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
L = 1: Level mode IRQ
supported
M = 1: Bit mask of IRQs
present
V = 0: No vender unique IRQ
B = 0: No bus error IRQ
I = 0: No IO check IRQ
N = 0: No NMI

Interrupt request description
structure
TPCE_IR

HB28H016A8H

Rev. 1, Jan. 2003, page 26 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

0BEH 1BH CISTPL_CFTABLE_ENTRY

Configuration table entry
tuple

Tuple code

0C0H

06H TPL_LINK

Link length is 6 bytes

Link to next tuple

0C2H

01H I

D Configuration index

Contiguous I/O mapped ATA
registers configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 1

Configuration table index
byte
TPCE_INDX

0C4H

01H M

IR IO T P

M = 0: No Misc info
MS = 00: No Memory space
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: V

only info

Feature selection byte
TPCE_FS

0C6H

21H R

DI PI AI SI HV LV NV

Power parameters for V

0C8H

B5H X

Mantissa

Exponent

Nominal voltage = 3.0 V

nominal value

0CAH 1EH X Extension

0.3 V

Extension byte

0CCH 4DH X

Mantissa

Exponent

Max average current over 10
msec is 45 mA

Max. average current

HB28H016A8H

Rev. 1, Jan. 2003, page 27 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

0CEH 1BH CISTPL_CFTABLE_ENTRY

Configuration table entry
tuple

Tuple code

0D0H

0FH TPL_LINK

Link length is 15 bytes

Link to next tuple

0D2H

C2H I

D Configuration INDEX

ATA primary I/O mapped
configuration
I = 1: Interface byte follows
D = 1: default entry follows
Configuration index = 2

Configuration table index
byte TPCE_INDX

0D4H

41H W

R P B Interface type

W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
IF type = 1: I/O interface

Interface description field
TPCE_IF

0D6H

99H M

IR IO T P

M = 1: misc info present
MS = 00: No memory space
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: V

only info

Feature selection byte
TPCE_FS

0D8H

01H R

DI PI AI SI HV LV NV

Power parameters for V

0DAH 55H X

Mantissa

Exponent

Nominal voltage = 5 V

nominal value

0DCH EAH R

S E IO AddrLine

R = 1: Range follows
S = 1: 16-bit hosts supported
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded

I/O space description field
TPCE_IO

0DEH 61H LS

N range

LS = 1: Size of lengths is 1
byte
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1

I/O range format description

HB28H016A8H

Rev. 1, Jan. 2003, page 28 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

0E0H

F0H

1st I/O base address (LSB)

1st I/O range address

0E2H

01H

1st I/O base address (MSB)

0E4H

07H

1st I/O length - 1

1st I/O range length

0E6H

F6H

2nd I/O base address (LSB) 2nd I/O range address

0E8H

03H

2nd I/O base address (MSB)

0EAH 01H

2nd I/O length - 1

2nd I/O range length

0ECH EEH S

P L M IRQ level

S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
L = 1: Level mode IRQ
supported
M = 0: Bit mask of IRQs
present
IRQ level is IRQ14

Interrupt request description
structure
TPCE_IR

0EEH 20H X R P R

A T

X = 0: Nomore misc fields
R: reserved
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive

Miscellaneous features field
TPCE_MI

HB28H016A8H

Rev. 1, Jan. 2003, page 29 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

0F0H

1BH CISTPL_CFTABLE_ENTRY

Configuration table entry
tuple

Tuple code

0F2H

06H TPL_LINK

Link length is 6 bytes

Link to next tuple

0F4H

02H I

D Configuration index

ATA primary I/O mapped
configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 2

Configuration table index
byte
TPCE_INDX

0F6H

01H M

IR IO T P

M = 0: No Misc info
MS = 00: No Memory space
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: V

only info

Feature selection byte
TPCE_FS

0F8H

21H R

DI PI AI SI HV LV NV

Power parameters for V

0FAH

B5H X

Mantissa

Exponent

Nominal voltage = 3.0 V

nominal value

0FCH 1EH X Extension

0.3 V

Extension byte

0FEH

4DH X

Mantissa

Exponent

Max average current over 10
msec is 45 mA

Max. average current

HB28H016A8H

Rev. 1, Jan. 2003, page 30 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

100H

1BH CISTPL_CFTABLE_ENTRY

Configuration table entry
tuple

Tuple code

102H

0FH TPL_LINK

Link length is 15 bytes

Link to next tuple

104H

C3H I

D Configuration INDEX

ATA secondary I/O mapped
configuration
I = 1: Interface byte follows
D = 1: default entry
Configuration index = 3

Configuration table index
byte TPCE_INDX

106H

41H W

R P B Interface type

W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
IF type = 1: I/O interface

Interface description field
TPCE_IF

108H

99H M

IR IO T P

M = 1: misc info present
MS = 00: No memory space
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: V

only info

Feature selection byte
TPCE_FS

10AH

01H R

DI PI AI SI HV LV NV

Power parameters for V

10CH

55H X

Mantissa

Exponent

Nominal voltage = 5 V

nominal value

10EH

EAH R

S E IO AddrLine

R = 1: Range follows
S = 1: 16-bit hosts supported
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded

I/O space description field
TPCE_IO

110H

61H LS

N range

LS = 1: Size of lengths is 1
byte
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1

I/O range format description

HB28H016A8H

Rev. 1, Jan. 2003, page 31 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

112H

70H

1st I/O base address (LSB)

1st I/O range address

114H

01H

1st I/O base address (MSB)

116H

07H

1st I/O length - 1

1st I/O range length

118H

76H

2nd I/O base address (LSB) 2nd I/O range address

11AH

03H

2nd I/O base address (MSB)

11CH

01H

2nd I/O length - 1

2nd I/O range length

11EH

EEH S

P L M IRQ level

S = 1: Share logic active
P = 1: Pulse mode IRQ
supported
L = 1: Level mode IRQ
supported
M = 0: Bit mask of IRQs
present
IRQ level is IRQ14

Interrupt request description
structure
TPCE_IR

120H 20H X R

P R

A T

X = 0: Nomore misc fields
R: reserved
P = 1: Power down
supported
RO = 0: Not read only mode
A = 0: Audio not supported
T = 0: Single drive

Miscellaneous features field
TPCE_MI

HB28H016A8H

Rev. 1, Jan. 2003, page 32 of 65

Address

Data 7 6 5 4 3 2 1 0

Description of contents

CIS function

122H

1BH CISTPL_CFTABLE_ENTRY

Configuration table entry
tuple

Tuple code

124H

06H TPL_LINK

Link length is 6 bytes

Link to next tuple

126H

03H I

D Configuration index

ATA secondary I/O mapped
configuration
I = 0: No Interface byte
D = 0: No Default entry
Configuration index = 3

Configuration table index
byte
TPCE_INDX

128H

01H M

IR IO T P

M = 0: No Misc info
MS = 00: No Memory space
info
IR = 0: No interrupt info
present
IO = 0: No I/O port info
present
T = 0: No timing info present
P = 1: V

only info

Feature selection byte
TPCE_FS

12AH

21H R

DI PI AI SI HV LV NV

Power parameters for V

12CH

B5H X

Mantissa

Exponent

Nominal voltage = 3.0 V

nominal value

12EH 1EH X Extension

0.3 V

Extension byte

130H

4DH X

Mantissa

Exponent

Max average current over 10
msec is 45 mA

Max. average current

132H

14H CISTPL_NO_LINK

No link control tuple

Tuple code

134H

00H

Link is 0 bytes

Link to next tuple

136H

FFH CISTPL_END

End of list tuple

Tuple code

HB28H016A8H

Rev. 1, Jan. 2003, page 33 of 65

Task File register specification

These registers are used for reading and writing the storage data in this card. These registers are mapped five
types by the configuration of INDEX in Configuration Option register. The decoded addresses are shown as
follows.

Memory map (INDEX = 0)

-REG A10

A9 to A4 A3

Offset

-OE = L

-WE = L

1 0

0 0 0 0 0H Data

Data

1 0

0 0 0 1 1H Error

Feature

1 0

Sector count register

1 0

Sector number register Sector number register

1 0

Cylinder low register

1 0

Cylinder high register

1 0

Drive head register

1 0

0 1 1 1 7H Status

Command

1 0

Dup. even data register Dup. even data register

1 0

Dup. odd data register Dup. odd data register

1 0

Dup. error register

Dup. feature register

1 0

Alt. status register

Device control register

1 0

1 1 1 1 FH Drive

address

Reserved

1 1

Even data register

1 1

Odd data register

HB28H016A8H

Rev. 1, Jan. 2003, page 34 of 65

Contiguous I/O map (INDEX = 1)

-REG A10 to A4 A3

Offset

-IORD = L

-IOWR = L

0 0 0 0 0H Data

Data

0 0 0 1 1H Error

Feature

0 0 1 0 2H Sector

count

Sector

count

0 0 1 1 3H Sector

number

Sector

number

0 1 0 0 4H Cylinder

low

Cylinder

low

0 1 0 1 5H Cylinder

high

Cylinder

high

0 1 1 0 6H Drive

head

0 1 1 1 7H Status

Command

Dup. even data register Dup. even data register

Dup. odd data register

1 1 0 1 DH Dup.

error

feature

1 1 1 0 EH Alt.

status

control

1 1 1 1 FH Drive

address

Reserved

Primary I/O map (INDEX = 2)

-REG A10

A9 to A4 A3

-IORD = L

-IOWR = L

1FH 0 0 0 0 Data

Data

1FH 0 0 0 1 Error

Feature

1FH 0 0 1 0 Sector

count

Sector

count

1FH 0 0 1 1 Sector

number

Sector

number

1FH 0 1 0 0 Cylinder

low

1FH 0 1 0 1 Cylinder

high

Cylinder

high

1FH 0 1 1 0 Drive

head

1FH 0 1 1 1 Status

Command

3FH 0 1 1 0 Alt.

status

control

3FH 0 1 1 1 Drive

address

Reserved

HB28H016A8H

Rev. 1, Jan. 2003, page 35 of 65

Secondary I/O map (INDEX = 3)

-REG A10

A9 to A4 A3

-IORD = L

-IOWR = L

17H 0 0 0 0 Data

Data

17H 0 0 0 1 Error

Feature

17H 0 0 1 0 Sector

count

Sector

count

17H 0 0 1 1 Sector

number

Sector

number

17H 0 1 0 0 Cylinder

low

17H 0 1 0 1 Cylinder

high

Cylinder

high

17H 0 1 1 0 Drive

head

17H 0 1 1 1 Status

Command

37H 0 1 1 0 Alt.

status

control

37H 0 1 1 1 Drive

address

Reserved

True IDE Mode I/O map

-CE2

-CE1

-IORD = L

-IOWR = L

1 0 0 0 0 Data

Data

1 0 0 0 1 Error

Feature

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

1 0 1 1 1 Status

Command

Alt. status register

Device control register

0 1 1 1 1 Drive

address

Reserved

HB28H016A8H

Rev. 1, Jan. 2003, page 36 of 65

1. Data register: This register is a 16-bit register that has read/write ability, and it is used for transferring 1
sector data between the card and the host. This register can be accessed in word mode and byte mode. This
register overlaps the Error or Feature register.

bit15

bit14

bit13

bit12

bit11

bit10

bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

D0 to D15

2. Error register: This register is a read only register, and it is used for analyzing the error content at the
card accessing. This register is valid when the BSY bit in Status register and Alternate Status register are set
to "0" (Ready).

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

BBK

UNC

"0" IDNF

"0" ABRT

"0" AMNF

bit Name

Function

BBK (Bad BlocK detected)

This bit is set when a Bad Block is detected in requested ID field.

UNC (Data ECC error)

This bit is set when Uncorrectable error is occurred at reading the

card.

IDNF (ID Not Found)

The requested sector ID is in error or cannot be found.

ABRT (ABoRTed command)

This bit is set if the command has been aborted because of the
card status condition. (Not ready, Write fault, Invalid command,
etc.)

AMNF (Address Mark Not Found) This bit is set in case of a general error.

3. Feature register: This register is write only register, and provides information regarding features of the
drive which the host wishes to utilize.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Feature byte

4. Sector count register: This register contains the numbers of sectors of data requested to be transferred on
a read or write operation between the host and the card. If the value of this register is zero, a count of 256
sectors is specified. In plural sector transfer, if not successfully completed, the register contains the number
of sectors which need to be transferred in order to complete the request. This register's initial value is "01H".

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Sector count byte

HB28H016A8H

Rev. 1, Jan. 2003, page 37 of 65

5. Sector number register: This register contains the starting sector number which is started by following
sector transfer command.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Sector number byte

6. Cylinder low register: This register contains the low 8-bit of the starting cylinder address which is
started by following sector transfer command.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Cylinder low byte

7. Cylinder high register: This register contains the high 8-bit of the starting cylinder address which is
started by following sector transfer command.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Cylinder high byte

8. Drive head register: This register is used for selecting the Drive number and Head number for the
following command.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

1 LBA

1 DRV

Head

number

bit Name

Function

This bit is set to "1".

LBA

LBA is a flag to select either Cylinder / Head / Sector (CHS) or
Logical Block Address (LBA) mode. When LBA=0, CHS mode is
selected. When LBA=1, LBA mode is selected. In LBA mode, the
Logical Block Address is interrupted as follows:
LBA07-LBA00 : Sector Number Register D7-D0.
LBA15-LBA08 : Cylinder Low Register D7-D0.
LBA23-LBA16 : Cylinder High Register D7-D0.
LBA27-LBA24 : Drive / Head Register bits HS3-HS0.

This bit is set to "1".

DRV (DRiVe select)

This bit is used for selecting the Master (Card 0) and Slave (Card 1)
in Master/Slave organization. The card is set to be Card 0 or 1 by
using DRV# of the Socket and Copy register.

3 to 0 Head number

This bit is used for selecting the Head number for the following
command. Bit 3 is MSB.

HB28H016A8H

Rev. 1, Jan. 2003, page 38 of 65

9. Status register: This register is read only register, and it indicates the card status of command execution.
When this register is read in configured I/O card mode (INDEX = 1, 2, 3) and level interrupt mode, -IREQ is
negated. This register should be accessed in byte mode. In word mode, it is recommended that Alternate
status register may be used as this register.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

BSY DRDY

DWF DSC DRQ CORR

IDX ERR

bit Name

Function

BSY (BuSY)

This bit is set when the card internal operation is executing. When
this bit is set to "1", other bits in this register are invalid.

DRDY (Drive ReaDY)

If this bit and DSC bit are set to "1", the card is capable of receiving

the read or write or seek requests. If this bit is set to "0", the card
prohibits these requests.

DWF (Drive Write Fault)

This bit is set if this card indicates the write fault status.

DSC (Drive Seek Complete)

This bit is set when the drive seek complete.

DRQ (Data ReQuest)

This bit is set when the information can be transferred between the
host and Data register. This bit is cleared when the card receives
the other command.

CORR (CORRected data)

This bit is set when a correctable data error has been occurred and
the data has been corrected.

IDX (InDeX)

This bit is always set to "0".

ERR (ERRor)

This bit is set when the previous command has ended in some type
of error. The error information is set in the other Status register or
Error register. This bit is cleared by the next command.

10. Alternate status register: This register is the same as Status register in physically, so the bit assignment
refers to previous item of Status register. But this register is different from Status register that -IREQ is not
negated when data read.

11. Command register: This register is write only register, and it is used for writing the command at
executing the drive operation. The command code written in the command register, after the parameter is
written in the Task File during the card is Ready state.

HB28H016A8H

Rev. 1, Jan. 2003, page 39 of 65

Used

parameter

Command

code FR SC SN CY DR HD LBA

Check power mode

E5H or 98H

Execute

drive

diagnostic

90H

N N N N Y N N

Erase

sector

C0H

N Y Y Y Y Y Y

Format

track

50H

N Y N Y Y Y Y

Identify

Drive

ECH

N N N N Y N N

Idle

E3H

97H

N Y N N Y N N

Idle

immediate

E1H

95H

N N N N Y N N

Initialize drive parameters

91H

Read

buffer

E4H

N N N N Y N N

Read

multiple

C4H

N Y Y Y Y Y Y

Read long sector

22H or 23H

Read

sector

20H

21H

N Y Y Y Y Y Y

Read verify sector

40H or 41H

Recalibrate

1XH

N N N N Y N N

Request

sense

03H

N N N N Y N N

Seek

7XH

N N Y Y Y Y Y

Set

features

EFH

Y N N N Y N N

Set

multiple

mode

C6H

N Y N N Y N N

Set sleep mode

E6H or 99H

Stand

E2H

96H

N N N N Y N N

Stand by immediate

E0H or 94H

Translate

sector

87H

N Y Y Y Y Y Y

Wear

level

F5H

N N N N Y Y N

Write

buffer

E8H

N N N N Y N N

Write long sector

32H or 33H

Write

multiple

C5H

N Y Y Y Y Y Y

Write

multiple

w/o

erase

CDH

N Y Y Y Y Y Y

Write

sector

30H

31H

N Y Y Y Y Y Y

Write

sector

w/o

erase

38H

N Y Y Y Y Y Y

Write

verify

3CH

N Y Y Y Y Y Y

Note: FR: Feature register

SC: Sector Count register
SN: Sector Number register
CY: Cylinder register
DR: DRV bit of Drive Head register
HD: Head Number of Drive Head register
LBA: Logical Block Address Mode Supported
Y: The register contains a valid parameter for this command.
N: The register does not contain a valid parameter for this command.

HB28H016A8H

Rev. 1, Jan. 2003, page 40 of 65

12. Device control register: This register is write only register, and it is used for controlling the card
interrupt request and issuing an ATA soft reset to the card.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

1 SRST

nIEN

bit Name

Function

7 to 4

don't care

This bit is set to "1".

SRST (Software ReSeT)

This bit is set to "1" in order to force the card to perform Task File

Reset operation. This does not change the Card Configuration
registers as a Hardware Reset does. The card remains in Reset
until this bit is reset to "0".

nIEN (Interrupt ENable)

This bit is used for enabling -IREQ. When this bit is set to "0", -
IREQ is enabled. When this bit is set to "1", -IREQ is disabled.

This bit is set to "0".

13. Drive Address register: This register is read only register, and it is used for confirming the drive status.
This register is provides for compatibility with the AT disk drive interface. It is recommended that this
register is not mapped into the host's I/O space because of potential conflicts on bit7.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

nWTG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0

bit Name

Function

This bit is unknown

nWTG (WriTing Gate)

This bit is unknown

5 to 2 nHS3-0 (Head Select3-0)

These bits is the negative value of Head Select bits (bit 3 to 0) in
Drive/Head register.

nDS1 (Idrive Select1)

This bit is unknown

nDS0 (Idrive Select0)

This bit is unknown

HB28H016A8H

Rev. 1, Jan. 2003, page 41 of 65

ATA Command specifications

This table summarizes the ATA command set with the paragraphs. Following shows the support commands
and command codes which are written in command registers.

ATA Command Set

No. Command

set

Code

FR SC SN CY DR HD LBA

Check power mode

E5H or 98H

Execute drive diagnostic

90H

3 Erase

sector(s)

C0H

Y Y Y Y Y Y

4 Format

track

50H

Y Y Y Y

5 Identify

Drive

ECH

Idle

E3H or 97H

Idle immediate

E1H or 95H

Initialize drive parameters

91H

Y Y

9 Read

buffer

E4H

10 Read

multiple

C4H

Y Y Y Y Y Y

Read long sector

22H, 23H

Y Y Y Y Y

Read sector (s)

20H, 21H

Y Y Y Y Y Y

Read verify sector (s)

40H, 41H

Y Y Y Y Y Y

14 Recalibrate

1XH

15 Request

sense

03H

16 Seek

7XH

Y Y Y Y Y

17 Set

features

EFH

Set multiple mode

C6H

Set sleep mode

E6H or 99H

Stand by

E2H or 96H

Stand by immediate

E0H or 94H

22 Translate

sector

87H

Y Y Y Y Y Y

23 Wear

level

F5H

Y Y

24 Write

buffer

E8H

Write long sector

32H or 33H

Y Y Y Y Y

26 Write

multiple

C5H

Y Y Y Y Y Y

Write multiple w/o erase

CDH

Y Y Y Y Y Y

Write sector

30H or 31H

Y Y Y Y Y Y

Write sector(s) w/o erase

38H

Y Y Y Y Y Y

30 Write

verify

3CH

Y Y Y Y Y Y

HB28H016A8H

Rev. 1, Jan. 2003, page 42 of 65

Note: FR: Feature Register

SC: Sector Count register (00H to FFH)
SN: Sector Number register (01H to 20H)
CY: Cylinder Low/High register (to)
DR: Drive bit of Drive/Head register
HD: Head No.(0 to 3) of Drive/Head register
NH: No. of Heads
Y: Set up

: Not set up

1. Check Power Mode (code: E5H or 98H): This command checks the power mode.

2. Execute Drive Diagnostic (code: 90H): This command performs the internal diagnostic tests
implemented by the Card.

3. Erase Sector(s) (code: C0H): This command is used to erase data sectors.

4. Format Track (code: 50H): This command writes the desired head and cylinder of the selected drive.
But selected sector data is not exchange. This card excepts a sector buffer of data from the host to follow the
command with same protocol as the Write Sector Command.

5. Identify Drive (code: ECH): This command enables the host to receive parameter information from the
Card.

HB28H016A8H

Rev. 1, Jan. 2003, page 43 of 65

Identify Drive Information

Word address Default value Total bytes Data field type information

848AH

General configuration bit-significant information

XXXX

Default number of cylinders

2 0000H

Reserved

00XXH

Default number of heads

0000H

Number of unformatted bytes per track

XXXX

Number of unformatted bytes per sector

XXXX

Default number of sectors per track

7 to 8

XXXX

Number of sectors per card (Word7 = MSW, Word8 = LSW)

9 0000H

Reserved

10 to 19

XXXX

Reserved

0002H

Buffer type (dual ported)

0002H

Buffer size in 512 byte increments

0004H

# of ECC bytes passed on Read/Write Long Commands

23 to 46

XXXX

Firmware revision in ASCII etc.

0001H

Maximum of 1 sector on Read/Write Multiple command

0000H

Double Word not supported

0200H

Capabilities: DMA NOT Supported (bit 8), LBA supported
(bit9)

50 0000H

Reserved

0100H

PIO data transfer cycle timing mode 1

0000H

DMA data transfer cycle timing mode not Supported

53 to 58

XXXX

Reserved

010XH

Multiple sector setting is valid

60 to 61

XXXX

Total number of sectors addressable in LBA Mode

62 to 255

0000H

388

Reserved

6. Idle (code: E3H or 97H): This command causes the Card to set BSY, enter the Idle mode, clear BSY and
generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the sector
count is zero, the automatic power down mode is disabled.

7. Idle Immediate (code: E1H or 95H): This command causes the Card to set BSY, enter the Idle (Read)
mode, clear BSY and generate an interrupt.

8. Initialize Drive Parameters (code: 91H): This command enables the host to set the number of sectors per
track and the number of heads per cylinder.

9. Read Buffer (code: E4H): This command enables the host to read the current contents of the card's sector
buffer.

HB28H016A8H

Rev. 1, Jan. 2003, page 44 of 65

10. Read Multiple (code: C4H): This command performs similarly to the Read Sectors command.
Interrupts are not generated on each sector, but on the transfer of a block which contains the number of
sectors defined by a Set Multiple command.

11. Read Long Sector (code: 22H or 23H): This command performs similarly to the Read Sector(s)
command except that it returns 516 bytes of data instead of 512 bytes.

12. Read Sector(s) (code: 20H, 21H): This command reads from 1 to 256 sectors as specified in the Sector
Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the
Sector Number register.

13. Read Verify Sector(s) (code: 40H or 41H): This command is identical to the Read Sectors command,
except that DRQ is never set and no data is transferred to the host .

14. Recalibrate (code: 1XH): This command is effectively a NOP command to the Card and is provided for
compatibility purposes.

15. Request Sense (code: 03H): This command requests an extended error code after command ends with
an error.

16. Seek (code: 7XH): This command is effectively a NOP command to the Card although it does perform a
range check.

17. Set Features (code: EFH): This command is used by the host to establish or select certain features.

Feature Operation

01H

Enable 8-bit data transfers.

55H

Disable Read Look Ahead.

66H

Disable Power on Reset (POR) establishment of defaults at Soft Reset.

81H

Disable 8-bit data transfers.

BBH

4 bytes of data apply on Read/Write Long commands.

CCH

Enable Power on Reset (POR) establishment of defaults at Soft Reset.

18. Set Multiple Mode (code: C6H): This command enables the Card to perform Read and Write Multiple
operations and establishes the block count for these commands.

19. Set Sleep Mode (code: E6H or 99H): This command causes the Card to set BSY, enter the Sleep mode,
clear BSY and generate an interrupt.

20. Stand By (code: E2H or 96H): This command causes the Card to set BSY, enter the Sleep mode (which
corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately.

21. Stand By Immediate (code: E0H or 94H): This command causes the Card to set BSY, enter the Sleep
mode(which corresponds to the ATA "Standby" Mode), clear BSY and return the interrupt immediately.

HB28H016A8H

Rev. 1, Jan. 2003, page 45 of 65

22. Translate Sector (code: 87H): This card does not support by this command the function of determining
the exact number of times a user sector has been erased and programmed because this card always responds
with "00H", though this command could provide information containing the desired cylinder, head and
sector, including its Logical Address, etc.

23. Wear Level (code: F5H): This command effectively a NOP command and only implemented for
backward compatibility. The Sector Count Register will always be returned with an 00H indicating Wear
Level is not needed.

24. Write Buffer (code: E8H): This command enables the host to overwrite contents of the Card's sector
buffer with any data pattern desired.

25. Write Long Sector (code: 32H or 33H): This command is provided for compatibility purposes and is
similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes.

26. Write Multiple (code: C5H): This command is similar to the Write Sectors command. Interrupts are not
presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set
Multiple command.

27. Write Multiple without Erase (code: CDH): This command is similar to the Write Multiple command
with the exception that an implied erase before write operation is not performed.

28. Write Sector(s) (code: 30H or 31H): This command writes from 1 to 256 sectors as specified in the
Sector Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified
in the Sector Number register.

29. Write Sector(s) without Erase (code: 38H): This command is similar to the Write Sector(s) command
with the exception that an implied erase before write operation is not performed.

30. Write Verify (code: 3CH): This command is similar to the Write Sector(s) command, except each sector
is verified immediately after being written.

HB28H016A8H

Rev. 1, Jan. 2003, page 50 of 65

Absolute Maximum Ratings

Parameter Symbol

Value

Unit

Note

All input/output voltages

Vin, Vout

0.3 to V

0.3

voltage

0.3 to

6.5 V

Operating temperature range

Topr

0 to

Storage temperature range

Tstg

20 to

Note: 1. Vin, Vout min =

2.0 V for pulse width

20 ns.

Recommended DC Operating Conditions

Parameter Symbol

Min

Typ

Max

Unit

Note

Operating temperature

voltage

5.0

10% 5.0

5.0

10% V

3.3

Capacitance (Ta = 25

C, f = 1MHz)

Parameter Symbol

Min

Typ

Max

Unit

Test

conditions

Input capacitance

Cin

Vin = 0 V

Output capacitance

Cout

Vout = 0 V

System Performance

Item Performance

Start up times (Reset to ready)

100 ms (max)

Start up times (Sleep to idle)

2 ms (max)

Data transfer rate to/from host

8 MB/s burst

Controller overhead (Command to DRQ)

2 ms (max)

Data transfer cycle end to ready (Sector write)

2 ms (typ)

HB28H016A8H

Rev. 1, Jan. 2003, page 51 of 65

DC Characteristics-1 (Ta = 0 to

C, V

= 5.0 V

10%)

Parameter Symbol

Min

Typ

Max

Unit

Test

conditions

Note

Input leakage current

Vin = GND to V

Input voltage (CMOS)

0.8 V

4.0

Input voltage (schmitt trigger) V

2.0

2.8

Output voltage

0.4 V

= 8 mA

0.8

8 mA

Note: 1. Except pulled up input pin.

DC Characteristics-2 (Ta = 0 to

C, V

= 3.3 V

5%)

Parameter Symbol

Min

Typ

Max

Unit

Test

conditions

Note

Input leakage current

Vin = GND to V

Input voltage (CMOS)

0.6 V

2.4

Input voltage (schmitt trigger) V

1.0

1.8

Output voltage

0.4 V

= 8 mA

0.8

8 mA

Note: 1. Except pulled up input pin.

HB28H016A8H

Rev. 1, Jan. 2003, page 52 of 65

DC Characteristics-3 (Ta = 0 to

C, V

= 5.0 V

10%)

16MB

Parameter Symbol

Typ

Max

Unit

Test

conditions

Sleep/
standby current

SP1

0.5

1.0

CMOS level (control signal
= V

0.2 V)

(In Memory card mode and
I/O card mode)

Sector read current I

CCR

(RMS)*

100

CMOS level (control signal
= V

0.2 V) during sector

read transfer

Sector write current I

CCW

(RMS)*

100

CMOS level (control signal
= V

0.2 V) during sector

write transfer

Read/Write
current peak

(Peak)

120 mA/50

CMOS level (control signal
= V

0.2 V)

Note: 1. Average value of the RMS operation current at the time of 128 sector transfer.

Reference

value.

DC Characteristics-4 (Ta = 0 to

C, V

= 3.3 V

5%)

16MB

Parameter Symbol

Typ

Max

Unit

Test

conditions

Sleep/
standby current

SP1

0.3

0.5

CMOS level (control signal
= V

0.2 V)

(In Memory card mode and
I/O card mode)

Sector read current I

CCR

(RMS)*

CMOS level (control signal
= V

0.2 V) during sector

read transfer

Sector write current I

CCW

(RMS)*

CMOS level (control signal
= V

0.2 V) during sector

write transfer

Read/Write
current peak

(Peak)

120 mA/50

CMOS level (control signal
= V

0.2 V)

Note: 1. Average value of the RMS operation current at the time of 128 sector transfer.

Reference

value.

HB28H016A8H

Rev. 1, Jan. 2003, page 53 of 65

AC Characteristics (Ta = 0 to

C, V

= 5.0 V

10%, V

= 3.3 V

5%)

Attribute Memory Read AC Characteristics

250

Parameter Symbol

Min

Typ

Max

Unit

Read cycle time

tCR

250

Address access time

ta(A)

250

-CE access time

ta(CE)

250

-OE access time

ta(OE)

125

Output disable time (-CE)

tdis(CE)

100

Output disable time (-OE)

tdis(OE)

100

Output enable time (-CE)

ten(CE)

Output enable time (-OE)

ten(OE)

Data valid time (A)

tv(A)

Address setup time

tsu(A)

Address hold time

th(A)

-CE setup time

su(CE) 0

-CE hold time

h(CE) 20

Attribute Memory Read Timing

h(A)

v(A)

dis(CE)

dis(OE)

h(CE)

Valid Output

su(CE)

su(A)

A0 to A10

-REG

-CE2/-CE1

-OE

D0 to D15

-WE, -IOWR, -IORD : High Fix

a(A)

a(CE)

a(OE)

en(OE)

en(CE)

HB28H016A8H

Rev. 1, Jan. 2003, page 54 of 65

Attribute Memory Write AC Characteristics

250

Parameter Symbol

Min

Typ

Max

Unit

Write cycle time

tCW

250

Write pulse time

tw(WE)

150

Address setup time

tsu(A)

Address setup time (-WE)

tsu(A-WEH)

180

-CE setup time (-WE)

tsu(CE-WEH) 180

Data setup time (-WE)

tsu(D-WEH)

Data hold time

th(D)

Write recover time

trec(WE)

Output disable time (-WE)

tdis(WE)

100

Output disable time (-OE)

tdis(OE)

100

Output enable time (-WE)

ten(WE)

Output enable time (-OE)

ten(OE)

Output enable setup time (-WE)

tsu(OE-WE)

Output enable hold time (-WE)

th(OE-WE)

-CE setup time

su(CE) 0

-CE hold time

h(CE) 20

Attribute Memory Write Timing

A0 to A10

-REG

-CE2/-CE1

-OE

D0 to D15(Din)

D0 to D15(Dout)

su(CE)

su(D-WEH)

nput Data

dis(WE)

dis(OE)

en(WE)

en(OE)

h(D)

h(OE-WE)

rec(WE)

h(CE)

su(OE-WE)

su(A)

-IOWR, -IORD : High Fix

-WE

su(CE-WEH)

su(A-WEH)

w(WE)

HB28H016A8H

Rev. 1, Jan. 2003, page 55 of 65

I/O Access Read AC Characteristics

Parameter Symbol

Min

Typ

Max

Unit

Data delay after -IORD

td(IORD)

100

Data hold following -IORD

th(IORD)

-IORD pulse width

tw(IORD)

165

Address setup before -IORD

tsuA(IORD)

Address hold following -IORD

thA(IORD)

-CE setup before -IORD

tsuCE(IORD)

-CE hold following -IORD

thCE(IORD)

-REG setup before -IORD

tsuREG(IORD)

-REG hold following -IORD

thREG(IORD)

-INPACK delay falling from -IORD

tdfINPACK(IORD) 0

45 ns

-INPACK delay rising from -IORD

tdrINPACK(IORD)

45 ns

-IOIS16 delay falling from address

tdfIOIS16(ADR)

35 ns

-IOIS16 delay rising from address

tdrIOIS16(ADR)

35 ns

I/O Access Read Timing

-REG

A0 to A10

-CE2/-CE1

-WE, -OE, -IOWR : High Fix

D0 to D15

-IORD

suREG(IORD)

suCE(IORD)

hA(IORD)

hREG(IORD)

hCE(IORD)

suA(IORD)

dfIOIS16(ADR)

dfINPACK(IORD)

drINPACK(IORD)

drIOIS16(ADR)

h(IORD)

Valid Output

d(IORD)

-INPACK

-IOIS16

w(IORD)

HB28H016A8H

Rev. 1, Jan. 2003, page 56 of 65

I/O Access Write AC Characteristics

Parameter Symbol

Min

Typ

Max

Unit

Data setup before -IOWR

tsu(IOWR)

Data hold following -IOWR

th(IOWR)

-IOWR pulse width

tw(IOWR)

165

Address setup before -IOWR

tsuA(IOWR)

Address hold following -IOWR

thA(IOWR)

-CE setup before -IOWR

tsuCE(IOWR)

-CE hold following -IOWR

thCE(IOWR)

-REG setup before -IOWR

tsuREG(IOWR)

-REG hold following -IOWR

thREG(IOWR)

-IOIS16 delay falling from address

tdfIOIS16(ADR)

35 ns

-IOIS16 delay rising from address

tdrIOIS16(ADR)

35 ns

I/O Access Write Timing

-WE, -OE, -IORD : High Fix

D0 to D15

-REG

A0 to A10

-CE2/-CE1

-IOWR

suREG(IOWR)

suCE(IOWR)

hA(IOWR)

hREG(IOWR)

hCE(IOWR)

suA(IOWR)

su(IOWR)

dfIOIS16(ADR)

drIOIS16(ADR)

h(IOWR)

-IOIS16

w(IOWR)

Data In

HB28H016A8H

Rev. 1, Jan. 2003, page 59 of 65

True IDE Mode Access Read AC Characteristics

Parameter Symbol

Min

Typ

Max

Unit

data delay after IORD

td(IORD)

100

data hold following IORD

th(IORD)

IORD width time

tw(IORD)

165

address setup before IORD

tsuA(IORD)

address hold following IORD

thA(IORD)

CE setup before IORD

tsuCE(IORD)

CE hold following IORD

thCE(IORD)

IOIS16 delay falling from address

tdfIOIS16(ADR)

35 ns

IOIS16 delay rising from address

tdrIOIS16(ADR)

35 ns

True IDE Mode Access Read Timing

-IORD

A0 to A2

-CE2/-CE1

-IOIS16

Valid Output

D0 to D15

-IOWR: High Fix, -OE: Low Fix, -WE: High Fix, A3 to A10: GND

suA(IORD)

suCE(IORD)

hA(IORD)

hCE(IORD)

h(IORD)

drlOIS16(ADR)

dflOIS16(ADR)

d(IORD)

w(IORD)

HB28H016A8H

Rev. 1, Jan. 2003, page 60 of 65

True IDE Mode Access Write AC Characteristics

Parameter Symbol

Min

Typ

Max

Unit

Data setup before IOWR

tsu(IOWR)

data hold following IOWR

th(IOWR)

IORD width time

tw(IOWR)

165

address setup before IOWR

tsuA(IOWR)

address hold following IOWR

thA(IOWR)

CE setup before IOWR

tsuCE(IOWR)

CE hold following IOWR

thCE(IOWR)

IOIS16 delay falling from address

tdfIOIS16(ADR)

35 ns

IOIS16 delay rising from address

tdrIOIS16(ADR)

35 ns

True IDE Mode Access Write Timing

-IOWR

A0 to A2

-CE2/-CE1

-IOIS16

Valid Output

D0 to D15

-IORD: High Fix, -OE: Low Fix, -WE: High Fix, A3 to A10: GND

suA(IOWR)

suCE(IOWR)

hA(IOWR)

hCE(IOWR)

h(IOWR)

drlOIS16(ADR)

dflOIS16(ADR)

su(IOWR)

w(IOWR)

HB28H016A8H

Rev. 1, Jan. 2003, page 61 of 65

Reset Characteristics (only Memory Card Mode or I/O Card Mode)

Hard Reset Characteristics

Parameter Symbol

Min

Typ

Max

Unit

Test

conditions

Note

Reset setup time

tsu(RESET)

-CE recover time

trec(VCC)

VCC rising up time

tpr

0.1

100

VCC falling down time

tpf

300

Reset pulse width

tw(RESET)

th(Hi-ZRESET)

ts(Hi-ZRESET)

Note: 1. As for this specification, it is fitted activity state when change. When reset signal is non-activity

state and a card is ready state, can shift to power supply cutoff sequence instantly.

Hard Reset Timing

-CE1, -CE2

10%

90%

10%

90%

h(Hi-ZRESET)

s(Hi-ZRESET)

su(RESET)

w(RESET)

Low

High-Z

rec(

cc)

RESET

HB28H016A8H

Rev. 1, Jan. 2003, page 62 of 65

Power on Reset Characteristics

All card status are reset automatically without Hard reset when V

voltage goes over about 2.3 V.

Parameter

Symbol

Min Typ Max Unit Test

conditions

-CE setup time

tsu(VCC)

VCC rising up time

tpr

0.1

100

Power on Reset Timing

su(

cc)

-CE1, -CE2

Attention for Card Use

In the reset or power off, all register informations are cleared.

All card status are cleared automatically when V

voltage turns below about 2.5V.

Notice that the card insertion/removal should not be executed while host is active, if the card is used in
True IDE mode.

After the card hard reset, soft reset, or power on reset, ATA reset, command applied the card cannot
access during +RDY/-BSY pin is "low" level. Flash card can't be operated in this case.

Card removal or power off should not be done during internal operations. When the removal or power off
occurrs during internal operation, there is a possibility that data are lost.

Before the card insertion V

can not be supplied to the card. After confirmation that -CD1, -CD2 pins are

inserted, supply V

to the card.

-OE must be kept at the V

level during power on reset in memory card mode and I/O card mode. -OE

must be kept constantly at the GND level in True IDE mode.

We recommend that a circuit to detect the level of power supply voltage be added to the host.

When a read error occurs, rewriting of the sector is recommended. This may avoid the error.

HB28H016A8H

Rev. 1, Jan. 2003, page 65 of 65

Disclaimer

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual
property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions
and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Sales Offices

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URL

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Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223

For further information write to:

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