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Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

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contained therein.

HD404369 Series

Rev. 6.0

Sept. 1998

Description

The HD404369 Series is a 4-bit HMCS400-Series microcomputer designed to increase program
productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input
capture timer, 32-kHz oscillator for clock, and four low-power dissipation modes.

The HD404369 Series includes nine chips: the HD404364, HD40A4364 with 4-kword ROM; the
HD404368, HD40A4368 with 8-kword ROM; the HD4043612, HD40A43612 with 12-kword ROM; the
HD404369, HD40A4369 with 16-kword ROM; the HD407A4369 with 16-kword PROM.

The HD40A4364, HD40A4368, HD40A43612, HD40A4369, and HD407A4369 are high speed versions
(minimum instruction cycle time: 0.47

s).

The HD407A4369 is a PROM version (ZTAT

microcomputer). A program can be written to the PROM

by a PROM writer, which can dramatically shorten system development periods and smooth the process
from debugging to mass production. (The ZTAT

version is 27256-compatible.)

Features

512-digit

4-bit RAM

54 I/O pins

One input-only pin

53 input/output pins: 8 pins are intermediate-voltage NMOS open drain with high-current pins (15

mA, max.)

On-chip A/D converter (8-bit

12-channel)

Low power voltage 2.7 V to 6.0 V

Three timers

One event counter input

One timer output

One input capture timer

Eight-bit clock-synchronous serial interface (1 channel)

Alarm output

HD404369 Series

Ordering Information

Type

Instruction Cycle Time

Product Name

Model Name

ROM (Words) Package

Mask ROM Standard version (f

OSC

= 5 MHz)

HD404364

HD404364S

4,096

DP-64S

HD404364F

FP-64B

HD404364H

FP-64A

HD404368

HD404368S

8,192

DP-64S

HD404368F

FP-64B

HD404368H

FP-64A

HD4043612

HD4043612S

12,288

DP-64S

HD4043612F

FP-64B

HD4043612H

FP-64A

HD404369

HD404369S

16,384

DP-64S

HD404369F

FP-64B

HD404369H

FP-64A

High speed versions

HD40A4364

HD40A4364S

4,096

DP-64S

OSC

= 8.5 MHz)

HD40A4364F

FP-64B

HD40A4364H

FP-64A

HD40A4368

HD40A4368S

8,192

DP-64S

HD40A4368F

FP-64B

HD40A4368H

FP-64A

HD40A43612

HD40A43612S

12,288

DP-64S

HD40A43612F

FP-64B

HD40A43612H

FP-64A

HD40A4369

HD40A4369S

16,384

DP-64S

HD40A4369F

FP-64B

HD40A4369H

FP-64A

ZTAT

OSC

= 8.5 MHz)

HD407A4369

HD407A4369S

16,384

DP-64S

HD407A4369F

FP-64B

HD407A4369H

FP-64A

HD404369 Series

Pin Arrangement

FP-64B

SCK

/SI

/SO

/TOC

TEST

RESET

OSC

GND

X1
X2

/AN

INT

/EVNB

/BUZZ

STOPC

/SI

/SO

/TOC

TEST

RESET

OSC

GND

X1
X2

/AN

SCK

/AN

INT

/EVNB

/BUZZ

STOPC

FP-64A

SCK

/SI

/SO

/TOC

TEST

RESET

OSC

GND

X1
X2

/AN

STOPC

/BUZZ

/EVNB

INT

DP-64S

HD404369 Series

Pin Description

Pin Number

Item

Symbol

DP-64S

FP-64B FP-64A I/O

Function

Power

Applies power voltage

Supply

GND

Connected to ground

Test

TEST

Cannot be used in user applications. Connect this
pin to GND.

Reset

RESET

Resets the MCU

Oscillator OSC

Input/output pin for the internal oscillator. Connect
these pins to the ceramic oscillator or crystal
oscillator, or OSC

to an external oscillator circuit.

OSC

Used with a 32.768-kHz crystal ocillator for clock
purposes

Port

3447

2841

2639

I/O

Input/output pins consisting of standard voltage
pins addressed individually by bits

One-bit standard-voltage input port pin

111,

2031,

4855

15,

1425,

4249,

5964

13,

1223,

4047,

5764

I/O

Four-bit input/output pins consisting of standard
voltage pins

5663

5057

4855

I/O

Four-bit input/output pins consisting of
intermediate voltage pins

Interrupt

INT

34, 35

28, 29

26, 27

Input pins for external interrupts

Stop clear

STOPC

Input pin for transition from stop mode to active
mode

Serial

SCK

I/O

Serial interface clock input/output pin

Interface

Serial interface receive data input pin

Serial interface transmit data output pin

Timer

TOC

Timer output pin

EVNB

Event count input pin

Alarm

BUZZ

Square waveform output pin

HD404369 Series

Pin Description (cont)

Pin Number

Item

Symbol

DP-64S

FP-64B FP-64A I/O

Function

A/D
converter

Power supply for the A/D converter. Connect this
pin as close as possible to the V

pin and at the

same voltage as V

. If the power supply voltage

to be used for the A/D converter is not equal to
V

, connect a 0.1-

F bypass capacitor between

the AV

and AV

pins. (However, this is not

necessary when the AV

pin is directly connected

to the V

pin.)

Ground for the A/D converter. Connect this pin as
close as possible to GND at the same voltage as
GND.

2031

1425

1223

Analog input pins for the A/D converter

HD404369 Series

Block Diagram

D port

R0 port

R1 port

R2 port

R3 port

R4 port

R5 port

R6 port

R7 port

R8 port

R9 port

RA port

ROM

(16,384

10 bits) (12,288

10 bits)

(4,096

10 bits)

(14 bits)

Instruction

decoder

(10 bits)

(4 bits)

(1 bit)

ALU

SPY

(4 bits)

SPX

(4 bits)

(2 bits)

RAM

(512

4 bits)

System control

Interrupt

control

Timer A

Timer B

Timer C

Serial

interface

A/D

converter

Buzzer

Internal data bus

Internal address bus

BUZZ

·
·
·

SCK

TOC

EVNB

INT

Data bus

Intermediate

voltage pin

Directional

signal line

GND

OSC

STOPC

TEST

RESET

(8,192

10 bits)

HD404369 Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.

Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000-$0FFF (HD404364, HD40A4364), $0000$1FFF (HD404368, HD40A4368),
$0000$2FFF (HD4043612, HD40A43612), $0000$3FFF (HD404369, HD40A4369, HD407A4369)):
The entire ROM area can be used for program coding.

$000F

$0FFF

$1000

$2FFF

$0010

$003F

$0040

Vector address

(16 words)

Zero-page subroutine

(64 words)

Program

(4,096 words)

Program

(8,192 words)

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007

$0008
$0009

$000A
$000B

$000C
$000D

$000E

$000F

JMPL instruction

(jump to

RESET

STOPC

routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B routine)

JMPL instruction

(jump to timer C routine)

JMPL instruction

(jump to A/D converter routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to serial routine)

Program

(12,288 words)

Program

(16,384 words)

For HD404369, HD40A4369,

HD407A4369

$1FFF

$2000

$3000

$3FFF

For HD404364, HD40A4364

For HD404368, HD40A4368

For HD4043612, HD40A43612

Note:

Since the ROM address areas between $0000$0FFF overlap, the user can determine how these
areas are to be used.

Figure 1 ROM Memory Map

RAM Memory Map

The MCU contains 512-digit

4 bit RAM areas. These RAM areas consist of a memory register area, a

data area, and a stack area. In addition, an interrupt control bits area, special function register area, and
register flag area are mapped onto the same RAM memory space labeled as a RAM-mapped register area.
The RAM memory map is shown in figure 2 and described below.

HD404369 Series

RAM Memory Map

A/D channel register (ACR)

$000

$040

$050

$003

$004

$005

$006

$007

$008
$009

$00A
$00B

$00C

$00D

$00E

$00F

$020
$023

$033

$034
$035
$036
$037

$00A

$00B

$00E

$00F

R/W

W
W

R/W

R/W
R/W

$3C0

RAM-mapped registers

Memory registers (MR)

Stack (64 digits)

Interrupt control bits area

Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)

Timer B (TRBL/TWBL)
(TRBU/TWBU)

Miscellaneous register (MIS)

Timer mode register C (TMC)
Timer C (TRCL/TWCL)
(TRCU/TWCU)

Port R0 DCR (DCR0)

Port R3 DCR (DCR3)

Not used

1. Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).

2. Undefined.

Timer read register B lower (TRBL)

Timer read register B upper (TRBU)

Timer read register C lower (TRCL)

Timer read register C upper (TRCU)

Timer write register B lower (TWBL)

Timer write register B upper (TWBU)

Timer write register C lower (TWCL)

Timer write register C upper (TWCU)

R: Read only
W: Write only
R/W: Read/write

$200

Notes:

$016

A/D data register lower (ADRL)

$017

$024
$025
$026
$027
$028

$018

$019

$01A

$3FF

A/D data register upper (ADRU)
A/D mode register 1 (AMR1)
A/D mode register 2 (AMR2)

W
W

Port mode register B (PMRB)
Port mode register C (PMRC)

Timer mode register B2 (TMB2)

System clock selection register 1 (SSR1)

Not used

Port R4 DCR (DCR4)
Port R5 DCR (DCR5)
Port R6 DCR (DCR6)
Port R7 DCR (DCR7)

W
W
W
W

W
W

W
W
W

$030

Not used

System clock selection register 2 (SSR2)

Not used

0000

0000
0000

Undefined

0000
0000

/0000

0000

0000
1000
0000

-000

0000

00-0
-000
000-

0000
0000
0000

-000

--00

Undefined

/0000

Undefined

Initial values

after reset

$03F

Data (432 digits)

0000

--00

Port D

, D

Port R1 DCR (DCR1)
Port R2 DCR (DCR2)

W
W

0000

0000
0000

W
W

Port R8 DCR (DCR8)
Port R9 DCR (DCR9)

DCR

(DCD0)

(DCD1)

(DCD2)

(DCD3)

$02C

$02D

$02E

$02F

$031
$032

$038
$039

Figure 2 RAM Memory Map

HD404369 Series

RAM-Mapped Register Area ($000$03F):

Interrupt Control Bits Area ($000$003)

This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

Special Function Register Area ($004$01F, $024$03F)

This area is used as mode registers and data registers for external interrupts, serial interface,
timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.

This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the
instructions are shown in figure 4.

Memory Register (MR) Area ($040$04F): Consisting of 16 addresses, this area (MR0MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.

Data Area ($050$1FF)

Stack Area ($3C0$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404369 Series

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

IMS

(IM of serial)

IFS

(IF of serial)

IMAD

(IM of A/D)

IFAD

(IF of A/D)

$000

$001

$002

$003

Interrupt control bits area

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

$020

$021

$022

$023

DTON

(Direct transfer

on flag)

ADSF

(A/D start flag)

WDON

(Watchdog

on flag)

LSON

(Low speed

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

IAOF

off flag)

IF:
IM:
IE:
SP:

Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

Not used

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

LSON

IAOF

ICSF
ICEF

RAME

RSP

WDON

ADSF

Not used

DTON

SEM/SEMD

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Allowed

Inhibited

Allowed

Not executed in active mode

Allowed

Used in subactive mode

Not executed

Inhibited

Note: WDON is reset by MCU reset or by

STOPC

enable for stop mode cancellation.

The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404369 Series

$000

$003

PMRA $004

SMR $005

SRL $006

SRU $007

TMA $008

TMB1 $009

TRBL/TWBL $00A

TRBU/TWBU $00B

MIS $00C

TMC $00D

TRCL/TWCL $00E

TRCU/TWCU $00F

ACR $016

ADRL $017

ADRU $018

AMR1$019

AMR2 $01A

$020

$023

PMRB $024

PMRC $025

TMB2 $026

SSR1 $027

SSR2 $028

DCD0 $02C

DCD1 $02D

DCD2 $02E

DCD3 $02F

DCR0 $030

DCR1 $031

DCR2 $032

DCR3 $033

DCR4 $034

DCR5 $035

DCR6 $036

DCR7 $037

DCR8 $038

DCR9 $039

$03F

Bit 3

Bit 2

Bit 1

Interrupt control bits area

/BUZZ

/TOC

/SO

Serial transmit clock speed selection

Serial data register (lower digit)

Serial data register (upper digit)

Clock source selection (timer A)

Clock source selection (timer B)

Timer B register (lower digit)

Timer B register (upper digit)

SO PMOS control Interrupt frame period selection

Clock source selection (timer C)

Timer C register (lower digit)

Timer C register (upper digit)

Analog channel selection

A/D data register (lower digit)

A/D data register (upper digit)

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port R0

DCR

Port R2

DCR

Port D

DCD

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R0

DCR

Port R2

DCR

Port D

DCD

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port D

DCD

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port D

DCD

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

1.
2.
3.
4.
5.
6.
7.
8.
9.

SCK

Bit 0

Timer-A/time-base
Auto-reload on/off
Pull-up MOS control
A/D conversion time
SO output level control in idle states
Serial clock source selection
Input capture selection
32-kHz oscillation stop
32-kHz oscillation division ratio

Notes:

/SI

Not used

/AN

R5/AN

R4/AN

Port R8

DCR

Port R9

DCR

Port R8

DCR

Port R9

DCR

Port R8

DCR

Port R9

DCR

Port R8

DCR

Port R9

DCR

STOPC

Buzzer output

/EVNB

INT

EVNB detection edge selection

Clock select

INT

Not used

Clock division ratio selection

Port R1

DCR

Port R3

DCR

Port R1

DCR

Port R3

DCR Port R3

DCR

Not used

Figure 5 Special Function Register Area

HD404369 Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter
Initial value: 0,
no R/W

Stack pointer
Initial value: $3FF, no R/W

Initial value: Undefined, R/W

Initial value: 1, no R/W

Figure 7 Registers and Flags

Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.

W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.

HD404369 Series

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction,
not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL,
CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or
bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read,
regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack
during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction.

Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.

The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.

Reset

The MCU is reset by inputting a low-level voltage to the

RESET pin. At power-on or when stop mode is

cancelled,

RESET must be low for at least one t

to enable the oscillator to stabilize. During operation,

RESET must be low for at least two instruction cycles.

Initial values after MCU reset are listed in table 1.

Interrupts

The MCU has 7 interrupt sources: two external signals (

INT

and

INT

), three timer/counters (timers A, B,

and C), serial interface, and A/D converter.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the
interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE)
and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in
table 3.

HD404369 Series

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.

The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.

HD404369 Series

Table 1

Initial Values After MCU Reset

Item

Abbr.

Initial Value Contents

Program counter

(PC)

$0000

Indicates program execution point from start
address of ROM area

Status flag

(ST)

Enables conditional branching

Stack pointer

(SP)

$3FF

Stack level 0

Interrupt
flags/mask

Interrupt enable flag

(IE)

Inhibits all interrupts

Interrupt request flag

(IF)

Indicates there is no interrupt request

Interrupt mask

(IM)

Prevents (masks) interrupt requests

I/O

Port data register

(PDR)

All bits 1

Enables output at level 1

Data control register

(DCD0-
DCD2)

All bits 0

Turns output buffer off (to high impedance)

(DCD3)

- - 00

(DCR0
DCR6,
DCR8,
DCR9)

All bits 0

(DCR7)

- 000

Port mode register A

(PMRA)

0000

Refer to description of port mode register A

Port mode register B
bits 20

(PMRB2
PMRB0)

000

Refer to description of port mode register B

Port mode register C

(PMRC)

00 - 0

Refer to description of port mode register C

Timer/count-
ers, serial
interface

Timer mode register A

(TMA)

0000

Refer to description of timer mode register A

Timer mode register B1 (TMB1)

0000

Refer to description of timer mode register B1

Timer mode register B2 (TMB2)

- 000

Refer to description of timer mode register B2

Timer mode register C

(TMC)

0000

Refer to description of timer mode register C

Serial mode register

(SMR)

0000

Refer to description of serial mode register

Prescaler S

(PSS)

$000

Prescaler W

(PSW)

$00

Timer counter A

(TCA)

$00

Timer counter B

(TCB)

$00

Timer counter C

(TCC)

$00

Timer write register B

(TWBU,
TWBL)

$X0

Timer write register C

(TWCU,
TWCL)

$X0

Octal counter

000

HD404369 Series

Item

Abbr.

Initial Value Contents

A/D

A/D mode register 1

(AMR1)

0000

Refer to description of A/D mode register

A/D mode register 2

(AMR2)

- 000

A/D channel register

(ACR)

0000

Refer to description of A/D channel register

A/D data register

(ADRL)

0000

Refer to description of A/D data register

(ADRU)

1000

Bit registers Low speed on flag

(LSON)

Refer to description of operati ng modes

Watchdog timer on flag (WDON) 0

Refer to description of timer C

A/D start flag

(ADSF)

Refer to description of A/D converter

off flag

(IAOF)

Refer to the description of A/D converter

Direct transfer on flag

(DTON)

Refer to description of operati ng modes

Input capture status
flag

(ICSF)

Refer to description of timer B

Input capture error flag

(ICEF)

Refer to description of timer B

Others

Miscellaneous register

(MIS)

0000

Refer to description of operati ng modes, I/O,
and serial interface

System clock select
register 1

(SSR1)

000 -

Refer to description of operati ng modes, and
oscillation circuits

System clock select
register 2

(SSR2)

- - 00

Refer to description of oscillation circuits

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. indicates that the bit does not exist.

HD404369 Series

Item

Abbr.

Status After Cancellation of Stop
Mode by

STOPC

Input

Status After all Other Types of
Reset

Carry flag

(CA)

Pre-stop-mode values are not
guaranteed; values must be
initialized by program

Pre-mcu-reset values are not
guaranteed; values must be
initialized by program

Accumulator

(A)

B register

(B)

W register

(W)

X/SPX register

(X/SPX)

Y/SPY register

(Y/SPY)

Serial data register

(SRL, SRU)

RAM

Pre-stop-mode values are retained

RAM enable flag

(RAME)

Port mode register B
bit 3

(PMRB3)

Pre-stop-mode values are retained

System clock select
register 1 bit 3

(SSR13)

Table 2

Vector Addresses and Interrupt Priorities

Reset/Interrupt

Priority

Vector Address

RESET

STOPC*

$0000

INT

$0002

INT

$0004

Timer A

$0006

Timer B

$0008

Timer C

$000A

A/D

$000C

Serial

$000E

Note:

The

STOPC

interrupt request is valid only in stop mode.

HD404369 Series

Table 3

Interrupt Processing and Activation Conditions

Interrupt Source

INT

Timer A

Timer B

Timer C

A/D

Serial

IF0

IM0

IF1

IM1

IFTA

IMTA

IFTB

IMTB

IFTC

IMTC

IFAD

IMAD

IFS

IMS

Note:

Bits marked

can be either 0 or 1. Their values have no effect on operation.

Instruction cycles

Instruction

execution

IE reset

Interrupt

acceptance

Execution of JMPL

instruction at vector address

Execution of

instruction at

start address

of interrupt

routine

Vector address

generation

Note:

The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.

Stacking

Figure 9 Interrupt Processing Sequence

HD404369 Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.

Table 4

Interrupt Enable Flag (IE: $000, Bit 0)

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

): Two external interrupt signals.

External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising
edge of signals input to

INT

and

INT

, as listed in table 5.

Table 5

External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0)

IF0, IF1

Interrupt Request

Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.

Table 6

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1)

IM0, IM1

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.

Table 7

Timer A Interrupt Request Flag (IFTA: $001, Bit 2)

IFTA

Interrupt Request

Yes

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as listed in table 8.

HD404369 Series

Table 8

Timer A Interrupt Mask (IMTA: 001, Bit 3)

IMTA

Interrupt Request

Enabled

Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.

Table 9

Timer B Interrupt Request Flag (IFTB: $002, Bit 0)

IFTB

Interrupt Request

Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer
B interrupt request flag, as listed in table 10.

Table 10

Timer B Interrupt Mask (IMTB: $002, Bit 1)

IMTB

Interrupt Request

Enabled

Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.

Table 11

Timer C Interrupt Request Flag (IFTC: $002, Bit 2)

IFTC

Interrupt Request

Yes

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as listed in table 12.

Table 12

Timer C Interrupt Mask (IMTC: $002, Bit 3)

IMTC

Interrupt Request

Enabled

Disabled (masked)

HD404369 Series

Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 13.

Table 13

Serial Interrupt Request Flag (IFS: $003, Bit 2)

IFS

Interrupt Request

Yes

Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 14.

Table 14

Serial Interrupt Mask (IMS: $003, Bit 3)

Mask IMS

Interrupt Request

Enabled

Disabled (masked)

A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in
table 15.

Table 15

A/D Interrupt Request Flag (IFAD: $003, Bit 0)

IFAD

Interrupt Request

Yes

A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 16.

Table 16

A/D Interrupt Mask (IMAD: $003, Bit 1)

IMAD

Interrupt Request

Enabled

Disabled (masked)

HD404369 Series

Operating Modes

The MCU has five operating modes as shown in table 17. The operations in each mode are listed in tables
18 and 19. Transitions between operating modes are shown in figure 11.

Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC

and OSC

Table 17

Operating Modes and Clock Status

Mode Name

Active

Standby

Stop

Watch

Subactive

Activation method

RESET

cancellation,

interrupt

STOPC

cancellation in stop
mode, STOP/SBY
instruction in
subactive mode
(when direct transfer
is selected)

SBY
instruction

STOP
instruction when
TMA3 = 0

STOP
instruction when
TMA3 = 1

INT

or timer A

interrupt request
from watch
mode

Status System

oscillator

Stopped

Subsystem
oscillator

Cancellation
method

RESET

input,

STOP/SBY instruction

RESET

input,
interrupt
request

RESET

input,

STOPC

input in

stop mode

RESET

input,

INT

or timer A

interrupt request

RESET

input,

STOP/SBY
instruction

Notes: OP implies in operation

1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select

2. Subactive mode is an optional function; specify it on the function option list.

HD404369 Series

Reset by

RESET

input or

by watchdog timer

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Stop
Oscillate
f

SUB

OSC

CPU

CLK

PER

Stop
Stop
Stop
Stop
Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

Standby mode

Stop mode

(TMA3 = 0, SSR13 = 1)

Watch mode

Subactive
mode

(TMA3 = 1)

(TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

SBY

Interrupt

SBY

Interrupt

STOP

INT

timer A

STOP

1. Interrupt source
2. STOP/SBY (DTON = 1, LSON = 0)
3. STOP/SBY (DTON = 0, LSON = 0)
4. STOP/SBY (DTON = Don't care, LSON = 1)

OSC

cyc

SUB

LSON:
DTON:

Main oscillation frequency
Suboscillation frequency
for time-base
f

OSC

/4, f

OSC

/8, f

OSC

/16, f

OSC

/32

/8 or f

(software selectable)
f

System clock
Clock for time-base
Clock for other
peripheral functions
Low speed on flag
Direct transfer on flag

Active
mode

Notes:

CPU

CLK

PER

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
Stop
Stop

(TMA3 = 0, SSR13 = 0)

RESET1

RESET2

RAME = 0

RAME = 1

INT

timer A

(TMA3 = 0)

STOP

STOPC

STOP

(software selectable)
f

Figure 11 MCU Status Transitions

HD404369 Series

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.

The MCU enters standby mode when the SBY instruction is executed in active mode.

Standby mode is terminated by a

RESET input or an interrupt request. If it is terminated by RESET input,

the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation
in standby mode is shown in figure 12.

HD404369 Series

Standby

Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop

Yes

(SBY
only)

Watch

Oscillator: Stop
Suboscillator: Active
Peripheral clocks: Stop
All other clocks: Stop

Restart

processor clocks

Reset MCU

Execute

next instruction

Accept interrupt

Restart

processor clocks

Yes

IF = 1,

IM = 0, and

IE = 1?

RESET

= 0?

IF0 ·

IM0

= 1?

IF1 ·

IM1

= 1?

IFTA ·

IMTA

= 1?

IFTB ·

IMTB

= 1?

IFTC ·

IMTC

= 1?

IFAD ·

IMAD

= 1?

Yes

IFS ·

IMS

= 1?

Stop

Oscillator: Stop
Suboscillator: Active/Stop
Peripheral clocks: Stop
All other clocks: Stop

RESET

= 0?

STOPC

= 0?

RAME = 1

RAME = 0

Yes

Execute

next instruction

(SBY
only)

Figure 12 MCU Operation Flowchart

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC

and OSC

oscillator stops. For the X1 and X2

oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (SSR1:
$027; operating: SSR13 = 0, stop: SSR13 = 1) (figure 23). The MCU enters stop mode if the STOP
instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3
= 0) (figure 37).

Stop mode is terminated by a

RESET input or a STOPC input as shown in figure 13. RESET or STOPC

must be applied for at least one t

to stabilize oscillation (refer to the AC Characteristics section). When

the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,

HD404369 Series

but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.

Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operates, but
other function operations stop. Therefore, the power dissipation in this mode is the second least to stop
mode, and this mode is convenient when only clock display is used. In this mode, the OSC

and OSC

oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP
instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in
subactive mode.

Watch mode is terminated by a

RESET input or a timer-A/INT

interrupt request. For details of

RESET

input, refer to the Stop Mode section. When terminated by a timer-A/

INT

interrupt request, the MCU

enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated,
the time required to enter active mode is t

for a timer A interrupt, and T

(where T + t

< T

< 2T + t

)

for an

INT

interrupt, as shown in figures 14 and 15.

Operation during mode transition is the same as that at standby mode cancellation (figure 12).

Stop mode

Oscillator

Internal

clock

STOP instruction execution

res

(stabilization period)

res

RESET

STOPC

Figure 13 Timing of Stop Mode Cancellation

Subactive Mode: The OSC

and OSC

oscillator stops and the MCU operates with a clock generated by

the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because the
operating clock is slow, the power dissipation becomes low, next to watch mode.

The CPU instruction execution speed can be selected as 244

s or 122

s by setting bit 2 (SSR12) of the

system clock select register 1 (SSR1: $027). Note that the SSR12 value must be changed in active mode. If
the value is changed in subactive mode, the MCU may malfunction.

When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).

Interrupt Frame: In watch and subactive modes, ø

CLK

is applied to timer A and the

INT

circuit. Prescaler

W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three
interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 15).

In watch and subactive modes, the timer-A/

INT

interrupt is generated synchronously with the interrupt

frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the

INT

signal is input asynchronously with the interrupt

HD404369 Series

frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt
strobe timing.

T:
t :

Interrupt frame length
Oscillation stabilization period

(During the transition
from watch mode to
active mode only)

Interrupt strobe

INT

Interrupt request
generation

Active mode

Watch mode

Active mode

Oscillation
stabilization period

T + t

2T + t

Figure 14 Interrupt Frame

Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on
flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described
below:

Set LSON to 0 and DTON to 1 in subactive mode.

Execute the STOP or SBY instruction.

The MCU automatically enters active mode from subactive mode after waiting for the MCU internal
processing time and oscillation stabilization time (figure 16).

Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active

mode.

2. The transition time (T

) from subactive mode to active mode:

< T

< T + t

HD404369 Series

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1

MIS0

0.24414 ms

0.12207 ms

0.24414 ms

7.8125 ms

62.5 ms

Oscillation Circuit Conditions

External clock input

Ceramic oscillator

15.625 ms

125 ms

Not used

Notes: 1.

The values of T and t

are applied when a 32.768-kHz crystal oscillator is used.

The value is applied only when direct transfer operation is used.

Buffer control.

Refer to figure 34.

MIS3

MIS2

Crystal oscillator

Figure 15 Miscellaneous Register (MIS)

Subactive mode

Interrupt strobe

Direct transfer
completion timing

MCU internal
processing period

Oscillation
stabilization
time

Active mode

T:
t

STOP/SBY instruction execution

(Set LSON = 0, DTON = 1)

Interrupt frame length
Oscillation stabilization period
Transition time

Figure 16 Direct Transition Timing

Stop Mode Cancellation by

STOPC: The MCU enters active mode from stop mode by inputting STOPC

as well as by

R E SE T . In either case, the MCU starts instruction execution from the starting address

(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by

STOPC and by R E SE T . When stop mode is cancelled by R ESET, RAME = 0;

when cancelled by

STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop

mode;

STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop

mode has been cancelled by

STOPC (for example, when the RAM contents before entering stop mode is

HD404369 Series

used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the
beginning of the program.

MCU Operation Sequence: The MCU operates in the sequence shown in figures 17 to 19. It is reset by an
asynchronous

RESET input, regardless of its status.

The low-power mode operation sequence is shown in figure 19. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a
STOP/SBYinstruction, make sure all interrupt flags are cleared or all interrupts are masked.

Power on

RESET

= 0 ?

RAME = 0

Reset MCU

MCU

operation

cycle

Yes

Figure 17 MCU Operating Sequence (Power On)

HD404369 Series

Low-power mode

operation cycle

IF = 1 and

IM = 0?

Hardware NOP

execution

PC Next

Iocation

MCU operation

cycle

Standby/watch

mode

IF = 1 and

IM = 0?

Hardware NOP

execution

PC Next

Iocation

Instruction

execution

Stop mode

Yes

For IF and IM operation, refer to figure 12.

STOPC

= 0?

RAME = 1

Reset MCU

Yes

Figure 19 MCU Operating Sequence (Low-Power Mode Operation)

Note:

When the MCU is in watch mode or subactive mode, if the high level period before the falling edge
of

INT

is shorter than the interrupt frame,

INT

is not detected. Also, if the low level period after

the falling edge of

INT

is shorter than the interrupt frame,

INT

is not detected. Edge detection is

shown in figure 20. The level of the

INT

signal is sampled by a sampling clock. When this

sampled value changes to low from high, a falling edge is detected. In figure 21, the level of the
INT

signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also

low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point
A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in
watch mode or subactive mode, keep the high level and low level period of

INT

longer than the

interrupt frame

HD404369 Series

Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 22. As shown in table 20, a ceramic
oscillator or crystal oscillator can be connected to OSC

and OSC

, and a 32.768-kHz oscillator can be

connected to X1 and X2. The system oscillator can also be operated by an external clock.

Registers for Oscillator Circuit Operation

System Clock Selection Register 1 (SSR1: $027): Four bit write-only register which sets the subsystem
clock frequency (f

SUB

) division ratio, and sets the subsystem clock oscillation in stop mode. Bit 1 (SSR11)

of system clock select register 1 must be set according to the frequency of the oscillator connected to OSC

and OSC

(figure 23).

Bit 1 (SSR11) and bit 2 (SSR12) are initialized to 0 on reset and in stop mode. Bit 3 (SSR13) is initialized
to 0 only on reset.

OSC

System

oscillator

Sub-

system

oscillator

1/4, 1/8,

1/16 or

1/32

division

circuit

Timing

generator

circuit

System

clock

selection

CPU with ROM,

RAM, registers,

flags, and I/O

Peripheral

function

interrupt

Time-base

interrupt

Time-base

clock

selection

1/8 or 1/4

division

circuit

Timing

generator

circuit

Timing

generator

circuit

1/8

division

circuit

SUB

subcyc

LSON

TMA3

cyc

OSC

Wcyc

CPU

PER

CLK

Notes:

1/4, 1/8, 1/16 or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock
select register 2 (SSR2: $028).
1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1
(SSR1: $027).

Figure 22 Clock Generation Circuit

HD404369 Series

Bit

Initial value

Read/Write

Bit name

SSR13

SSR12

Not used

SSR11

System clock selection register 1 (SSR1: $027)

System Clock Selection

0.4 to 1.0 MHz

1.6 to 5.0 MHz (HD404369 Series)

1.6 to 8.5 MHz (HD40A4369 Series)

SSR11

SSR12

Ratio Selection

SUB

= f

SUB

= f

32-kHz Oscillation Division

SSR13

32-kHz Oscillation Stop

Oscillation operates in stop mode

Oscillation stops in stop mode

Notes:

SSR13 will only be cleared to 0 by a

RESET

input. A

STOPC

input during stop mode will

not clear SSR13. Also note that SSR13 will not be cleared upon transition to stop mode.

If f

OSC

= 0.4 to 1.0 MHz, SSR11 must be set 0; if f

OSC

= 1.6 to 8.5 MHz, SSR11 must be set to

1. Do not use f

OSC

= 1.0 to 1.6 MHz with 32-kHz oscillation.

Figure 23 System Clock Selection Register 1 (SSR1)

System Clock Selection Register 2 (SSR2: $028): Four bit write-only register which is used to select the
system clock divisor (figure 24).

The division ratio of the system clock can be selected as 1/4, 1/8, 1/16, or 1/32 by setting bits 0 and 1
(SSR20, SSR21) of system clock select register 2 (SSR2).

The values of SSR20 and SSR21 are valid after the MCU enters watch mode. The system clock must be
stopped when the division ratio is to be changed.

There are two methods for changing the system clock divisor, as follows.

In active mode, set the divisor by writing to SSR20 and SSR21. At this point, the prior divisor setting
will remain in effect. Now, switch to watch mode, and then return to active mode. When active mode
resumes, the system clock divisor will have switched to the new value.

In subactive mode, set the divisor by writing to SSR20 and SSR21. Then return to active mode through
watch mode. When active mode resumes, the system clock divisor will have switched to the new value.
(The change will also take effect for direct transition to active mode.)

HD404369 Series

Table 20

Oscillator Circuit Examples

Circut Configuration

Circut Constants

External clock
operation

External
oscillator

OSC

Open

OSC

Ceramic oscillator
(OSC

, OSC

)

OSC

Ceramic

GND

Ceramic oscillator: CSA4.00MG (Murata)

= 1 M

20%

= C

= 30 pF

20%

Crystal oscillator
(OSC

, OSC

)

OSC

Crystal

GND

OSC

= 1 M

20%

= C

= 10 to 22 pF

20%

Crystal: Equivalent to circuit shown below

= 7 pF max.

= 100

max.

Crystal oscillator
(X1, X2)

Crystal

GND

Crystal: 32.768 kHz: MX38T

(Nippon Denpa)

= C

= 20 pF

20%

= 14 k

= 1.5 pF

Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray

capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.

2. Wiring among OSC

, OSC

, X1, X2 and elements should be as short as possible, and must not

cross other wiring (see figure 25).

3. When a 32.768-kHz crystal oscillator is not used, fix pin X1 to GND and leave pin X2 open.

HD404369 Series

Input/Output

The MCU has 53 input/output pins (D

, R0R9) and an input pin (RA

). The features are described

below.

Eight pins (R1R2) are high-current (15 mA max) input/output with intermediate voltage NMOS open
drain pins.

The D

, R0, R3R5 input/output pins are multiplexed with peripheral function pins such as for the

timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port
setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output
selection are automatically switched according to the setting.

Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.

Peripheral function output pins are CMOS output pins. Only the R0

/SO pin can be set to NMOS open-

drain output by software.

In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.

Each input/output pin except for R1 and R2 has a built-in pull-up MOS, which can be individually
turned on or off by software.

I/O buffer configuration is shown in figure 26, programmable I/O circuits are listed in table 21, and I/O pin
circuit types are shown in table 22.

HD404369 Series

I/O Pin Type

Circuit

Pins

Peripheral
function pins

Input/output
pins

Pull-up control signal

Output data

Input data

HLT

MIS3

SCK

Output pins

Pull-up control signal

PMOS control

signal

Output data

HLT

MIS3

MIS2

Pull-up control signal

Output data

HLT

MIS3

TOC, BUZZ

Input pins

Input data

HLT

MIS3

SI,

INT

EVNB,

STOPC

PDR

SI,

INT

EVNB,

STOPC

HLT

MIS3

A/D input

PDR

Input control signal

Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The

HLT

signal goes low, and input/output pins enter the high-impedance state.

2. The

HLT

signal is 1 in active, standby, watch, and subactive modes.

HD404369 Series

Evaluation Chip Set and

ZTAT

/Mask ROM Product Differences

As shown in figure 27, the NMOS intermediate-voltage open drain pin circuit in the evaluation chip set
differs from that used in the ZTAT

microcomputer and built-in mask ROM microcomputer products.

Please note that although these outputs in the ZTAT

microcomputer and built-in mask ROM

microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs
cannot be set to high impedance in the evaluation chip set.

Table 23

Program Control of High Impedance States

Register

Set Value

DCR

PDR

Notes:

An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation.

This applies to the ZTAT

and built-in mask ROM microcomputer NMOS open drain pins.

HLT

MIS3

DCR

PDR

CPU input

Input control signal

(a) Evaluation Chip Set Circuit Structure

Input control signal

(b) ZTAT and Built-In Mask ROM Microcomputer Circuit Structure

HLT

DCR

PDR

CPU input

Figure 27 NMOS Intermediate-Voltage Open Drain Pin Circuits

HD404369 Series

D Port (D

): Consist of 14 input/output pins addressed by one bit.

Pins D

are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. All pins D

are tested by the TD and

TDD instructions.

The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0DCD3:
$02C$02F) that are mapped to memory addresses (figure 28).

Pins D

, D

are multiplexed with peripheral function pins

INT

, EVNB, and

STOPC, respectively.

The peripheral function modes of these pins are selected by bits 03 (PMRB0 PMRB3) of port mode
register B (PMRB: $024) (figure 29).

Pin D

is multiplexed with peripheral function pin BUZZ. The peripheral function mode of this pin is

selected by bit 3 (PMRA3) of port mode register A (PMRA: $004) (figure 30).

R Ports (R0

R9

): 39 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR

and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the
port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled
by R-port data control registers (DCR0DCR9: $030$039) that are mapped to memory addresses (figure
28).

Pin R0

is multiplexed with peripheral function pin

SCK. The peripheral function mode of this pin is

selected by bit 3 (SMR3) of serial mode register (SMR: $005) (figure 31).

Pins R0

are multiplexed with peripheral pins SI, SO and TOC, respectively. The peripheral function

modes of these pins are selected by bits 02 (PMRA0PMRA2) of port mode register A (PMRA: $004), as
shown in figure 30.

Port R3 is multiplexed with peripheral function pins AN

, respectively. The peripheral function

modes of these pins can be selected by individual pins, by setting A/D mode register 1 (AMR1: $019)
(figure 32).

Ports R4 and R5 are multiplexed with peripheral function pins AN

, respectively. The peripheral

function modes of these pins can be selected in 4-pin units by setting bits 1 and 2 (AMR21, AMR22) of
A/D mode register 2 (AMR2: $01A) (figure 33).

Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous
register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data
register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 21 and figure 34).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V

to prevent LSI malfunctions due to noise. These pins must either be pulled up to V

their pull-up MOS transistors or by resistors of about 100 k

HD404369 Series

Bit

Initial value

Read/Write

Bit name

DCD0 to DCD3, DCR0 to DCR9

Data control register

(DCD0 to 3: $02C to $02F)
(DCR0 to 9: $030 to $039)

Correspondence between ports and DCD/DCR bits

DCD0

DCD1

DCD2

DCD3

DCR0

DCR1

DCR2

DCR3

DCR4

DCR5

DCR6

DCR7

DCR8

DCR9

Off (high-impedance)

Bits 0 to 3

CMOS Buffer On/Off Selection

Register Name

Not used

Bit 3

Not used

Bit 2

Bit 1

Bit 0

DCD03
DCD23,
DCR03
DCR63,
DCR83
DCR93

DCD02
DCD22,
DCR02
DCR92

DCD01
DCD31,
DCR01
DCR91

DCD00
DCD30,
DCR00
DCR90

Figure 28 Data Control Registers (DCD, DCR)

HD404369 Series

Bit

Initial value

Read/Write

Bit name

PMRB3

PMRB2

PMRB0

PMRB1

PMRB0

INT

Mode Selection

INT

Port mode register B (PMRB: $024)

PMRB1

INT

Mode Selection

INT

PMRB2

/EVNB Mode Selection

EVNB

PMRB3

STOPC

Mode Selection

STOPC

Note:

PMRB3 is reset to 0 only by

RESET

input. When

STOPC

is input in stop mode, PMRB3 is not

reset but retains its value.

Figure 29 Port Mode Register B (PMRB)

Bit

Initial value

Read/Write

Bit name

PMRA3

PMRA2

PMRA0

PMRA1

PMRA0

/SO Mode Selection

Port mode register A (PMRA: $004)

PMRA1

/SI Mode Selection

PMRA2

/TOC Mode Selection

TOC

PMRA3

/BUZZ Mode Selection

BUZZ

Figure 30 Port Mode Register A (PMRA)

HD404369 Series

Bit

Initial value

Read/Write

Bit name

SMR3

SMR2

SMR0

SMR1

Serial mode register (SMR: $005)

SMR2

SMR0

SMR1

SMR3

SCK

Mode Selection

SCK

Transmit clock selection.
Refer to figure 62 in the
serial interface section.

Figure 31 Serial Mode Register (SMR)

Bit

Initial value

Read/Write

Bit name

AMR13

AMR12

AMR10

AMR11

AMR10

A/D mode register 1 (AMR1: $019)

AMR11

AMR12

/AN

Mode Selection

AMR13

/AN

Mode Selection

/AN

Mode Selection

/AN

Mode Selection

Figure 32 A/D Mode Register 1 (AMR1)

HD404369 Series

Bit

Initial value

Read/Write

Bit name

Not used

AMR22

AMR20

AMR21

AMR20

67 t

cyc

A/D mode register 2 (AMR2: $01A)

AMR21

AMR22

R5/AN

Pin Selection

Conversion Time

34 t

cyc

R4/AN

Pin Selection

Figure 33 A/D Mode Register 2 (AMR2)

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

MIS2

CMOS Buffer
On/Off Selection
for Pin R0

/SO

Miscellaneous register (MIS: $00C)

PMOS active

PMOS off

Refer to figure 15 in the
operation modes section.

selection.

MIS3

Pull-Up MOS
On/Off Selection

Pull-up MOS off

Pull-up MOS on
(refer to table 21)

MIS1

MIS0

Figure 34 Miscellaneous Register (MIS)

HD404369 Series

Prescalers

The MCU has the following two prescalers, S and W.

The prescaler operating conditions are listed in table 24, and the prescaler output supply is shown in figure
35. The timer AC input clocks except external events and the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.

Prescaler Operation

Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and
at MCU reset.

Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by
eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset
by software.

Table 24

Prescaler Operating Conditions

Prescaler

Input Clock

Reset Conditions

Stop Conditions

Prescaler S

System clock
(in active and standby
mode), subsystem clock
(in subactive mode)

MCU reset

MCU reset, stop mode,
watch mode

Prescaler W

32-kHz crystal oscillation

MCU reset, software

MCU reset, stop mode

Subsystem

clock

Prescaler W

Timer A

Timer B

Timer C

Serial

Alarm output

circuit

System

clock

Prescaler S

Clock

selector

/4 or f

Figure 35 Prescaler Output Supply

HD404369 Series

Timers

The MCU has four timer/counters (A to C).

Timer A: Free-running timer

Timer B: Multifunction timer

Timer C: Multifunction timer

Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunction timers, whose functions are
listed in table 25. The operating modes are selected by software.

Timer A

Timer A Functions: Timer A has the following functions.

Free-running timer

Clock time-base

The block diagram of timer A is shown in figure 36.

Timer A Operations:

Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).

Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.

Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode
register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates
interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and
timer A can be reset to $00 by software.

Registers for Timer A Operation: Timer A operating modes are set by the following registers.

Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode
and input clock source as shown in figure 37.

HD404369 Series

Table 25

Timer Functions

Functions

Timer A

Timer B

Timer C

Clock source

Prescaler S

Available

Prescaler W

Available

External event

Available

Timer functions

Free-running

Available

Time-base

Available

Event counter

Available

Reload

Available

Watchdog

Available

Input capture

Available

Timer output

PWM

Available

Note:

-- implies not available.

1/4

1/2

32.768-kHz
oscillator

System
clock

Prescaler W

(PSW)

Selector

Prescaler S (PSS)

Selector

Internal data bus

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

2 f

1/2 t

Wcyc

PER

128

512

1024

2048

÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷

÷ ÷ ÷ ÷

Figure 36 Timer A Block Diagram

HD404369 Series

Bit

Initial value

Read/Write

Bit name

TMA3

TMA2

TMA0

TMA1

Timer mode register A (TMA: $008)

PSS

PSW

Operating Mode

Timer A mode

TMA3

TMA1

TMA2

TMA0

Source
Prescaler

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

Input Clock
Frequency

32t

Wcyc

16t

Wcyc

1/2t

Wcyc

Time-base
mode

Inhibited

PSW and TCA reset

Notes: 1.

2.
3.

Wcyc

= 244.14

s (when a 32.768-kHz crystal oscillator is used)

Timer counter overflow output period (seconds) = input clock period (seconds)

256.

The division ratio must not be modified during time-base mode operation, otherwise an overflow
cycle error will occur.

Don't

care

Figure 37 Timer Mode Register A (TMA)

HD404369 Series

Timer B

Timer B Functions: Timer B has the following functions.

Free-running/reload timer

External event counter

Input capture timer

The block diagram for each operation mode of timer B is shown in figures 38 and 39.

Timer B Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).

Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer B is used as an external event counter by selecting the external
event input as an input clock source. In this case, pin D

/EVNB must be set to EVNB by port mode

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling
edges detection is selected, the time between the falling edge and rising edge of input signals must be
2t

cyc

or longer.

Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026).
The other operation is basically the same as the free-running/reload timer operation.

Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVNB.

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by timer mode register 2 (TMB2: $026).

When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL:
$00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF
is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture
error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0.

HD404369 Series

Timer counter B

(TCB)

Internal data bus

128

512

2048

Timer mode

(TMB2)

EVNB

Selector

System

clock

PER

Prescaler S (PSS)

Edge

detector

Edge detection control signal

Timer mode

(TMB1)

Clock

Input capture

timer control

signal

Timer read

(TRBL)

Interrupt request

flag of timer B

(IFTB)

Timer read

(TRBU)

Overflow

Read

signal

Input capture

status flag

(ICSF)

Input capture

error flag

(ICEF)

Error

controller

Figure 39 Timer B Input Capture Operation Block Diagram

Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.

Timer mode register B1 (TMB1: $009)

Timer mode register B2 (TMB2: $026)

Timer write register B (TWBL: $00A, TWBU: $00B)

Timer read register B (TRBL: $00A, TRBU: $00B)

Port mode register B (PMRB: $024)

HD404369 Series

Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 40. It is reset to $0
by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.

When selecting the input capture timer operation, select the internal clock as the input clock source.

Bit

Initial value

Read/Write

Bit name

TMB13

TMB12

TMB10

TMB11

Timer mode register B1 (TMB1: $009)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMB12

TMB10

TMB11

Input Clock Period and Input
Clock Source

/EVNB (external event input)

TMB13

Free-Running/Reload
Timer Selection

Free-running timer

Reload timer

Figure 40 Timer Mode Register B1 (TMB1)

Timer mode register B2 (TMB2: $026): Three-bit write-only register that selects the detection edge of
signals input to pin EVNB and input capture operation as shown in figure 41. It is reset to $0 by MCU
reset.

Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value is invalid (figures 42 and 43).

Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.

HD404369 Series

Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 44 and 45).

The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained,
and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading
TRBL, the count of timer B when TRBU is read can be obtained.

When the input capture timer operation is selected and if the count of timer B is read after a trigger is
input, either the lower or upper digit can be read first.

Port mode register B (PMRB: $024): Write-only register that selects D

/EVNB pin function as shown in

figure 46. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

Not used

TMB22

TMB20

TMB21

Timer mode register B2 (TMB2: $026)

TMB21

TMB20

EVNB Edge Detection Selection

No detection

Falling edge detection

Rising edge detection

Rising and falling edge detection

TMB22

Free-Running/Reload and Input Capture Selection

Free-running/reload

Input capture

Figure 41 Timer Mode Register B2 (TMB2)

Bit

Initial value

Read/Write

Bit name

TWBL3

TWBL2

TWBL0

TWBL1

Timer write register B (lower digit) (TWBL: $00A)

Figure 42 Timer Write Register B Lower Digit (TWBL)

HD404369 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWBU3

Undefined

TWBU2

Undefined

TWBU0

Undefined

TWBU1

Timer write register B (upper digit) (TWBU: $00B)

Figure 43 Timer Write Register B Upper Digit (TWBU)

Bit

Initial value

Read/Write

Bit name

Undefined

TRBL3

Undefined

TRBL2

Undefined

TRBL0

Undefined

TRBL1

Timer read register B (lower digit) (TRBL: $00A)

Figure 44 Timer Read Register B Lower Digit (TRBL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRBU3

Undefined

TRBU2

Undefined

TRBU0

Undefined

TRBU1

Timer read register B (upper digit) (TRBU: $00B)

Figure 45 Timer Read Register B Upper Digit (TRBU)

HD404369 Series

Timer C

Timer C Functions: Timer C has the following functions.

Free-running/reload timer

Watchdog timer

Timer output operation (PWM output)

The block diagram of timer C is shown in figure 47.

Timer counter C

(TCC)

128

512

1024

2048

Port mode

Selector

System

clock

PER

Prescaler S (PSS)

Timer write

(TWCL)

Timer mode

Timer write

(TWCU)

Clock

Free-running
timer control
signal

Timer read

(TRCL)

Interrupt request

flag of timer C

(IFTC)

Timer read register C upper (TRCU)

Overflow

TOC

Timer

output

control

signal

Watchdog timer

controller

Watchdog on

flag (WDON)

System reset signal

Internal data bus

Timer output

control logic

Figure 47 Timer C Block Diagram

HD404369 Series

Timer C Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C (TMC: $00D).

Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. The watchdog timer operation flowchart is
shown in figure 48. Program run can be controlled by initializing timer C by software before it reaches
$FF.

Timer output operation: The PWM output modes can be selected for timer C by setting port mode
register A (PMRA: $004).

By selecting the timer output mode, pin R0

/TOC is set to TOC. The output from TOC is reset low by

MCU reset.

PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C (TMC:
$00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in
figure 49.

$FF + 1

$00

Timer C

count value

Overflow

Time

CPU

operation

Normal

operation

Timer C

clear

Normal

operation

Timer C

clear

Program
runaway

Normal

operation

Reset

Figure 48 Watchdog Timer Operation Flowchart

HD404369 Series

T (N + 1)

T 256

T (256 N)

TMC3 = 0
(free-running
timer)

TMC3 = 1
(reload timer)

Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are

determined by timer mode register C.)

N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.)

Figure 49 PWM Output Waveform

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.

Timer mode register C (TMC: $00D)

Port mode register A (PMRA: $004)

Timer write register C (TWCL: $00E, TWCU: $00F)

Timer read register C (TRCL: $00E, TRCU: $00F)

Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 50. It is reset to $0
by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C write instruction. Setting timer C's initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.

HD404369 Series

Bit

Initial value

Read/Write

Bit name

TMC3

TMC2

TMC0

TMC1

Timer mode register C (TMC: $00D)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMC2

TMC0

TMC1

Input Clock Period

TMC3

Free-Running/Reload
Timer Selection

Free-running timer

Reload timer

1024t

cyc

Figure 50 Timer Mode Register C (TMC)

Port mode register A (PMRA: $004): Write-only register that selects R0

/TOC pin function as shown in

figure 51. It is reset to $0 by MCU reset.

Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit
(TWCL) and the upper digit (TWCU) as shown in figures 52 and 53. The operation of timer write
register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).

Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit
(TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit (figures 54 and 55).
The operation of timer read register C is basically the same as that of timer read register B (TRBL:
$00A, TRBU: $00B).

HD404369 Series

Bit

Initial value

Read/Write

Bit name

PMRA3

PMRA2

PMRA0

PMRA1

PMRA0

/SO Mode Selection

Port mode register A (PMRA: $004)

PMRA1

/SI Mode Selection

PMRA2

/TOC Mode Selection

TOC

PMRA3

/BUZZ Mode Selection

BUZZ

Figure 51 Port Mode Register A (PMRA)

Bit

Initial value

Read/Write

Bit name

TWCL3

TWCL2

TWCL0

TWCL1

Timer write register C (lower digit) (TWCL: $00E)

Figure 52 Timer Write Register C Lower Digit (TWCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWCU3

Undefined

TWCU2

Undefined

TWCU0

Undefined

TWCU1

Timer write register C (upper digit) (TWCU: $00F)

Figure 53 Timer Write Register C Upper Digit (TWCU)

HD404369 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TRCL3

Undefined

TRCL2

Undefined

TRCL0

Undefined

TRCL1

Timer read register C (lower digit) (TRCL: $00E)

Figure 54 Timer Read Register C Lower Digit (TRCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRCU3

Undefined

TRCU2

Undefined

TRCU0

Undefined

TRCU1

Timer read register C (upper digit) (TRCU: $00F)

Figure 55 Timer Read Register C Upper Digit (TRCU)

Notes on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 26. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

In this case, the lower digit (TWCL) must be written to first, bit writing only to the lower digit does not
change the timer C value. Timer C is changed to the value in timer write register B at the same time the
upper digit (TWCU) is written to.

HD404369 Series

Alarm Output Function

The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the
prescaler S's outputs, and the output frequency depends on the state of port mode register C (PMRC: $025).
The duty cycle of the pulse output is fixed at 50%.

Port Mode Register C (PMRC: $025): Four-bit write-only register that selects the alarm frequencies as
shown in figure 57. It is reset to $0 by MCU reset.

Port Mode Register A (PMRA: $004): Four-bit write-only register that selects D

/BUZZ pin function as

shown in figure 51. It is reset to $0 by MCU reset.

Internal data bus

256

512

1024

2048

Selector

System

clock

PER

Prescaler S (PSS)

Alarm output

control signal

BUZZ

Alarm output

controller

Port mode

(PMRC)

Port mode

(PMRA)

Figure 56 Alarm Output Function Block Diagram

HD404369 Series

Internal data bus

128

512

2048

Port mode

(PMRC)

SCK

Selector

System

clock

PER

Prescaler S (PSS)

Idle

controller

Serial mode

(SMR)

Clock

Serial data

Serial interrupt

request flag

(IFS)

Selector

1/2

Octal

counter (OC)

I/O

controller

Transfer
control
signal

Figure 58 Serial Interface Block Diagram

Serial Interface Operation

Selecting and Changing the Operating Mode: Table 27 lists the serial interface's operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and the
serial mode register (SMR: $005) settings; to change the operating mode, always initialize the serial
interface internally by writing data to the serial mode register. Note that the serial interface is initialized by
writing data to the serial mode register. Refer to the following Serial Mode Register section for details.

Pin Setting: The R0

SCK pin is controlled by writing data to the serial mode register (SMR: $005). The

/SI and R0

/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the

following Registers for Serial Interface section for details.

Transmit Clock Source Setting: The transmit clock source is set by writing data to the serial mode
register (SMR: $005) and port mode register C (PMRC: $025). Refer to the following Registers for Serial
Interface section for details.

Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU, $007).
Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the
transmit clock and is input from or output to an external system.

HD404369 Series

The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.

Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000
by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops.

When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t

cyc

to 8192t

cyc

by setting bits 0 to 2 (SMR0 SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0)

of port mode register C (PMRC: $025) as listed in table 28.

Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 59.

STS wait state

Transmit clock wait state

Transfer state

Continuous clock output state (only in internal clock mode)

STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.

Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state.
However, note that if continuous clock output mode is selected in internal clock mode, the serial
interface does not enter transfer state but enters continuous clock output state (17).

The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04,
14) in transmit clock wait state.

Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.

In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.

If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set
by the octal counter that is reset to 000.

Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the

SCK pin.

HD404369 Series

When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait
state is entered.

Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC:
$025) to 0 or 1. The output level control example is shown in figure 60. Note that the output level cannot be
controlled in transfer state.

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 61.

Table 27

Serial Interface Operating Modes

SMR

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

Table 28

Serial Transmit Clock (Prescaler Output)

PMRC

SMR

Bit 0

Bit 2

Bit 1

Bit 0

Prescaler Division Ratio

Transmit Clock Frequency

2048

4096t

cyc

512

1024t

cyc

128

256t

cyc

64t

cyc

16t

cyc

4096

8192t

cyc

1024

2048t

cyc

256

512t

cyc

128t

cyc

32t

cyc

HD404369 Series

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode
register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.

Notes on Use:

Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode
register (SMR: $005) again.

Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by
writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register write or STS instruction execution must be programmed to be executed after
confirming that the

SCK pin is at 1, that is, after executing the input instruction to port R0.

STS wait state

(octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(octal counter = 000)

Transfer state

(octal counter

000)

MCU reset

SMR write

STS instruction

Transmit clock

8 transmit clocks

STS instruction (IFS 1)

SMR write (IFS 1)

External clock mode

STS wait state

(octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(octal counter = 000)

Transfer state

(octal counter

000)

SMR write

STS instruction

Transmit clock

STS instruction (IFS 1)

8 transmit clocks

Internal clock mode

Continuous clock output state

(PMRA 0, 1 = 0, 0)

SMR write

Transmit clock 17

Note: Refer to the Operating States section for the corresponding encircled numbers.

MCU reset

SMR write (IFS 1)

Figure 59 Serial Interface State Transitions

HD404369 Series

State

MCU reset

PMRA write

SMR write

PMRC write

SRL, SRU write

STS instruction

SCK

pin (input)

SO pin

IFS

STS wait state

Transmit clock
wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

External clock selection

Output level control in

idle states

Dummy write for
state transition

Output level control in

idle states

Data write for transmission

Undefined

LSB

MSB

Flag reset at transfer completion

External clock mode

State

MCU reset

PMRA write

SMR write

PMRC write

SRL, SRU write

STS instruction

SCK

pin (output)

SO pin

IFS

STS wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

Internal clock selection

Output level control in

idle states

Data write for transmission

Output level control in

idle states

Undefined

LSB

MSB

Flag reset at transfer completion

Internal clock mode

Figure 60 Example of Serial Interface Operation Sequence

HD404369 Series

Transfer completion

(IFS 1)

Interrupts inhibited

IFS 0

SMR write

IFS = 1

Transmit clock
error processing

Normal
termination

Yes

Transmit clock error detection flowchart

Transmit clock error detection procedure

State

SCK

pin (input)

Transmit clock
wait state

Transfer state

Transmit clock wait state

Noise

Transfer state has been
entered by the transmit clock
error. When SMR is written,
IFS is set.

Flag set because octal
counter reaches 000

Flag reset at
transfer completion

SMR write

IFS

Figure 61 Transmit Clock Error Detection

Registers for Serial Interface

The serial interface operation is selected, and serial data is read and written by the following registers.

Serial Mode Register (SMR: $005)

Serial Data Register (SRL: $006, SRU: $007)

Port Mode Register A (PMRA: $004)

Port Mode Register C (PMRC: $025)

Miscellaneous Register (MIS: $00C)

HD404369 Series

Serial Mode Register (SMR: $005): This register has the following functions (figure 62).

SCK pin function selection

Transmit clock selection

Prescaler division ratio selection

Serial interface initialization

Serial mode register (SMR: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.

A write signal input to serial mode register (SMR: $005) discontinues the input of the transmit clock to the
serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed
during data transfer, the serial interrupt request flag (IFS: $003, bit 2) is set.

Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.

Bit

Initial value

Read/Write

Bit name

SMR3

SMR2

SMR0

SMR1

Serial mode register (SMR: $005)

SMR2

SMR0

SMR1

SMR3

SCK

Mode Selection

SCK

Output

Input

Clock Source

External clock

Prescaler
Division Ratio

Refer to
table 28

Prescaler

System clock

Figure 62 Serial Mode Register (SMR)

HD404369 Series

Port Mode Register C (PMRC: $025): This register has the following functions (figure 63).

Prescaler division ratio selection

Output level control in idle states

Port mode register C (PMRC: $025) is a 4-bit write-only register. It cannot be written during data transfer.

By setting bit 0 (PMRC0) of this register, the prescaler division ratio is selected. Bit 0 (PMRC0) can be
reset to 0 by MCU reset. By setting bit 1 (PMRC1), the output level of the SO pin is controlled in idle
states. The output level changes at the same time that PMRC1 is written to.

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

PMRC0

Undefined

PMRC1

Port mode register C (PMRC: $025)

PMRC1

Output Level Control in Idle States

Low level

High level

PMRC0

Serial Clock Division Ratio

Prescaler output divided by 2

Prescaler output divided by 4

Alarm output function.
Refer to figure 57.

Figure 63 Port Mode Register C (PMRC)

HD404369 Series

Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 64 and
65).

Transmission data write and shift

Receive data shift and read

Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 66.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR3

Undefined

R/W

SR2

Undefined

R/W

SR0

Undefined

R/W

SR1

Serial data register (lower digit) (SRL: $006)

Figure 64 Serial Data Register (SRL)

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR7

Undefined

R/W

SR6

Undefined

R/W

SR4

Undefined

R/W

SR5

Serial data register (upper digit) (SRU: $007)

Figure 65 Serial Data Register (SRU)

LSB

MSB

Transmit clock

Serial output
data

Serial input data
latch timing

Figure 66 Serial Interface Output Timing

HD404369 Series

A/D Converter

The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It
can measure twelve analog inputs with 8-bit resolution. The block diagram of the A/D converter is shown
in figure 69.

off flag

(IAOF)

Selector

A/D channel

A/D mode

(AMR2)

A/D mode

(AMR1)

A/D interrupt

request flag

(IFAD)

Encoder

A/D data

(ADRU, L)

A/D start flag

(ADSF)

D/A

Operating mode signal (1 in
stop, watch, and subactive modes)

Internal data bus

Comp

A/D

controller

Control signal

for conversion

time

Figure 69 A/D Converter Block Diagram

HD404369 Series

Registers for A/D Converter Operation

A/D Mode Register 1 (AMR1: $019): Four-bit write-only register which selects digital or analog ports, as
shown in figure 70.

Bit

Initial value

Read/Write

Bit name

AMR13

AMR12

AMR10

AMR11

AMR10

A/D mode register 1 (AMR1: $019)

AMR11

AMR12

/AN

Mode Selection

AMR13

/AN

Mode Selection

/AN

Mode Selection

/AN

Mode Selection

Figure 70 A/D Mode Register 1 (AMR1)

A/D Mode register 2 (AMR2: $01A): Three-bit write-only register which is used to set the A/D
conversion period and to select digital or analog ports. Bit 0 of the A/D mode register selects the A/D
conversion period, and bits 1 and 2 select ports R4R5 as pins AN

in 4-pin units (figure 71).

Bit

Initial value

Read/Write

Bit name

Not used

AMR22

AMR20

AMR21

AMR20

67 t

cyc

A/D mode register 2 (AMR2: $01A)

AMR21

AMR22

R5/AN

Pin Selection

Conversion Time

34 t

cyc

R4/AN

Pin Selection

Figure 71 A/D Mode Register 2 (AMR2)

HD404369 Series

A/D Start Flag (ADSF: $02C, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the
completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 73.

Bit

Initial value

Read/Write

Bit name

R/W

DTON

R/W

ADSF

R/W

LSON

WDON

A/D start flag (ADSF: $020, bit 2)

Refer to the description of operating
modes

DTON

Refer to the description of timers

WDON

Refer to the description of operating
modes

LSON

A/D conversion completed

A/D conversion started

A/D Start Flag (ADSF)

Figure 73 A/D Start Flag (ADSF)

Off Flag (IAOF: $021, Bit 2): By setting the I

A D

off flag to 1, the current flowing through the

resistance ladder can be cut off even while operating in standby or active mode, as shown in figure 74.

Bit

Initial value

Read/Write

Bit name

R/W

RAME

R/W

IAOF

R/W

ICSF

R/W

ICEF

off flag (IAOF: $021, bit 2)

Refer to the description of operating
modes

RAME

Refer to the description of timers

ICEF

Refer to the description of timers

ICSF

current flows

current is cut off

Off Flag (IAOF)

Figure 74 I

Off Flag (IAOF)

HD404369 Series

A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower
digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the
resultant eight-bit data is held in this register until the start of the next conversion (figures 75, 76, and 77).

MSB

LSB

Bit 0

Bit 7

ADRU: $018

ADRL: $017

Figure 75 A/D Data Registers (ADRU, ADRL)

Bit

Initial value

Read/Write

Bit name

ADRL3

ADRL2

ADRL0

ADRL1

A/D data register (lower digit) (ADRL: $017)

Figure 76 A/D Data Register Lower Digit (ADRL)

Bit

Initial value

Read/Write

Bit name

A/D data register (upper digit) (ADRU: $018)

ADRU2

ADRU1

ADRU0

ADRU3

Figure 77 A/D Data Register Upper Digit (ADRU)

HD404369 Series

Notes on Usage

Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)

Do not write to the A/D start flag during A/D conversion

Data in the A/D data register during A/D conversion is undefined

Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these
modes, all current flowing through the converter's resistance ladder is cut off.

If the power supply for the A/D converter is to be different from V

, connect a 0.1-

F bypass capacitor

between the AV

and AV

pins. (However, this is not necessary when the AV

pin is directly

connected to the V

pin.)

The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D
converter operates stably, do not execute port output instructions during A/D conversion.

The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to V

. When using a

shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by A/D mode register 1 or 2 (AMR1 or AMR2) as an analog
pin will remain pulled up (figure 78).

HLT

MIS3

DCR

PDR

CPU input

Input control signal

ACR

A/D input

A/D channel register value

AMR

A/D mode register value

Figure 78 R Port/Analog Multiplexed Pin Circuit

HD404369 Series

Pin Description in PROM Mode

The HD407A4369 is a PROM version of a ZTAT

microcomputer. In PROM mode, the MCU stops

operating, thus allowing the user to program the on-chip PROM.

Pin Number

MCU Mode

PROM Mode

DP-64S

FP-64B

FP-64A

Pin

I/O

Pin

I/O

I/O

SCK

I/O

/SI

I/O

/SO

I/O

/TOC

I/O

TEST

RESET

OSC

GND

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

HD404369 Series

Pin Number

MCU Mode

PROM Mode

DP-64S

FP-64B

FP-64A

Pin

I/O

Pin

I/O

/AN

I/O

INT

I/O

INT

I/O

/EVNB

I/O

/BUZZ

I/O

STOPC

I/O

Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin

2. O

to O

consist of two pins each. Tie each pair together before using them.

HD404369 Series

Programming the Built-In PROM

The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling

RESET, M

and

low, as shown in figure 79. In PROM mode, the MCU does not operate, but it can be programmed

in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a
100-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table
29.

Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if,
for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer,
a 32-kbyte address space ($0000$7FFF) must be specified.

Control signals

Address bus

Data bus

GND
V

RESET

GND

HD407A4369

PROM mode pins

Socket adapter

PROM programmer

Figure 79 PROM Mode Connections

HD404369 Series

Table 29

Recommended PROM Programmers and Socket Adapters

PROM Programmer

Socket Adapter

Manufacture

Model Name

Package

Manufacture

Model Name

DATA I/O corp

121 B

DP-64S

Hitachi

HS4369ESS01H

FP-64B

HS4369ESF01H

FP-64A

HS4369ESH01H

AVAL corp

PKW-1000

DP-64S

Hitachi

HS4369ESS01H

FP-64B

HS4369ESF01H

FP-64A

HS4369ESH01H

Warnings

1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address

$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.

Note that the plastic-package version cannot be erased and reprogrammed.

2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1

positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure
that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.

3. PROM programmers have two voltages (V

): 12.5 V and 21 V. Remember that ZTAT

devices

require a V

of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.

Programming and Verification

The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.

Programming and verification modes are selected as listed in table 30.

For details of PROM programming, refer to the following Notes on PROM Programming section.

Table 30

PROM Mode Selection

Pin

Mode

Programming

Low

High

Data input

Verification

High

Low

Data output

Programming inhibited

High

High impedance

HD404369 Series

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes, as shown in figure 80 and described below.

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.

W register

X register

Y register

RAM address

Register Direct Addressing

RAM address

Direct Addressing

2nd word of Instruction

Opcode

1st word of Instruction

RAM address

Memory Register Addressing

Opcode

Instruction

Figure 80 RAM Addressing Modes

HD404369 Series

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes, as shown in figure 81 and described below.

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC

) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC

) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 83. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.

Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC

), and 0s are placed in the eight high-

order bits (PC

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 82. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.

The P instruction has no effect on the program counter.

HD404369 Series

2nd word of instruction

Opcode

1st word of instruction

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 81 ROM Addressing Modes

HD404369 Series

101

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to V

+ 0.3 V

0.3 to +15.0

Total permissible input current

105

Total permissible output current

Maximum input current

6, 7

6, 8

Maximum output current

7, 9

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.

1. Applies to pin TEST (V

) of HD407A4369.

2. Applies to all standard voltage pins.

3. Applies to intermediate-voltage pins.

4. The total permissible input current is the total of input currents simultaneously flowing in from all

the I/O pins to GND.

5. The total permissible output current is the total of output currents simultaneously flowing out from

to all I/O pins.

6. The maximum input current is the maximum current flowing from each I/O pin to GND.

7. Applies to ports D

to D

, R0, R3 to R9.

8. Applies to ports R1 and R2.

9. The maximum output current is the maximum current flowing from V

to each I/O pin

HD404369 Series

102

Electrical Characteristics

DC Characteristics (HD407A4369: V

C C

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A4369:V

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition Notes

Input high
voltage

RESET

SCK

INT

STOPC

, EVNB

0.8V

+ 0.3

0.7 V

+ 0.3

OSC

0.5 --

+ 0.3

Input low voltage V

RESET

SCK

INT

STOPC

, EVNB

0.3

0.2V

0.3

0.3V

OSC

0.3

0.5

Output high
voltage

SCK

, SO, TOC

0.5 --

= 0.5 mA

Output low
voltage

SCK

, SO, TOC

0.4

= 0.4 mA

I/O leakage
current

RESET

SCK

SI, SO, TOC,

OSC

INT

STOPC

EVNB

= 0 V to V

Current
dissipation in
active mode

5.0

= 5 V,

OSC

= 4 MHz

Current
dissipation in
standby mode

SBY

2.0

= 5 V,

OSC

= 4 MHz

Current
dissipation in
subactive mode

SUB

100

= 5 V,

32 kHz oscillator

Current
dissipation in
watch mode

WTC

= 5 V,

32 kHz oscillator

HD404369 Series

103

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition Notes

Current
dissipation in
stop mode

STOP

= 5V,

X1 = GND,

X2 = Open

Stop mode
retaining voltage

STOP

Notes: 1. Excludes current flowing through pull-up MOS and output buffers.

2. I

is the source current when no I/O current is flowing while the MCU is in reset state.

Test conditions:

MCU:

Reset

Pins:

RESET

, TEST at GND

3. I

SBY

is the source current when no I/O current is flowing while the MCU timer is operating.

Test conditions:

MCU:

I/O reset

Standby mode

Pins:

RESET

at V

TEST at GND

, R0R9, RA

at V

4. This is the source current when no I/O current is flowing.

Test conditions:

Pins:

RESET

at V

TEST at GND

, R0R9, RA

at V

HD404369 Series

104

I/O Characteristics for Standard Pins (HD407A4369: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to

+75

C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A

4369: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition Note

Input high voltage

R0, R3R9, RA

0.7V

+ 0.3 V

Input low voltage

R0, R3R9, RA

0.3

0.3V

Output high voltage

R0, R3R9

0.5

= 0.5 mA

Output low voltage

R0, R3R9

0.4

= 1.6 mA

Input leakage
current

R0, R3R9, RA

= 0 V to V

Pull-up MOS current I

R0, R3R9

150

300

= 5 V,

= 0 V

Note:

1. Output buffer current is excluded.

I/O Characteristics for Intermediate-Voltage Pins (HD407A4369: V

= 2.7 to 5.5 V, GND = 0 V, T

20 to +75

C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/

HD40A4369: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Input high voltage

R1, R2

0.7V

Input low voltage

R1, R2

0.3

0.3V

Output high voltage

R1, R2

11.5

500 k

at 12 V

Output low voltage

R1, R2

0.4

= 0.4 mA

2.0

= 15 mA,

= 4.5 to 5.5 V

I/O leakage current

R1, R2

= 0 V to 12 V

Note:

1. Excludes output buffer current.

HD404369 Series

105

A/D Converter Characteristics (HD407A4369: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to

+75

C;HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A

4369: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Notes

Analog supply
voltage

0.3

+ 0.3 V

Analog input voltage AV

Current flowing
between AV

and

200

= AV

= 5.0 V

Analog input
capacitance

Resolution

Bit

Number of input
channels

Chan
nel

Absolute accuracy

2.0

LSB

Conversion time

cyc

Input impedance

Note:

1. Connect this to V

if the A/D converter is not used.

HD404369 Series

106

Standard f

OSC

= 5 MHz Version AC Characteristics (HD404364/HD404368/HD4043612/HD404369:

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Notes

Clock oscillation
frequency

OSC

, OSC

0.4

5.0

MHz

1/4 system clock
division ratio

X1, X2

32.768 --

kHz

Instruction cycle
time

cyc

0.8

subcyc

244.14 --

32-kHz oscillator,
1/8 system clock
division ratio

122.07 --

32-kHz oscillator,
1/4 system clock
division ratio

Oscillation
stabilization time
(ceramic oscillator)

OSC

, OSC

7.5

Oscillation
stabilization time
(crystal oscillator)

OSC

, OSC

X1, X2

External clock high
width

CPH

OSC

External clock low
width

CPL

OSC

External clock rise
time

CPr

OSC

External clock fall
time

CPf

OSC

INT

, EVNB

high widths

INT

, EVNB

cyc

subcyc

INT

, EVNB

low widths

INT

, EVNB

cyc

subcyc

RESET

low width

RSTL

RESET

cyc

STOPC

low width

STPL

STOPC

RESET

rise time

RSTr

RESET

STOPC

rise time

STPr

STOPC

Input capacitance

All input pins
except R1 and R2

f = 1 MHz,

= 0 V

R1, R2

f = 1 MHz,

= 0 V

HD404369 Series

107

Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f

OSC

must be applied.

0.4 MHz

OSC

1.0 MHz or 1.6 MHz

OSC

5.0 MHz

The operating range for f

OSC

can be set with bit 1 of system clock selection register 1 (SSR1:

$027).

2. The oscillation stabilization time is the period required for the oscillator to stabilize in the

following situations:

a. After V

reaches 2.7 V at power-on.

b. After

RESET

input goes low when stop mode is cancelled.

c. After

STOPC

input goes low when stop mode is cancelled.

To ensure the oscillation stabilization time at power-on or when stop mode is cancelled,

RESET

STOPC

must be input for at least a duration of t

When using a crystal or ceramic oscillator, consult with the manufacturer to determine what

stabilization time is required, since it will depend on the circuit constants and stray capacitance.

3. Refer to figure 84.

4. Refer to figure 85.

5. Refer to figure 86.

6. Refer to figure 87.

HD404369 Series

108

High-Speed f

OSC

= 8.5 MHz Version AC Characteristics (HD407A4369: V

= 2.7 to 5.5 V, GND = 0

V, T

= 20 to +75

C; HD40A4364/HD40A4368/HD40A43612/HD40A4369: V

= 2.7 to 6.0 V, GND

= 0 V, T

= 20 to +75

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Notes

Clock oscillation
frequency

OSC

, OSC

0.4

5.0

MHz

1/4 system clock
division ratio

0.4

8.5

MHz

2, 3

X1, X2

32.768 --

kHz

Instruction cycle
time

cyc

0.8

0.47

2, 3

subcyc

244.14 --

32-kHz oscillator,
1/8 system clock
division ratio

122.07 --

32-kHz oscillator,
1/4 system clock
division ratio

Oscillation
stabilization time
(ceramic oscillator)

OSC

, OSC

7.5

Oscillation
stabilization time
(ceramic oscillator)

OSC

, OSC

X1, X2

External clock high
width

CPH

OSC

3, 5

External clock low
width

CPL

OSC

3, 5

External clock rise
time

CPr

OSC

3, 5

External clock fall
time

CPf

OSC

3, 5

INT

, EVNB

high widths

INT

EVNB

cyc

subcyc

INT

, EVNB

low widths

INT

EVNB

cyc

subcyc

HD404369 Series

109

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Notes

RESET

low width

RSTL

RESET

cyc

STOPC

low width

STPL

STOPC

RESET

rise time

RSTr

RESET

STOPC

rise time

STPr

STOPC

Input capacitance

All input pins except
TEST, R1 and R2

f = 1 MHz, V

= 0 V

TEST

f = 1 MHz, V

= 0 V 9

TEST

180

f = 1 MHz, V

= 0 V 10

R1, R2

f = 1 MHz, V

= 0 V

Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f

OSC

must be applied.

0.4 MHz

OSC

1.0 MHz or 1.6 MHz

OSC

5.0 MHz

The operating range for f

OSC

can be set with bit 1 of system clock selection register 1 (SSR1:

$027).

2. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f

OSC

must be applied.

0.4 MHz

OSC

1.0 MHz or 1.6 MHz

OSC

8.5 MHz

The operating range for f

OSC

can be set with bit 1 of system clock selection register 1 (SSR1:

$027).

3. V

= 4.5 to 5.5V

4. The oscillation stabilization time is the period required for the oscillator to stabilize in the

following situations:

a. After V

reaches 2.7 V at power-on.

b. After

RESET

input goes low when stop mode is cancelled.

c. After

STOPC

input goes low when stop mode is cancelled.

To ensure the oscillation stabilization time at power-on or when stop mode is cancelled,

RESET

STOPC

must be input for at least a duration of t

When using a crystal or ceramic oscillator, consult with the manufacturer to determine what

stabilization time is required, since it will depend on the circuit constants and stray capacitance.

5. Refer to figure 84.

6. Refer to figure 85.

7. Refer to figure 86.

8. Refer to figure 87.

9. Applies to the HD40A4364, HD40A4368, HD40A43612, and HD40A4369.

10. Applies to the HD407A4369.

HD404369 Series

110

Serial Interface Timing Characteristics (HD407A4369: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to

+75

C; HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/HD40A43612/HD40A

4369: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

During Transmit Clock Output

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Transmit clock cycle
time

Scyc

SCK

cyc

Load shown in figure 89

Transmit clock high
width

SCKH

SCK

0.4

Scyc

Load shown in figure 89

Transmit clock low
width

SCKL

SCK

0.4

Scyc

Load shown in figure 89

Transmit clock rise
time

SCKr

SCK

Load shown in figure 89

Transmit clock fall
time

SCKf

SCK

Load shown in figure 89

Serial output data
delay time

DSO

300

Load shown in figure 89

Serial input data setup
time

SSI

100

Serial input data hold
time

HSI

200

During Transmit Clock Input

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Transmit clock cycle
time

Scyc

SCK

cyc

Transmit clock high
width

SCKH

SCK

0.4

Scyc

Transmit clock low
width

SCKL

SCK

0.4

Scyc

Transmit clock rise
time

SCKr

SCK

Transmit clock fall
time

SCKf

SCK

Serial output data
delay time

DSO

300

Load shown in figure 89

Serial input data setup
time

SSI

100

Serial input data hold
time

HSI

200

Note:

1. Refer to figure 88.

HD404369 Series

113

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404364,
HD40A4364, HD404368, HD40A4368, HD4043612 and HD40A43612 as a 16-kword version
(HD404369, HD40A4369). The 16-kword data sizes are required to change ROM data to mask
manufacturing data since the program used is for a 16-kword version.

This limitation applies when using an EPROM or a data base.

Vector address

Zero-page
subroutine

(64 words)

Pattern & program

(4,096 words)

Not used

Vector address

Zero-page
subroutine

(64 words)

Pattern & program

(12,288 words)

Not used

ROM 4-kword version:
HD404364, HD40A4364

ROM 12-kword version:
HD4043612, HD40A43612

$0000

$000F
$0010

$003F
$0040

$0FFF
$1000

$3FFF

$0000

$000F
$0010

$003F
$0040

$2FFF
$3000

$3FFF

Fill this area with 1s

Vector address

Zero-page
subroutine

(64 words)

Pattern & program

(8,192 words)

Not used

ROM 8-kword version:
HD404368, HD40A4368

$0000

$000F
$0010

$003F
$0040

$1FFF
$2000

$3FFF

HD404369 Series

114

HD404364/HD404368/HD4043612/HD404369/HD40A4364/HD40A4368/
HD40A43612/HD40A4369 Option List

Please check off the appropriate applications and enter the necessary information.

3. ROM Code Media

Date of order

Customer

Department

Name

ROM code name

LSI number

EPROM:

Ceramic oscillator

Crystal oscillator

External clock

f = MHz

4. System Oscillator (OSC1, OSC2)

With 32-kHz CPU operation, with time base for clock

Without 32-kHz CPU operation, with time base for clock

Without 32-kHz CPU operation, without time base

2. Optional Functions

Note:

Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).

The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are

programmed to different EPROMS.

5 MHz operation

8.5 MHz operation

5 MHz operation

8.5 MHz operation

5 MHz operation

8.5 MHz operation

5 MHz operation

8.5 MHz operation

HD404364

HD40A4364

HD404368

HD40A4368

HD4043612

HD40A43612

HD404369

HD40A4369

4-kword

8-kword

12-kword

16-kword

1. ROM size

DP-64S

FP-64B

FP-64A

6. Package

Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTATTM version).

Used

Not used

5. Stop mode

HD404369 Series

115

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404368

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404368