Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

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Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

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Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

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these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
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Remember to give due consideration to safety when making your circuit designs, with appropriate
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contained therein.

HD404618 Series

4-Bit Single-Chip Microcomputer

Rev. 6.0

Sept. 1998

Description

The HD404618 Series is designed with the powerful and efficient architecture of the HMCS400 family.
The MCU incorporates a high-precision dual-tone multifrequency (DTMF) circuit, LCD driver/controller,
voltage comparator, and 32-kHz watch oscillator circuit.

The HD404618 Series includes five chips: the HD404612 with 2-kword ROM; the HD404614 with 4-
kword ROM; the HD404616 with 6-kword ROM; the HD404618 with 8-kword ROM; the HD4074618
with 8-kword PROM.

The HD4074618, incorporating PROM, is a ZTAT

microcomputer that can dramatically shorten system

development periods and smooth the process from debugging to mass production.

ZTATTM : Zero Turn Around time ZTAT is a trademark of Hitachi Ltd.

Features

2048-word

10-bit ROM (HD404612)

4096-word

10-bit ROM (HD404614)

6144-word

10-bit ROM (HD404616)

8192-word

10-bit ROM (HD404618, HD4074618)

1184-digit

4-bit RAM

30 I/O pins

10 high-current output pins

CMOS I/O pin circuit configuration

Input/output pull-up MOS can be selected by software

On-chip DTMF generator

LCD controller/driver (32 segments

4 commons)

Three timer/counters

Clock-synchronous 8-bit serial interface

Six interrupt sources

Two by external sources

Four by internal sources

HD404618 Series

Subroutine stack up to 16 levels, including interrupts

Instruction cycle time

s (f

OSC

= 400 kHz)

s (f

OSC

= 800 kHz)

Four low-power dissipation modes

Stop mode

Standby mode

Watch mode

Subactive mode

Built-in oscillator

Crystal or ceramic oscillator (an external clock also possible)

Voltage comparator (2 channels)

Two operating modes

MCU mode

PROM mode (HD4074618)

Package

80-pin plastic flat package

(FP-80B) (FP-80A)

80-pin plastic thin flat package (TFP-80)

Ordering Information

Type

Product Name

Model Name

ROM (Word)

Package

Mask ROM

HD404612

HD404612FS

2,048

FP-80B

HD404612H

FP-80A

HD404612TF

TFP-80

HD404614

HD404614FS

4,096

FP-80B

HD404614H

FP-80A

HD404614TF

TFP-80

HD404616

HD404616FS

6,144

FP-80B

HD404616H

FP-80A

HD404616TF

TFP-80

HD404618

HD404618FS

8,192

FP-80B

HD404618H

FP-80A

HD404618TF

TFP-80

ZTAT

HD4074618

HD4074618FS

8,192

FP-80B

HD4074618H

FP-80A

HD4074618TF

TFP-80

HD404618 Series

Pin Arrangement

RESET

OSC

COM4

TONER

TONEC

COM3

COM2

COM1

ref

SEG2

SEG3

SEG4

SEG5

TIMO/R3

INT

/R3

INT

/R3

SEG1

SEG6

SEG7

SEG8

1
2
3
4
5
6
7
8
9
10
11
12

64
63
62

61
60
59
58
57
56
55
54
53

(top view)

FP-80B

SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16

SEG15
SEG14
SEG13

SEG12
SEG11
SEG10
SEG9

D
D
D

VC /D

COMP

TEST

SCK

/R0

GND

SI/R0

SO/R0

R1
R1

ref

D
D

FP-80A
TFP-80

RESET

OSC

COM4

COM3

COM2

COM1

SEG32

SEG31

OSC

ref

TONER

TONEC

SEG2

SEG3

SEG4

SEG5

TIMO/R3

INT

/R3

INT

/R3

SEG1

SEG6

SEG7

SEG8

SEG9

SEG10

D
D
D
D
D

VC /D

ref

COMP

TEST

X1
X2

GND

SCK

/R0

SI/R0

SO/R0

SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11

HD404618 Series

Pin Description

Pin Number

FP-80B

FP-80A,
TFP-80

Pin Name

I/O

FP-80B

FP-80A,
TFP-80

Pin Name

I/O

I/O

SEG1

I/O

SEG2

I/O

SEG3

I/O

SEG4

I/O

SEG5

I/O

SEG6

I/O

SEG7

I/O

SEG8

SEG9

/VC

ref

SEG10

/COMP

SEG11

/COMP

SEG12

TEST

SEG13

SEG14

SEG15

GND

SEG16

SCK

I/O

SEG17

/SI

I/O

SEG18

/SO

I/O

SEG19

I/O

SEG20

I/O

SEG21

I/O

SEG22

I/O

SEG23

I/O

SEG24

I/O

SEG25

I/O

SEG26

I/O

SEG27

I/O

SEG28

I/O

SEG29

/TIMO

I/O

SEG30

INT

I/O

SEG31

INT

I/O

SEG32

HD404618 Series

Pin Number

FP-80B

FP-80A,
TFP-80

Pin Name

I/O

FP-80B

FP-80A,
TFP-80

Pin Name

I/O

COM1

TONER

COM2

ref

COM3

COM4

OSC

RESET

I/O

TONEC

I/O

Note: I/O: Input/output pin, I: Input pin, O: Output pin

Pin Functions

Power Supply

: Apply power voltage to this pin.

GND: Connect to ground.

TEST: Used for test purposes only. Connect it to V

RESET: Resets the MCU.

Oscillators

OSC

, OSC

: Used as pins for the internal oscillator circuit. They can be connected to a ceramic

resonator, or OSC

can be connected to an external oscillator circuit.

X1, X2: Used for a 32.768-kHz crystal oscillator that acts as a clock.

Ports

(D Port): Input/output port addressable by individual bits. D

are I/O pins and D

are

input pins. D

are high current output pins (15 mA, max.). D

are also available as voltage

comparators.

R0R3 (R Ports): Input/output ports addressable in 4-bit units. R0

, R0

, R3

, and R3

, are

multiplexed with

SCK, SI, SO, TIMO, INT

, and

INT

, respectively.

HD404618 Series

Interrupts

INT

: Input external interrupts to the MCU.

INT

is also used as an external event input for timer B.

INT

and

INT

are multiplexed with R3

and R3

, respectively.

Serial Communications Interface

SCK: Input/output serial clock pin multiplexed with R0

SI: Serial receive data input pin multiplexed with R0

SO: Serial transmit data output pin multiplexed with R0

Timers

TIMO: Outputs a variable-duty square wave. It is multiplexed with R3

LCD Driver/Controller

, V

: Power supply pins for the LCD driver. Internal resistors provide the voltage level for each pin.

The voltage condition is V

GND.

COM1COM4: Common signal output pins for LCD display.

SEG1SEG32: Segment signal output pins for LCD display.

DTMF Generator

TONER, TONEC, VT

ref

: DTMF signal pins. TONER and TONEC transmit signals for row and column,

respectively. VT

ref

is a reference voltage for DTMF signals. Apply condition V

ref

GND to VT

ref

Voltage Comparator

COMP0, COMP1, VC

ref

: COMP0 and COMP1 are analog inputs for the voltage comparator. VC

ref

is a

reference voltage pin that inputs the threshold voltage of the analog input pin.

HD404618 Series

Block Diagram

Internal address bus

System control circuit

RAM

(1,184 4 bits)

W (2 bits)

X (4 bits)

SPX (4 bits)

Y (4 bits)

SPY (4 bits)

(1 bit)

A (4 bits)

B (4 bits)

SP (10 bits)

Instruction

decoder

PC (14 bits)

ROM

(2,048

10 bits)

(4,096

10 bits)

(6,144

10 bits)

(8,192

10 bits)

D port

ALU

CPU

INT

Timer B

Timer C

TIMO

R0 port

R1 port

R2 port

R3 port

RESET

TEST

OSC

GND

Timer A

External
interrupt

control

circuit

Internal data bus

High
current
pins

LCD

controller/

driver

circuit

COM1
COM2
COM3
COM4

SEG1
SEG2
SEG3

SEG31
SEG32

DTMF

generation

circuit

ref

TONER
TONEC

ref

COMP

Compa-

rator

Serial

interface

SCK

: Data bus

: Signal lines

HD404618 Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1, and the ROM is described below.

4095

4096

8191

8192

16383

$000F

$0FFF

$1000

$1FFF

$2000

$3FFF

$0010

$003F

$0040

Vector address

Zero-page subroutine
(64 words)

Pattern
(4096 words)

Not used

2
3

4
5

6
7
8
9

10
11
12

13
14
15

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007

$0008
$0009

$000A
$000B

$000C
$000D

$000E
$000F

JMPL instruction

(jump to reset routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B routine)

JMPL instruction

(jump to timer C routine)

JMPL instruction

(jump to serial routine)

JMPL instruction

(jump to

INT

routine)

HD404612: 2048 words
HD404614: 4096 words
HD404616: 6144 words
HD404618, HD4074618: 8192 words

Program

Note:

Figure 1 ROM Memory Map

Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After an MCU reset or interrupt execution, the program starts from the
vector address.

Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000$07FF (HD404612), $0000$0FFF (HD404614), $0000$17FF (HD404616),
$0000$1FFF (HD404618, HD4074618)): Used for program coding.

HD404618 Series

RAM Memory Map

The MCU contains a 1,184-digit

4-bit RAM area consisting of a data area and a stack area. In addition,

interrupt control bits and special registers are mapped onto the same RAM memory space outside this area.
The RAM memory map is shown in figure 2, and described below.

Interrupt Control Bits Area ($000$003): Used for interrupt control bits and the bit register (figure 3).
The register flag area consists of LSON, WDON, TGSP, and DTON flags. Both areas can be accessed
only by RAM bit manipulation instructions. In addition, note that the interrupt request flag cannot be set
by software, the RSP bit is used only to reset the stack pointer. Limitations on using the instructions are
shown in figure 4.

Register Flag Area ($020$023): Consist of the LSON, WDON, TGSP, and DTON flags which are bit
registers accessible by RAM bit manipulation instructions.

The WDON flag can only be set, only by the SEM/SEMD instruction.

The TGSP flag can be set and reset by the SEM/SEMD and REM/REMD instructions.

The DTON flag can be set, reset, and tested by the SEM/SEMD, REM/REMD, and TMD instructions.
Note that the DTON flag is active only in subactive mode, and is normally reset in active mode.

Special Function Registers Area ($004$01F, $024$03F): Used as mode or data registers for serial
interface, timer/counters, LCD, and DTMF, and as data control registers for I/O ports. These registers are
classified into three types: write-only, read-only, and read/write as shown in figure 2.

The SEM/REM and SEMD/REMD instructions can be used for the LCD control register (LCR), but RAM
bit manipulation instructions cannot be used for other registers.

LCD Data Area ($050$06F): Used for storing LCD data which is automatically output to LCD segments
as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. This area can be
used as data area.

Data Area ($040$2CF, $100$2CF; Bank 0, 1): The memory registers (MR), which consist of 16 digits
($040$04F), can be accessed by the LAMR and XMRA instructions (see figure 5). In the 464 digits from
$100$2CF, a bank can be selected by the V register (see section on V register).

Stack Area ($3C0$3FF): Used for saving the contents of the program counter (PC), status flag (ST),
and carry flag (CA) at subroutine call (CAL or CALL instruction) and interrupt processing. This area can
be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved
and the save conditions are shown in figure 5.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404618 Series

$000

112

959

960

1023

$03F
$040
$050

$070

$100

$3FF

12
13

50
51

$001

$002

$003

$004

$005

$006

$007

$008

$009

$00A

$00B

$00C

$00D

$00E

$00F

$010

$011

$012

$013

$014

$020

$023

$030

$031

$032

$033

$03B

$03C

$03D

$03F

$00A

$00B

$00E

$00F

R/W

$100

$2CF

$3BF

$3C0

$2CF

RAM-mapped registers

Memory registers (MR)

LCD display area (32 digits)

Data (144 digits)

Data (464 digits 2)
V = 0 (bank 0)
V = 1 (bank 1)

Not used

Stack (64 digits)

Interrupt control bits area

Port mode register A (PMRA)
Serial mode register (SMR)

Serial data register lower (SRL)

Serial data register upper (SRU)

Timer mode register A (TMA)

Timer mode register B (TMB)

Timer B (TCBL/TLRL)
(TCBU/TLRU)

Miscellaneous register (MIS)

Timer mode register C (TMC)

Timer C (TCCL/TCRL)
(TCCU/TCRU)

TG mode register (TGM)

TG control register (TGC)

Port mode register B (PMRB)

LCD control register (LCR)

LCD mode register (LMR)

Not used

Port R0 DCR (DCR0)
Port R1 DCR (DCR1)

Port R2 DCR (DCR2)
Port R3 DCR (DCR3)

Not used

Port D D DCR (DCRB)

Port D D DCR (DCRC)

Port D D DCR (DCRD)

Not used

V register (V-REG)

Data (464 digits)

V = 0 (bank 0)

Data (464 digits)

V = 1 (bank 1)

Timer counter B, lower

(TCBL)

Timer counter B, upper

(TCBU)

Timer counter C, lower

(TCCL)

Timer counter C, upper

(TCCU)

Timer load register B, lower

(TLRL)

Timer load register B, upper

(TLRU)

Timer load register C, lower

(TCRL)

Timer load register C, upper

(TCRU)

R: Read only

W: Write only

R/W: Read/write

Note: Do not use any area labelled "Not used"

The data area has two banks:
V = 0 (bank 0) and V = 1 (bank 1)

Figure 2 RAM Memory Map

HD404618 Series

Bit 3

Bit 2

Bit 1

Bit 0

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt enable flag)

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

Not used

IMS

(IM of serial)

IFS

(IF of serial)

$000

$001

$002

$003

DTON

Direct transfer on flag

TGSP

(Tone generator

speed flag)

WDON

(Watchdog on flag)

LSON

(Low speed on flag)

Not Used

$020

$021

$023

IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Note: Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD

instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction.
Other instructions have no effect.

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

RSP

WDON

TGSP

DTON

SEM/SEMD

REM/REMD

TM/TMD

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Allowed

Inhibited

Not executed in active mode

Allowed

Used in subactive mode

Note: WDON is always reset in active mode.

DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404618 Series

PC PC : Program counter
ST: Status flag
CA: Carry flag

Memory registers

Stack area

$040

960

$3C0

$041

$042

$043

$044

$045

$046

$047

$048

$049

$04A

$04B

$04C

$04D

$04E

$04F

MR (0)

MR (1)

MR (2)

MR (3)

MR (4)

MR (5)

MR (6)

MR (7)

MR (8)

MR (9)

MR (10)

MR (11)

MR (12)

MR (13)

MR (14)

MR (15)

Level 16

Level 15

Level 14

Level 13

Level 12

Level 11

Level 10

Level 9

Level 8

Level 7

Level 6

Level 5

Level 4

Level 3

Level 2

Level 1

1023

$3FF

Bit 3

Bit 2

Bit 1

Bit 0

$3FC

$3FD

$3FE

$3FF

1022

1023

1020

1021

Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position

HD404618 Series

V Register (V): Used for RAM address expansion and selecting the bank of RAM addresses $100$2CF
(464 digits). Thus, when accessing locations $100$2CF, specify the value of the V register (V = $0 for
bank 0, V = $1 for bank 1). Locations $000$0FF and $3C0$3FF can be accessed independent of the V
register. The V register is located at RAM address $03F.

W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. During an interrupt, a carry is pushed onto the
stack and popped from the stack by the RTNI instructionbut not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare
instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the
BR, BRL, CAL, or CALL instruction. The contents of ST remain unchanged until the next arithmetic,
compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is
read, regardless of whether the instruction is executed or skipped. During an interrupt, the contents of ST
are pushed onto the stack and popped from the stack by the RTNI instruction, but not by the RTN
instruction.

Program Counter (PC): A 14-bit counter that points to the ROM address of the instruction being
executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset, is decremented by 4 when data is pushed onto the stack, and is
incremented by 4 when data is popped from the stack. Since the top four bits of the SP are fixed at 1111, a
stack of up to 16 levels can be used.

The SP can also be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.

HD404618 Series

Reset

The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one t

to enable the oscillator to stabilize.

During operation, RESET must be high for at least two instruction cycles.

I/O pins go to high-impedance at power-on.

Initial values after MCU reset are shown in table 1.

Table 1 Initial Values After MCU Reset

Item

Abbr.

Initial Value Contents

Program counter

(PC)

$0000

Indicates program execution
point from start address of ROM
area

Status flag

(ST)

Enables conditional branching

Stack pointer

(SP)

$3FF

Stack level 0

V register (bank register)

(V)

Bank 0 (memory)

Interrupt flags/mask Interrupt enable flag

(IE)

Inhibits all interrupts

Interrupt request flag

(IF)

Indicates there is no interrupt
request

Interrupt mask

(IM)

Prevents (masks) interrupt
request

I/O

Port data register

(PDR)

All bits 1

Enables output at level 1

Data control register

(DCR)

All bits 0

Turns output buffer off (to high
impedance)

Port mode register A

(PMRA)

0000

Refer to description of port mode
register A

Port mode register B

(PMRB)

0000

Refer to description of port mode
register B

Timer/
counters, serial

interface

Timer mode register A

(TMA)

0000

Refer to description of timer
mode register A

Timer mode register B

(TMB)

0000

Refer to description of timer
mode register B

Timer mode register C

(TMC)

0000

Refer to description of timer
mode register C

Serial mode register

(SMR)

0000

Refer to description of serial
mode register

Prescaler S

$000

Prescaler W

$00

Timer counter A

(TCA)

$00

HD404618 Series

Table 1 Initial Values After MCU Reset (cont)

Item

Abbr.

Initial Value Contents

Timer/
counters, serial

interface

Timer counter B

(TCB)

$00

Timer counter C

(TCC)

$00

Timer load register B

(TLR)

$00

Timer load register C

(TCR)

$00

Octal counter

000

LCD

LCD control register

(LCR)

000

Refer to description of LCD
control register

LCD mode register

(LMR)

0000

Refer to description of LCD duty
cycle/clock control

DTMF generator

Tone generator control
register

(TGC)

000

Refer to description of tone
generator control register

Tone generator mode
register

(TGM)

0000

Refer to description of generator
mode register

Bit registers

Low speed on flag

(LSON)

Refer to description of operating
modes

Watchdog timer on flag (WDON)

Refer to description of timer C

Tone generator speed
flag

(TGSP)

Refer to description of DTMF
generation circuit

Direct transfer on flag

(DTON)

Refer to description of operating
modes

Miscellaneous
register

(MIS)

000

Item

Abbr.

Status after Cancellation of
Stop Mode by MCU Reset

Status after Cancellation of All
Other Modes by MCU Reset

Carry flag

(CA)

Pre-MCU-reset values are not
guaranteed; values must be
initialized by program

Accumulator

(A)

B register

(B)

W register

(W)

X/SPX register

(X/SPX)

Y/SPY register

(Y/SPY)

Serial data register

(SR)

RAM

Pre-MCU-reset (pre-STOP-
instruction) values are retained

HD404618 Series

Interrupts

The MCU has six interrupt sources: two external signals (

INT

and

INT

), three timer/counters (timers A,

B, and C), and serial interface (serial).

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.

Interrupt Control Bits and Interrupt Servicing: Locations $000 through $003 in RAM space are
reserved for interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.

Figure 7 is a block diagram of the interrupt control circuit. Table 2 lists interrupt priorities and vector
addresses, and table 3 lists the interrupt processing conditions for the six interrupt sources.

An interrupt request occurs when the IF is set to 1 and IM to 0. If the IE is 1 at that point, the interrupt is
processed. A priority programmable logic array (PLA) generates the vector address assigned to that
interrupt source.

Figure 8 shows the interrupt processing sequence, and figure 9 shows an interrupt processing flowchart.
After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset
in the second cycle, the carry flag, status flag, and program counter values are pushed onto the stack during
the second and third cycles, and the program jumps to the vector address to execute the instruction in the
third cycle.

Program the JMPL instruction at each vector address to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.

HD404618 Series

Table 3 Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt
Control Bit

INT

Timer A

Timer B

Timer C

Serial

IF0·

IM0

IF1·

IM1

IFTA·

IMTA

IFTB·

IMTB

IFTC·

IMTC *

IFS·

IMS

Note: Bits marked by

can be either 0 or 1. Their values have no effect on operation.

Instruction cycles

Instruction

execution

IE reset

Interrupt

acceptance

Execution of JMPL

instruction at vector address

Execution of

instruction at

start address

of interrupt

routine

Vector address

generation

Note:

The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.

Stacking

Figure 8 Interrupt Processing Sequence

HD404618 Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as shown in table 4.

Table 4 Interrupt Enable Flag

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

): Specified by port mode register A (PMRA: $004).

The

INT

input can be used as a clock signal input to timer B. Timer B increments at each falling edge of

the

INT

input. When using

INT

as a timer B external event input, external interrupt mask IM1 must be

set to prevent the

INT

interrupt request from being accepted (see table 6).

To detect the edge of

INT

, more than two instruction cycle times are required (2t

cyc

or 2t

subcyc

External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): Set at the falling edge of the
INT

and

INT

inputs as shown in table 5.

Table 5 External Interrupt Request Flags

IF0, IF1

Interrupt Request

Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as shown in table 6.

Table 6 External Interrupt Masks

IM0, IM1

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A as shown in
table 7.

Table 7 Timer A Interrupt Request Flag

IFTA

Interrupt Request

Yes

HD404618 Series

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as shown in table 8.

Table 8 Timer A Interrupt Mask

IMTA

Interrupt Request

Enabled

Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B as shown in
table 9.

Table 9 Timer B Interrupt Request Flag

IFTB

Interrupt Request

Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as shown in table 10.

Table 10 Timer B Interrupt Mask

IMTB

Interrupt Request

Enabled

Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C as shown in
table 11.

Table 11 Timer C Interrupt Request Flag

IFTC

Interrupt Request

Yes

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as shown in table 12.

HD404618 Series

Operating Modes

The MCU has five operating modes that are specified by how the clock is used. The functions available in
each mode are listed in table 15, and operations are shown in table 16. Transitions between operating
modes are shown in figure 10. Table 17 provides additional information for table 15.

Table 15 Functions Available in Each Operating Mode

Mode Name

Active

Standby

Stop

Watch

Subactive

Activation
method

Reset
cancellation,
interrupt
request

SBY
instruction

TMA3 = 0,
STOP
instruction

TMA3 = 1,
STOP
instruction

INT

or timer

A interrupt
request from
watch mode

Status

System
oscillator

Operating

Stopped

Subsystem
oscillator

Operating

Instruction
execution
(ø

CPU

)

Operating

Stopped

Operating

Peripheral
function
interrupt(ø

PER

)

Operating

Stopped

Operating

Clock function
interrupt (ø

CLK

)

Operating

Stopped

Operating

RAM

Operating

Retained

Operating

Registers/
flags

Operating

Retained

Reset

Retained

Operating

I/O

Operating

Retained

High
impedance

Retained

Operating

Cancellation
method

RESET input,
STOP/SBY
instruction

RESET input,
interrupt
request

RESET input RESET input,

INT

or timer

A interrupt
request

RESET input,
STOP/SBY
instruction

Notes: 1. To reduce current dissipation, stop all oscillation in external circuits.

2. Refer to the Interrupt Frame section for details.

3. Refer to table 17.

4. Subactive mode is an optional function, specify it on the function option list.

5. In the watch and subactive modes, the MCU requires a 32.768-kHz crystal oscillator.

HD404618 Series

System Clock (ø

CPU

)

Operating

Stopped

Non-time-base peripheral function clock (ø

PER

)

Operating

Active mode

Standby mode

Subactive mode

Stopped

Watch mode (TMA3 = 1)

Stop mode (TMA3 = 0)

Table 16 Operations in Low-Power Dissipation Modes

Function

Stop Mode

Watch Mode

Standby Mode

Subactive Mode

2, 3

CPU

Reset

Retained

RAM

Retained

Timer A

Reset

Timer B

Reset

Stopped

Timer C

Reset

Stopped

Serial interface

Reset

Stopped

LCD

Reset

DTMF

Reset

Stopped

Reset

I/O

Reset

Retained

Notes: OP indicates operating.

1. Output pins are at high impedance.

2. Subactive mode is an optional function specified on the function option list.

3. In the watch and subactive modes, the MCU requires a 32.768 kHz crystal oscillator.

4. Transmission/reception is activated if a clock is input in external clock mode. (However,

interrupts stop.)

HD404618 Series

Reset

f :
f :
ø :
ø :
ø :

CPU

CLK

PER

OSC

Operating
Operating
Stopped
f
f

cyc

f :
f :
ø :
ø :
ø :

CPU

CLK

PER

OSC

Operating
Operating
Stopped
f
f

SUB

cyc

f :
f :
ø :
ø :
ø :

CPU

CLK

PER

OSC

Operating
Operating
f
f
f

cyc

f :
f :
ø :
ø :
ø :

CPU

CLK

PER

OSC

Operating
Operating
f
f
f

cyc

SUB

cyc

f :
f :
ø :
ø :
ø :

CPU

CLK

PER

OSC

Stopped
Operating
f
f
f

SUB

f :
f :
ø :
ø :
ø :

CPU

CLK

PER

OSC

Stopped
Operating
Stopped
Stopped
Stopped

f :
f :
ø :
ø :
ø :

CPU

CLK

PER

OSC

Stopped
Operating
Stopped
f
Stopped

SUB

f :
f :
ø :
ø :
ø :

CPU

CLK

PER

OSC

Stopped
Operating
Stopped
f
Stopped

SUB

Standby mode

Stop mode

(TMA3 = 0)

Watch mode

Subactive mode

(TMA3 = 1)

(TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

(TMA3 = 0)

SBY (standby)

Interrupt

Timers A, B, C,
Serial,

INT

0 1

SBY (standby)

Interrupt

STOP

INT

Timer A

INT

Timer A

STOP

STOP/SBY

(LSON = 1)

1.
2.
3.
4.

f :
f :

f :
f :
ø :
ø :
ø :

LSON:
DTON:

cyc

SUB

OSC

Main oscillation frequency
Suboscillation frequency
for time-base
f /4
f /8
System clock
Clock for time-base
Clock for other
peripheral functions
Low speed on flag
Direct transfer on flag

OSC

CPU

CLK

PER

Active mode

Timers A, B, C,
Serial,

INT

0 1

Notes:

Time-base interrupt
STOP/SBY (DTON = 1, LSON = 0)
STOP/SBY (DTON = 0, LSON = 0)
DTON is not affected

Figure 10 MCU Status Transitions

Table 17 I/O Status in Low-Power Dissipation Modes

Output

Input

Standby Mode, Watch Mode

Stop Mode

Active Mode, Subactive Mode

Retained

High impedance

Input enabled

R0R3

Retained

High impedance

Input enabled

HD404618 Series

Active Mode: The MCU operates according to the clock generated by the system oscillators OSC

and

OSC

Standby Mode: The MCU enters standby mode when the SBY instruction is executed from active mode.
In this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all
instruction execution-related clocks stop. The stopping of these clocks stops the CPU, retaining all RAM
and register contents and maintaining the current I/O pin status.

Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and resumes, executing
the next instruction after the SBY instruction. If the interrupt enable flag is 1, that interrupt is then
processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A
flowchart of operation in standby mode is shown in figure 11.

HD404618 Series

Standby

Oscillator: Active
Peripheral clocks:
Active
All other clocks:
Stopped

RESET

= 1 ?

Yes

IF0 =

1 ?

Yes

IM0 =

0 ?

IF1 =

1 ?

Yes

IM1 =

0 ?

IFTA =

1 ?

Yes

IMTA =

0 ?

IFTB =

1 ?

Yes

IMTB =

0 ?

IFTC =

1 ?

Yes

IMTC =

0 ?

IFS =

1 ?

Yes

IMS =

0 ?

Yes

(SBY only)

Watch

Oscillator: Stopped
Sub-oscillator: Active
Peripheral clocks: Stopped
All other clocks: Stopped

Restart
processor clocks

Reset MCU

Execute
next instruction

Accept
interrupt

Execute
next instruction
(active mode)

Restart
processor clocks

Yes

IF = 1,

IM = 0, and

IE = 1 ?

Figure 11 MCU Operation Flowchart in Watch and Standby Modes

Stop Mode: The MCU enters stop mode if the STOP instruction is executed in active mode when TMA3 =
0. In this mode, the system oscillator stops, which stops all MCU functions as well.

Stop mode is terminated by a RESET input as shown in figure 12. RESET must be high for at least one t

to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is
cancelled, all RAM contents are retained, but the accuracy of the contents of the accumulator, B register, W
register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.

HD404618 Series

Stop mode

Oscillator

Internal clock

RESET

STOP instruction execution

t > t (stabilization time)

res

Figure 12 Timing of Stop Mode Cancellation

Watch Mode: The MCU enters watch mode if the STOP instruction is executed in active mode when
TMA3 = 1, or if the STOP or SBY instruc-tion is executed in subactive mode.

Watch mode is terminated by a RESET input or a timer-A/

INT

interrupt request. For details of RESET

input, refer to the Stop Mode section. When terminated by a timer-A/

INT

interrupt request, the MCU

enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated,
the time required to enter active mode is t

for a timer A interrupt, and T

(where T + t

< T

< 2T + t

)

for an

INT

interrupt, as shown in figure 13.

Operation during mode transition is the same as that at standby mode cancellation (figure 12).

Active mode

Watch mode

Active mode

Oscillation
stabilization period

Interrupt strobe

INT

Interrupt request
generation

(During the transition
from watch mode to
active mode only)

T = 2

: Interrupt frame length

: Oscillation stabilization period

Figure 13 Interrupt Frame

Subactive Mode: The CPU operates with a clock generated by the X1 and X2 oscillation circuits.
Functions that can operate in subactive mode are listed in table 16. When the STOP or SBY instruction is
executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of

HD404618 Series

LSON and DTON. The DTON flag can only be set in subactive mode; it is automatically reset after a
transition to active mode.

Subactive mode is an optional function that the user must specify on the function option list.

Interrupt Frame: In watch and subactive modes, Ø

CLK

is supplied for timer A and the

I NT

circuit.

Prescaler W and timer A operate as time bases to generate interrupt frame timing. Three interrupt frame
cycles (T) can be selected by the settings of the miscellaneous register, as shown in figure 14.

In watch and subactive modes, timer A and

INT

interrupts are generated in synchronism with the interrupt

frame. An interrupt request is generated at the interrupt strobe timing, except when the MCU enters active
mode from watch mode. The

INT

falling edge is acknowledged regardless of the interrupt frame, but the

interrupt is executed simultaneously with the next interrupt strobe. Timer A generates an overflow and
interrupt request at the timing of an interrupt strobe.

MIS: $00C

MIS1

MIS0

MIS2

Refer to
table 20

t selection

MIS

Bit 1

Bit 0

15.625 ms

0.24414 ms

62.5 ms

31.25 ms

0.24414 ms

7.8125 ms

0.12207 ms

Not used

400/800-kHz
ceramic oscillator

External clock input

Oscillation circuit
condition

Notes: 1.

The value of t applies only when using a 32.768-kHz oscillator.
Only direct transfer.

Figure 14 Miscellaneous Register

Direct Transfer: By controlling the DTON, the MCU would be placed directly from subactive to active
mode. The detailed procedure is as follows:

Set the DTON flag in subactive mode while LSON = 0.

Execute the STOP or SBY instruction.

After the oscillation stabilization time (a fixed value), the MCU will move automatically from subactive
to active mode.

Note that DTON ($020, bit 3) is valid only in subactive mode. When the MCU is in active mode, this flag
is always at reset.

The transition time (t

) from subactive to active mode is t

< t

< T + t

HD404618 Series

Subactive mode

Interrupt
strobe

Direct transfer
timing

Internal
execution
time

Oscillation
stabilization
time

Active mode

T: Interrupt frame length
t : Oscillation stabilization period

STOP/SBY
execution

(LSON = 0, DTON = 1)

(< T)

Figure 15 Direct Transfer Timing

MCU Operating Sequence: The MCU operates in the sequence shown in figures 16 to 18. It is reset by
an asynchronous RESET input, regardless of its state.

The low-power mode operation sequence is shown in figure 18. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.

Power on

RESET = 1 ?

Reset
MCU

MCU

operation

cycle

Yes

Figure 16 MCU Operating Sequence (power on)

HD404618 Series

Low-power mode

operation cycle

IF = 1
IM = 0 ?

Hardware NOP

execution

PC next

Iocation

MCU operation

cycle

Standby/watch

mode

IF = 1
IM = 0 ?

Hardware NOP

execution

PC next

Iocation

Instruction

execution

Stop mode

Yes

For IF and IM operation, refer to figure 12.

Figure 18 MCU Operating Sequence (low-power mode operation)

Notes on Use:

In subactive mode, the timer A interrupt request or the external interrupt request (

INT

) occurs in

synchronism with the interrupt strobe.

If the STOP or SBY instruction is executed at the same time with the interrupt strobe, these interrupt
requests will be cancelled and the corresponding interrupt request flags (IFTA, IF0) will not be set.

In subactive mode, do not use the STOP or SBY instruction at the time of the interrupt strobe.

HD404618 Series

When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of
INT

is shorter than the interrupt frame,

INT

is not detected. Also, if the low level period after the

falling edge of

INT

is shorter than the interrupt frame,

INT

is not detected.

Edge detection is shown in figure 19. The level of the

INT

signal is sampled by a sampling clock.

When this sampled value changes to low from high, a falling edge is detected.

In figure 20, the level of the

INT

signal is sampled by an interrupt frame. In (a) the sampled value is

low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled
value is high at point A, and also high at point B. A falling edge is not detected in this case either.

When the MCU is in watch mode or subactive mode, keep the high level and low level period of

INT

longer than interrupt frame.

High

Low

INT

Sampling

Low

Figure 19 Edge Detection

A: Low

B: Low

INT

Interrupt
frame

A: High

B: High

INT

Interrupt
frame

(a) High level period

(b) Low level period

Figure 20 Sampling Example

HD404618 Series

Internal Oscillator Circuit

Figure 21 shows a block diagram of the internal oscillator circuit. A ceramic oscillator can be connected to
OSC

and OSC

, and a 32.768-kHz crystal oscillator can be connected to X1 and X2. The system oscillator

can also be operated by an external clock.

OSC

Subsystem

oscillator

Divider

(1/4)

Divider

(1/8)

Mode

control

circuit

Timing

generator

OSC

cyc

SUB

Timing

generator

System clock
(ø )

CPU

System clock
(ø )

PER

Timer-base
clock (ø )

CLK

OSC

System

oscillator

Figure 21 Internal Oscillator Circuit

RESET

OSC

ref

COMP

TEST

GND

SCK

/R0

GND

Figure 22 Layout of Crystal and Ceramic Oscillators

HD404618 Series

Table 18 Oscillator Circuit Examples

Circuit Configuration

Circuit Constants

External clock operation
(OSC

, OSC

)

External
oscillator

OSC

Open

OSC

Ceramic oscillator
(OSC

, OSC

)

OSC

Ceramic

GND

Ceramic oscillator: CSB400P22,
CSB400P (Murata)
R

= 1 M

20%

= C

= 220 pF

Ceramic oscillator: CSB800J122,
CSB800J(Murata)
R

= 1 M

20%

= C

= 220 pF

Crystal oscillator

Crystal

GND

C R

Crystal: 32.768 kHz: MX38T
(Nippon Denpa Kogyo)
R

= 14 k

= 1.5 pF

= 20 pF

20%

= 20 pF

20%

Notes: 1. The circuit constants given above are recommended values provided by the oscillator

manufacturer. Since they may be affected by stray capacitances from the oscillator or board,
consult the crystal or ceramic oscillator manufacturer to determine the actual circuit parameters
required.

2. Wiring between the OSC

/OSC

pins (X1, X2 pins) and other elements must be as short as

possible, and must not cross other wiring. Refer to the recommended layout of the crystal and
ceramic oscillator in figure 22.

3. If a 32.768-kHz crystal oscillator is not used, fix the X1 pin to V

and leave the X2 pin open.

HD404618 Series

Input/Output

The MCU provides 26 input/output pins and 4 input pins, including 10 high-current pins (15 mA, max.). A
program-controlled pull-up MOS transistor is provided for each input/output pin.

The output buffer is turned on and off by the data control register (DCR) during input through an
input/output pin.

I/O pin circuit types are shown in table 19.

D Ports (D

): Consist of ten 1-bit input/output pins and four input pins. Pins D

are high-current

I/O pins (15 mA, max.). The sum current of the pins can go up to 100 mA. These pins are set by the SED
and SEDD instructions, reset by the RED and REDD instructions, and tested by the TD and TDD
instructions. Output data is stored in the port data register.

The on/off status of the output buffer is controlled by D port data control registers (DCRB, DCRC, and
DCRD) that are mapped to the memory address area. Pins D

are input-only pins.

Two operating modes are available to pins D

and D

: digital input mode and analog input mode. The

operating modes are set by bits 0 and 1 of port mode register B (PMRB). In the digital input mode, these
pins can be used as input pins with the same input characteristics as the I/O pins. In the analog input mode,
the result of a comparison with the reference voltage can be read as input data. The reference voltage is
input by the D

/VC

ref

pin.

R Ports: Consist of sixteen 4-bit I/O ports. Data is input to these ports by the LAR and LBR instructions
and output from them by the LRA and LRB instructions.

The on/off status of the output buffers of the R ports are controlled by R port data control registers (DCR0
DCR3) that are mapped to memory addresses.

Pins R0

, R0

, and R0

are multiplexed with pins

SCK, SI, and SO, respectively.

Pins R3

, R3

, and R3

are multiplexed with TIMO,

INT

, and

INT

, respectively. Refer to figure 24.

Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin.

The on/off status of all these transistors is controlled by bit 3 of port mode register B (PMRB), and the
on/off status of an individual transistor can also be controlled by the port data register (PDR) of the
corresponding pin. This enables on/off control of each individual pin. Refer to table 20.

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system must be connected to
V

to prevent LSI malfunctions due to noise. These pins must either be pulled up to V

by their pull-up

transistors or by resistors of about 100 k

HD404618 Series

Table 19 Circuit Configurations of I/O Pins

I/O Pin Type

Circuit

Applicable Pins

Common I/O pin
(with pull-up MOS
transistor)

Input control signal

Input data

Output data

PDR

DCR

Pull-up control signal

SCK

Output data

SCK

(internal)

DCR

Pull-up control signal

SCK

Output pin (with
pull-up MOS
transistor)

Output data

SO or TIMO

DCR

Pull-up control signal

SO, TIMO

Input pin

PDR

Pull-up control signal

INT

Input control signal

Input data

/VC

ref

Analog input

Input control

Input data

Mode select signal

/COMP

(multiplexed with
analog inputs)

Note: Refer to table 20, note 3 concerning R0

/SO.

HD404618 Series

Port mode register A: $004 (PMRA)

R0 /SO pin mode selection

R0 /SI pin mode selection

R3 /

INT

pin mode selection

R3 /

INT

pin mode selection

Port
selection

Bit 3

INT

PMRA

Bit 2

PMRA

INT

Port
selection

Bit 1

PMRA

Port
selection

Bit 0

PMRA

Port
selection

Pull-up
MOS
on/off

Bit 3

Off

PMRB

Bit 2

PMRB

TIMO

Port
selection

Bit 1

PMRB

COMP

Port
selection

Bit 0

PMRB

COMP

Port
selection

D /COMP0 pin mode selection

Port mode register B: $012 (PMRB)

D /COMP1 pin mode selection
R3 /TIMO pin mode selection
Pull-up MOS on/off selection

Port
selection

Bit 3

SCK

SMR

Serial mode register: $005 (SMR)

R0 /

SCK

pin mode selection

Figure 24 I/O Switching Mode Registers

HD404618 Series

Table 20 Programmable I/O Circuits

PMRB Bit 3 (PMRB3)

DCR

PDR

CMOS Buffer

PMOS (A)

NMOS (B)

Pull-up MOS Transistor

Notes: 1. --: Off

2. Various I/O methods can be selected by different combinations of settings of the above mode

registers (PMRB3, DCR, PDR).

3. The PMOS (A) transistor of the R1

/SO pin can be turned off by setting bit 2 of the miscellaneous

MIS

Bit 2

/SO Pin

PMOS (A)

Off

4. The relationships between DCRs and pins are as shown below.

DCR

Bit 3

Bit 2

Bit 1

Bit 0

DCR0

DCR1

DCR2

DCR3

DCRB

DCRC

DCRD

HD404618 Series

Timers

The MCU has two prescalers (S and W) and three timer/counters (A, B, and C). Figures 26, 27 and 28
show their diagrams.

Prescaler S: Eleven-bit counter that inputs the system clock signal. After being initialized to $000 by
MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except at MCU reset and in
the stop and watch modes. Of the prescaler S outputs, timer A input clock, timer B input clock, timer C
input clock, and serial interface transmit clock are selected by timer mode register A (TMA), timer mode
register B (TMB), timer mode register C (TMC), and the serial mode register (SMR), respectively.

Prescaler W: Five-bit counter that inputs the X1 input clock signal divided by eight. Prescaler W output
can be selected as a timer A input clock by timer mode register A (TMA).

Timer A: Eight-bit timer that can be used as a clock time-base (figure 26). It is initialized to $00 and
incremented at each clock input. If an input clock is applied to timer A after it has reached $FF, an
overflow that sets the timer A interrupt request flag (IFTA: $001, bit 2) is generated, and timer A restarts
from $00.

Timer A is used to generate regular interrupts (every 256 clocks) for measuring times between events. It
can also be used as a clock time-base when bit 3 of timer mode register A (TMA) is set to 1. The timer is
driven by the 32-kHz oscillator clock frequency divided by prescaler W, and the clock input to timer A is
controlled by TMA. In this case, prescaler W and timer A can be initialized to $00 by software.

1/4

1/2

32.768-kHz
oscillator

System
clock

Prescaler W

(PSW)

Selector

Prescaler S (PSS)

Selector

Internal data bus

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

2 f

SUB

1/2 t

subcyc

)

PER

128

512

1024

2048

÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷

÷ ÷ ÷ ÷

SUB

Figure 26 Timer A Block Diagram

HD404618 Series

Timer B (TCBL and TLRL: $00A, TCBU and TLRU: $00B): Eight-bit write-only timer load register
(TLRL and TLRU) and read-only timer counter (TCBL and TCBU) located at the same addresses. The
eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. A block
diagram of timer B is shown in figure 27.

Timer counter B is initialized by writing to timer load register B (TLR). In this case, the lower digit must
be written to first. The contents of TLR are loaded into the timer counter at the same time the upper digit is
written to, initializing the timer counter. TLR is initialized to $00 by MCU reset.

The count of timer B is obtained by reading timer counter B. In this case, the upper digit must be read first;
the count is latched when the upper digit is read.

An auto-reload function, input clock source, and prescaler division ratio of timer B depend on the state of
timer mode register B (TMB). When an external event input is used as the input clock source of TMB, the
R3

INT

pin must be set to

INT

by setting port mode register A (PMRA: $004).

Timer B is initialized to the value set in TMB by software, and is then incremented by one each clock
input. If an input is applied to timer B after it has reached $FF, an overflow is generated. In this case, if
the auto-reload function is enabled, timer B is initialized to its initial value; if auto-reload is disabled, the
timer is initialized to $00. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0).

HD404618 Series

System
clock

INT

Selector

Prescaler S (PSS)

Clock

Timer counter register BU (TCBU)

Timer counter

(TCBL)

Timer counter B

(TCB)

Timer load

(TLRU)

Timer load

(TLRL)

Timer mode

(TMB)

Timer B interrupt

request flag

(IFTB)

cyc

SUB

cyc

subcyc

)

Internal data bus

128

512

2048

÷ ÷ ÷ ÷ ÷ ÷

Free-running
control

Overflow

Figure 27 Timer B Block Diagram

Timer C (TCCL and TCRL: $00E, TCCU and TCRU: $00F): Eight-bit write-only timer load register
(TCRL and TCRU) and read-only timer counter (TCCL and TCCU) located at the same addresses. The
eight-bit configuration consists of lower and upper 4-bit digits located at sequential addresses. The
operation of timer C is basically the same as that of timer B.

The auto-reload function and prescaler division ratio of timer C depend on the state of timer mode register
C (TMC). Timer C is initialized to the value set in TMC by software, and is then incremented by one at
each clock input. If an input is applied to timer C after it has reached $FF, an overflow is generated. In
this case, if the auto-reload function is enabled, timer C is initialized to its initial value; if auto-reload is
disabled, the timer is initialized to $00. The overflow sets the timer C interrupt request flag (IFTC: $002,
bit 2).

Timer C also functions as a watchdog timer. If a program routine runs out of control and an overflow is
generated while the watchdog on (WDON) flag is set, the MCU is reset. This error can be detected by
having the program control timer C reset before timer C reaches $FF.

The WDON can only have 1 written to it ; it is cleared to 0 only by MCU reset.

Timer Mode Register A (TMA: $008): Four-bit write-only register that controls timer A as shown in
table 21.

HD404618 Series

Table 21 Timer Mode Register A

TMA

Bit 3

Bit 2

Bit 1

Bit 0

Source Prescaler, Input Clock Period,
Operating Mode

PSS, 2048 t

cyc

Timer A mode

PSS, 1024 t

cyc

PSS, 512 t

cyc

PSS, 128 t

cyc

PSS, 32 t

cyc

PSS, 8 t

cyc

PSS, 4 t

cyc

PSS, 2 t

cyc

PSW, 32 t

subcyc

Time-base mode

PSW, 16 t

subcyc

PSW, 8 t

subcyc

PSW, 2 t

subcyc

PSW, 1/2 t

subcyc

Not used

PSW, TCA reset

Notes: 1. t

subcyc

= 244.14

s (when 32.768-kHz crystal oscillator is used)

2. Timer counter overflow output period(s) = input clock period(s)

256

3. If PSW or TCA reset is selected while the LCD is operating, LCD operation halts (power switch

goes off).

When LCD is connected for display, the PSW and TCA reset periods must be set in the program
to the minimum.

4. In time base mode, the timer counter overflow output cycle must be greater than half of the

interrupt frame period (T/2 = t

If 1/2 t

subcyc

is selected, t

must be 7.8125 ms ((MIS1, MIS0) = (0, 1), see figure 14).

5. The division ratio must not be modified during time-base mode operation, otherwise an overflow

cycle error will occur.

HD404618 Series

T (TCR + 1)

T 256

T (256 TCR)

TMC3 = 0

Period of clock input to the counter (table 23)
Value of timer load register C (0255)

Note: This waveform is always fixed low
when TCR = $FF.

TMC3 = 1

TCR:

Figure 29 Variable-Duty Pulse Output Waveform

Timer Mode Register B (TMB: $009): Four-bit write-only register that selects the auto-reload function,
the prescaler division ratio, and input clock source as shown in table 22. Timer mode register B is
initialized to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle. Timer B initialization set by
writing to TMB must be done after a mode change becomes valid.

Table 22 Timer Mode Register B

TMB

Bit 3

Auto-Reload Function

Disabled

Enabled

TMB

Bit 2

Bit 1

Bit 0

Prescaler Division Ratio, Clock Input Source

2048

512

128

INT

(external event input)

HD404618 Series

Note on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register untill the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 24. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

Table 24 PWM Output Following Update of Timer Write Register

PWM Output

Mode

Timer Load Register is Updated during
High PWM Output

Timer Load Register is Updated during
Low PWM Output

Free running

Timer load
register
updated to
value N

Interrupt
request

Timer load
register
updated to
value N

Interrupt
request

(255 N) T

(N + 1)

(N' + 1)

(255 N)

(N + 1)

Reload

Timer load
register
updated to
value N

Interrupt
request

Timer load
register
updated to
value N

Interrupt
request

(255 N)

HD404618 Series

Serial Interface

The MCU has a clock-synchronous serial interface which transmits and receives 8-bit data.

The serial interface consists of a serial data register (SR), serial mode register (SMR), port mode register A
(PMRA), octal counter, and multiplexers (see figure 30). The R0

SCK pin and the transmit clock are

controlled by writing to the SMR. The transmit clock shifts the contents of the SR, which can be read and
written to by software.

The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction,

starts counting at the falling edge of the transmit clock (

SCK), and it increments at the rising edge of the

clock. A serial interrupt request flag is set when the eighth transmit clock signal is input (the serial

interface is reset) or when serial transmission is discontinued (the octal counter is reset).

Internal data bus

Port mode

(PMRA)

SCK

Selector

System

clock

cyc

sub

cyc

subcyc

)

Prescaler S (PSS)

I/O

control

logic

Serial mode

(SMR)

Clock

Serial data

Serial interrupt

request flag

(IFS)

Selector

1/2

Octal

counter (OC)

I/O

control

logic

Transfer
control
signal

128

512

2048

Figure 30 Serial Interface Block Diagram

Serial Mode Register (SMR: $005): Four-bit write-only register that controls the R0

SCK pin, prescaler

division ratio, and transmit clock source (table 25 and figure 31). Writing to this register initializes the
serial interface.

HD404618 Series

A write signal input to the serial mode register discontinues the input of the transmit clock to the serial data
register and octal counter. Therefore, if a write is performed during data transmission, the octal counter is
reset to 000 to stop transmission, and at the same time, the serial interrupt request flag is set.

Write operations are valid from the second instruction execution cycle, so the STS instruction must be
executed after at least two cycles have been executed. The serial mode register is initialized to $0 by MCU
reset.

Table 25 Serial Mode Register

SMR

Bit 3

SCK

Pin

port input/output pin

SCK

input/output pin

SMR

Transmit Clock

Bit 2

Bit 1

Bit 0

SCK

Pin

Clock Source

Prescaler
Division Ratio

System Clock
Division Ratio

SCK

output

Prescaler

2048

4096

SCK

output

Prescaler

512

1024

SCK

output

Prescaler

128

256

SCK

output

Prescaler

SCK

output

Prescaler

SCK

output

Prescaler

SCK

output

System clock

SCK

input

External clock

PMRA3 PMRA2 PMRA1

PMRA: $004

SMR3

SMR2

SMR1

SMR0

SMR: $005

R0 /SO pin mode selection

Transmit clock selection

R0 /

SCK

pin mode selection

R0 /SI pin mode selection

PMRA0

Figure 31 Configurations and Functions of the Mode Registers

HD404618 Series

Serial Data Register (SRL: $006, SRU: $007): Eight-bit read/write register separated into upper and
lower digits located at sequential addresses.

Data in this register is output from the SO pin, LSB first, in synchronism with the falling edge of the
transmit clock, and data is input LSB first through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 32.

Data cannot be read or written during serial data transmission. If a read/write occurs during transmission,
the accuracy of the resultant data cannot be guaranteed.

LSB

MSB

Transmit
clock

Serial
output
data

Serial input
data
latch timing

Figure 32 Serial Interface Timing

Selecting and Changing Operating Mode: Table 26 lists the serial interface operating modes. To select
an operating mode, use one of these combinations of PMR and SMR settings; to change the operating
mode, always initialize the serial interface internally by writing to the SMR.

Table 26 Serial Interface Operating Modes

SMR

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

Serial Interface Operation: Three operating modes are provided for the serial interface; transitions
between them are shown in figure 33.

In STS waiting state, the serial interface is initialized and the transmit clock is ignored. If the STS
instruction is then executed, the serial interface enters transmit clock wait state.

In transmit clock wait state, input of the transmit clock increments the octal counter, shifts the serial clock
register, and activates serial transmission. However, note that if clock output mode is selected, the transmit
clock is continuously output but data is not transmitted.

HD404618 Series

During transmission, the input of eight clocks or the execution of the STS instruction sets the octal counter
to 000, and the serial interface enters transmit clock wait state. If the state changes from transmit to another
state, the serial interrupt request flag is set by the octal counter reaching 000.

octal counter = 000
transmit clock disabled

STS instruction wait state

Transmit clock

8 transmit clocks (external clock)

STS instruction

(IFS 1)

(octal counter = 000)

Transmit clock wait state

Transfer state

(octal counter 000)

SMR write

STS instruction

SMR write

8 transmit clocks (internal

clock)

(IFS 1)

Figure 33 Serial Interface Mode Transitions

In this state, if the internal clock has been selected, the transmit clock is output in answer to the execution
of the STS instruction, but serial transmission is inhibited after the eighth clock is output.

If port mode register A (PMRA) is written to in transmit clock wait state or during transmission, the serial
mode register (SMR) must be written to, to initialize the serial interface. The serial interface then enters
STS wait state.

If the serial interface shifts from transfer state to another state, the octal counter returns to 000, setting the
serial interrupt request flag.

Transmit Clock Error Detection: The serial interface will malfunction if a spurious pulse caused by
external noise conflicts with a normal transmit clock during transmission. A transmit clock error of this
type can be detected as shown in figure 34.

If more than eight transmit clocks are input in transmit clock wait state, the serial interface state changes to
transfer, transmit clock wait, then back to transfer.

If the serial interface is set to STS wait state by writing data to the SMR after the serial interrupt request
flag has been reset, the flag is set again.

HD404618 Series

Liquid Crystal Display (LCD)

The MCU has an LCD controller and driver which drive 4 common signal pins and 32 segment signal pins.
The controller consists of a RAM area in which display data is stored, a display control register (LCR), and
a duty/clock control register (LMR), as shown in figure 37.

Four duties and the LCD clock are program-controllable, and a built-in dual-port RAM ensures that display
data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz
oscillation clock is selected as the LCD clock source, the LCD can be used even in watch mode, in which
the system clock stops.

Power switch

GND

LCD

power

control

circuit

LCD

common

driver

Display on/off

Display

area

LCD duty/clock

control

(LMR: $014)

(Dual-port

RAM)

LCD

control

(LCR: $013)

LCD

segment

driver

LCD
clock

$050

$06F

RAM area

Duty cycle selection
Clock selection

LCD
clock

SEG32

SEG2

SEG1

COM4

COM3

COM2

COM1

Divided system clock
output (CL1CL3)
Divided 32-kHz clock
output (CL0)

LCD: Liquid crystal display

Figure 35 Liquid Crystal Display Block Diagram

LCD Data Area and Segment Data ($050 $06F): Figure 36 shows the configuration of LCD RAM
area. Each bit of the storage area corresponds to one of four types of duties. If data is written to an area
corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display
data.

HD404618 Series

Bit 3

Bit 2

Bit 1

Bit 0

$050

$051

$052

$053

$054

$055

$056

$057

$058

$059

$05A

$05B

$05C

$05D

$05E

$05F

COM4

COM3

COM2

COM1

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

Bit 3

Bit 2

Bit 1

Bit 0

100

101

102

103

104

105

106

107

108

109

110

111

$060

$061

$062

$063

$064

$065

$066

$067

$068

$069

$06A

$06B

$06C

$06D

$06E

$06F

COM4

COM3

COM2

COM1

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

Figure 36 Configuration of LCD RAM Area

LCD Control Register (LCR: $013): Three-bit write-only register which controls LCD blanking, the
turning on and off of the LCD's power supply division resistor, and display in watch and subactive modes
(see table 27).

Blank/display

Blank:

Segment signals are turned off regardless of LCD RAM data setting.

Display: LCD RAM data is output as segment signals.

Power switch on/off

Off: The power switch is off.

On: The power switch is on and V

is V

Watch/subactive mode display

Off: In watch and subactive modes, all common and segment pins are grounded and the liquid crystal
power switch is turned off.

On: In watch and subactive modes, LCD RAM data is output as segment signals.

HD404618 Series

Table 27 LCD Control Register

LCR

Bit 2

Display in
Watch Mode or
Subactive Mode Bit 1

Power Switch
On/Off

Bit 0

Blank/Display

Off

Blank

Display

Note:

When using an LCD in watch mode or subactive mode, use the divided output of a 32-kHz oscillator
as the LCD clock and set bit 2 of the LCR to 1. If using the divided output of the system clock as the
LCD clock, always set bit 2 of the LCR to 0.

LCD Duty/Clock Control Register (LMR: $014): Four-bit write-only register which selects the display
duty and LCD clock source, as shown in table 28.

Table 28 LCD Duty/Clock Control Register

LMR

Bit 3

Bit 2

Bit 1

Bit 0

Duty Selection/Input Clock Selection

1/4 duty cycle

1/3 duty cycle

1/2 duty cycle

Static

CL0 (32.768/64 kHz when using 32.768-kHz oscillator)

CL1 (f

cyc

/256)

CL2 (f

cyc

/2048)

CL3 (refer to table 29)

Note: f

cyc

is the divided system clock output.

HD404618 Series

Table 29 LCD Frame Periods for Different Duties

Static Duty

LMR

Instruction
cycle time

Bit 3
0

Bit 2
0

Bit 3
0

Bit 2
1

Bit 3
1

Bit 2
0

Bit 3
1

Bit 2
1

CL0

CL1

CL2

CL3

512 Hz

390.6 Hz

48.8 Hz

24.4 Hz/64 Hz

512 Hz

781.2 Hz

97.6 Hz

48.8 Hz/64 Hz

1/2 Duty

LMR

Instruction
cycle time

Bit 3
0

Bit 2
0

Bit 3
0

Bit 2
1

Bit 3
1

Bit 2
0

Bit 3
1

Bit 2
1

CL0

CL1

CL2

CL3

256 Hz

195.3 Hz

24.4 Hz

12.2 Hz/32 Hz

256 Hz

390.6 Hz

48.8 Hz

24.4 Hz/32 Hz

1/3 Duty

LMR

Instruction
cycle time

Bit 3
0

Bit 2
0

Bit 3
0

Bit 2
1

Bit 3
1

Bit 2
0

Bit 3
1

Bit 2
1

CL0

CL1

CL2

CL3

170.6 Hz

130.2 Hz

16.3 Hz

8.1 Hz/21.3 Hz

170.6 Hz

260.4 Hz

32.6 Hz

16.2 Hz/21.3 Hz

1/4 Duty

LMR

Instruction
cycle time

Bit 3
0

Bit 2
0

Bit 3
0

Bit 2
1

Bit 3
1

Bit 2
0

Bit 3
1

Bit 2
1

CL0

CL1

CL2

CL3

128 Hz

97.7 Hz

12.2 Hz

6.1 Hz/16 Hz

128 Hz

195.4 Hz

24.4 Hz

12.2 Hz/16 Hz

Note:

The division ratio depends on the value of bit 3 of timer mode register A (TMA3): The first value is
for TMA3 = 0 and the second is for TMA3 = 1.

When TMA3 = 0, CL3 = f

cyc

duty cycle/4096.

When TMA3 = 1, CL3 = 32.768 kHz

duty cycle/512

HD404618 Series

Large Liquid-Crystal Panel Drive and V

LCD

: To drive a large-capacity LCD, decrease the resistance of

the built-in division resistors by attaching external resistors in parallel, as shown in figure 38.

The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix
configuration of the LCD complicates the paths of charge/discharge currents flowing through the
capacitors. The resistance will also vary with lighting conditions. This size must be determined by trial
and error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 to 10
k

would usually be suitable. (Another effective method is to attach capacitors of 0.1 to 0.3

F.)

Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid crystal drive

voltage (V

LCD

GND

COM1

SEG1

SEG32

GND

COM1
COM2

SEG1

SEG32

GND

COM1

COM3

SEG1

SEG32

GND

COM1

COM4

SEG1

SEG32

LCD

V (V )

CC 1

GND

V (V )

CC 1

GND

C = 0.1 to 0.3

4-digit LCD
with sign

8-digit LCD

10-digit LCD
with sign

16-digit LCD

Static drive

1/2 duty cycle, 1/2 bias drive

1/3 duty cycle, 1/3 bias drive

1/4 duty cycle, 1/3 bias drive

GND

LCD

Figure 38 LCD Connection Examples

HD404618 Series

DTMF Generation Circuit

The MCU has a dual-tone multifrequency (DTMF) generation circuit.

The DTMF signal consists of two sine waves to access the switching system.

Figure 39 shows the DTMF keypad and frequencies. Pressing a key generates a tone corresponding to its
frequency. Figure 40 shows a block diagram of the DTMF circuit.

The MCU uses an oscillation frequency reduced to 400 kHz, an eighth of the conventionally used
frequency, for low-power consumption. This, however, causes a potential frequency deviation. The MCU
provides transformed programmable dividers in addition to sine wave counters and a control register to
reduce frequency deviation.

The DTMF generation circuit is controlled by the following three registers.

R1 (697 Hz)

R2 (770 Hz)

R3 (852 Hz)

R4 (941 Hz)

C1 (1209 Hz)

C2 (1336 Hz)

C3 (1477 Hz)

C4 (1633 Hz)

Figure 39 DTMF Keypad and Frequencies

HD404618 Series

400 kHz (selected at TGSP reset)

800 kHz

TGSP

flag

TONER

ref

TONEC

Sine wave

counter D/A

Transformed

programmable

divider

Transformed

programmable

divider

Sine wave

counter D/A

DTMF

Feedback

Figure 40 DTMF Circuit Block Diagram

Tone Generator Mode Register (TGM: $010): Four-bit write-only register which controls output
frequencies (see table 30). It is cleared to $0 by MCU reset.

Table 30 Tone Generator Mode Register

TGM

Bit 3

Bit 2

Bit 1

Bit 0

Output Frequencies

Option
(TONER output
is not affected)

(697 Hz)

Output through
TONER pin

(770 Hz)

(852 Hz)

(941 Hz)

Option
(TONEC output is not affected)

(1,209 Hz)

Output through
TONEC pin

(1,336 Hz)

(1,477 Hz)

(1,633 Hz)

Tone Generator Control Register (TGC: $011): Three-bit write-only register which controls the start
and stop of DTMF signal output (see table 31). It is cleared to $0 by MCU reset.

HD404618 Series

Table 31 Tone Generator Control Register

TGC

Bit 1

DTMF Enable Bit

DTMF disabled

DTMF enabled

TGC

Bit 2

TONER Output Control (row)

Stopped

TONER output (active)

TGC

Bit 3

TONEC Output Control (column)

Stopped

TONEC output (active)

Tone Generator Speed Flag (TGSP: $020,Bit 2): One-bit register which can be set and reset by the
SEM/REM and SEMD/REMD instructions. The DTMF generation circuit generates output frequencies
with a 400-kHz clock (table 30). With an 800-kHz clock, the DTMF generation circuit generates these
same frequencies by pulling the TGSP flag high.

DTMF Output: The sine waves of the row-group and column-group are individually converted from
digital to analog in the D/A conversion circuit, which provides high-precision ladder resistance. The
DTMF output pins, TONER and TONEC, transmit the sine waves of the row-group and column-group,
respectively. Figure 41 shows thetone output equivalent circuit. Figure 42 shows the output waveform.
One cycle of this wave consists of 32 time slots, making the output waveform stable with little distortion.
Table 32 lists the frequency deviation of the MCU from standard DTMF signals.

ref

GND

Switch control

TONER

TONEC

Figure 41 Tone Output Equivalent Circuit

HD404618 Series

ref

GND

Time slots

1 2 3 4 5 6 7 8 9 10

13 14 15 16

18 19

20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 42 Waveform of Tone Output

Table 32 Frequency Deviation of the MCU from Standard DTMF Signals

Standard

DTMF (Hz)

MCU (Hz)

Deviation from
Standard (%)

697

694.44

0.37

770

769.23

0.10

852

851.06

0.11

941

938.97

0.22

1,209

1,212.12

0.26

1,336

1,333.33

0.20

1,477

1,481.48

0.30

1,633

1,639.34

0.39

Note:

This frequency deviation value does not include the frequency deviation due to the oscillator
element. Also note that in this case the ratio of the high level and low level widths in the oscillator
waveform due to the oscillator element will be 50% : 50%.

HD404618 Series

Programmable ROM

The HD4074618 is a ZTAT

microcomputer with built-in PROM that can be programmed in PROM

mode.

PROM Mode Pin Description

Pin Number

MCU Mode

PROM Mode

Pin Number

MCU Mode

PROM
Mode

FP-80B

FP-80A,
TFP-80

Pin Name

I/O

Pin
Name

I/O

FP-80B

FP-80A,
TFP-80

Pin Name

I/O

Pin
Name

I/O

I/O

/TIMO I/O

I/O

INT

I/O

INT

I/O

SEG1

I/O

SEG2

I/O

SEG3

SEG4

/VC

ref

SEG5

/COMP

SEG6

/COMP

SEG7

TEST

SEG8

GND

SEG9

SEG10

GND

SEG11

SCK

I/O

SEG12

/SI

I/O

SEG13

/SO

I/O

SEG14

I/O

SEG15

I/O

SEG16

I/O

SEG17

I/O

SEG18

I/O

SEG19

I/O

SEG20

I/O

SEG21

I/O

SEG22

HD404618 Series

Pin Number

MCU Mode

PROM Mode

Pin Number

MCU Mode

PROM Mode

FP-80B

FP-80A,
TFP-80

Pin Name

I/O

Pin
Name

I/O

FP-80B

FP-80A,
TFP-80

Pin
Name

I/O

Pin
Name

I/O

SEG23

COM4

SEG24

SEG25

SEG26

SEG27

TONEC O

SEG28

TONER O

SEG29

ref

SEG30

SEG31

OSC

SEG32

OSC

COM1

RESET I

RESET

COM2

I/O

COM3

I/O

HD404618 Series

Programming the Built-in PROM

The MCU's built-in PROM is programmed in PROM mode which is set by pulling

TEST, M

, and

low,

and RESET high, as shown in figure 43. In PROM mode, the MCU does not operate, but it can be
programmed in the same way as any other commercial 27256 EPROM using a standard PROM
programmer and a 80-to-28-pin socket adaptor. Recommended PROM programmers and socket adapters
are listed in table 34.

Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable use of a general-purpose PROM programmer. This circuit splits each instruction into a
lower 5 bits and an upper 5 bits that are read from or written to consecutive addresse. This means that if,
for example, 8 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer,
a 16-kbyte address space ($0000$3FFF) must be specified.

Programming and Verification: The built-in PROM of the MCU can be programmed at high-speed
programming sequence without risk of voltage stress or damage to data reliability.

For details of PROM programming, refer to the notes on PROM Programming section.

Warnings

1. Always specify addresses $0000 to $3FFF when programming with a PROM programmer. If address

$4000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.

Note that the plastic-package version cannot be erased and reprogrammed.

2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1

positions match), otherwise overcurrents may damage the LSI. Before starting programming, make
sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.

3. PROM programmers have two voltages (V

): 12.5 V and 21 V. Remember that ZTAT

devices

require a V

of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel's 27256 setting.

Table 33 PROM Mode Selection

Pin

Mode

Programming

Low

High

Data input

Verification

High

Low

Data output

Programming inhibition

High

High impedance

HD404618 Series

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes, as shown in figure 44 and described below.

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode: The memory registers (MR), consisting of 16 digits from $040 to
$04F, are accessed with the LAMR and XMRA instructions.

W register

X register

Y register

RAM address

Register Indirect Addressing

RAM address

Direct Addressing

2nd word of instruction

Opcode

1st word of instruction

RAM address

Memory Register Addressing

Opcode

Instruction

Figure 44 RAM Addressing Modes

HD404618 Series

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes, as shown in figure 45 and described below.

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC

) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 32 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC

) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 46. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.

Note that the HMCS400-series cross macro-assembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $000
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC

), and 0s are placed in the eight high-

order bits (PC

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-
bit immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 47. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers.
If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.

The P instruction has no effect on the program counter.

HD404618 Series

2nd word of instruction

Opcode

1st word of instruction

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 45 ROM Addressing Modes

HD404618 Series

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to (V

+ 0.3)

Total permissible input current

100

Total permissible output current

Maximum input current

4, 5

4, 6

Maximum output current

7, 8

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.

1. D

) of the HD4074618.

2. Total permissible input current is the total of input currents simultaneously flowing in from all the

I/O pins to GND.

3. Total permissible output current is the total of output currents simultaneously flowing out from V

to all I/O pins.

4. The maximum input current is the maximum current flowing from any I/O pin to ground.

5. Applies to R0R3

6. Applies to D

7. The maximum output current is the maximum current flowing from V

to any I/O pin.

8. Applies to D

, R0R3

HD404618 Series

Electrical Characteristics (Please inquire about the characteristics of HD404612,
HD404614, HD404616, and HD404618 at V

= 2.2 V)

DC Characteristics (HD404612, HD404614, HD404616, HD404618: V

C C

= 2.7 V to 6.0 V;

HD4074618: V

= 3.0 V to 5.5 V, GND = 0.0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test
Condition

Notes

Input high
voltage

RESET,

SCK

INT

0.9V

+ 0.3

OSC

0.3

+ 0.3

External clock
operation

0.9V

+ 0.3

Input low
voltage

RESET,

SCK

INT

0.3

0.1V

OSC

0.3

External clock
operation

0.3

0.1V

Output high
voltage

SCK

, TIMO, SO

1.0

= 0.5 mA

Output low
voltage

SCK

, TIMO, SO

0.4

= 0.4 mA

I/O leakage
current

RESET,

SCK

INT

SI,

SO, TIMO, OSC

= 0 to V

Stop mode
retaining
voltage

STOP

No 32-kHz
oscillator

Current
dissipation in

CC1

400

1000

= 3 V

OSC

= 400 kHz

active mode

CC2

500

1500

= 3 V

DTMF: active
f

OSC

= 400 kHz

CC3

= 3 V

OSC

= 400 kHz

, D

analog input
mode

Current
dissipation in
standby
mode

SBY

200

500

= 3 V

LCD on
f

OSC

= 400 kHz

Current
dissipation in
stop mode

STOP

= 3 V

No 32-kHz
oscillator

HD404618 Series

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test
Condition

Notes

Current
dissipation in
subactive
mode

SUB

100

= 3 V

LCD on

Current
dissipation in
watch mode
(1)

WTC1

= 3 V

LCD off

Current
dissipation in
watch mode
(2)

WTC2

= 3 V

LCD on

Comparator
input
reference
voltage
scope

ref

1.2

Notes: 1. Output buffer current is excluded.

2. I

is the source current when no I/O current is flowing while the MCU is in reset state.

Test conditions:

MCU: Reset

Pins: RESET,

TEST

at V

3. I

SBY

is the source current when no I/O current is flowing while the MCU timer is in operation.

Test conditions:

, D

in digital input mode

DTMF in operation (excludes current flowing from VT

ref

to GND)

4. Pins D

and D

are in analog input mode and I/O current is not flowing.

Test conditions:

ref

, COMP0/D

, COMP1/D

at GND

DTMF stopped

5. Timer is in operation and I/O current is not flowing.

Test conditions:

MCU:

I/O in reset state

Serial interface stopped

, D

in digital input mode

DTMF stopped

Stanby mode

Pins :

RESET at GND

TEST

at V

6. Applies only to HD404612, HD404614, HD404616, and HD404618.

7. RAM data retention.

HD404618 Series

I/O Characteristics for Standard Pins (HD404612, HD404614, HD404616, HD404618: V

= 2.7 V to

6.0 V; HD4074618: V

= 3.0 V to 5.5 V, GND = 0.0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Test Conditions

Unit Notes

Input high
voltage

R0 R3

0.7V

+ 0.3

Input low
voltage

R0R3

0.3

0.3V

Output high
voltage

R0R3

1.0 --

= 0.5 mA

Pull-up MOS
current

R0R3

= 3 V,

= 0 V

Output low
voltage

R0R3

0.4

= 0.4 mA

I/O leakage
current

to D

R0 to R3

HD404612,
HD404614
HD404616,
HD404618:
V

= 0 V to V

HD4074618:
V

= 0 V to V

Input high
voltage

IHA

, D

(analog
compare mode)

ref

0.1

Input low
voltage

ILA

, D

(analog
compare mode)

ref

0.1

Note: 1. Output buffer current is excluded.

2. The Max value for the HD404618, HD404616, HD404614, and HD404612 is 1

HD404618 Series

I/O Characteristics for High-Current Pins (HD404612, HD404614, HD404616, HD404618: V

= 2.7

V to 6.0 V; HD4074618: V

C C

= 3.0 V to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise

specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Test Conditions Unit

Notes

Input high
voltage

0.7V

+ 0.3

Input low
voltage

0.3

0.3V

Output high
voltage

1.0 --

= 0.5 mA

Pull-up MOS
current

= 3 V,

= 0 V

Output low
voltage

2.0

= 15 mA

= 4.5 V to 6 V

0.4

= 0.4 mA

I/O leakage
current

= 0 to V

Note: 1. Output buffer current is excluded.

LCD Circuit Characteristics (HD404612, HD404614, HD404616, HD404618: V

= 2.7 V to 6.0 V;

HD4074618: V

= 3.0 V to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Test Condition

Unit

Notes

Segment driver
voltage drop

SEG1
SEG32

0.6

= 3

Common driver
voltage drop

COM1
COM4

0.3

= 3

LCD power
supply division
resistor

Well

100

300

900

Between V

and GND

LCD voltage

LCD

2.7

HD404612, HD404614,
HD404616, HD404618

3.0

HD4074618

Notes: 1. V

and V

are the voltage drops from power supply pins V

, V

, and V

, and GND to each

segment pin and each common pin.

2. When V

LCD

is supplied from an external source, the following relations must be retained:

GND

HD404618 Series

DTMF Characteristics (HD404612, HD404614, HD404616, HD404618: V

C C

= 2.7 V to 6.0 V;

HD4074618: V

= 3.0 V to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Test Conditions

Unit

Notes

Tone output
voltage (1)

TONER

500

660

ref

GND = 2.0 V,

= 100 k

rms

Tone output
voltage (2)

TONEC

520

690

ref

GND = 2.0 V,

= 100 k

rms

Tone output
distortion

%DIS

Short circuit between
TONER and TONEC,
R

= 100 k

Tone output
ratio

2.5

Short circuit between
TONER and TONEC,
R

= 100 k

Notes: 1. See figure 48.

2. See figure 49.

HD404618 Series

AC Characteristics (HD404612, HD404614, HD404616, HD404618: V

C C

= 2.7 V to 6.0 V;

HD4074618: V

= 3.0 V to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Test Condition

Unit

Notes

Clock
oscillation
frequency

OSC

400

1/4 division

kHz

800

kHz

X1, X2

32.768

kHz

Instruction
cycle time

cyc

OSC

/ f

= 400 kHz

OSC

/ f

= 800 kHz

Oscillator
stabilization
time

OSC

7.5

OSC

= 400 kHz

7.5

OSC

= 800 kHz

X1, X2

= 10 to +60

External
clock
frequency

OSC

400

kHz

800

kHz

External
clock high
width

CPH

OSC

1100

= 400 kHz

550

= 800 kHz

External
clock low
width

CPL

OSC

1100

= 400 kHz

550

= 800 kHz

External
clock rise
time

CPr

OSC

150

= 400 kHz

= 800 kHz

External
clock fall time

CPf

OSC

150

= 400 kHz

= 800 kHz

INT

high

width

INT

cyc

subcyc

4, 6

INT

low

width

INT

cyc

subcyc

4, 6

INT

high

width

INT

cyc

HD404618 Series

Item

Symbol

Pin(s)

Min

Typ

Max

Test Condition

Unit

Notes

INT

low

width

INT

cyc

RESET high
width

RSTH

RESET

cyc

Input
capacitance

HD4074618:
f = 1 MHz,
V

= 0 V

All pins
except D

f = 1 MHz,
V

= 0 V

RESET fall
time

RSTf

Analog
comparator
stabilization
time

CSTB

, D

(analog input
mode)

cyc

Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize after V

reaches 2.7 V (3.0 V for HD4074618) at power-on or after RESET input goes high after stop
mode is cancelled. At power-on or when stop mode is cancelled, RESET must remain high for
at least t

to ensure the oscillation stabilization time. Since t

depends on the ceramic

oscillator's circuit constant and stray capacitance, contact the manufacturer when designing a
reset circuit.

2. The oscillation stabilization time is the period required for the oscillator to stabilize after V

reaches 2.7 V (3.0 V for HD4074618) at power-on. The oscillation stabilization time (t

) must be

ensured. If using a crystal oscillator, contact the manufacturer to determine what oscillation
stabilization time is required, since it depends on the circuit constants and stray capacitances.

3. See figure 50.

4. See figure 51. The unit t

cyc

applies when the MCU is in standby mode or active mode.

5. See figure 52.

6. The unit t

subcyc

applies when the MCU is in watch mode or subactive mode.

subcyc

= 244.14

s (32.768-kHz crystal oscillator)

7. The analog comparator stabilization time is the period required for the oscillator to stabilize and

for correct data to be read after D

is input to enter analog input mode.

8. The Max value for the HD404618, HD404616, HD404614, and HD404612 is 15pF.

HD404618 Series

Serial Interface Timing Characteristics (HD404612, HD404614, HD404616, HD404618: V

= 2.7 V

to 6.0 V; HD4074618: V

= 3.0 V to 5.5 V, GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

During Transmit Clock Output

Item

Symbol

Pin(s)

Min

Typ

Max

Test Condition Unit

Notes

Transmit clock
cycle time

Scyc

SCK

Load shown in
figure 54

cyc

subcyc

1, 3

Transmit clock
high width

SCKH

SCK

0.5

Load shown in
figure 54

Scyc

Transmit clock
low width

SCKL

SCK

0.5

Load shown in
figure 54

Scyc

Transmit clock
rise time

SCKr

SCK

200

Load shown in
figure 54

Transmit clock
fall time

SCKf

SCK

200

Load shown in
figure 54

Serial output
data delay time

DSO

500

Load shown in
figure 54

Serial input data
setup time

SSI

300

Serial input data
hold time

HSI

300

HD404618 Series

During Transmit Clock Input

Item

Symbol

Pin(s)

Min

Typ

Max

Test Condition Unit

Notes

Transmit clock
cycle time

Scyc

SCK

cyc

subcyc

1, 3

Transmit clock
high width

SCKH

SCK

0.5

Scyc

Transmit clock
low width

SCKL

SCK

0.5

Scyc

Transmit clock
rise time

SCKr

SCK

200

Transmit clock
fall time

SCKf

SCK

200

Serial output
data delay time

DSO

500

Load shown in
figure 54

Serial input data
setup time

SSI

300

Serial input data
hold time

HSI

300

Transmit clock
completion
detect time

SCKHD

SCK

cyc

subcyc

1, 2, 3

Notes: 1. See figure 53.

2. The transmit clock completion detect time is the high level period after eight transmit clock

pulses have been input. The serial interrupt request flag is not set if the next transmit clock is
input before the transmit clock completion detect time has passed.

3. The unit t

subcyc

applies when the MCU is in subactive mode.

subcyc

= 244.14

s (32.768-kHz crystal oscillator)

TONEC

TONER

R = 100 k

Figure 48 Tone Output Load Circuit

HD404618 Series

TONEC

TONER

R = 100 k

Figure 49 Distortion and dB

Load Circuit

CPr

CPf

V 0.3 V

0.3 V

OSC

CPH

CPL

1/f

Figure 50 Oscillator Timing

0.9V

0.1V

INT

Figure 51 Interrupt Timing

RESET

RSTf

RSTH

0.9V

0.1V

Figure 52 Reset Timing

0.9V

0.1V

DSO

SCKf

SCKL

SSI

HSI

Scyc

SCKr

SCKH

0.4 V

V 0.5 V

V 1.0 V (0.9V )

0.4 V (0.1V )

SCK

SCKHD

After 8 transmit clock
pulses are input

V 1.0 V and 0.4 V are the threshold voltages for transmit clock output.
0.9V and 0.1V are threshold voltages for transmit clock input.

Note:

Figure 53 Serial Interface Timing

HD404618 Series

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 8-kword version
(HD404618). An 8-kword data size is required to change ROM data to mask manufac turing data since the
program used is for a 8-kword version.

This limitation applies when using an EPROM or a data base.

Vector

address

Zero-page
subroutine

(64 words)

Pattern &

program

(2,048 words)

Not used

Vector

address

Zero-page
subroutine

(64 words)

Pattern &

program

(4,096 words)

Not used

ROM 2-kword version:
HD404612
Address $0800$1FFF

$0000

$000F
$0010

$003F
$0040

$07FF
$0800

$1FFF

$0000

$000F
$0010

$003F
$0040

$0FFF
$1000

$1FFF

Fill this area with 1s

ROM 4-kword version:
HD404614
Address $1000$1FFF

Vector

address

Zero-page
subroutine

(64 words)

Pattern &

program

(6,144 words)

Not used

$0000

$000F
$0010

$003F
$0040

$17FF
$1800

$1FFF

ROM 6-kword version:
HD404616
Address $1800$1FFF

HD404618 Series

HD404612, HD404614, HD404616, HD404618 Option List

Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTATTM version).

5. ROM Code Media

7. Stop Mode

Used

Not used

8. Package

FP-80A

FP-80B

TFP-80

EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are

programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are

programmed to different EPROMS.

6. System oscillator (OSC1 and OSC2)

Ceramic oscillator

External clock

f =

MHz

Date of order

Customer

Department

ROM code name

LSI number
(to be filled in
by HITACHI)

/ /

1. ROM Size

Please check off the appropriate applications and
enter the necessary information.

HD404612

HD404614

HD404616

HD404618

2-kword

4-kword

6-kword

8-kword

2. Optional Functions

Note:

Options marked with an asterisk require a subsystem
crystal oscillator

With 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, without time-base

HD404618 Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404618

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404618