Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but

there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire

or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i)

placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or

mishap.

Notes regarding these materials

These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation

product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any

other rights, belonging to Renesas Technology Corporation or a third party.

Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,

originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in

these materials.

All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents

information on products at the time of publication of these materials, and are subject to change by Renesas Technology

Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact

Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product

information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these

inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corporation by various means, including the

Renesas Technology Corporation Semiconductor home page (http://www.renesas.com).

When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and

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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is

prohibited.

Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

HD404629R Series

AS Microcomputer Incorporating a DTMF Generator Circuit

ADE-202-048D

Rev.5.0

Sept. 1999

Description

The HD404629R Series is part of the HMCS400-Series microcomputers designed to increase program
productivity and also incorporate large-capacity memory. Each microcomputer has a high precision dual-
tone multifrequency (DTMF) generator, LCD controller/driver, A/D converter, input capture circuit, 32-
kHz oscillator for clock, and four low-power dissipation modes.

The HD404629R Series includes four chips: the HD404628R with 8-kword ROM; the HD4046212R with
12-kword ROM; the HD404629R with 16-kword ROM; the HD4074629 with 16-kword PROM.

A program can be written to the PROM by a PROM writer, which can dramatically shorten system
development periods and smooth the process from debugging to mass production.

Features

1,876-digit

4-bit RAM

44 I/O pins, including 10 high-current pins (15 mA, max.) and 20 pins multiplexed with LCD segment
pins

Four timer/counters

8-bit input capture circuit

Three timer outputs (including two PWM out-puts)

Two event counter inputs (including one double-edge function)

Clock-synchronous 8-bit serial interface

A/D converter (4 channels

8 bits)

LCD controller/driver (52 segments

4 commons)

On-chip DTMF generator

Built-in oscillators

Main clock: 4-MHz ceramic (an external clock is also possible)

Subclock: 32.768-kHz crystal

Eleven interrupt sources

Five by external sources, including three double-edge functions

Six by internal sources

Subroutine stack up to 16 levels, including interrupts

HD404629R Series

Ordering Information

Type

Product Name

Model Name

ROM (Words)

Package

Mask ROM

HD404628R

HD404628RH

8,192

100-pin plastic QFP
(FP-100B)

HD404628RFS

100-pin plastic QFP
(FP-100A)

HD404628RTF

100-pin plastic TQFP
(TFP-100B)

HD4046212R

HD4046212RH

12,288

100-pin plastic QFP
(FP-100B)

HD4046212RFS

100-pin plastic QFP
(FP-100A)

HD4046212RTF

100-pin plastic TQFP
(TFP-100B)

HD404629R

HD404629RH

16,384

100-pin plastic QFP
(FP-100B)

HD404629RFS

100-pin plastic QFP
(FP-100A)

HD404629RTF

100-pin plastic TQFP
(TFP-100B)

ZTAT

HD4074629

HD4074629H

16,384

100-pin plastic QFP
(FP-100B)

HD4074629FS

100-pin plastic QFP
(FP-100A)

HD4074629TF

100-pin plastic TQFP
(TFP-100B)

ZTAT

: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Cautions about operaton!

Like the ZTAT

HD4074629 and the HD404629 Series, the HD404629R Series has been verified to fully

meet the standard electrical characteristics described in the data sheet or other related documents. However,
due to differences in the manufacturing process, the type of built-in ROMs used, and internal wiring
patterns, the HD404629R Series has different power factors, operating margins, and noise margins.

Therefore, you should test both of your systems incorporating the ZTAT

and mask ROM versions. When

your system is modified to use an HD404629R Series in place of a conventional chip, you should also
perform a similar evaluation test to verify performance of your new system.

HD404629R Series

List of Functions

Product name

HD404628R

HD4046212R

HD404629R

HD4074629

ROM (Words)

8,192

12,288

16,384

16,384 PROM

RAM (Digits)

1,876

I/O

44 (max)

Large-current I/O pins

10 (Sink 15 mA max)

LCD segment multiplexed pins

Timer / Counter

Input capture

8 bit

Timer output

3 (PWM output possible for 2)

Event input

2 (edge selection possible for 1)

Serial interface

1 (8-bit syncronous)

DTMF generation circuit

Available

A/D converter

8 bit

4 channels

LCD controller / driver circuit

Max. 52 seg

4 com

Interrupts

External

5 (edge selection possible for 3)

Internal

Low-Power Dissipation Mode

Stop mode

Available

Watch mode

Available

Standby mode

Available

Subactive mode

Available

Main Oscillator

Ceramic oscillation

400 kHz, 800 kHz, 2 MHz, 4 MHz

Crystal oscillation

400 kHz, 800 kHz, 2 MHz, 4 MHz

Sub oscillator

Crystal oscillation

32.768 kHz

Minimum instruction execution time

s (f

OSC

= 4 MHz)

Operating voltage (V)

2.7 to 6.0

2.7 to 5.5

Package

100-pin plastic QFP (FP-100B)

100-pin plastic QFP (FP-100A)

100-pin plastic TQFP (TFP-100B)

Guaranteed operation temperature
(°C)

20 to +75

HD404629R Series

Pin Arrangement

FP-100B

TFP-100B

AN
AN
AN
AN

TEST

OSC
OSC

RESET

X1
X2

GND

D
D
D
D
D
D
D
D
D
D

D /

STOPC

INT

SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
R7 /SEG20
R7 /SEG19
R7 /SEG18
R7 /SEG17
R6 /SEG16
R6 /SEG15
R6 /SEG14

R0 /

INT

R0 /INT

R1 /TOB

R1 /TOC

R1 /TOD

R1 /

EVNB

R2 /EVND

R2 /

SCK

R2 /SI

R2 /SO

R3 /SEG1

R3 /SEG2

R3 /SEG3

R3 /SEG4

R4 /SEG5

R4 /SEG6

R4 /SEG7

R4 /SEG8

R5 /SEG9

R5 /SEG10

R5 /SEG11

R5 /SEG12

R6 /SEG13

TONER

TONEC

COM4

COM3

COM2

COM1

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

Top view

100

ref

HD404629R Series

Pin Arrangement

FP-100A

TONER

AN
AN
AN
AN

TEST

OSC
OSC

RESET

X1
X2

GND

D
D
D
D
D
D
D
D
D
D

D /

STOPC

D /

INT

R0 /

INT

R0 /INT
R0 /INT

SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
R7 /SEG20
R7 /SEG19
R7 /SEG18
R7 /SEG17
R6 /SEG16
R6 /SEG15
R6 /SEG14
R6 /SEG13
R5 /SEG12

R0 /INT

R1 /TOB

R1 /TOC

R1 /TOD

R1 /

EVNB

R2 /EVND

R2 /

SCK

R2 /SI

R2 /SO

R3 /SEG1

R3 /SEG2

R3 /SEG3

R3 /SEG4

R4 /SEG5

R4 /SEG6

R4 /SEG7

R4 /SEG8

R5 /SEG9

R5 /SEG10

R5 /SEG11

TONEC

COM4

COM3

COM2

COM1

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

100

ref

HD404629R Series

Pin Description

Pin Number

Item

Symbol

FP-100B
TFP-100B

FP-100A

I/O

Function

Power

Applies power voltage

supply

GND

Connected to ground

Test

TEST

Used for factory testing only: Connect this pin
to V

Reset

RESET

Resets the MCU

Oscillato
r

OSC

Input/output pins for the internal oscillator
circuit:

OSC

Connect them to a ceramic oscillator ,crystal
oscillator or connect OSC

to an external

oscillator
curcuit

Used for a 32.768-kHz crystal for clock
purposes.

If not to be used, fix the X1 pin to V

and

leave
the X2 pin open.

Port

1423

1625

I/O

Input/output pins addressed by individual bits;
pins D

are high-current pins that can each

supply up to 15 mA

, D

24, 25

26, 27

Input pins addressable by individual bits

2657

2859

I/O

Input/output pins addressable in 4-bit units

Interrupt

INT

2529

2731

Input pins for external interrupts

Stop clear

STOPC

Input pin for transition from stop mode to active
mode

Serial

SCK

I/O

Serial interface clock input/output pin

interface

Serial interface receive data input pin

Serial interface transmit data output pin

Timer

TOB, TOC,
TOD

3032

3234

Timer output pins

EVNB

, EVND

33, 34

35, 36

Event count input pins

LCD

, V

9496

9698

Power pins for LCD controller/driver; may be left
open during operation since they are connected by
internal voltage division resistors.
Voltage conditions are: V

GND

COM1COM4

9093

9295

Common signal pins for LCD

SEG1SEG52

3889

4091

Segment signal pins for LCD

HD404629R Series

Block Diagram

: High current pins

RESET

TEST

STOP

OSC

GND

HMCS400 CPU

ROM

RAM

Timer A

8-bit free-running timer

Timer B

8-bit free-running / reload timer

TOC

EVNB

TOB

AVcc
AVss
AN0
AN1
AN2
AN3

COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3

SEG52

A/D converter

4 channels x 8 bits

External interrupt

control circuit

INT

INT2
INT3
INT4

R6 Port

R5 Port

R4 Port

R3 Port

R2 Port

R1 Port

R0 Port

D Port

R7 Port

EVND
TOD

Clock-synchronous

8-bit serial interface

SCK

SI
SO

LCD controller / driver

circuit

52 segments x 4 commons

DTMF

generation circuit

ref

TONER
TONEC

Timer C

8-bit free-running / reload timer

Timer D

8-bit free-running / reload timer

HD404629R Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

$000F

$0FFF

$3FFF

$003F

Vector address

(16 words)

Zero-page subroutine

(64 words)

Pattern

(4,096 words)

HD404628R

Program

(8,192 words)

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007

$0008
$0009

$000A
$000B

$000C
$000D

$000E
$000F

JMPL instruction

(jump to RESET,

STOPC

routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B, INT routine)

JMPL instruction

(jump to timer C, INT routine)

JMPL instruction

(jump to timer D, INT routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to A/D, serial routine)

$1FFF

$2FFF

HD4046212R

Program

(12,288 words)

HD404629R, HD4074629

Program

(16,384 words)

$0010

$0040

$1000

$2000

$3000

ROM address

Figure 1 ROM Memory Map

Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.

Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000$1FFF: HD404628R; $0000$2FFF: HD4046212R; $0000$3FFF;
HD404629R, HD4074629): Used for program coding.

HD404629R Series

RAM Memory Map

The MCU contains a 1,876-digit

4-bit RAM area consisting of a memory register area, an LCD data area,

a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register
flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above
areas. The RAM memory map is shown in figure 2 and described below.

RAM-Mapped Register Area ($000$03F):

Interrupt Control Bits Area ($000$003)

This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

Special Function Register Area ($004$01F, $024$03F)

This area is used as mode registers and data registers for external interrupts, serial interface,
timer/counters, LCD, A/D converter, and as data control registers for I/O ports. The structure is shown
in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). The SEM, SEMD, REM, and REMD instructions can be used for the LCD control
register (LCR: $01B), but RAM bit manipulation instructions cannot be used for other registers.

This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.

HD404629R Series

A/D mode register (AMR)

Data

(464 digits)

V = 1

(bank = 1)

$000

$040

$050

$003

$004

$005

$006

$007

$008
$009

$00A
$00B

$00C

$00D

$00E
$00F

$010

$011
$012

$013
$014

$020
$023

$032
$033

$034
$035
$036
$037
$038

$03F

$00A

$00B

$00E

$00F

R/W

W
W

W
W
W
W

W
W
W

R/W

R/W
R/W

R/W

$090

$25F

$3C0

$260

RAM-mapped register area

Memory registers (10 digits)

LCD display area (52 digits)

Not used

Data (464 digits 3)
V = 0 (bank 0)
V = 1 (bank 1)
V = 2 (bank 2)

Data (352 digits)

Stack (64 digits)

Interrupt control bits area

Port mode register A (PMRA)
Serial mode register A (SMRA)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)

Timer B (TRBL/TWBL)
(TRBU/TWBU)

Miscellaneous register (MIS)

Timer mode register C1 (TMC1)
Timer C (TRCL/TWCL)
(TRCU/TWCU)

Timer mode register B2 (TMB2)

Timer mode register D2 (TMD2)

Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)

Port D

DCR (DCD0)

Port D

DCR (DCD1)

Port D

and D

DCR (DCD2)

Not used

V register (V)

Data

(464 digits)

V = 0

(bank = 0)

The data area has three banks:
bank 0 (V = 0) to bank 2 (V = 2).
Two registers are mapped
on the same area.

Timer read register B lower (TRBL)

Timer read register B upper (TRBU)

Timer read register C lower (TRCL)

Timer read register C upper (TRCU)

Timer write register B lower (TWBL)

Timer write register B upper (TWBU)

Timer write register C lower (TWCL)

Timer write register C upper (TWCU)

R:
W:
R/W:

$090

Read only
Write only
Read/write

Data

(464 digits)

V = 2

(bank = 2)

Notes: 1.

$011

$012

17
18

Timer read register D lower (TRDL)

Timer read register D upper (TRDU)

Timer write register D lower (TWDL)

Timer write register D upper (TWDU)

$084

Timer mode register D1 (TMD1)

R/W

Timer D (TRDL/TWDL)
(TRDU/TWDU)

Timer mode register C2 (TMC2)

$015
$016

A/D data register lower (ADRL)

$017

$024
$025
$026
$027
$028
$029
$02A
$02B

$018

$019
$01A
$01B

$01C
$01D
$01E
$01F

$3FF

A/D data register upper (ADRU)

LCD control register (LCR)

LCD mode register (LMR)
LCD output register 1 (LOR1)
LCD output register 2 (LOR2)
LCD output register 3 (LOR3)

Port mode register B (PMRB)
Port mode register C (PMRC)

Detection edge select register 1 (ESR1)

Detection edge select register 2 (ESR2)

Serial mode register B (SMRB)
System clock select register (SSR)

Not used

Port R4 DCR (DCR4)
Port R5 DCR (DCR5)
Port R6 DCR (DCR6)
Port R7 DCR (DCR7)

W
W
W
W

$03E

$02C
$02D
$02E
$02F

$031

$030

R/W
R/W

R/W

TG mode register (TGM)
TG control register (TGC)

W
W

RAM address

Figure 2 RAM Memory Map

HD404629R Series

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

IMAD

(IM of A/D)

IFAD

(IF of A/D)

IMTD

(IM of timer D)

IFTD

(IF of timer D)

$000

$001

$002

$003

Interrupt control bits area

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

IM3

(IM of INT

)

IF3

(IF of INT

)

IM2

(IM of INT

)

IF2

(IF of INT

)

IMS

(IM of serial

interface)

IFS

(IF of serial

interface)

IM4

(IM of INT

)

IF4

(IF of INT

)

$020

$021

$022

$023

DTON

(Direct transfer

on flag)

ADSF

(A/D start flag)

WDON

(Watchdog

on flag)

LSON

(Low speed

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

Not used

IF:
IM:
IE:
SP:

Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

LSON

ICSF
ICEF

RAME

RSP

WDON

ADSF

Not used

DTON

SEM/SEMD

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Allowed

Inhibited

Allowed

Not executed in active mode

Allowed

Used in subactive mode

Not executed

Inhibited

Note: WDON is reset by MCU reset or by

STOPC

enable for stop mode cancellation.

The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404629R Series

$000

$003

PMRA $004

SMRA $005

SRL $006

SRU $007

TMA $008

TMB1 $009

TRBL/TWBL $00A

TRBU/TWBU $00B

MIS $00C

TMCI $00D

TRCL/TWCL $00E

TRCU/TWCU $00F

TMDI $010

TRDL/TWDL $011

TRDU/TWDU $012

TMB2 $013

TMC2 $014

TMD2 $015

AMR $016

ADRL $017

ADRU $018

TGM $019

TGC $01A

LCR $01B

LMR $01C

LOR1 $01D

LOR2 $01E

LOR3 $01F

$020

$023

PMRB $024

PMRC $025

ESR1 $026

ESR2 $027

SMRB $028

SSR $029

DCD0 $02C

DCD1 $02D

DCD2 $02E

DCR0 $030

DCR1 $031

DCR2 $032

DCR3 $033

DCR4 $034

DCR5 $035

DCR6 $036

DCR7 $037

V $03F

Bit 3

Bit 2

Bit 1

Interrupt control bits area

Not used

/SI

/SO

Serial transmit clock speed selection

Serial data register (lower digit)

Serial data register (upper digit)

Clock source setting (timer A)

Clock source setting (timer B)

Timer B register (lower digit)

Timer B register (upper digit)

R23/SO PMOS control

Interrupt frame period selection

Clock source setting (timer C)

Timer C register (lower digit)

Timer C register (upper digit)

Clock source setting (timer D)

Timer D register (lower digit)

Timer D register (upper digit)

Not used

Timer-B output mode selection

Not used

Timer-C output mode setting

Timer-D output mode setting

Not used

Analog channel selection

A/D data register (lower digit)

A/D data register (upper digit)

Not used

LCD duty cycle selection

LCD input clock source selection

/SEG4

/SEG8

Not used

/SEG3

/SEG7

R7/SEG1720

/SEG2

/SEG6

R6/SEG1316

/SEG1

/SEG5

R5/SEG912

/INT

/EVND

INT

detection edge selection

INT

detection edge selection

INT

detection edge selection

EVND detection edge selection

Not used

Port D

DCR

Port D

DCR

Not used

Port D

DCR

Port D

DCR

Not used

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Not used

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Not used

Bank 0 to bank 2 selection

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.

/INT

STOPC

/INT

INT

EVNB

SCK

Bit 0

Clock select

Timer-A/time-base
Auto-reload on/off
Pull-up MOS control
Input capture selection
A/D conversion time
TONEC output control
TONER output control
Display on/off in watch mode
LCD power switch
LCD display on/off
SO idle H/L setting
Transmit clock source selection
32-kHz oscillation stop setting
32-kHz oscillation division ratio

Notes:

TONEC output frequency

TONER output frequency

DTMF enable

Not used

RAM address

Figure 5 Special Function Register Area

HD404629R Series

Memory Register (MR) Area ($040$04F): Consisting of 16 addresses, this area (MR0MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.

Memory registers

$040

$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F

$3C0

$3FF

MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)

Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1

MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)

Bit 3

Bit 2

Bit 1

Bit 0

PC PC :
ST: Status flag
CA: Carry flag

Program counter

Stack area

$3FC

$3FD

$3FE

$3FF

Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

HD404629R Series

LCD Data Area ($050$083): Used for storing 52-digit LCD data which is automatically output to LCD
segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Refer to
the LCD description for details.

Data Area ($090$3BF): 464 digits from $090 to $25F have three banks, which can be selected by setting
the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure
7). The area from $260 to $3BF is accessed without setting the bank register.

Bit

Initial value

Read/Write

Bit name

Not used

R/W

Bank area selection

Bank 0 is selected

Bank 1 is selected

Bank 2 is selected

Not Used

Note: After reset, the value in the bank register is 0, and therefore bank 0 is

selected. If V1 = 1 and V0 = 1, no bank is selected, and the operation is not
guaranteed.

Bank register (V: $03F)

Figure 7 Bank Register (V)

Stack Area ($3C0$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404629R Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described
below.

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter
Initial value: $0000,
R/W not possible

Stack pointer
Initial value: $3FF, R/W not possible

Initial value: Undefined, R/W

Initial value: 1, R/W not possible

Figure 8 Registers and Flags

Accumulator (A) and B Register (B): A and B are 4-bit registers, and are used to hold the results of ALU
(arithmetic and logical unit) operations and to transfer data between memory, I/O ports, and other registers.

W Register (W), X Register (X), and Y Register (Y): W is a 2-bit register and X and Y are 4-bit
registers. These registers are used in RAM register indirect addressing. The Y register is also used in D port
addressing.

HD404629R Series

SPX Register (SPX) and SPY Register (SPY): The SPX and SPY registers are 4-bit registers used to
supplement the X and Y registers.

Carry Flag (CA): CA is a 1-bit flag that stores ALU overflow generated by an arithmetic operation. CA is
set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred.
CA is also affected by the carry set/carry clear instructions (SEC and REC), and by the rotate with carry
instructions (ROTL and ROTR).

During interrupt handling, CA is saved on the stack, and is restored from the stack by the RTNI instruction.

Status Flag (ST): ST is a 1-bit flag that stores the results of arithmetic instructions, compare instructions,
and bit test instructions, and is used as the branch condition for the BR, BRL, CAL, and CALL conditional
branch instructions.

The contents of the ST flag are held until the next arithmetic, compare, bit test, or conditional branch
instruction is executed. After the execution of a conditional branch instruction, the value of ST is set to 1
without regard to the condition.

During interrupt handling, ST is saved on the stack, and is restored from the stack by the RTNI instruction.

Program Counter (PC): The PC is a 14-bit counter that indicates the ROM address of the next instruction
the CPU will execute.

Stack Pointer (SP): The SP is a 10-bit register that indicates the RAM address of the next stack frame in
the stack area.

The SP is initialized to $3FF by a reset. The SP is decremented by 4 by a subroutine call or by interrupt
handling, and is incremented by 4 when the saved data has been restored by a return instruction.

The upper 4 bits of the SP are fixed at 1111; the maximum number of stack levels is thus 16.

In addition to the reset method described above, the SP can also be initialized to $3FF by clearing the reset
stack pointer (RSP) in the interrupt control bits area with a RAM bit manipulation instruction, i.e., REM or
REMD.

Reset

The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one t

to enable the oscillator to stabilize. During operation,

RESET must be high for at least two instruction cycles.

Initial values after MCU reset are listed in table 1.

HD404629R Series

Table 1 Initial Values After MCU Reset

Item

Abbr.

Initial
Value

Contents

Program
counter

(PC)

$0000

Indicates program execution point from start

address of ROM area

Status flag

(ST)

Enables conditional branching

Stack pointer

(SP)

$3FF

Stack level 0

Interrupt

Interrupt enable flag

(IE)

Inhibits all interrupts

flags/mask

Interrupt request flag

(IF)

Indicates there is no interrupt request

Interrupt mask

(IM)

Prevents (masks) interrupt requests

I/O

Port data register

(PDR)

All bits 1

Enables output at level 1

Data control register

(DCD0,
DCD1)

All bits 0

Turns output buffer off (to high impedance)

(DCD2)

- - 00

(DCR0,
DCR7)

All bits 0

Port mode register A

(PMRA)

- - 00

Refer to description of port mode register A

Port mode register B

(PMRB)

0000

Refer to description of port mode register B

Port mode register C
bits 3, 1, 0

(PMRC3,
PMRC1,
PMRC0)

000

Refer to description of port mode register C

Detection edge select
register 1

(ESR1)

0000

Disables edge detection

Detection edge select
register 2

(ESR2)

0000

Disables edge detection

Timer/

Timer mode register A

(TMA)

0000

Refer to description of timer mode register A

counters,

Timer mode register B1

(TMB1)

0000

Refer to description of timer mode register B1

serial

Timer mode register B2

(TMB2)

- - 00

Refer to description of timer mode register B2

interface

Timer mode register C1

(TMC1)

0000

Refer to description of timer mode register C1

Timer mode register C2

(TMC2)

- 000

Refer to description of timer mode register C2

Timer mode register D1

(TMD1)

0000

Refer to description of timer mode register D1

Timer mode register D2

(TMD2)

0000

Refer to description of timer mode register D2

Serial mode register A

(SMRA)

0000

Refer to description of serial mode register A

Serial mode register B

(SMRB)

- - X0

Refer to description of serial mode register B

Prescaler S

(PSS)

$000

Prescaler W

(PSW)

$00

Timer counter A

(TCA)

$00

Timer counter B

(TCB)

$00

Timer counter C

(TCC)

$00

Timer counter D

(TCD)

$00

HD404629R Series

Table 1 Initial Values After MCU Reset (cont)

Item

Abbr.

Initial
Value

Contents

Timer/
counters,

Timer write register B

(TWBU,
TWBL)

$X0

serial
interface

Timer write register C

(TWCU,
TWCL)

$X0

Timer write register D

(TWDU,
TWDL)

$X0

Octal counter

(OC)

000

A/D

A/D mode register

(AMR)

00 - 0

Refer to description of A/D mode register

A/D data register

(ADRL,
ADRU)

$80

Refer to description of A/D data register

LCD

LCD control register

(LCR)

- 000

Refer to description of LCD control register

LCD mode register

(LMR)

0000

Refer to description of LCD duty-cycle/clock
control register

LCD output register 1

(LOR1)

0000

Sets R-port/LCD segment pins to R port mode

LCD output register 2

(LOR2)

0000

LCD output register 3

(LOR3)

- 000

DTMF

Tone generator mode
register

(TGM)

0000

Refer to description of tone generator mode
register

Tone generator control
register

(TGC)

000 -

Refer to description of tone generator control
register

Bit registers

Low speed on flag

(LSON)

Refer to description of operating modes

Watchdog timer on flag

(WDON)

Refer to description of timer C

A/D start flag

(ADSF)

Refer to description of A/D converter

Direct transfer on flag

(DTON)

Refer to description of operating modes

Input capture status flag

(ICSF)

Refer to description of timer D

Input capture error flag

(ICEF)

Refer to description of timer D

Others

Miscellaneous register

(MIS)

0000

Refer to description of operating modes, I/O, and
serial interface

System clock select
register

(SSR)

0000

Refer to description of operating modes,
oscillation circuits, and DTMF generator

Bank register

(V)

- - 00

Refer to description of RAM memory map

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. indicates that the bit does not exist.

HD404629R Series

Item

Abbr.

Status After Cancel-
lation of Stop Mode by

STOPC

Input

Status After Cancel-
lation of Stop Mode by
RESET Input

Status After all Other Types
of Reset

Carry flag

(CA)

Pre-stop-mode values are not guaranteed;

Pre-MCU-reset values

Accumulator

(A)

values must be initialized by program

are not guaranteed; val-

B register

(B)

ues must be initialized by

W register

(W)

program

X/SPX register

(X/SPX)

Y/SPY register

(Y/SPY)

Serial data register

(SRL, SRU)

RAM

Pre-stop-mode values are retained

RAM enable flag

(RAME)

Port mode
register C bit 2

(PMRC2)

Pre-stop-mode
values are retained

System clock
select register bit 3

(SSR3)

Interrupts

The MCU has 11 interrupt sources: five external signals (

INT

, INT

INT

), four timer/ counters

(timers A, B, C, and D), serial interface, and A/D converter.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.

Some vector addresses are shared by two different interrupts. They are timer B and INT

, timer C and

INT

, timer D and INT

, and A/D converter and serial interface interrupts. So the type of request that has

occurred must be checked at the beginning of interrupt processing.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in
table 3.

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.

The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack

HD404629R Series

Table 3 Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt
Cuntrol Bit

INT

Timer A

Timer B or
INT

Timer C or
INT

Timer D or
INT

A/D or
Serial

IF0 .

IM0

IF1 .

IM1

IFTA .

IMTA

IFTB .

IMTB

+ IF2

IM2

IFTC .

IMTC

+ IF3

IM3

IFTD .

IMTD

+ IF4

IM4

IFAD .

IMAD

+ IFS

IMS

Note:

Bits marked * can be either 0 or 1. Their values have no effect on operation.

Instruction cycles

Instruction

execution

IE reset

Interrupt

acceptance

Execution of JMPL

instruction at vector address

Execution of

instruction at

start address

of interrupt

routine

Vector address

generation

Note:

Stacking

The stack is accessed and the IE reset after the instruction
is executed, even if it is a 2-cycle instruction.

Figure 10 Interrupt Processing Sequence

HD404629R Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.

Table 4 Interrupt Enable Flag (IE: $000, Bit 0)

Interrupt
Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

, INT

INT

): Five external interrupt signals.

External Interrupt Request Flags (IF0IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling
edge of signals input to

INT

and

INT

, and IF2IF4 are set at the rising or falling edge of signals input to

INT

, as listed in table 5. The INT

INT

interrupt edges are selected by the detection edge select

registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13.

Table 5 External Interrupt Request Flags (IF0IF4: $000, $001, $022, $023)

IF0IF4

Interrupt Request

Yes

Bit

Initial value

Read/Write

Bit name

ESR13

ESR12

ESR10

ESR11

Detection edge selection register 1 (ESR1: $026)

ESR11

ESR10

INT

detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

ESR13

ESR12

INT

detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

Figure 12 Detection Edge Selection Register 1 (ESR1)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

ESR23

ESR22

ESR20

ESR21

Detection edge selection register 2 (ESR2: $027)

ESR21

ESR20

INT

detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

ESR23

ESR22

EVND detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

Figure 13 Detection Edge Selection Register 2 (ESR2)

External Interrupt Masks (IM0IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.

Table 6 External Interrupt Masks (IM0IM4: $000, $001, $022, $023)

IM0IM4

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.

Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)

IFTA

Interrupt Request

Yes

HD404629R Series

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.

Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)

IMTA

Interrupt Request

Enabled

Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.

Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)

IFTB

Interrupt Request

Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as listed in table 10.

Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1)

IMTB

Interrupt Request

Enabled

Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.

Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)

IFTC

Interrupt Request

Yes

HD404629R Series

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 12.

Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3)

IMTC

Interrupt Request

Enabled

Disabled (masked)

Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling of signals input to EVND when the input capture function is used, as listed in table 13.

Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)

IFTD

Interrupt Request

Yes

Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 14.

Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1)

IMTD

Interrupt Request

Enabled

Disabled (masked)

Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 15.

Table 15 Serial Interrupt Request Flag (IFS: $023, Bit 2)

IFS

Interrupt Request

Yes

HD404629R Series

Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 16.

Table 16 Serial Interrupt Mask (IMS: $023, Bit 3)

IMS

Interrupt Request

Enabled

Disabled (masked)

A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as listed in
table 17.

Table 17 A/D Interrupt Request Flag (IFAD: $003, Bit 2)

IFAD

Interrupt Request

Yes

A/D Interrupt Mask (IMAD: $003, Bit 3): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 18.

Table 18 A/D Interrupt Mask (IMAD: $003, Bit 3)

IMAD

Interrupt Request

Enabled

Disabled (masked)

HD404629R Series

Operating Modes

The MCU has five operating modes as shown in table 19. The operations in each mode are listed in tables
20 and 21. Transitions between operating modes are shown in figure 14.

Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC

and OSC

Table 19 Operating Modes and Clock Status

Mode Name

Active

Standby

Stop

Watch

Subactive

Activation
method

RESET
cancellation,
interrupt
request,

STOPC

cancellation
in stop mode,
STOP/SBY
instruction in
subactive mode
(when direct
transfer is
selected)

SBY
instruction

STOP
instruction
when
TMA3 = 0

STOP
instruction
when
TMA3 = 1

INT

or timer A

interrupt request
from watch
mode

Status

System
oscillator

Stopped

Subsystem
oscillator

OP*1

Cancellation
method

RESET input,
STOP/SBY
instruction

RESET input,
interrupt
request

RESET input,

STOPC

input

in stop mode

RESET input,

INT

or timer A

interrupt
request

RESET input,
STOP/SBY
instruction

Notes:

OP implies in operation.

1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select

2. Subactive mode is an optional function; specify it on the function option list.

HD404629R Series

Table 20 Operations in Low-Power Dissipation Modes

Function

Stop Mode

Watch Mode

Standby Mode

Subactive Mode

CPU

Reset

Retained

RAM

Retained

Timer A

Reset

Timer B

Reset

Stopped

Timer C

Reset

Stopped

Timer D

Reset

Stopped

Serial interface

Reset

Stopped

A/D

Reset

Stopped

LCD

Reset

DTMF

Reset

Stopped

Reset

I/O

Reset

Retained

Notes: OP implies in operation.

Output pins are at high impedance.

Subactive mode is an optional function specified on the function option list.

Transmission/Reception is activated if a clock is input in external clock mode. However,
interrupts stop.

When a 32-kHz clock source is used.

Table 21 I/O Status in Low-Power Dissipation Modes

Output

Input

Standby Mode,
Watch Mode

Stop Mode

Active Mode,
Subactive Mode

Retained

High impedance

Input enabled

R0R7

Retained or output
of peripheral functions

High impedance

Input enabled

HD404629R Series

Reset by

RESET input or

by watchdog timer

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Stop
Oscillate
f

SUB

OSC

CPU

CLK

PER

Stop
Stop
Stop
Stop
Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

Standby mode

Stop mode

(TMA3 = 0, SSR3 = 1)

Watch mode

Subactive
mode

(TMA3 = 1)

(TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

SBY

Interrupt

SBY

Interrupt

STOP

INT

timer A

STOP

1. Interrupt source
2. STOP/SBY (DTON = 1, LSON = 0)
3. STOP/SBY (DTON = 0, LSON = 0)
4. STOP/SBY (DTON = Don't care, LSON = 1)

OSC

cyc

SUB

LSON:
DTON:

Main oscillation frequency
Suboscillation frequency
for time-base
f

OSC

/8 or f

(software selectable)
f

CPU operating clock
Timer A operating clock
Clock for peripheral
functions (except timer A)
Low speed on flag
Direct transfer on flag

Active
mode

Notes:

CPU

CLK

PER

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
Stop
Stop

(TMA3 = 0, SSR3 = 0)

RESET1

RESET2

RAME = 0

RAME = 1

INT

timer A

(TMA3 = 0)

STOP

STOPC

STOP

Figure 14 MCU Status Transitions

HD404629R Series

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.

The MCU enters standby mode when the SBY instruction is executed in active mode.

Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of
operation in standby mode is shown in figure 15.

Standby mode

Yes

Watch mode

System clock

oscillator started

System clock

oscillator started

System reset

Interrupts

enabled

Yes

IF = 1,

IM = 0,

IE = 1?

RESET = 1?

IF0 ·

IM0

= 1?

IF1 ·

IM1

= 1?

IFTA ·

IMTA

= 1?

IFTB ·

IMTB

+ IF2 ·

IM2

= 1?

IFTC ·

IMTC

+ IF3 ·

IM3

= 1?

IFTD ·

IMTD

+ IF4 ·

IM4

= 1?

Yes

IFAD ·

IMAD

+ IFS ·

IMS

= 1?

Stop mode

RESET = 1?

STOPC

= 0?

RAME = 1

RAME = 0

Yes

Next instruction

execution

Next instruction

execution

Note: 1. Only when clearing from standby mode

Figure 15 MCU Operation Flowchart

HD404629R Series

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC

and OSC

oscillator stops. For the X1 and X2

oscillator to operate or stop can be selected by setting bit 3 of the system clock select register (SSR: $029;
operating: SSR3 = 0, stop: SSR3 = 1) (figure 27). The MCU enters stop mode if the STOP instruction is
executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure
44).

Stop mode is terminated by a RESET input or a

STOPC input as shown in figure 16. RESET or STOPC

must be applied for at least one t

to stabilize oscillation (refer to the AC Characteristics section). When

the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.

Stop mode

Oscillator

Internal

clock

STOP instruction execution

(at least equal to oscillator stabilization time t

)

res

RESET

STOPC

Figure 16 Timing of Stop Mode Cancellation

Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator and the LCD
function operate, but other function operations stop. Therefore, the power dissipation in this mode is the
second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the
OSC

and OSC

oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the

STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is
executed in subactive mode.

Watch mode is terminated by a RESET input or a timer-A/

INT

interrupt request. For details of RESET

input, refer to the Stop Mode section. When terminated by a timer-A/

INT

interrupt request, the MCU

enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated,
the time required to enter active mode is t

for a timer A interrupt, and T

(where T + t

< T

< 2T + t

)

for an

INT

interrupt, as shown in figures 17 and 18.

Operation during mode transition is the same as that at standby mode cancellation (figure 15).

HD404629R Series

Subactive Mode: The OSC

and OSC

oscillator stops and the MCU operates with a clock generated by

the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because
the operating clock is slow, the power dissipation becomes low, next to watch mode.

The CPU instruction execution speed can be selected as 244

s or 122

s by setting bit 2 (SSR2) of the

system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the
value is changed in subactive mode, the MCU may malfunction.

When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).

Subactive mode is an optional function that the user must specify on the function option list.

Interrupt Frame: In watch and subactive modes,

CLK

is applied to timer A and the

INT

circuit.

Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame.
Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure
18).

In watch and subactive modes, the timer-A/

INT

interrupt is generated synchronously with the interrupt

frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the

INT

signal is input asynchronously with the interrupt

frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt
strobe timing.

HD404629R Series

Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on
flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described
below:

Set LSON to 0 and DTON to 1 in subactive mode.

Execute the STOP or SBY instruction.

The MCU automatically enters active mode from subactive mode after waiting for the MCU internal
processing time and oscillation stabilization time (figure 19).

Notes: 1. The DTON flag can be set only in subactive mode. It is always reset in active mode.

2. The transition time (T

) from subactive mode to active mode:

< T

< T + t

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1

MIS0

0.24414 ms

0.12207 ms

0.24414 ms

7.8125 ms

31.25 ms

Oscillation circuit conditions

External clock input

Ceramic oscillator

Crystal oscillator

15.625 ms

62.5 ms

Not used

Notes: 1.

Values of T and t

when a 32.768-kHz crystal oscillator is used to pins x1 and x2.

The value is applied only when direct transfer operation is used.

Buffer control.

Refer to figure 41.

MIS3

MIS2

Figure 18 Miscellaneous Register (MIS)

Subactive mode

Interrupt strobe

Direct transfer
completion timing

MCU internal
processing time

Oscillation
stabilization
time

Active mode

T:
t :

T :

STOP/SBY instruction execution

(Set LSON = 0, DTON = 1)

Interrupt frame length
Oscillation stabilization period

Direct transition time

Figure 19 Direct Transition Timing

HD404629R Series

Stop Mode Cancellation by

STOPC

: The MCU enters active mode from stop mode by inputting

STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting
address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3)
differs between cancellation by

STOPC and by RESET. When stop mode is cancelled by RESET, RAME

= 0; when cancelled by

STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in

stop mode;

STOPC input is ignored in other modes. Therefore, when the program requires to confirm that

stop mode has been cancelled by

STOPC (for example, when the RAM contents before entering stop mode

is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at
the beginning of the program.

MCU Operation Sequence: The MCU operates in the sequence shown in figures 20 to 22. It is reset by
an asynchronous RESET input, regardless of its status.

The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.

Power on

RESET = 1 ?

RAME = 0

Reset MCU

MCU

operation

cycle

Yes

Figure 20 MCU Operating Sequence (Power On)

HD404629R Series

Notes: 1. When watch or subactive mode on HD404629R Series/HD4074629 is used and the LCD

function is off in that mode, the watch mode or subactive mode current is larger, and
consequently the following settings should be made.

Perform the following writes in the order shown before the transition to watch mode (before
execution of the STOP instruction):

Write $0 to LCR

Write $3 to LMR

Also, when returning to active mode from watch mode or subactive mode, perform the
following writes in the order shown:

Write a value appropriate to the conditions of use to LMR

Write a value appropriate to the conditions of use to LCR

A sample programming flowchart for the above procedures is shown in figure 23.

.
.
.

LMR

LCR

.
.
.

Initialization routine

Include these
operations

.
.
.

LCR = $0

LMR = $3

.
.
.

Main routine

STOP instruction

Watch mode

Or transition to
subactive mode

.
.
.

LMR

LCR

.
.
.

Set
appropriate
values for
active mode

INT

or timer A

interrupt processing
routine

After the MCU enters active mode again

Set
appropriate
values for
active mode

Figure 23 Programming Flowchart (LCD Display Off in Watch or Subactive Mode)

HD404629R Series

Notes: 2. When the MCU is in watch mode or subactive mode, if the high level period before the falling

edge of

I NT

is shorter than the interrupt frame,

I NT

is not detected. Also, if the low level

period after the falling edge of

I NT

is shorter than the interrupt frame,

I NT

is not detected.

Edge detection is shown in figure 24. The level of the

INT

signal is sampled by a sampling

clock. When this sampled value changes to low from high, a falling edge is detected.

In figure 25, the level of the

I NT

signal is sampled by an interrupt frame. In (a) the sampled

value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In
(b), the sampled value is high at point A, and also high at point B. A falling edge is not detected
in this case either.

When the MCU is in watch mode or subactive mode, keep the high level and low level period of
INT

longer than interrupt frame.

High

Low

INT

Sampling

Low

Figure 24 Edge Detection

A: Low

B: Low

INT

Interrupt
frame

A: High

B: High

INT

Interrupt
frame

(a) High level period

(b) Low level period

Figure 25 Sampling Example

HD404629R Series

Internal Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 26. As shown in table 22, a ceramic
oscillator can be connected to OSC

and OSC

, and a 32.768-kHz oscillator can be connected to X1 and

X2. The system oscillator can also be operated by an external clock. Bit 0 and 1 (SSR1) of the system
clock select register (SSR: $029) must be set according to the frequency of the oscillator connected to
OSC

and OSC

(figure 27).

Note:

If the system clock select register (SSR: $029) setting does not match the oscillator frequency,

DTMF generator and subsystems using the 32.768-kHz oscillation will malfunction.

OSC

System

clock

oscillator

Sub-

system

clock

oscillator

1/4

division

circuit

Timing

generation

circuit

System

clock

selection

circuit

CPU with ROM,

RAM, registers,

flags, and I/O

Internal

Peripheral

module

interrupts

(other than timer A)

Timer A

interrupt

Clock

Time-base

clock

selection

circuit

1/8 or 1/4

division

circuit

Timing

generator

circuit

Timing

generation

circuit

1/8

division

circuit

SUB

subcyc

LSON

TMA3 bit

cyc

OSC

Wcyc

CPU

PER

CLK

Note:

1/8 or 1/4 division ratio can be selected by setting bit 2 of the system
clock select register (SSR: $029).

Figure 26 Clock Generation Circuit

HD404629R Series

Bit

Initial value

Read/Write

Bit name

SSR3

SSR2

SSR0

SSR1

System clock select register (SSR: $029)

SSR2

ratio selection

SUB

= f

SUB

= f

SSR3

32-kHz oscillation stop

Oscillation operates in stop mode

Oscillation stops in stop mode

32-kHz oscillation division

SSR1

System clock selection

400 kHz

800 kHz

2 MHz

4 MHz

SSR0

Note: SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a

STOPC

input during

stop mode, and will retain its value.
SSR3 will also not be cleared upon entering stop mode.

Figure 27 System Clock Select Register (SSR)

GND

RESET

OSC

TEST

GND

Figure 28 Typical Layouts of Crystal and Ceramic Oscillator

HD404629R Series

Table 22 Oscillator Circuit Examples

Circuit Configuration

Circuit Constants

External clock

operation

External
oscillator

OSC

Open

OSC

Ceramic oscillator

(OSC1, OSC2)

OSC

Ceramic
oscillator

GND

Ceramic oscillator: CSB400P22 (Murata)

CSB400P (Murata)

Rf = 1 M

20%

C1 = C2 = 220 pF

Ceramic oscillator: CSB800J122 (Murata),

CSB800J (Murata)

Rf = 1 M

20%

C1 = C2 = 220 pF

Ceramic oscillator: CSA2.00MG (Murata)
Rf = 1 M

20%

C1 = C2 = 30 pF

20%

Ceramic oscillator: CSA4.00MG (Murata)
Rf = 1 M

20%

C1 = C2 = 30 pF

20%

Crystal oscillator

(OSC1, OSC

)

OSC

Crystal
oscillator

GND

OSC

Rf = 1 M

20%

C1 = C2 = 10 to 22pF

20%

Crystal : Equivalent circuit at left
C0 =7pF max
Rs = 100

max

f = 400kHz, 800kHz, 2MHz, 4MHz

Crystal oscillator

(X1, X2)

Crystal
oscillator

GND

Crystal oscillator: 32.768 kHz: MX38T
(Nippon Denpa)
C

= C

= 20 pF

20%

: 14 k

: 1.5 pF

HD404629R Series

Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with

the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the
circuit parameters.

2. The wiring between the OSC

, OSC

(X1 and X2 pins), and the other elements should be as

short as possible, and must not cross other wiring. Refer to figure 28.

3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to V

and leave the X2 pin open.

Input/Output

The MCU has 42 input/output pins (D

, R0

) and 2 input pins (D

, D

). The features are

described below.

Ten pins (D

) are high-current input/output pins.

The D

and D

, and R0

input/output pins are multiplexed with peripheral function pins such as

for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or
R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and
input/output selection are automatically switched according to the setting.

Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.

Peripheral function output pins are CMOS output pins. Only the R2

/SO pin can be set to NMOS open-

drain output by software.

In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.

Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by
software.

I/O buffer configuration is shown in figure 29, programmable I/O circuits are listed in table 23, and I/O pin
circuit types are shown in table 24.

Table 23 Programmable I/O Circuits

MIS3 (bit 3 of MIS)

DCD, DCR

PDR

CMOS buffer

PMOS

NMOS

Pull-up MOS

Note:

-- indicates off status.

HD404629R Series

MIS3

Input control signal

Pull-up
MOS

DCD, DCR

PDR

Input data

HLT

Pull-up control signal

Buffer control signal

Output data

Figure 29 I/O Buffer Configuration

Table 24 Circuit Configurations of I/O Pins

I/O Pin Type

Circuit

Pins

Input/output pins

Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

DCD, DCR

PDR

Input control signal

Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

DCR

PDR

Input control signal

MIS2

Input pins

Input data

Input control signal

, D

HD404629R Series

Table 24 Circuit Configurations of I/O Pins (cont)

I/O Pin Type

Circuit

Pins

Peripheral
function
pins

Input/output
pins

Pull-up control signal

Output data

Input data

HLT

MIS3

SCK

Output pins

Pull-up control signal

PMOS control

signal

Output data

HLT

MIS3

MIS2

Pull-up control signal

Output data

HLT

MIS3

TOB, TOC, TOD

Input pins

Input data

SI,

INT

, etc

HLT

MIS3

PDR

SI,

INT

, INT

INT

, INT

EVNB

, EVND

Input data

INT

STOPC

INT

STOPC

Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The

HLT

signal

becomes low, and input/output pins enter high-impedance state.

2. The

HLT

signal is 1 in watch and subactive modes.

HD404629R Series

D Port (D

): Consist of 10 input/output pins and 2 input pins addressed by one bit. D

are high-

current I/O pins, and D

and D

are input-only pins.

Pins D

are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. All pins D

are tested by the TD and

TDD instructions.

The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0DCD2:
$02C$02E) that are mapped to memory addresses (figure 30).

Pins D

and D

are multiplexed with peripheral function pins

S T OP C and I NT

, respectively. The

peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 31).

R Ports (R0

R7

): 32 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR

and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the
port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled
by R-port data control registers (DCR0DCR7: $030$037) that are mapped to memory addresses (figure
30).

Pins R0

are multiplexed with peripheral pins

INT

, respectively. The peripheral function

modes of these pins are selected by bits 03 (PMRB0PMRB3) of port mode register B (PMRB: $024)
(figure 32).

Pins R1

are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral

function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2
(TMB2: $013), bits 02 (TMC20TMC22) of timer mode register C2 (TMC2: $014), and bits 03
(TMD20TMD23) of timer mode register D2 (TMD2: $015) (figures 33, 34, and 35).

Pins R1

and R2

are multiplexed with peripheral pins

EVNB and EVND, respectively. The peripheral

function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C
(PMRC: $025) (figure 31).

Pins R2

are multiplexed with peripheral pins

SCK, SI, and SO, respectively. The peripheral function

modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and
1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 36 and 37.

Ports R3 and R4 are multiplexed with segment pins SEG1SEG8, respectively. The function modes of
these pins can be selected by individual pins, by setting LCD output registers 1 and 2 (LOR1, LOR2: $01D,
$01F) (figures 38 and 39).

Ports R5R7 are multiplexed with segment pins SEG9SEG20, respectively. The function modes of these
pins can be selected in 4-pin units by setting LCD output register 3 (LOR3: $01F) (figure 40).

HD404629R Series

Bit

Initial value

Read/Write

Bit name

DCD03,

DCD02,

DCD00,

DCD01,

DCD0, DCD1

Data control register

(DCD0 to 2: $02C to $02E)
(DCR0 to 7: $030 to $037)

DCD13

DCD12

DCD10

DCD11

Bit

Initial value

Read/Write

Bit name

Not used

DCD20

DCD21

DCD2

Bit

Initial value

Read/Write

Bit name

DCR03

DCR02

DCR00

DCR01

DCR0 to DCR7

DCR73

DCR72

DCR70

DCR71

All Bits

CMOS Buffer On/Off Selection

Off (high-impedance)

Correspondence between ports and DCD/DCR bits

Register Name

Bit 3

Bit 2

Bit 1

Bit 0

DCD0

DCD1

DCD2

DCR0

DCR1

DCR2

DCR3

DCR4

DCR5

DCR6

DCR7

Figure 30 Data Control Registers (DCD, DCR)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

PMRC0

PMRC1

Port mode register C (PMRC: $025)

PMRC0

PMRC1

/EVND mode selection

EVND

EVNB

mode selection

EVNB

PMRC2

STOPC

PMRC3

INT

mode selection

INT

STOPC

mode selection

Note:

PMRC2 is reset to 0 only by RESET input. When

STOPC

is input in stop

mode, PMRC2 is not reset but retains its value.

Figure 31 Port Mode Register C (PMRC)

Bit

Initial value

Read/Write

Bit name

PMRB3

PMRB2

PMRB0

PMRB1

PMRB0

INT

mode selection

INT

Port mode register B (PMRB: $024)

PMRB1

/INT

mode selection

INT

PMRB2

/INT

mode selection

INT

PMRB3

/INT

mode selection

INT

Figure 32 Port Mode Register B (PMRB)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMB20

R/W

TMB21

Timer mode register B2 (TMB2: $013)

TMB21

TMB20

/TOB mode selection

TOB

port

Toggle output

0 output

1 output

Figure 33 Timer Mode Register B2 (TMB2)

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMC22

R/W

TMC20

R/W

TMC21

Timer mode register C2 (TMC2: $014)

TMC22

TMC20

TMC21

/TOC mode selection

TOC

port

Toggle output

0 output

1 output

Not Used

PWM output

Figure 34 Timer Mode Register C2 (TMC2)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

R/W

TMD23

R/W

TMD22

R/W

TMD20

R/W

TMD21

Timer mode register D2 (TMD2: $015)

TMD22

TMD20

TMD21

/TOD mode selection

TOD

port

Toggle output

0 output

1 output

Not used

PWM output

Input capture (R1

port)

TMD23

: Don't care

Figure 35 Timer Mode Register D2 (TMD2)

Bit

Initial value

Read/Write

Bit name

SMRA3

SMRA2

SMRA0

SMRA1

Serial mode register A (SMRA: $005)

Output

Input

Prescaler

System clock

External clock

2048

512

128

Prescaler
division
ratio

SMRA2

SMRA0

SMRA1

Clock source

SMRA3

SCK

mode selection

SCK

SCK

Figure 36 Serial Mode Register A (SMRA)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

Not used

PMRA0

PMRA1

PMRA0

/SO mode selection

Port mode register A (PMRA: $004)

PMRA1

/SI mode selection

Figure 37 Port Mode Register A (PMRA)

Bit

Initial value

Read/Write

Bit name

LOR13

LOR12

LOR10

LOR11

LCD output register 1 (LOR1: $01D)

LOR12

/SEG3 mode selection

SEG3

LOR13

/SEG4 mode selection

SEG4

LOR10

/SEG1 mode selection

SEG1

LOR11

/SEG2 mode selection

SEG2

Figure 38 LCD Output Register 1 (LOR1)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

LOR23

LOR22

LOR20

LOR21

LCD output register 2 (LOR2: $01E)

LOR21

/SEG6 mode selection

SEG6

LOR20

/SEG5 mode selection

SEG5

LOR22

/SEG7 mode selection

SEG7

LOR23

/SEG8 mode selection

SEG8

Figure 39 LCD Output Register 2 (LOR2)

Bit

Initial value

Read/Write

Bit name

Not used

LOR32

LOR30

LOR31

LCD output register 3 (LOR3: $01F)

LOR31

/SEG13R6

/SEG16 mode selection

to R6

SEG13SEG16

LOR30

/SEG9R5

/SEG12 mode selection

to R5

SEG9SEG12

LOR32

/SEG17R7

/SEG20 mode selection

to R7

SEG17SEG20

Figure 40 LCD Output Register 3 (LOR3)

HD404629R Series

Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin other than input-only pins D

and D

. The on/off status of all these transistors is

controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual
transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off
control of that pin alone (table 23 and figure 41).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V

to prevent LSI malfunctions due to noise. These pins must either be pulled up to V

their pull-up MOS transistors or by resistors of about 100 k

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

MIS2

CMOS buffer
on/off selection
for pin R2

/SO

Miscellaneous register (MIS: $00C)

Off

Refer to figure 18 in the
operation modes section.

selection.

MIS3

Pull-up MOS
on/off selection

Off

MIS1

MIS0

Figure 41 Miscellaneous Register (MIS)

HD404629R Series

Prescalers

The MCU has the following two prescalers, S and W.

The prescalers operating conditions are listed in table 25, and the prescalers output supply is shown in
figure 42. The timers AD input clocks except external events, the serial transmit clock except the external
clock, and the LCD circuit operating clock are selected from the prescaler outputs, depending on
corresponding mode registers.

Prescaler Operation

Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and
at MCU reset.

Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by
eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be
reset by software.

Table 25 Prescaler Operating Conditions

Prescaler

Input Clock

Reset Conditions

Stop Conditions

Prescaler S

System clock (in active and standby mode),
Subsystem clock (in subactive mode)

MCU reset

MCU reset,
stop mode,
watch mode

Prescaler W

32-kHz crystal oscillation

MCU reset,
software

MCU reset,
stop mode

Subsystem

clock

Prescaler W

LCD

Timer A

Timer B

Timer C

Timer D

Serial

System

clock

Prescaler S

Clock

selector

Figure 42 Prescaler Output Supply

HD404629R Series

Timers

The MCU has four timer/counters (A to D).

Timer A: Free-running timer

Timer B: Multifunction timer

Timer C: Multifunction timer

Timer D: Multifunction timer

Timer A is an 8-bit free-running timer. Timers BD are 8-bit multifunction timers, whose functions are
listed in table 26. The operating modes are selected by software.

Table 26 Timer Functions

Functions

Timer A

Timer B

Timer C

Timer D

Clock

Prescaler S

Available

source

Prescaler W

Available

External event

Available

Timer

Free-running

Available

functions

Time-base

Available

Event counter

Available

Reload

Available

Watchdog

Available

Input capture

Available

Timer

Toggle

Available

outputs

0 output

Available

1 output

Available

PWM

Available

Note:

-- implies not available.

Timer A

Timer A Functions: Timer A has the following functions.

Free-running timer

Clock time-base

The block diagram of timer A is shown in figure 43.

HD404629R Series

1/4

1/2

32.768-kHz
oscillator

System
clock

Prescaler W

(PSW)

Selector

Prescaler S (PSS)

Selector

Internal data bus

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

2 f

1/2 tw

cyc

PER

128

512

1024

2048

÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷

÷ ÷ ÷ ÷

Data bus

Clock line

Signal line

Figure 43 Block Diagram of Timer A

Timer A Operations:

Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).

Timer A is reset to $00 by MCU reset and

incremented at each input clock. If an input clock is applied to timer A after it has reached

$FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt
request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore
it generates regular interrupts every 256 clocks.

Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer
mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A
generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case,
prescaler W and timer A can be reset to $00 by software.

Registers for Timer A Operation: Timer A operating modes are set by the following registers.

Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode
and input clock source as shown in figure 44.

HD404629R Series

Bit

Initial value

Read/Write

Bit name

TMA3

TMA2

TMA0

TMA1

Timer mode register A (TMA: $008)

PSS

PSW

Operating mode

Timer A mode

TMA3

TMA1

TMA2

TMA0

Source
prescaler

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

Input clock
frequency

32t

Wcyc

16t

Wcyc

1/2t

Wcyc

Time-base
mode

X : Don't care

Note: 1.

2.
3.

Wcyc

= 244.14

s (when a 32.768-kHz crystal oscillator is used)

Timer counter overflow output period (seconds) = input clock period (seconds)

256.

If PSW of TCA reset is selected while the LCD is operating, LCD operation halts (power switch
goes off and all SEG and COM pins are grounded).
When an LCD is connected for display, the PSW and TCA reset periods must be set in the
program to the minimum.
The division ratio must not be modified during time-base mode operation, otherwise an overflow
cycle error will occur.

Not used

Reset PSW and TCA

Figure 44 Timer Mode Register A (TMA)

Timer B

Timer B Functions: Timer B has the following functions.

Free-running/reload timer

External event counter

Timer output operation (toggle, 0, and 1 outputs)

HD404629R Series

Timer B Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).
Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer B is used as an external event counter by selecting external
event input as input clock source. In this case, pin R1

EVNB must be set to EVNB by port mode

EVNB. The other operation

is basically the same as the free-running/reload timer operation.

Timer output operation: The following three output modes can be selected for timer B by setting timer
mode register B2 (TMB2: $013).

Toggle

0 output

1 output

By selecting the timer output mode, pin R1

/TOB is set to TOB. The output from TOB is reset low by

MCU reset.

Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input

after timer B has reached $FF. By using this function and reload timer function, clock signals can
be output at a required frequency for the buzzer. The output waveform is shown in figure 46.

0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after

timer B has reached $FF. Note that this function must be used only when the output level is high.

1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer

B has reached $FF. Note that this function must be used only when the output level is low.

HD404629R Series

Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.

Timer mode register B1 (TMB1: $009)

Timer mode register B2 (TMB2: $013)

Timer write register B (TWBL: $00A, TWBU: $00B)

Timer read register B (TRBL: $00A, TRBU: $00B)

Port mode register C (PMRC: $025)

Timer mode register B1 (TMB1: $009):

Four-bit write-only register that selects the free-running/reload timer function, input clock source, and
the prescaler division ratio as shown in figure 47. It is reset to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.

Bit

Initial value

Read/Write

Bit name

TMB13

TMB12

TMB10

TMB11

Timer mode register B1 (TMB1: $009)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMB12

TMB10

TMB11

Input clock period and input
clock source

EVNB

(external event input)

TMB13

Free-running/reload
timer selection

Free-running timer

Reload timer

Figure 47 Timer Mode Register B1 (TMB1)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMB20

R/W

TMB21

Timer mode register B2 (TMB2: $013)

TMB21

TMB20

/TOB mode selection

TOB

port

Toggle output

0 output

1 output

Figure 48 Timer Mode Register B2 (TMB2)

Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output
mode as shown in figure 48. It is reset to $0 by MCU reset.

Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU) as shown in figures 49 and 50. The lower digit is reset to $0 by
MCU reset, but the upper digit value is invalid.

Timer B is initialized by writing to timer write register B. In this case, the lower digit (TWBL) must be
written to first, but writing only to the lower digit does not change the timer B value. Timer B is
initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to.
When timer write register B is written to again and if the lower digit value needs no change, writing
only to the upper digit initializes timer B.

Bit

Initial value

Read/Write

Bit name

TWBL3

TWBL2

TWBL0

TWBL1

Timer write register B (lower digit) (TWBL: $00A)

Figure 49 Timer Write Register B Lower Digit (TWBL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWBU3

Undefined

TWBU2

Undefined

TWBU0

Undefined

TWBU1

Timer write register B (upper digit) (TWBU: $00B)

Figure 50 Timer Write Register B Upper Digit (TWBU)

Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 51 and 52).

HD404629R Series

The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is
obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by
reading TRBL, the count of timer B when TRBU is read can be obtained.

Bit

Initial value

Read/Write

Bit name

Undefined

TRBL3

Undefined

TRBL2

Undefined

TRBL0

Undefined

TRBL1

Timer read register B (lower digit) (TRBL: $00A)

Figure 51 Timer Read Register B Lower Digit (TRBL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRBU3

Undefined

TRBU2

Undefined

TRBU0

Undefined

TRBU1

Timer read register B (upper digit) (TRBU: $00B)

Figure 52 Timer Read Register B Upper Digit (TRBU)

Port mode register C (PMRC: $025): Write-only register that selects R1

EVNB pin function as shown

in figure 53. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

PMRC0

PMRC1

PMRC1

/EVND mode selection

EVND

Port mode register C (PMRC: $025)

PMRC0

EVNB

mode selection

EVNB

PMRC3

INT

mode selection

INT

PMRC2

STOPC

mode selection

STOPC

Figure 53 Port Mode Register C (PMRC)

HD404629R Series

Timer C

Timer C Functions: Timer C has the following functions.

Free-running/reload timer

Watchdog timer

Timer output operation (toggle, 0, 1, and PWM outputs)

The block diagram of timer C is shown in figure 54.

(TWCL)

(TWCU)

128

512

1024

ø PER

TOC

2048

(TCCL)

(TCCU)

System reset signal

Watchdog on

flag

(WDON)

Timer output

control logic

System

clock

Prescalers

(PSS)

Watchdog timer

control logic

Timer C

interrupt request

flag

(IFTC)

Timer read
register CL

(TRCL)

Timer read

(TRCU)

Timer counter C

Timer write register C

Timer mode

(TMC1)

Timer output

control

Timer mode

(TMC2)

Selector

Free-running/reload control

Internal data bus

Data bus

Clock line

Signal line

Figure 54 Block Diagram of Timer C

HD404629R Series

Timer C Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).

Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing
timer C by software before it reaches $FF.

Timer output operation: The following four output modes can be selected for timer C by setting timer
mode register C2 (TMC2: $014).

Toggle

0 output

1 output

PWM output

By selecting the timer output mode, pin R1

/TOC is set to TOC. The output from TOC is reset low by

MCU reset.

Toggle output: The operation is basically the same as that of timer-B's toggle output.

0 output: The operation is basically the same as that of timer-B's 0 output.

1 output: The operation is basically the same as that of timer-B's 1 output.

PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output

function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 46.

HD404629R Series

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.

Timer mode register C1 (TMC1: $00D)

Timer mode register C2 (TMC2: $014)

Timer write register C (TWCL: $00E, TWCU: $00F)

Timer read register C (TRCL: $00E, TRCU: $00F)

Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in
figure 55. It is reset to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.

Bit

Initial value

Read/Write

Bit name

TMC13

TMC12

TMC10

TMC11

Timer mode register C1 (TMC1: $00D)

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

TMC12

TMC10

TMC11

TMC13

Free-running/reload timer selection

Free-running timer

Reload timer

Input clock period

Figure 55 Timer Mode Register C1 (TMC1)

Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output
mode as shown in figure 56. It is reset to $0 by MCU reset.

Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit
(TWCL) and the upper digit (TWCU). The operation of timer write register C is basically the same as
that of timer write register B (TWBL: $00A, TWBU: $00B).

Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit
(TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit. The operation of
timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).

HD404629R Series

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMC22

R/W

TMC20

R/W

TMC21

Timer mode register C2 (TMC2: $014)

TMC22

TMC21

/TOC mode selection

TOC

port

Toggle output

0 output

1 output

Not used

PWM output

TMC20

Figure 56 Timer Mode Register C2 (TMC2)

Bit

Initial value

Read/Write

Bit name

TWCL3

TWCL2

TWCL0

TWCL1

Timer write register C (lower digit) (TWCL: $00E)

Figure 57 Timer Write Register C Lower Digit (TWCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWCU3

Undefined

TWCU2

Undefined

TWCU0

Undefined

TWCU1

Timer write register C (upper digit) (TWCU: $00F)

Figure 58 Timer Write Register C Upper Digit (TWCU)

HD404629R Series

Timer D

Timer D Functions: Timer D has the following functions.

Free-running/reload timer

External event counter

Timer output operation (toggle, 0, 1, and PWM outputs)

Input capture timer

The block diagram for each operation mode of timer D is shown in figures 61 and 62.

Timer D Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register D1 (TMD1: $010).

Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by
software and incremented by one at each clock input. If an input clock is applied to timer D after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is
initialized to its initial value set in timer write register D; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer D is used as an external event counter by selecting the
external event input as an input clock source. In this case, pin R2

/EVND must be set to EVND by port

mode register C (PMRC: $025).

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and
falling edges detection is selected, the time between the falling edge and rising edge of input signals
must be 2t

cyc

or longer.

Timer D is incremented by one at each detection edge selected by detection edge select register 2
(ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.

Timer output operation: The following four output modes can be selected for timer D by setting timer
mode register D2 (TMD2: $015).

Toggle

0 output

1 output

PWM output

By selecting the timer output mode, pin R1

/TOD is set to TOD. The output from TOD is reset low by

MCU reset.

Toggle output: The operation is basically the same as that of timer-B's toggle output.

0 output: The operation is basically the same as that of timer-B's 0 output.

HD404629R Series

1 output: The operation is basically the same as that of timer-B's 1 output.

PWM output: The operation is basically the same as that of timer-C's PWM output.

Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVND.

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by detection edge select register 2 (ESR2: $027).

When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.

By selecting the input capture operation, pin R1

/TOD is set to R1

and timer D is reset to $00.

HD404629R Series

EVND

Input capture

status flag

(ICSF)

Input capture

error flag

(ICEF)

Timer D interrupt

request flag

(IFTD)

Error control

logic

Read signal

Edge detection

logic

System

clock

Prescaler S (PSS)

Selector

Timer read register D

Timer counter D

(TRDL)

(TRDU)

(TCDL)

(TCDU)

Input capture
timer control

Overflow

Internal data bus

Timer mode

(TMD2)

Data bus

Clock line

Signal line

Edge
detection
control

Edge detection

selection register

2 (ESR2)

Time mode

(TMD1)

128

512

2048

øPER

Figure 62 Block Diagram of Timer D (Input Capture Timer)

Registers for Timer D Operation: By using the following registers, timer D operation modes are selected
and the timer D count is read and written.

Timer mode register D1 (TMD1: $010)

Timer mode register D2 (TMD2: $015)

Timer write register D (TWDL: $011, TWDU: $012)

Timer read register D (TRDL: $011, TRDU: $012)

HD404629R Series

Port mode register C (PMRC: $025)

Detection edge select register 2 (ESR2: $027)

Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 63. It is reset to
$0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.

When selecting the input capture timer operation, select the internal clock as the input clock source.

Bit

Initial value

Read/Write

Bit name

TMD13

TMD12

TMD10

TMD11

Timer mode register D1 (TMD1: $010)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMD12

TMD10

TMD11

Input clock period and

input clock source

/EVND

(external event input)

TMD13

Free-running/reload timer selection

Free-running timer

Reload timer

Figure 63 Timer Mode Register D1 (TMD1)

Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output
mode and input capture operation as shown in figure 64. It is reset to $0 by MCU reset.

Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of the lower digit
(TWDL) and the upper digit (TWDU). The operation of timer write register D is basically the same as
that of timer write register B (TWBL: $00A, TWBU: $00B).

Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of the lower digit
(TRDL) and the upper digit (TRDU). The operation of timer read register D is basically the same as
that of timer read register B (TRBL: $00A, TRBU: $00B).
When the input capture timer operation is selected and if the count of timer D is read after a trigger is
input, either the lower or upper digit can be read first.

HD404629R Series

Port mode register C (PMRC: $025): Write-only register that selects R2

/EVND pin function as shown

in figure 53. It is reset to $0 by MCU reset.

Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of
signals input to pin EVND as shown in figure 69. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

R/W

TMD23

R/W

TMD22

R/W

TMD20

R/W

TMD21

Timer mode register D2 (TMD2: $015)

TMD22

TMD20

TMD21

/TOD mode selection

TOD

port

Toggle output

0 output

1 output

Not used

PWM output

Input capture (R1

port)

TMD23

: Don't care

Figure 64 Timer Mode Register D2 (TMD2)

Bit

Initial value

Read/Write

Bit name

TWDL3

TWDL2

TWDL0

TWDL1

Timer write register D (lower digit) (TWDL: $011)

Figure 65 Timer Write Register D Lower Digit (TWDL)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWDU3

Undefined

TWDU2

Undefined

TWDU0

Undefined

TWDU1

Timer write register D (upper digit) (TWDU: $012)

Figure 66 Timer Write Register D Upper Digit (TWDU)

Bit

Initial value

Read/Write

Bit name

Undefined

TRDL3

Undefined

TRDL2

Undefined

TRDL0

Undefined

TRDL1

Timer read register D (lower digit) (TRDL: $011)

Figure 67 Timer Read Register D Lower Digit (TRDL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRDU3

Undefined

TRDU2

Undefined

TRDU0

Timer read register D (upper digit) (TRDU: $012)

Undefined

TRDU1

Figure 68 Timer Read Register D Upper Digit (TRDU)

HD404629R Series

Note on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register untill the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 27. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

Table 27 PWM Output Following Update of Timer Write Register

PWM Output

Mode

Timer Write Register is Updated
during High PWM Output

Timer Write Register is Updated
during Low PWM Output

Free
running

Timer write
register
rewrite (set
value is N)

Interrupt request
generated

(255 N) T

(N + 1)

(N' + 1)

(255 N)

(N + 1)

Reload

Timer write
register
rewrite (set
value is N)

Interrupt request
generated

(255 N)

HD404629R Series

Serial Interface Operation

Selecting and Changing the Operating Mode: Table 28 lists the serial interface's operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial
mode register A (SMRA: $005) settings; to change the operating mode, always initialize the serial interface
internally by writing data to serial mode register A. Note that the serial interface is initialized by writing
data to serial mode register A. Refer to the following Serial Mode Register A section for details.

Pin Setting: The R2

SCK pin is controlled by writing data to serial mode register A (SMRA: $005). The

/SI and R2

/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the

following Registers for Serial Interface section for details.

Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register A
(SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following Registers for Serial
Interface section for details.

Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU: $007).
Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the
transmit clock and is input from or output to an external system.

The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.

Table 28 Serial Interface Operating Modes

SMRA

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to
000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $023, bit 2) is set, and the transfer stops.

When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t

cyc

to 8192t

cyc

by setting bits 2 to 0 (SMRA2 SMRA0) of serial mode register A (SMRA: $005) and bit 0

(SMRB0) of serial mode register B (SMRB: $028) as listed in table 29.

HD404629R Series

Table 29 Serial Transmit Clock (Prescaler Output)

SMRB

SMRA

Bit 0

Bit 2

Bit 1

Bit 0

Prescaler Division Ratio

Transmit Clock Frequency

2048

4096t

cyc

512

1024t

cyc

128

256t

cyc

64t

cyc

16t

cyc

4096

8192t

cyc

1024

2048t

cyc

256

512t

cyc

128t

cyc

32t

cyc

Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 71.

STS wait state

Transmit clock wait state

Transfer state

Continuous clock output state (only in internal clock mode)

STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 71). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.

Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However,
note that if continuous clock output mode is selected in internal clock mode, the serial interface does not
enter transfer state but enters continuous clock output state (17).

The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04,
14) in transmit clock wait state.

Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.

HD404629R Series

In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.

If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 2) is set
by the octal counter that is reset to 000.

Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/
receive data but only outputs the transmit clock from the

SCK pin.

When bits 1 and 0 (PMRA1, PMRA0) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait
state is entered.

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

MCU reset

SMRA write

STS instruction

Transmit clock

8 transmit clocks

STS instruction (IFS 1)

SMRA write (IFS 1)

External clock mode

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

SMRA write

STS instruction

Transmit clock

STS instruction (IFS 1)

8 transmit clocks

Internal clock mode

Continuous clock output state

(PMRA 0, 1 = 00)

SMRA write

Transmit clock 17

Note: Refer to the Operating States section for the corresponding encircled numbers.

MCU reset

SMRA write (IFS 1)

Figure 71 Serial Interface State Transitions

Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB:
$028) to 0 or 1. The output level control example is shown in figure 72. Note that the output level cannot
be controlled in transfer state.

HD404629R Series

State

MCU reset

PMRA write

SMRA write

SMRB write

SRL, SRU write

STS instruction

SCK

pin (input)

SO pin

IFS

Idle

STS wait state

Transmit clock
wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

External clock selection

Output level control in

idle states

Dummy write for
state transition

Output level control in

idle states

Data write for transmission

Undefined

LSB

MSB

Flag reset at transfer completion

External clock mode

State

MCU reset

PMRA write

SMRA write

SMRB write

SRL, SRU write

STS instruction

SCK

pin (output)

SO pin

IFS

STS wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

Internal clock selection

Output level control in

idle states

Data write for transmission

Output level control in

idle states

Undefined

LSB

MSB

Flag reset at transfer completion

Internal clock mode

Figure 72 Example of Serial Interface Operation Sequence

HD404629R Series

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to serial mode
register A (SMRA: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.

Notes on Use:

Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register A (SMRA: $005) again.

Serial interrupt request flag (IFS: $023, bit 2) set: If the state is changed from transfer to another by
writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register A write or STS instruction execution must be programmed to be executed after
confirming that the

SCK pin is at 1, that is, after executing the input instruction to port R2.

Registers for Serial Interface

The serial interface operation is selected, and serial data is read and written by the following registers.

Serial Mode Register A (SMRA: $005)

Serial Mode Register B (SMRB: $028)

Serial Data Register (SRL: $006, SRU: $007)

Port Mode Register A (PMRA: $004)

Miscellaneous Register (MIS: $00C)

Serial Mode Register A (SMRA: $005): This register has the following functions (figure 74).

SCK pin function selection

Transfer clock selection

Prescaler division ratio selection

Serial interface initialization

Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.

A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to
the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is
performed during data transfer, the serial interrupt request flag (IFS: $023, bit 2) is set.

Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.

HD404629R Series

Bit

Initial value

Read/Write

Bit name

SMRA3

SMRA2

SMRA0

SMRA1

Serial mode register A (SMRA: $005)

SMRA2

SMRA0

SMRA1

SMRA3

SCK

mode selection

SCK

Output

Input

Clock source

Prescaler
division ratio

Refer to
table 29

SCK

Prescaler

System clock

External clock

Figure 74 Serial Mode Register A (SMRA)

Serial Mode Register B (SMRB: $028): This register has the following functions (figure 75).

Prescaler division ratio selection

Output level control in idle states

Serial mode register B is a 2-bit write-only register. It cannot be written during data transfer.

By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can
be reset to 0 by MCU reset. By setting bit 1 (SMRB1), the output level of the SO pin is controlled in idle
states. The output level changes at the same time that SMRB1 is written to.

HD404629R Series

Bit

Initial value

Read/Write

Bit name

Not used

SMRB0

Undefined

SMRB1

SMRB0

Transmit clock division ratio

Prescaler output divided by 2

Prescaler output divided by 4

Serial mode register B (SMRB: $028)

SMRB1

Output level control in idle states

Low level

High level

Figure 75 Serial Mode Register B (SMRB)

Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 76 and
77).

Transmission data write and shift

Receive data shift and read

Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 78.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR3

Undefined

R/W

SR2

Undefined

R/W

SR0

Undefined

R/W

SR1

Serial data register (lower digit) (SRL: $006)

Figure 76 Serial Data Register (SRL)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR7

Undefined

R/W

SR6

Undefined

R/W

SR4

Undefined

R/W

SR5

Serial data register (upper digit) (SRU: $007)

Figure 77 Serial Data Register (SRU)

LSB

MSB

Transmit clock

Serial output
data

Serial input data
latch timing

Figure 78 Serial Interface Output Timing

Port Mode Register A (PMRA: $004): This register has the following functions (figure 79).

/SI pin function selection

/SO pin function selection

Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

Not used

PMRA0

PMRA1

PMRA0

/SO mode selection

Port mode register A (PMRA: $004)

PMRA1

/SI mode selection

Figure 79 Port Mode Register A (PMRA)

HD404629R Series

Miscellaneous Register (MIS: $00C): This register has the following function (figure 80).

/SO pin PMOS control

Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1

MIS0

0.12207 ms

0.24414 ms

7.8125 ms

31.25 ms

Not used

MIS2

/SO PMOS on/off selection

Off

MIS3

Pull-up MOS on/off selection

Off

Figure 80 Miscellaneous Register (MIS)

A/D Converter

The MCU has a built-in A/D converter that uses a successive approximation method with a resistor ladder.
It can measure four analog inputs with 8-bit resolution. As shown in the block diagram of figure 81, the
A/D converter has a 4-bit A/D mode register, a 1-bit A/D start flag, and a 4-bit plus 4-bit A/D data register.

HD404629R Series

Bit

Initial value

Read/Write

Bit name

AMR3

AMR2

AMR0

Not used

A/D mode register (AMR: $016)

AMR0

Conversion time

34t

cyc

67t

cyc

AMR3

AMR2

Analog input selection

Figure 82 A/D Mode Register (AMR)

A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower
digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion,
the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and
85).

MSB

LSB

Bit 0

Bit 7

ADRU: $018

ADRL: $017

Figure 83 A/D Data Registers (ADRU, ADRL)

HD404629R Series

Bit

Initial value

Read/Write

Bit name

ADRL3

ADRL2

ADRL0

ADRL1

A/D data register (lower digit) (ADRL: $017)

Figure 84 A/D Data Register Lower Digit (ADRL)

Bit

Initial value

Read/Write

Bit name

A/D data register (upper digit) (ADRU: $018)

ADRU2

ADRU1

ADRU0

ADRU3

Figure 85 A/D Data Register Upper Digit (ADRU)

A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the
completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 86.

Bit

Initial value

Read/Write

Bit name

R/W

DTON

R/W

ADSF

R/W

LSON

R/W

WDON

A/D start flag (ADSF: $020, bit 2)

ADSF (A/D start flag)

A/D conversion started

A/D conversion completed

Refer to the description of operating
modes

DTON

Refer to the description of timers

WDON

Refer to the description of operating
modes

LSON

Figure 86 A/D Start Flag (ADSF)

HD404629R Series

Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2),
but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data
register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed.

The A/D converter does not operate in the stop, watch, and subactive modes because of the OSC clock.
During these low-power dissipation modes, current through the resistor ladder is cut off to decrease the
power input.

DTMF Generation Circuit

The MCU provides a dual-tone multifrequency (DTMF) generation circuit. The DTMF signal consists of
two sine waves to access the switching system.

Figure 87 shows the DTMF keypad and frequencies. Each key enables tones to be generated corresponding
to each frequency. Figure 88 shows a block diagram of the DTMF circuit.

The OSC clock (400 kHz, 800 kHz, 2 MHz, or 4 MHz) is changed into four clock signals through the
division circuit (

1/2

1/5

, and 1/10). The DTMF circuit uses one of the four clock signals, which is

selected by the system clock select register (SSR: $029) depending on the OSC clock frequency. The
DTMF circuit has transformed programmable dividers, sine wave counters, and control registers.

The DTMF generation circuit is controlled by the following three registers.

R1 (697 Hz)

R2 (770 Hz)

R3 (852 Hz)

R4 (941 Hz)

C1 (1,209 Hz)

C2 (1,336 Hz)

C3 (1,477 Hz)

C4 (1,633 Hz)

Figure 87 DTMF Keypad and Frequencies

HD404629R Series

100

Tone Generator Mode Register (TGM: $019): Four-bit write-only register, which controls output
frequencies as shown in figure 89, and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

TGM3

TGM2

TGM0

TGM1

Tone generator mode register (TGM: $019)

TGM3

TGM2

TONEC output frequencies

(1,209 Hz)

(1,336 Hz)

(1,477 Hz)

(1,633 Hz)

TGM1

TGM0

TONER output frequencies

(697 Hz)

(770 Hz)

(852 Hz)

(941 Hz)

Figure 89 Tone Generator Mode Register (TGM)

Tone Generator Control Register (TGC: $01A): Three-bit write-only register, which controls the
start/stop of the DTMF signal output as shown in figure 90, and is reset to $0 by MCU reset. TONER and
TONEC output can be independently controlled by bits 3 and 2 (TGC3, TGC2), and the DTMF circuit is
controlled by bit 1 (TGC1) of this register.

Bit

Initial value

Read/Write

Bit name

TGC3

TGC2

Not used

TGC1

Tone generator control register (TGC: $01A)

TGC1

DTMF enable bit

DTMF disable

DTMF enable

TGC2

TONER output control (row)

No output

TONER output (active)

TGC3

TONEC output control (column)

No output

TONEC output (active)

Figure 90 Tone Generator Control Register (TGC)

HD404629R Series

101

System Clock Select Register (SSR: $029): Four-bit write-only register. This register must be set to the
value specified in figure 91 depending on the frequency of the oscillator connected to the OSC

and OSC

pins. Note that if the combination of the oscillation frequency and the value in this register is different
from that specified in figure 91, the DTMF output frequencies will differ from the correct frequencies as
listed in figure 89.

Bit

Initial value

Read/Write

Bit name

SSR3

SSR2

SSR0

SSR1

System clock select register (SSR: $029)

SSR1

System clock selection

400 kHz

800 kHz

2 MHz

4 MHz

SSR0

SSR2

ratio selection

SUB

= f

SUB

= f

SSR3

32-kHz oscillation stop

Oscillation operates in stop mode

Oscillation stops in stop mode

32-kHz oscillation division

Note: SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a

STOPC

input during stop

mode, and will retain its value. SSR3 will also not be cleared upon entering stop mode.

Figure 91 System Clock Select Register (SSR)

HD404629R Series

102

DTMF Output: The sine waves of the row-group and column-group are individually converted in the D/A
conversion circuit which provides a high-precision ladder resistance. The DTMF output pins (TONER,
TONEC) transmit the sine waves of the row-group and column-group, respectively.

Figure 92 shows the tone output equivalent circuit. Figure 93 shows the output waveform. One cycle of
this wave consists of 32 slots. Therefore, the output waveform is stable with little distortion. Table 30 lists
the frequency deviation of the MCU from standard DTMF signals.

Table 30 Frequency Deviation of the MCU from Standard DTMF

Standard DTMF (Hz)

MCU (Hz)

Deviation from Standard (%)

697

694.44

0.37

770

769.23

0.10

852

851.06

0.11

941

938.97

0.22

1,209

1,212.12

0.26

1,336

1,333.33

0.20

1,477

1,481.48

0.30

1,633

1,639.34

0.39

Note:

This frequency deviation value does not include the frequency deviation due to the oscillator
element. Also note that in this case the ratio of the high level and low level widths in the oscillator
waveform due to the oscillator element will be 50%:50%.

GND

ref

Switch control

TONER

TONEC

Figure 92 Tone Output Equivalent Circuit

HD404629R Series

104

LCD Controller/Driver

The MCU has an LCD controller and driver which drive 4 common signal pins and 52 segment pins. The
controller consists of a RAM area in which display data is stored, a display control register (LCR: $01B),
and a duty-cycle/clock-control register (LMR: $01C) (figure 94).

Four duty cycles and the LCD clock are programmable, and a built-in dual-port RAM ensures that display
data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz
oscillation clock is selected as the LCD clock source, the LCD can even be used in watch mode, in which
the system clock stops.

Internal LCD power supply switch

LCD mode

(LMR)

GND

COM1

COM2

COM3

COM4

SEG1

SEG4

SEG5

SEG8

SEG9

SEG20

SEG21

SEG52

CL0

CL1

CL2

CL3

Note: Pin function switching circuit

LCD power supply

control circuit

Common
signal
output
circuit

LCD control

(LCR)

LCD output

(LOR1)

LCD output

(LOR2)

LCD output

(LOR3)

Dual-port

display RAM

(52 digits)

Display
control

Display data

Duty
selection

Clock

Internal data bus

Segment

signal

output

circuit

Selector

Data bus

Clock line

Signal line

Pin
control

Figure 94 Block Diagram of Liquid Crystal Display Control System

HD404629R Series

105

LCD Data Area and Segment Data ($050$083): As shown in figure 95, each bit of the storage area
corresponds to one of four duty cycles. If data is written to an area corresponding to a certain duty cycle, it
is automatically output to the corresponding segments as display data.

$060

$061

$062

$063

$064

$065

$066

$067

$068

$069

COM4

COM3

COM2

COM1

Bit 3

Bit 2

Bit 1

Bit 0

$050

$051

$052

$053

$054

$055

$056

$057

$058

$059

$05A

$05B

$05C

$05D

$05E

$05F

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

Bit 3

Bit 2

Bit 1

Bit 0

$06A

$06B

$06C

$06D

$06E

$06F

$070

$071

$072

$073

$074

$075

$076

$077

$078

$079

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

$07A

$07B

$07C

$07D

$07E

$07F

$080

$081

$082

$083

COM4

COM3

COM2

COM1

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG17

SEG18

SEG19

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

RAM
address

Figure 95 Configuration of LCD RAM Area (for Dual-Port RAM)

HD404629R Series

106

LCD Control Register (LCR: $01B): Three-bit write-only register which controls LCD blanking, on/off
switching of the liquid-crystal display's power supply division resistor, and display in watch and subactive
modes, as shown in figure 96.

Blank/display

Blank: Segment signals are turned off, regardless of LCD RAM data setting.

Display: LCD RAM data is output as segment signals.

Power switch on/off

Off: The power switch is off.

On: The power switch is on and V1 is V

Watch/subactive mode display

Off: In watch and subactive modes, all common and segment pins are grounded and the liquid-crystal

power switch is turned off.

On: In watch and subactive modes, LCD RAM data is output as segment signals.

Bit

Initial value

Read/Write

Bit name

Not used

LCR2

LCR0

LCR1

LCD display control register (LCR: $01B)

LCR1

Power switch on/off

Off

LCR0

Blank/display

Blank

Display

Display on/off selection in
watch and subactive modes

LCR2

Off

Figure 96 LCD Control Register (LCR)

HD404629R Series

107

LCD Duty-Cycle/Clock Control Register (LMR: $01C): Four-bit write-only register which selects the
display duty cycle and LCD clock source, as shown in figure 97. The dependence of frame
frequency on duty cycle is listed in table 31.

Bit

Initial value

Read/Write

Bit name

LMR3

LMR2

LMR0

LMR1

LCD duty cycle/clock control register (LMR: $01C)

LMR3

LMR2

Input clock source selection

LMR1

LMR0

Duty cycle selection

1/4 duty

1/3 duty

1/2 duty

Static

CL0 (32.768-kHz

duty/64: when

32.768-kHz oscillation is used)

CL1 (f

OSC

duty cycle/1024)

CL2 (f

OSC

duty cycle/8192)

CL3 (refer to table 31)

Figure 97 LCD Duty-Cycle/Clock Control Register (LMR)

HD404629R Series

108

Table 31 LCD Frame Frequencies for Different Duty Cycles

Frame Frequencies

Duty Cycle

LMR3

LMR2

OSC

400 kHz

OSC

800 kHZ

OSC

2 MHz

OSC

4 MHz

Static

CL0

512 Hz

CL1

390.6 Hz

781.3 Hz

1953 Hz

3906 Hz

CL2

48.8 Hz

97.7 Hz

244.1 Hz

488.3 Hz

CL3*

24.4 Hz

48.8 Hz

122.1 Hz

244.1 Hz

64 Hz

1/2

CL0

256 Hz

CL1

195.3 Hz

390.6 Hz

976.6 Hz

1953 Hz

CL2

24.4 Hz

48.8 Hz

122.1 Hz

244.1 Hz

CL3*

12.2 Hz

24.4 Hz

61 Hz

122.1 Hz

32 Hz

1/3

CL0

170.7 Hz

CL1

130.2 Hz

260.4 Hz

651 Hz

1302 Hz

CL2

16.3 Hz

32.6 Hz

81.4 Hz

162.8 Hz

CL3*

8.1 Hz

16.3 Hz

40.7 Hz

81.4 Hz

21.3 Hz

1/4

CL0

128 Hz

CL1

97.7 Hz

195.3 Hz

488.3 Hz

976.6 Hz

CL2

12.2 Hz

24.4 Hz

61 Hz

122.1 Hz

CL3*

6.1 Hz

12.2 Hz

30.5 Hz

61 Hz

16 Hz

Note: * The division ratio depends on the value of bit 3 of timer mode register A (TMA).

Upper value: When TMA3 = 0, CL3 = f

OSC

duty cycle/16384.

Lower value: When TMA3 = 1, CL3 = 32.768 kHz

duty cycle/512.

HD404629R Series

109

LCD Output Register 1 (LOR1: $01D): Write-only register used to specify ports R3

as pins SEG1

SEG4 by individual pins (figure 98).

Bit

Initial value

Read/Write

Bit name

LOR13

LOR12

LOR10

LOR11

LCD output register 1 (LOR1: $01D)

LOR10

/SEG1 mode selection

SEG1

LOR11

/SEG2 mode selection

SEG2

LOR12

/SEG3 mode selection

SEG3

LOR13

/SEG4 mode selection

SEG4

Figure 98 LCD Output Register 1 (LOR1)

LCD Output Register 2 (LOR2: $01E): Write-only register used to specify ports R4

as pins SEG5

SEG8 by individual pins (figure 99).

Bit

Initial value

Read/Write

Bit name

LOR23

LOR22

LOR20

LOR21

LCD output register 2 (LOR2: $01E)

LOR20

/SEG5 mode selection

SEG5

LOR21

/SEG6 mode selection

SEG6

LOR22

/SEG7 mode selection

SEG7

LOR23

/SEG8 mode selection

SEG8

Figure 99 LCD Output Register 2 (LOR2)

HD404629R Series

110

LCD Output Register 3 (LOR3: $01F): Write-only register used to specify ports R5R7 as pins SEG9
SEG20 in 4-pin units (figure 100).

Bit

Initial value

Read/Write

Bit name

Not used

LOR32

LOR30

LOR31

LCD output register 3 (LOR3: $01F)

LOR30

/SEG9R5

/SEG12 mode selection

-R5

SEG9SEG12

LOR31

/SEG13R6

/SEG16 mode selection

-R6

SEG13SEG16

LOR32

/SEG17R7

/SEG20 mode selection

-R7

SEG17SEG20

Figure 100 LCD Output Register 3 (LOR3)

Large Liquid-Crystal Panel Drive and V

LCD

: To drive a large-capacity LCD, decrease the resistance of

the built-in division resistors by attaching external resistors in parallel, as shown in figure 101.

The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix
configuration of the LCD complicates the paths of charge/discharge currents flowing through the
capacitors--the resistance will also vary with lighting conditions. This size must be determined by trial-
and-error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 to 10
k

would usually be suitable. (Another effective method is to attach capacitors of 0.1 to 0.3

F.)

Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid-crystal drive
voltage (V

LCD

HD404629R Series

112

ZTAT

Microcomputer with Built-in programmable ROM

Programming of Built-in programmable ROM

The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM.

PROM mode is set up by setting the

TEST, M

, and

terminals to "Low" level and the RESET terminal

to "High" level.

Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256.
Using a socket adapter for specific use of each product, programming is possible with a general-purpose
PROM writer.

Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the
general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits
to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to
write to a 16kword of built-in PROM with a general-purpose PROM writer, specify 32kbyte address
($0000-$7FFF).

Notes:

1. When programming with a PROM writer, set up each ROM size to the address given in table b. If it is

programmed erroneously to an address given in Table 33 or later, check of writing of PROM may
become impossible. Particularly, caution should be exercised in the case of a plastic package since
reprogramming is impossible with it. Set the data in unused addresses to $FF.

2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the

product may break down due to overcurrent. Be sure to check that they are properly set to the writer
before starting the writing process.

3. Two levels of program voltages (V

) are available for the PROM: 12.5 V and 21 V. Our product

employs a V

of 12.5 V. If a voltage of 21 V is applied, permanent breakdown of the product will

result. The V

of 12.5 V is obtained for the PROM writer by setting it according to the Intel 27258

specifications.

Writing/verification

Programming of the built-in program ROM employs a high speed programming method. With this method,
high speed writing is effected without voltage stress to the device or without damaging the reliability of the
written data.

For precautions for PROM writing procedure, refer to section 2, "Characteristics of ZTAT

Microcomputer's Built-in Programmable ROM and precautions for its Applications."

HD404629R Series

114

Programmable ROM (HD4074629)

The HD4074629 is a ZTAT

microcomputer with built-in PROM that can be programmed in PROM

mode.

PROM Mode Pin Description

Pin No.

MCU Mode

PROM Mode

Pin No.

MCU Mode

PROM Mode

FP-100B
TFP-100B

FP-100A

Pin
Name

I/O

Pin
Name

I/O

FP-100B
TFP-100B

FP-100A

Pin
Name

I/O

Pin
Name

I/O

STOPC

I/O

INT

I/O

INT

I/O

GND

/INT

I/O

GND

/INT

I/O

GND

/INT

I/O

TEST

GND

/TOB

I/O

OSC

/TOC

I/O

OSC

/TOD

I/O

RESET

EVNB

I/O

GND

/EVND

I/O

SCK

I/O

GND

/SI

I/O

/SO

I/O

/SEG1

I/O

/SEG2

I/O

/SEG3

I/O

/SEG4

I/O

/SEG5

I/O

/SEG6

I/O

/SEG7

I/O

/SEG8

I/O

/SEG9

I/O

Notes on next page.

HD404629R Series

115

PROM Mode Pin Description (cont)

Pin No.

MCU Mode

PROM Mode

Pin No.

MCU Mode

PROM Mode

FP-100B
TFP-100B

FP-100A

Pin
Name

I/O

Pin
Name

I/O

FP-100B
TFP-100B

FP-100A

Pin
Name

I/O

Pin
Name

I/O

/SEG10 I/O

I/O

SEG37

/SEG11 I/O

I/O

SEG38

/SEG12 I/O

I/O

SEG39

/SEG13 I/O

I/O

SEG40

/SEG14 I/O

I/O

SEG41

/SEG15 I/O

I/O

SEG42

/SEG16 I/O

SEG43

/SEG17 I/O

SEG44

/SEG18 I/O

SEG45

/SEG19 I/O

SEG46

/SEG20 I/O

SEG47

SEG21

SEG48

SEG22

SEG49

SEG23

SEG50

SEG24

SEG51

SEG25

SEG52

SEG26

COM1

SEG27

COM2

SEG28

COM3

SEG29

COM4

SEG30

SEG31

SEG32

SEG33

SEG34

100

TONEC

SEG35

TONER

SEG36

100

ref

Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin

2. Each of O

has two pins; before using, each pair must be connected together.

HD404629R Series

116

PROM Mode Pin Functions

: Applies the programming voltage (12.5 V

0.3 V) to the built-in PROM.

CE: Inputs a control signal to enable PROM programming and verification.

: Inputs a data output control signal for verification.

: Act as address input pins of the built-in PROM.

: Act as data bus input pins of the built-in PROM. Each of O

has two pins; before using these

pins, connect each pair together.

, RESET,

TEST: Used to set PROM mode. The MCU is set to the PROM mode by pulling M

, and

TEST low, and RESET high.

Other Pins (FP-100B/FP-100A): Connect pins 1/3 (AV

), 8/10 (OSC

), 16/18 (D

), 17/19 (D

), 53/55

(R6

/SEG16), and 97/99 (V

) to V

, and pins 6/8 (AV

) and 11/13 (X1) to GND. Leave other pins

open.

$0000

Vector address

Zero-page subroutine
(64 words)

Pattern
(4,096 words)

Program
(16,384 words)

$0001

$001F

$0080

$007F

$2000

$1FFF

$0020

$7FFF

Bit 4

Bit 8

Bit 3

Bit 7

Bit 2

Bit 6

Bit 1

Bit 5

Bit 0

Bit 9

Upper three bits are not to be used
(fill them with 111)

Upper 5 bits

Lower 5 bits

$0000

$000F
$0010

$003F
$0040

$3FFF

$0000

$0001

$0002

$0003

$0004

$0005
$0006

$0007
$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

JMPL instruction

(jump to RESET,

STOPC

routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B, INT

routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer C, INT

routine)

JMPL instruction

(jump to timer D, INT

routine)

JMPL instruction

(jump to A/D, serial routine)

$0FFF
$1000

Figure 102 Memory Map in PROM Mode

HD404629R Series

118

Programming Electrical Characteristics

DC Characteristics (V

= 6.0 V

0.25 V, V

= 12.5 V

0.3 V, T

= 25

C, unless otherwise

specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Input high

, A

2.2

+ 0.3

voltage level

Input low

, A

0.3

0.8

voltage level

Output high

2.4

= 200

voltage level

Output low

0.4

= 1.6 mA

voltage level

Input leakage

, A

= 5.25 V/0.5 V

current

AC Characteristics (V

= 6.0 V

0.25 V, V

= 12.5 V

0.3 V, T

= 25

C, unless otherwise

specified)

Item

Symbol

Min

Typ

Max

Unit

Test Condition

Address setup time

See figure 108

setup time

OES

Data setup time

Address hold time

Data hold time

Data output disable time

130

setup time

VPS

Program pulse width

0.95

1.0

1.05

pulse width during

OPW

2.85

78.75

overprogramming

setup time

VCS

Data output delay time

500

HD404629R Series

120

Notes on PROM Programming

Principles of Programming/Erasure: A memory cell in a ZTATTM microcomputer is the same as an
EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot
electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an
SiO

film. The change in threshold voltage of a memory cell with a charged floating gate makes the

corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 105).

The charge in a memory cell may decrease with time. This decrease is usually due to one of the following
causes:

Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure
principle.

Heat excites trapped electrons, allowing them to escape.

High voltages between the control gate and drain may erase electrons.

If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However,
electron erasure does not often occur because defective devices are detected and removed at the testing
stage.

Control gate

Floating gate

Drain

SiO

Source

Control gate

Floating gate

Drain

SiO

Source

Erasure (1)

Write (0)

Figure 105 Cross-Sections of a PROM Cell

PROM Programming: PROM memory cells must be programmed under specific voltage and timing
conditions. The higher the programming voltage V

and the longer the programming pulse t

is applied,

the more electrons are injected into the floating gates. However, if V

exceeds specifications, the pn

junctions may be permanently damaged. Pay particular attention to overshooting in the PROM
programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may
reduce breakdown voltages.

The ZTATTM microcomputer is electrically connected to the PROM programmer by a socket adapter.
Therefore, note the following points:

Check that the socket adapter is firmly mounted on the PROM programmer.

Do not touch the socket adapter or the LSI
during the programming. Touching them may affect the quality of the contacts, which will cause
programming errors.

HD404629R Series

121

PROM Reliability after Programming: In general, semiconductor devices retain their reliability,
provided that some initial defects can be excluded. These initial defects can be detected and rejected by
screening. Baking devices under high-temperature conditions is one method of screening that can rapidly
eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure
section.)

ZTATTM microcomputer devices are extremely reliable because they have been subjected to such a
screening method during the wafer fabrication process, but Hitachi recommends that each device be
exposed to 150

C at one atmosphere for at least 48 hours after it is programmed, to ensure its best

performance. The recommended screening procedure is shown in figure 106.

Note:

If programming errors occur continuously during PROM programming, suspend programming and
check for problems in the PROM programmer or socket adapter. If programming verification
indicates errors in programming or after high-temperature exposure, please inform Hitachi.

Note: Exposure time is measured from when the temperature in the heater reaches 150°C.

Programming, verification

Exposure to high temperature, without power

150°C ± 10°C, 48 h

+8 h
0 h

Program read check
V = 4.5 V or 5.5 V

Figure 106 Recommended Screening Procedure

HD404629R Series

122

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes, as shown in figure 107 and described below.

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.

W register

X register

Y register

RAM address

Register Direct Addressing

RAM address

Direct Addressing

2nd word of Instruction

Opcode

1st word of Instruction

RAM address

Memory Register Addressing

Opcode

Instruction

Figure 107 RAM Addressing Modes

HD404629R Series

123

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes, as shown in figure 108 and described below.

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC

) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC

) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 105. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.

Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC

), and 0s are placed in the eight high-

order bits (PC

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 109. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.

The P instruction has no effect on the program counter.

HD404629R Series

124

2nd word of instruction

Opcode

1st word of instruction

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 108 ROM Addressing Modes

HD404629R Series

127

Instruction Set

The MCU has 101 instructions, classified into the following 10 groups:

Immediate instructions

RAM addressing instructions

RAM register instructions

Arithmetic instructions

Compare instructions

RAM bit manipulation instructions

ROM addressing instructions

Input/output instructions

Control instructions

The functions of these instructions are listed in tables 34 to 43, and an opcode map is shown in table 44.

Table 34 Immediate Instructions

Words/

Operation Mnemonic

Operation

Code

Function

Status Cycles

Load A from

LAI i

1/1

immediate

Load B from

LBI i

1/1

immediate

Load memory

LMID i,d

2/2

from

immediate

Load memory

LMIIY i

1/1

from immediate,

Y + 1

increment Y

HD404629R Series

128

Table 35 Register-Register Instructions

Words/

Operation Mnemonic

Operation

Code

Function

Status Cycles

Load A

LAB

1/1

from B

Load B

LBA

1/1

from A

Load A

LAW

2/2

from W

Load A

LAY

1/1

from Y

Load A

LASPX

SPX

1/1

from SPX

Load A

LASPY

SPY

1/1

from SPY

Load A

LAMR m

MR (m)

1/1

from MR

Exchange

XMRA m

MR (m)

1/1

MR and A

Note:

Although the LAW and LWA instructions require an operand ($000) in the second word, the

assembler generates it automatically and thus there is no need to specify it explicitly.

HD404629R Series

129

Table 36 RAM Address Instructions

Words/

Operation Mnemonic

Operation

Code

Function

Status Cycles

Load W from

LWI i

1/1

immediate

Load X from

LXI i

1/1

immediate

Load Y from

LYI i

1/1

immediate

Load W

LWA

2/2

from A

Load X

LXA

1/1

from A

Load Y

LYA

1/1

from A

Increment Y

Y + 1

1/1

Decrement Y

Y 1

1/1

Add A to Y

AYY

Y + A

OVF

1/1

Subtract A

SYY

Y A

1/1

from Y

Exchange X

XSPX

SPX

1/1

and SPX

Exchange Y

XSPY

SPY

1/1

and SPY

Exchange X

XSPXY

SPX,

1/1

and SPX,

SPY

Y and SPY

Note:

Although the LAW and LWA instructions require an operand ($000) in the second word, the

assembler generates it automatically and thus there is no need to specify it explicitly.

HD404629R Series

130

Table 37 RAM Register Instructions

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Load A from
memory

LAM

1/1

LAMX

SPX

LAMY

SPY

LAMXY

SPX,

SPY

Load A from
memory

LAMD d

0
d

1
d

0
d

1
d

0
d

2/2

Load B from
memory

LBM

1/1

LBMX

SPX

LBMY

SPY

LBMXY

SPX,

SPY

Load memory
from A

LMA

1/1

LMAX

SPX

LMAY

SPY

LMAXY

SPX,

SPY

Load memory
from A

LMAD d

0
d

1
d

0
d

1
d

0
d

2/2

HD404629R Series

131

Table 37 RAM Register Instructions (cont)

Operation

Mnemonic

Operation Code

Function

Status

Words/
Cycles

Load memory
from A,
increment Y

LMAIY

Y + 1

1/1

LMAIYX

Y + 1

SPX

Load memory
from A,
decrement Y

LMADY

Y 1

1/1

LMADYX

Y 1

SPX

Exchange
memory
and A

XMA

1/1

XMAX

SPX

XMAY

SPY

XMAXY

SPX,

SPY

Exchange
memory
and A

XMAD d

0
d

1
d

0
d

2/2

Exchange
memory
and B

XMB

1/1

XMBX

SPX

XMBY

SPY

XMBXY

SPX,

SPY

HD404629R Series

132

Table 38 Arithmetic Instructions

Words/

Operation Mnemonic Operation

Code

Function

Status

Cycles

Add immediate to AI i

A + i

OVF

1/1

Increment B

B + 1

1/1

Decrement B

B 1

1/1

Decimal

DAA

1/1

adjust for addition

Decimal

DAS

1/1

adjust for
subtraction

Negate A

NEGA

+ 1

1/1

Complement

COMB

1/1

Rotate right A

ROTR

1/1

with carry

Rotate left A

ROTL

1/1

with carry

Set carry

SEC

1/1

Reset carry

REC

1/1

Test carry

1/1

Add A to memory

M + A

OVF

1/1

Add A to memory

AMD d

M + A

OVF

2/2

Add A to memory

AMC

M + A + CA

A OVF

1/1

with carry

OVF

Add A to memory

AMCD d

M + A + CA

A OVF

2/2

with carry

OVF

Subtract A

SMC

M A

A NB

1/1

from memory

with carry

Subtract A

SMCD d

M A

A NB

2/2

from memory

with carry

OR A and B

1/1

HD404629R Series

133

Table 38 Arithmetic Instructions (cont)

Words/

Operation Mnemonic

Operation

Code

Function

Status Cycles

AND memory

ANM

1/1

with A

AND memory

ANMD d

2/2

with A

OR memory

ORM

1/1

with A

OR memory

ORMD d

2/2

with A

EOR memory

EORM

NZ 1/1

with A

EOR memory

EORMD d

NZ 2/2

with A

HD404629R Series

134

Table 39 Compare Instructions

Words/

Operation Mnemonic

Operation

Code

Function

Status Cycles

Immediate not

INEM i

1/1

equal to
memory

Immediate not

INEMD i, d

2/2

equal to

memory

A not equal to

ANEM

1/1

memory

A not equal to

ANEMD d

2/2

memory

B not equal to

BNEM

1/1

memory

Y not equal to

YNEI i

1/1

immediate

Immediate

ILEM i

1/1

less or equal
to memory

Immediate

ILEMD i, d

2/2

less or equal

to memory

A less or

ALEM

1/1

equal to
memory

A less or

ALEMD d

2/2

equal to

memory

B less or

BLEM

1/1

equal to
memory

A less or

ALEI i

1/1

equal to
immediate

HD404629R Series

135

Table 40 RAM Bit Manipulation Instructions

Words/

Operation Mnemonic

Operation

Code

Function

Status

Cycles

Set memory bit

SEM n

M (n)

1/1

Set memory bit

SEMD n,d

M (n)

2/2

Reset memory

REM n

M (n)

1/1

bit

Reset memory

REMD n,d

M (n)

2/2

bit

Test memory bit

TM n

M (n)

1/1

Test memory bit

TM n,d

M (n)

2/2

Table 41 ROM Addressing Instructions

Words/

Operation Mnemonic

Operation

Code

Function

Status Cycles

Branch on

BR b

1/1

status 1

Long branch

BRL u

2/2

on status 1

Long jump

JMPL u

2/2

unconditionally d

Subroutine jump

CAL a

1/2

on status 1

Long subroutine

CALL u

2/2

jump on status 1

Table branch

TBR p

1/1

Return from

RTN

1/3

subroutine

Return from

RTNI

IE,

1/3

interrupt

carry restored

HD404629R Series

136

Table 42 Input/Output Instructions

Words/

Operation Mnemonic

Operation

Code

Function

Status Cycles

Set discrete

SED

D (Y)

1/1

I/O latch

Set discrete

SEDD m

D (m)

1/1

I/O latch
direct

Reset

RED

D (Y)

1/1

discrete I/O latch

Reset

REDD m

D (m)

1/1

discrete I/O latch
direct

Test discrete I/O

D (Y)

1/1

latch

Test discrete I/O

TDD m

D (m)

1/1

latch direct

Load A

LAR m

R (m)

1/1

from R-port
register

Load B

LBR m

R (m)

1/1

from R-port
register

Load R-port

LRA m

R (m)

1/1

Load R-port

LRB m

R (m)

1/1

Pattern

P p

1/2

generation

HD404629R Series

138

Table 44 Opcode Map

LBI i(4)

LYI i(4)

LXI i(4)

LAI i(4)

LBR m(4)

LAR m(4)

REDD m(4)

LAMR m(4)

AI i(4)

LMIIY i(4)

TDD m(4)

ALEI i(4)

LRB m(4)

LRA m(4)

SEDD m(4)

XMRA m(4)

1-word/2-cycle
instruction

1-word/3-cycle
instruction

RAM direct address
instruction
(2-word/2-cycle)

2-word/2-cycle
instruction

NOP

XSPX

XSPY XSPXY ANEM

ORM

LBM(XY)

BNEM

LAB

LMAIY(X)

AYY

LASPY

RTN

RTNI

ALEM

AMC

EORM

NEGA

RED

LASPX

INEM i(4)

ILEM i(4)

YNEI i(4)

XMA(XY)

LAM(XY)

SEM n(2)

LMA(XY)

REM n(2)

SMC

TM n(2)

ANM

ROTR

DAA

DAS

LAY

ROTL

SEC

LBA

LYA

REC

LXA

BLEM

SYY

SED

XMB(XY)

LMADY(X)

LWI i(2)

TBR p(4)

HD404629R Series

140

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to (V

+ 0.3)

Total permissible input current

100

Total permissible output current

Maximum input current

4, 5

4, 6

Maximum output current

7, 8

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal

operation must be under the conditions stated in the electrical characteristics tables. If these
conditions are exceeded, the LSI may malfunction or its reliability may be affected.

1. Applies to D

) of the HD4074629.

2. The total permissible input current is the total of input currents simultaneously flowing in from all

the I/O pins to ground.

3. The total permissible output current is the total of output currents simultaneously flowing out from

to all I/O pins.

4. The maximum input current is the maximum current flowing from each I/O pin to ground.

5. Applies to R0R7.

6. Applies to D

7. The maximum output current is the maximum current flowing out from V

to each I/O pin.

8. Applies to D

and R0R7.

HD404629R Series

141

Electrical Characteristics

DC Characteristics (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V, GND = 0 V,

= 20

C to +75

C; HD4074629: V

C C

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

RESET,

SCK

SI,

INT

, INT

INT

STOPC

EVNB

, EVND

0.9V

+ 0.3

OSC

0.3

+ 0.3

External clock
operation

Input low
voltage

RESET,

SCK

SI,

INT

, INT

INT

STOPC

EVNB

, EVND

0.3

0.1V

OSC

0.3

External clock
operation

Output high
voltage

SCK

, SO, TOB,

TOC, TOD

1.0

= 0.5 mA

Output low
voltage

SCK

, SO, TOB,

TOC, TOD

0.4

= 0.4 mA

I/O leakage
current

I L

RESET,

SCK

SI,

INT

, INT

INT

STOPC

EVNB

, EVND,

OSC

, TOB,

TOC, TOD, SO

1.0

= 0 V to V

Current
dissipation in
active mode

CC1

(HD404628R,
HD4046212R,
HD404629R)

2.5

5.0

= 5.0 V,

OSC

= 4 MHz

2, 4

(HD4074629)

CC2

(HD404628R,
HD4046212R,
HD404629R)

0.3

0.9

= 3.0 V,

OSC

= 800 kHz

2, 4

(HD4074629)

0.6

1.8

Current
dissipation in
standby mode

SBY1

(HD404628R,
HD4046212R,
HD404629R)

1.0

2.0

= 5.0 V,

OSC

= 4 MHz,

LCD on

3, 4

(HD4074629)

1.2

SBY2

0.2

0.7

= 3.0 V,

OSC

= 800 kHz,

LCD on

3, 4

Notes on next page.

HD404629R Series

142

DC Characteristics (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V, GND = 0 V,

= 20

C to +75

C; HD4074629: V

C C

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

unless otherwise specified) (cont)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Current
dissipation in
subactive mode

SUB

HD404628R,
HD4046212R,
HD404629R:
V

= 3.0 V,

LCD on
32-kHz oscillator

150

HD4074629:
V

= 3.0 V,

LCD on
32-kHz oscillator

Current
dissipation in

WTC1

(HD404628R,
HD4046212R,
HD404629R)

= 3.0 V,

LCD on
32-kHz oscillator

(HD4074629)

watch mode

WTC2

(HD404628R,
HD4046212R,
HD404629R)

= 3.0 V,

LCD off
32-kHz oscillator

(HD4074629)

Current
dissipation in
stop mode

STOP

(HD404628R,
HD4046212R,
HD404629R)

0.5

= 3.0 V,

No 32-kHz oscillator

(HD4074629)

Stop mode
retaining voltage

STOP

No 32-kHz
oscillator

Notes:

1. Output buffer current is excluded.
2. I

CC1

and I

CC2

are the source currents when no I/O current is flowing while the MCU is in reset state.

Test conditions:

MCU:

Reset

Pins:

RESET at V

0.3 V to V

)

TEST

at V

0.3 V to V

)

3. I

SBY1

and I

SBY2

are the source currents when no I/O current is flowing while the MCU timer is operating.

Test conditions:

MCU:

I/O reset
Serial interface stopped
DTMF stopped
Standby mode

Pins:

RESET at GND (0 V to 0.3 V)

TEST

at V

0.3 V to V

)

4. These are the source currents when no I/O current is flowing.

Test conditions:

Pins:

RESET at GND (0 V to 0.3 V)

TEST

at V

0.3 V to V

)

) at V

0.3 V to V

) for the HD4074629

5. The required voltage for RAM data retention.

HD404629R Series

143

I/O Characteristics for Standard Pins (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20

C to +75

C; HD4074629: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

, D

R0R7

0.7V

+ 0.3

Input low
voltage

R0R7

0.3

0.3V

Output high
voltage

R0R7

1.0

= 0.5 mA

Output low
voltage

R0R7

0.4

= 0.4 mA

I/O leakage

I L

, R0R7

= 0 V to V

current

HD404628R,
HD4046212R,
HD404629R:
V

= 0 V to V

HD4074629:
V

= V

0.3 V

to V

HD4074629:
V

= 0 V to 0.3 V

Pull-up MOS
current

R0R7

= 3.0 V,

= 0 V

Note: 1. Output buffer current is excluded.

HD404629R Series

144

I/O Characteristics for High-Current Pins (HD404628R, HD4046212R, HD404629R: V

= 2.7 to

6.0 V, GND = 0 V, T

= 20

C to +75

C; HD4074629: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to

+75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

0.7V

+ 0.3

Input low
voltage

0.3

0.3V

Output high
voltage

1.0

= 0.5 mA

Output low

0.4

= 0.4 mA

voltage

2.0

= 15 mA,

= 4.5 V to 6.0 V

I/O leakage
current

I L

= 0 V to V

Pull-up MOS
current

= 3 V,

= 0 V

Note:

1. The test condition of HD4074629 is V

= 4.5 V to 5.5 V.

2. Output buffer current is excluded.

LCD Circuit Characteristics (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V, GND =

0 V, T

= 20

C to +75

C; HD4074629: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

C, unless

otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Segment driver
voltage drop

SEG1SEG52

0.6

= 3

Common driver
voltage drop

COM1COM4

0.3

= 3

LCD power
supply division
resistance

--
(HD404628R,
HD4046212R,
HD404629R)

300

900

Between V

and

GND

--
(HD4074629)

100

300

900

LCD voltage

LCD

2.7

Notes: 1. V

and V

are the voltage drops from power supply pins V

, V

, and GND to each segment

pin and each common pin, respectively.

2. When V

LCD

is supplied from an external source, the following relations must be retained:

GND

HD404629R Series

145

DTMF Characteristics (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V, GND = 0 V,

= 20

C to +75

C; HD4074629: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

C, unless

otherwise specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Tone output
voltage (1)

TONER

500

660

rms

ref

GND = 2.0 V,

= 100 k

Tone output
voltage (2)

TONEC

520

690

rms

ref

GND = 2.0 V,

= 100 k

Tone output
distortion

DIS

Short circuit
between TONER
and TONEC,
R

= 100 k

Tone output
ratio

2.5

Short circuit
between TONER
and TONEC,
R

= 100 k

Notes: 1. See figure 106.

2. See figure 107.

3. 400 kHz, 800 kHz, 2 MHz, or 4 MHz can be used as the operating frequency (f

OSC

HD404629R Series

146

A/D Converter Characteristics (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20

C to +75

C; HD4074629: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Analog power
voltage

0.3

+ 0.3

2.7 V

Analog input
voltage

Current between
AV

and AV

A D

--
(HD404628R,
HD4046212R,
HD404629R)

250

= AV

= 5.0 V

--
(HD4074629)

150

Analog input
capacitance

Resolution

Bit

Number of inputs

Chan-
nel

Absolute accuracy

2.0

LSB

= 25

= 4.55.5 V

Conversion time

cyc

Input impedance

OSC

= 1 MHz,

= 0.0 V

HD404629R Series

147

AC Characteristics (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V, GND = 0 V,

= 20

C to +75

C; HD4074629: V

C C

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Clock oscillation

OSC

, OSC

400

kHz

1/4 division

frequency

800

kHz

1/4 division

MHz

1/4 division

MHz

1/4 division;
HD404628,
HD4046212,
HD404629:
V

= 3.0 to 6.0 V

X1, X2

32.768

kHz

Instruction cycle

cyc

OSC

= 400 kHz

time

OSC

= 800 kHz

OSC

= 2 MHz

OSC

= 4 MHz;

HD404628,
HD4046212,
HD404629:
V

= 3.0 to 6.0 V

subcyc

244.14

32-kHz oscillator,
1/8 division

122.07

32-kHz oscillator,
1/4 division

Oscillation

OSC

, OSC

7.5

Ceramic oscillator

stabilization time

OSC

, OSC

(HD404628R,
HD4046212R,
HD404629R)

Crystal oscillator
V

= 3.0 to 6.0 V

X1, X2

= 10

C to

+60

External clock

CPH

OSC

1100

OSC

= 400 kHz

high width

550

OSC

= 800 kHz

215

OSC

= 2 MHz

105

OSC

= 4 MHz

External clock

CPL

OSC

1100

OSC

= 400 kHz

low width

550

OSC

= 800 kHz

215

OSC

= 2 MHz

105

OSC

= 4 MHz

External clock

CPr

OSC

150

OSC

= 400 kHz

rise time

OSC

= 800 kHz

OSC

= 2 MHz

OSC

= 4 MHz

Notes on next page.

HD404629R Series

148

AC Characteristics (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V, GND = 0 V, T

20

C to +75

C; HD4074629: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

C, unless otherwise

specified) (cont)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

External clock

CPf

OSC

150

OSC

= 400 kHz

fall time

OSC

= 800 kHz

OSC

= 2 MHz

OSC

= 4 MHz

INT

EVNB

EVND high widths

I H

INT

EVNB

, EVND

cyc

subcyc

INT

EVNB

EVND low widths

I L

INT

EVNB

, EVND

cyc

subcyc

RESET high width

RSTH

RESET

cyc

STOPC

low width

STPL

STOPC

RESET fall time

RSTf

RESET

STOPC

rise time

STPr

STOPC

Input capacitance

All pins
except D

f = 1 MHz
V

= 0 V,

HD404628R,
HD4046212R,
HD404629R:
f = 1 MHz,
V

= 0 V

180

HD4074629:
f = 1 MHz,
V

= 0 V

Notes: 1. Be sure to set system clock selection register (SSR) bits SSR1 and SSR0 to match the system

clock oscillator frequency.

2. Applies to voltage ranges V

= 3.5 to 5.5 V for the HD4074629.

3. There are three oscillator stabilization times.

(1) At power on, the time between the point where V

reaches 2.7 V and the point where

oscillation has stabilized.

(2) At clearing stop mode, the time between the point where the RESET pin reaches the high

level and the point where oscillation has stabilized.

(3) At clearing stop mode, the time between the point where the

STOPC

pin reaches the low level

and the point where oscillation has stabilized.
At power on or when stop mode is cleared, RESET or

STOPC

must be input for at least t

ensure the oscillation stabilization time.
Since the oscillator stabilization time will depend on circuit constants and stray capacitances,
determine the oscillator by consulting with the oscillator's manufacturer.
Be sure to set miscellaneous register (MIS) bits MIS1 and MIS0 to match the system clock
oscillator stabilization time.

4. Refer to figure 108.
5. Refer to figure 109. The t

cyc

unit applies when the MCU is in standby or active mode.

The t

subcyc

unit applies when the MCU is in watch or subactive mode.

6. Refer to figure 110.
7. Refer to figure 111.

HD404629R Series

149

Serial Interface Timing Characteristics (HD404628R, HD4046212R, HD404629R: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20

C to +75

C; HD4074629: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

unless otherwise specified)
During Transmit Clock Output

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time

Scyc

SCK

1.0

cyc

Load shown in
figure 113

Transmit clock high width

SCKH

SCK

0.5

Scyc

Load shown in
figure 113

Transmit clock low width

SCKL

SCK

0.5

Scyc

Load shown in
figure 113

Transmit clock rise time

SCKr

SCK

200

Load shown in
figure 113

Transmit clock fall time

SCKf

SCK

200

Load shown in
figure 113

Serial output data
delay time

DSO

500

Load shown in
figure 113

Serial input data
setup time

SSI

300

Serial input data
hold time

HSI

300

Note: 1. Refer to figure 112.

During Transmit Clock Input

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time

Scyc

SCK

1.0

cyc

Transmit clock high width

SCKH

SCK

0.5

Scyc

Transmit clock low width

SCKL

SCK

0.5

Scyc

Transmit clock rise time

SCKr

SCK

200

Transmit clock fall time

SCKf

SCK

200

Serial output data
delay time

DSO

500

Load shown in
figure 113

Serial input data
setup time

SSI

300

Serial input data
hold time

HSI

300

Note: 1. Refer to figure 112.

HD404629R Series

153

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version
(HD404629R). A 16-kword data size is required to change ROM data to mask manufacturing data since the
program used is for a 16-kword version.

This limitation applies when using an EPROM or a data base.

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(8,192 words)

Not used

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(12,288 words)

Not used

ROM 8-kword version:
HD404628R
Address $2000$3FFF

ROM 12-kword version:
HD4046212R
Address $3000$3FFF

$0000

$000F
$0010

$003F
$0040

$1FFF
$2000

$3FFF

$0000

$000F
$0010

$003F
$0040

$2FFF
$3000

$3FFF

Fill this area with 1s

HD404629R Series

154

HD404628R/HD4046212R/ HD404629R Option List

Please check off the appropriate applications and enter the necessary information.

Date of order

Customer

Department

Name

ROM code name

LSI number
(Hitachi entry)

1. ROM Size

HD404628R

8-kword

HD4046212R

12-kword

HD404629R

16-kword

2. Optional Functions

With 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, without time-base for clock

Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).

3. ROM Code Data Type

Please specify the first type below (the upper bits and lower bits are mixed together), when using the
EPROM on-package microcomputer type (including ZTAT

version).

The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the
same EPROM in alternating order (i.e., LULULU...).

The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different
EPROMs.

4. System Oscillator (OSC1 and OSC2)

Ceramic oscillator

f =

MHz

Crystal oscillator

f =

MHz

External clock

f =

MHz

5. Stop Mode

Used

Not used

6. Package

FP-100A

FP-100B

TFP-100B

HD404629R Series

155

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404629R

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404629R