Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.

2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any

third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and

algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corporation
or an authorized Renesas Technology Corporation product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various
means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams,

charts, programs, and algorithms, please be sure to evaluate all information as a total system before
making a final decision on the applicability of the information and products. Renesas Technology
Corporation assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.

5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device

or system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in

whole or in part these materials.

7. If these products or technologies are subject to the Japanese export control restrictions, they must be

exported under a license from the Japanese government and cannot be imported into a country other
than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.

8. Please contact Renesas Technology Corporation for further details on these materials or the products

contained therein.

HD404818 Series

4-Bit Single-Chip Microcomputer

Preliminary

Rev. 2.0

Sept. 1998

Description

T he H D4 04 81 8 Se ri es of 4-bit single-chip HMCS400 series microcomputers provide high program
productivity. It incorporates a large size memory, LCD controller/driver, voltage comparator, and 32-kHz
watch oscillator circuit.

The HD404818 Series has both standard voltage versions and low voltage versions available. The standard
voltage versions operate at 4.0 V to 6.0 V (mask ROM version) and 4.0 V to 5.5 V (PROM version), while
the low voltage versions operate at 2.7 V to 6.0 V (mask ROM) and 3.0 V to 5.5 V (PROM). Low voltage
versions include an L in their product name.

Standard voltage versions: HD404812, HD404814, HD404816, HD404818, HD4074818

Low voltage versions: HD40L4812, HD40L4814, HD40L4816, HD40L4818, HD407L4818

The HD4074818 and HD407L4818, containing PROMs, are ZTAT

microcomputers which can

dramatically shorten system development time and smoothly proceed from debugging to mass production.

ZTAT

: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

2048-word

10-bit ROM (HD404812, HD40L4812)

4096-word

10-bit ROM (HD404814, HD40L4814)

6144-word

10-bit ROM (HD404816, HD40L4816)

8192-word

10-bit ROM (HD404818, HD40L4818, HD4074818, HD407L4818)

1184-digit

4-bit RAM

30 I/O pins, including 10 high-current output pins, all CMOS and programmable as I/O pull-up MOS

LCD controller/driver (32 segments

4 commons)

Three timer/counters

Clock-synchronous 8-bit serial interface

Six interrupt sources

Two by external sources

Four by internal sources

HD404818 Series

Ordering Information

Type

Supply
Voltage

Product
Name

Model Name

ROM (Word)

Clock
Frequency

Package

Mask ROM

Standard
(4.0 to 6.0 V)

HD404812

HD404812FS

2,048

FP-80B

HD404812H

FP-80A

HD404812TF

TFP-80

HD404814

HD404814FS

4,096

FP-80B

HD404814H

FP-80A

HD404814TF

TFP-80

HD404816

HD404816FS

6,144

FP-80B

HD404816H

FP-80A

HD404816TF

TFP-80

HD404818

HD404818FS

8,192

FP-80B

HD404818H

FP-80A

HD404818TF

TFP-80

Low-voltage
operation

HD40L4812

HD40L4812FS

2,048

0.8

FP-80B

(2.7 to 6.0 V)

HD40L4812H

FP-80A

HD40L4812TF

TFP-80

HD40L4814

HD40L4814FS

4,096

FP-80B

HD40L4814H

FP-80A

HD40L4814TF

TFP-80

HD40L4816

HD40L4816FS

6,144

FP-80B

HD40L4816H

FP-80A

HD40L4816TF

TFP-80

HD40L4818

HD40L4818FS

8,192

FP-80B

HD40L4818H

FP-80A

HD40L4818TF

TFP-80

ZTAT

Standard
(4.0 to 5.5 V)

HD4074818

HD4074818FS

8,192

FP-80B

HD4074818H

FP-80A

HD4074818TF

TFP-80

Low-voltage
operation

HD407L4818

HD407L4818FS

0.8

FP-80B

(3.0 to 5.5 V)

HD407L4818H

FP-80A

HD407L4818TF

TFP-80

HD404818 Series

Pin Arrangement

RESET

OSC

COM4

NUMG

NUMO

COM3

COM2

COM1

SEG2

SEG3

SEG4

SEG5

TIMO/R3

INT

/R3

INT

/R3

SEG1

SEG6

SEG7

SEG8

1
2
3
4
5
6
7
8
9
10
11
12

64
63
62

61
60
59
58
57
56
55
54
53

(top view)

SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16

SEG15
SEG14
SEG13

SEG12
SEG11
SEG10
SEG9

D
D
D

VC /D

COMP0/D
COMP1/D

TEST

SCK

/R0

GND

SI/R0

SO/R0

R1
R1

ref

D
D

(top view)

RESET

OSC

COM4

COM3

NUMG

COM2

COM1

SEG32

SEG31

OSC

NUMO

SEG2

SEG3

SEG4

SEG5

TIMO/R3

INT

/R3

INT

/R3

SEG1

SEG6

SEG7

SEG8

SEG9

SEG10

D
D
D
D
D

VC /D

ref

COMP0/D
COMP1/D

TEST

X1
X2

GND

SCK

/R0

SI/R0

SO/R0

SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11

FP-80B

TFP-80
FP-80A

HD404818 Series

Pin Description

Pin Number

FP-80B

FP-80A, TFP-80

Pin Name

I/O

FP-80B

FP-80A, TFP-80

Pin Name

I/O

I/O

INT

I/O

INT

I/O

SEG1

I/O

SEG2

I/O

SEG3

I/O

SEG4

I/O

SEG5

I/O

SEG6

SEG7

/VC

ref

SEG8

/COMP

SEG9

/COMP

SEG10

TEST

SEG11

SEG12

SEG13

GND

SEG14

SCK

I/O

SEG15

/SI

I/O

SEG16

/SO

I/O

SEG17

I/O

SEG18

I/O

SEG19

I/O

SEG20

I/O

SEG21

I/O

SEG22

I/O

SEG23

I/O

SEG24

I/O

SEG25

I/O

SEG26

I/O

SEG27

/TIMO

I/O

SEG28

HD404818 Series

Pin Functions

Power Supply

: Apply the V

power supply voltage to this pin.

GND: Connect to ground.

TEST: For test purposes only. Connect it to V

RESET: MCU reset pin. Refer to the Reset section for details.

NUMG: Non-user pin. Connect it to GND.

NUMO: Non-user pin. Do not connect it to any lines.

Oscillators

OSC

, OSC

: Internal oscillator input pins. They both can be connected to a crystal, ceramic resonator, or

external oscillator circuit. Refer to the Internal Oscillator Circuit section for details.

X1, X2: Watch oscillator 32-kHz crystal pins.

Ports

(D Port): Fourteen 1-bit I/O ports. D

to D

are I/O ports and D

to D

are input ports. D

are

high current output ports (15 mA max.). D

are also available as voltage comparators. Refer to the

Input/Output section for details.

R0R3 (R Ports): 4-bit I/O ports. R0

, R0

, R3

, and R3

are multiplexed with

SCK, SI, SO,

TIMO,

INT

, and

INT

, respectively.

Interrupts

INT

: External interrupt pins.

INT

can be used as an external event input pin for timer B.

INT

and

INT

are multiplexed with R3

and R3

, respectively. For details, see the Interrupts section.

Serial Interface

SCK, SI, SO: The transmit clock I/O pin (SCK), serial data input pin (SI), and serial data output pin (SO)
are used for serial interface.

SCK, SI, and SO are multiplexed with R0

, R0

, and R0

, respectively. For

details, see the Serial Interface section.

Timer

TIMO: Variable duty-cycle pulse waveform output pin. See the Timer C section for details.

HD404818 Series

LCD Driver/Controller

, V

: Power supply pins for the LCD driver. Since the LCD driving resistors are provided internally,

no lines should be connected to these pins. The voltage on each pin is V

GND. See the

Liquid Crystal Display section for details.

COM1 to COM4: Common signal output pins for the LCD display. See the Liquid Crystal Display section
for details.

SEG1 to SEG32: Segment signals output pins for the LCD display. See the Liquid Crystal Display section
for details.

Voltage Comparator

COMP

, COMP

, VC

ref

: Analog input pins for the voltage comparator. VC

ref

is used as a reference voltage

pin to input the threshold voltage of the analog input pin.

HD404818 Series

Block Diagram

Internal address bus

System control circuit

RAM

(1,184 4 bits)

W (2 bits)

X (4 bits)

SPX (4 bits)

Y (4 bits)

SPY (4 bits)

(1 bit)

A (4 bits)

B (4 bits)

SP (10 bits)

Instruction

decoder

PC (14 bits)

ROM

(2,048

10 bits)

(4,096

10 bits)

(6,144

10 bits)

(8,192

10 bits)

D port

ALU

CPU

INT

Timer B

Timer C

TIMO

R0 port

R1 port

R2 port

R3 port

RESET

TEST

OSC

GND

Timer A

External
interrupt

control

circuit

Internal data bus

High-
current
pins

LCD

driver

circuit

COM1
COM2
COM3
COM4

SEG1
SEG2
SEG3

SEG31
SEG32

ref

Compa-

rator

Serial

interface

SCK

: Data bus

: Signal lines

COMP

HD404818 Series

Memory Map

ROM Memory Map

The ROM is described in the following paragraphs with the ROM memory map in figure 1.

4095

4096

8191

8192

16383

$000F

$0FFF

$1000

$1FFF

$2000

$3FFF

$0010

$003F

$0040

Vector address

Zero-page subroutine
(64 words)

Pattern
(4096 words)

Program

Not used

2
3

4
5

6
7
8
9

10
11
12

13
14
15

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007

$0008
$0009

$000A
$000B

$000C
$000D

$000E
$000F

JMPL instruction

(jump to reset routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B routine)

JMPL instruction

(jump to timer C routine)

JMPL instruction

(jump to serial routine)

JMPL instruction

(jump to

INT

routine)

HD404812, HD40L4812: 2048 words
HD404814, HD40L4814: 4096 words
HD404816, HD40L4816: 6144 words
HD404818, HD40L4818,
HD4074818, HD407L4818: 8192 words

Note:

Figure 1 ROM Memory Map

Vector Address Area ($0000 to $000F): Locations $0000 through $000F are reserved for JMPL
instructions to branch to the starting address of the initialization program and of the interrupt programs.
After reset or an interrupt routine, the program is executed from the vector address.

Zero-Page Subroutine Area ($0000 to $003F): Locations $0000 through $003F are reserved for
subroutines. The program sequence branches to subroutines by the CAL instruction.

Pattern Area ($0000 to $0FFF): Locations $0000 through $0FFF are reserved for ROM data. The P
instruction allows the MCU to reference ROM data as a pattern.

Program Area ($0000 to $07FF: HD404812, HD40L4812; $0000 to $0FFF: HD404814, HD40L4814;
$0000 to $17FF: HD404816, HD40L4816; $0000 to $1FFF: HD404818, HD40L4818, HD4074818,
HD407L4818): Used for program coding.

HD404818 Series

RAM Memory Map

The MCU also contains a 1,184-digit

4-bit RAM as the data and stack area. In addition to these areas,

interrupt control bits and special function registers are mapped on the RAM memory space. The RAM
memory map (figure 2) is described in the following paragraphs.

Interrupt Control Bits Area ($000 to $003): The interrupt control bits area (figure 3) is used for interrupt
control. It is accessible only by RAM bit manipulation instructions. However, the interrupt request flag
cannot be set by software. The RSP bit is used only to reset the stack pointer.

Special Function Registers Area ($004 to $01F, $024 to $03F): The special function registers are the
mode or data registers for the serial interface, timer/counters, LCD, and the data control registers for the
I/O ports. These registers are classified into three types: write-only, read-only, and read/write as shown in
figure 2.

The SEM/REM and SEMD/REMD instructions are available for the LCD control register (LCR).

Other registers cannot be accessed by RAM bit manipulation instructions.

Register Flag Area ($020 to $023): Consist of the LSON, WDON, TGSP, and DTON flags which are bit
registers accessible by the RAM bit manip ula tion instruction.

The WDON flag can only be set, and only by the SEM/SEMD instruction.

The DTON flag can be set, reset, and tested by the SEM/SEMD, REM/REMD, and TMD instructions. Note
that the DTON flag is active only in subactive mode, and is normally reset in active mode.

LCD Data Area ($050 to $06F): Locations $050 to $06F store the LCD data which is automatically
transmitted to the segment driver as display data. The LCD is illuminated with 1s and faded with 0s. This
area can be used as a data area.

Data Area ($040 to $2CF, $100 to $2CF; Bank 0/1): The 16 digits of $040 through $04F are called
memory registers (MR) and are accessible by the LAMR and XMRA instructions (figure 4). 464 digits of
$100 through $2CF are selected as bank 0 or 1 depending on the value of the V register.

Stack Area ($3C0 to $3FF): Locations $3C0 through $3FF are reserved for LIFO stacks to save the
contents of the program counter (PC), status flag (ST), and carry flag (CA) when subroutine calls (CAL or
CALL instruction) and interrupts are processed. This area can be used as a 16-level nesting stack in which
one level requires 4 digits.

Figure 4 shows the save condition. The program counter is restored by the RTN and RTNI instructions. The
status and carry flags are restored only by the RTNI instruction. This area, when not used as a stack, is
available as a data area.

HD404818 Series

$000

112

959

960

1023

$03F
$040
$050

$070

$3FF

12
13

50
51

$001

$002

$003

$004

$005

$006

$007

$008

$009

$00A

$00B

$00C

$00D

$00E

$00F

$010

$011

$012

$013

$014

$020

$023

$030

$031

$032

$033

$03B

$03C

$03D

$03F

$00A

$00B

$00E

$00F

R/W

$100

$2CF

$3BF

$3C0

$2CF

RAM-mapped registers

Memory registers (MR)

LCD display area (32 digits)

Data (144 digits)

Data (464 digits 2)

V = 0 (bank 0)
V = 1 (bank 1)

Not used

Stack (64 digits)

Interrupt control bits area

Port mode register A (PMRA)
Serial mode register (SMR)

Serial data register lower (SRL)

Serial data register upper (SRU)

Timer mode register A (TMA)

Timer mode register B (TMB)

Timer B (TCBL/TLRL)
(TCBU/TLRU)

Miscellaneous register (MIS)

Timer mode register C (TMC)

Timer C (TCCL/TCRL)
(TCCU/TCRU)

Not used

Port mode register B (PMRB)

LCD control register (LCR)

LCD mode register (LMR)

Not used

Port R0 DCR (DCR0)

Port R1 DCR (DCR1)

Port R2 DCR (DCR2)

Port R3 DCR (DCR3)

Not used

Port D D DCR (DCRB)

Port D D DCR (DCRC)

Port D D DCR (DCRD)

Not used

V register (V-REG)

Data (464 digits)

V = 1 (bank 1)

Data (464 digits)

V = 0 (bank 0)

Note: Do not use any area labelled "Not used".

Timer counter B lower

(TCBL)

Timer counter B upper

(TCBU)

Timer counter C lower

(TCCL)

Timer counter C upper

(TCCU)

Timer load register B lower

(TLRL)

Timer load register B upper

(TLRU)

Timer load register C lower

(TCRL)

Timer load register C upper

(TCRU)

R:
W:
R/W:

$100

Read only
Write only
Read/write

The data area has two banks:
bank 0 (V = 0) and bank 1 (V = 1)

Figure 2 RAM Memory Map (1,184-digit

4-bit)

HD404818 Series

Bit 3

Bit 2

Bit 1

Bit 0

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt enable flag)

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

Not used

IMS

(IM of serial)

IFS

(IF of serial)

$000

$001

$002

$003

DTON

Direct transfer on flag

Not used

WDON

(Watchdog on flag)

LSON

(Low speed on flag)

Not used

$020

$021

$023

IF:
IM:
IE:
SP:
Note: Bits in the interrupt control bits area and register flag area are set by the SEM or SEMD

instruction, reset by the REM or REMD instruction, and tested by the TM or TMD instruction.
Other instructions have no effect.
However, note the following usage limitations of RAM bit manipulation instructions.

Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer

RSP

WDON

DTON

SEM/SEMD

Not executed

Allowed

Not executed in active mode

Used in subactive mode

REM/REMD

Allowed

Not executed

Allowed

TM/TMD

Allowed

Inhibited

Allowed

Note:

WDON is reset only by MCU reset.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in
ST becomes invalid.

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

HD404818 Series

PC to PC :
ST:
CA:

Memory registers

Stack area

$040

960

$3C0

$041

$042

$043

$044

$045

$046

$047

$048

$049

$04A

$04B

$04C

$04D

$04E

$04F

MR (0)

MR (1)

MR (2)

MR (3)

MR (4)

MR (5)

MR (6)

MR (7)

MR (8)

MR (9)

MR (10)

MR (11)

MR (12)

MR (13)

MR (14)

MR (15)

Level 16

Level 15

Level 14

Level 13

Level 12

Level 11

Level 10

Level 9

Level 8

Level 7

Level 6

Level 5

Level 4

Level 3

Level 2

Level 1

1023

$3FF

Bit 3

Bit 2

Bit 1

Bit 0

$3FC

$3FD

$3FE

$3FF

1022

1023

1020

1021

Program counter
Status flag
Carry flag

Figure 4 Configuration of Memory Registers, Stack Area, and Stack Position

HD404818 Series

Functional Description

Registers and Flags

The MCU provides ten registers and two flags for CPU operations. They are illustrated in figure 5 and
described in the following paragraphs.

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter
Initial value: 0,
no R/W

Stack pointer
Initial value: $3FF, no R/W

(V)

Initial value: Undefined, R/W

V register

Initial value: 0, R/W

Initial value: Undefined, R/W

Initial value: 1, no R/W

Figure 5 Registers and Flags

Accumulator (A), B Register (B): The accumulator and B register are 4-bit registers which hold the
results of the arithmetic logic unit (ALU), and exchange data between memory, I/O, and other registers.

HD404818 Series

V Register (V): The V register, available for RAM address expansion, selects the bank of locations $100
$2CF on the RAM address (464 digits) depending on its value. Therefore, when accessing locations $100
$2CF on the RAM address, specify the value of the V register (V = $0: bank 0; V = $1: bank 1). Locations
$000$0FF and $300$3FF can be accessed independently of the V register. The V register is located at
$03F of the RAM address area.

W Register (W), X Register (X), Y Register (Y): The 2-bit W register and 4-bit X and Y registers address
RAM indirectly. The Y register is also available for addressing port D.

SPX Register (SPX), SPY Register (SPY): The 4-bit SPX and SPY registers are available for assisting the
X and Y registers, respectively.

Carry Flag (CA): The carry flag holds the ALU overflow generated by an arithmetic operation. It is also
affected by the SEC, REC, ROTL, and ROTR instructions. During an interrupt, the carry flag is pushed
onto the stack and restored back from the stack by the RTNI instruction. (It is unaffected by the RTN
instruction.)

Status Flag (ST): The status flag holds the ALU overflow, ALU non-zero, and the results of a bit test
instruction for arithmetic or compare instructions. The status flag is a branch condition of the BR, BRL,
CAL, or CALL instruction. The value of the status flag remains unchanged until an instruction which
affects the next status is executed. The status flag becomes 1 after the BR, BRL, CAL, or CALL instruction
is either executed or skipped. During an interrupt, the status flag is pushed onto the stack and restored back
from the stack by the RTNI instruction, not by the RTN instruction.

Program Counter (PC): The program counter is a 14-bit binary counter for holding the ROM address.

Stack Pointer (SP): The stack pointer is a 10-bit register to indicate the next stacking area up to 16 levels.
The stack pointer is initialized to RAM address $3FF at MCU reset. It is decremented by 4 as data is
pushed onto the stack, and incremented by 4 as data is restored back from the stack. The stack pointer is
initialized to $3FF either by MCU reset or by the RSP bit reset from the REM/REMD instruction.

HD404818 Series

Reset

Setting the RESET pin high resets the MCU. At power-on or when cancelling the stop mode for the
oscillator, apply the reset input for at least t

for the oscillator to stabilize. In all other cases, at least two

instruction cycles of reset input are required for the MCU reset.

Table 1 shows the components initialized by MCU reset, and each of its status.

Table 1 Initial Values after MCU Reset

Items

Initial Value

Contents

Program counter (PC)

$0000

Execute program from the top of the ROM
address

Status flag (ST)

Enable branching with conditional branch
instructions

Stack pointer (SP)

$3FF

Stack level is 0

V register (bank register) (V)

Bank 0 (memory)

Interrupt
flags/mask

Interrupt enable flag (IE)

Inhibit all interrupts

Interrupt request flag (IF)

No interrupt request

Interrupt mask (IM)

Masks interrupt request

I/O

Port data register (PDR)

All bits are 1

Enable to transmit high

Data control register (DCR)

All bits are 0

Output buffer is off (high impedance)

Port mode register A (PMRA)

0000

See Port Mode Register A section

Port mode register B (PMRB)

0000

See Port Mode Register B section

Timer/counters,
serial interface

Timer mode register A (TMA)

0000

See Timer Mode Register A section

Timer mode register B (TMB)

0000

See Timer Mode Register B section

Timer mode register C (TMC)

0000

See Timer Mode Register C section

Serial mode register (SMR)

0000

See Serial Mode Register section

Prescaler S

$000

Prescaler W

$00

Timer counter A (TCA)

$00

Timer counter B (TCB)

$00

Timer counter C (TCC)

$00

Timer load register B (TLR)

$00

Timer load register C (TCR)

$00

Octal counter

000

HD404818 Series

Table 1 Initial Values after MCU Reset (cont)

Items

Initial Value

Contents

LCD

LCD control register (LCR)

000

Refer to description of LCD Control
Register

LCD mode register (LMR)

0000

Refer to description of LCD Duty/Clock
Control

Bit register

Low speed on flag (LSON)

Refer to description of Low-Power
Dissipation Mode

Watchdog timer on flag
(WDON)

Refer to description of Timer C

Direct transfer on flag (DTON) 0

Refer to description of Low-Power
Dissipation Mode

Miscellaneous
register

(MIS)

000

Item

After MCU Reset to Recover from
Stop Mode

After MCU Reset to Recover from
Other Modes

Carry flag (CA)

The contents of the items before
MCU reset are not retained. It is
necessary to initialize them by
software.

The contents of the items before MCU
reset are not retained. It is necessary to
initialize them by software.

Accumulator (A)

B register (B)

W register (W)

X/SPX registers (X/SPX)

Y/SPY registers (Y/SPY)

Serial data register (SR)

RAM

The contents of RAM before MCU
reset (just before STOP instruction)
are retained.

HD404818 Series

Interrupts

Six interrupt sources are available on the MCU: external requests (

INT

), timer/counters (timers A,

B, and C), and the serial interface. For each source, an interrupt request flag (IF), interrupt mask (IM), and
interrupt vector addresses are provided to control and maintain the interrupt request. The interrupt enable
flag (IE) is also used to control interrupt operations.

Interrupt Control Bits and Interrupt Servicing: The interrupt control bits are mapped on $000 through
$003 by the RAM space. They are accessible by RAM bit manipulations instructions, although the interrupt
request flag (IF) cannot be set by software. The interrupt enable flag (IE) and IF are cleared to 0, and the
interrupt mask (IM) is set to 1 after MCU reset.

Figure 6 is a block diagram of the interrupt control circuit. Table 2 shows the interrupt priority and vector
addresses, and table 3 shows the interrupt conditions corresponding to each interrupt source.

The interrupt request is generated when IF is set to 1 and IM is 0. If IE is 1 at this time, the interrupt will be
activated and vector addresses will be generated from the priority PLA corresponding to the interrupt
sources.

HD404818 Series

Table 3 Interrupt Conditions

Interrupt Source

Interrupt Control Bit

INT

Timer A

Timer B

Timer C

Serial

IF0

IM0

IF1

IM1

IFTA

IMTA

IFTB

IMTB

IFTC

IMTC

IFS

IMS

Note:

Don't care.

Figure 7 shows the interrupt processing sequence, and figure 8 shows the interrupt processing flowchart. If
an interrupt is requested, the instruction being executed finishes in the first cycle. The IE is reset in the
second cycle. In the second and third cycles, the carry flag, status flag, and program counter are pushed
onto the stack. In the third cycle, the instruction is executed after jumping to the vector address.

In each vector address, program the JMPL instruction to branch to the starting address of the interrupt
program. The IF, which caused the interrupt, must be reset by software in the interrupt program.

Instruction
cycles

Instruction

execution

Stacking;

reset of IE

Interrupt

acceptance

JMPL instruction execution

on the vector address

Instruction

execution at

starting address

of the interrupt

routine

Stacking;

vector address

generated

Figure 7 Interrupt Processing Sequence

HD404818 Series

Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests
(table 4). It is reset by an interrupt and set by the RTNI instruction.

Table 4 Interrupt Enable Flag

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

): The external interrupt request inputs (

INT

) can be selected by

port mode register A (PMRA: $004).

The external interrupt request flags (IF0, IF1) are set at the falling edge of

I NT

and

I NT

inputs,

respectively (table 5).

The

INT

input can be used as a clock signal input to timer B, in which timer B counts up at each falling

edge of the

INT

input. When using

INT

as the timer B external event input, the external interrupt mask

(IM1) has to be set so that the interrupt request by

INT

will not be accepted (table 6).

More than two instruction cycle times (2t

cyc

/2t

subcyc

) are needed to detect the edge of

INT

External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request
flags (IF0, IF1) are set at the falling edge of the

INT

and

INT

inputs, respectively (table 5).

Table 5 External Interrupt Request Flags

IF0, IF1

Interrupt Request

Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt masks mask the
external interrupt requests (table 6).

Table 6 External Interrupt Masks

IM0, IM1

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the
overflow output of timer A (table 7).

HD404818 Series

Table 7 Timer A Interrupt Request Flag

IFTA

Interrupt Request

Yes

Timer A Interrupt Mask (IMTA: $001, Bit 3): The timer A interrupt mask prevents an interrupt request
from being generated by the timer A interrupt request flag (table 8).

Table 8 Timer A Interrupt Mask

IMTA

Interrupt Request

Enabled

Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): The timer B interrupt request flag is set by the
overflow output of timer B (table 9).

Table 9 Timer B Interrupt Request Flag

IFTB

Interrupt Request

Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): The timer B interrupt mask prevents an interrupt request
from being generated by the timer B interrupt request flag (table 10).

Table 10 Timer B Interrupt Mask

IMTB

Interrupt Request

Enabled

Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): The timer C interrupt request flag is set by the
overflow output of timer C (table 11).

Table 11 Timer C Interrupt Request Flag

IFTC

Interrupt Request

Yes

HD404818 Series

Timer C Interrupt Mask (IMTC: $002, Bit 3): The timer C interrupt mask prevents the interrupt from
being generated by the timer C interrupt request flag (table 12).

Table 12 Timer C Interrupt Mask

IMTC

Interrupt Request

Enabled

Disabled (masked)

Serial Interrupt Request Flag (IFS: $003, Bit 0): The serial interrupt request flag is set when the octal
counter counts eight transmit clock signals, or when data transfer is discontinued by resetting the octal
counter (table 13).

Table 13 Serial Interrupt Request Flag

IFS

Interrupt Request

Yes

Serial Interrupt Mask (IMS: $003, Bit 1): The serial interrupt mask masks the interrupt request (table
14).

Table 14 Serial Interrupt Mask

IMS

Interrupt Request

Enabled

Disabled (masked)

HD404818 Series

Operating Modes

The MCU has five operating modes that are specified by how the clock is used. The functions available in
each mode are listed in table 15, and operations are shown in table 16. Transitions between operating
modes are shown in figure 9.

Table 16 provides additional information for table 26.

Table 15 Functions Available in Each Operating Mode

Mode Name

Active

Standby

Stop

Watch

Subactive

Activation method

RESET
cancellation,
interrupt
request

SBY
instruction

TMA3 = 0,
STOP
instruction

TMA3 = 1,
STOP
instruction

INT

or timer A

interrupt
request from
watch mode

Status

System oscillator

Stopped

Subsystem oscillator OP

Instruction execution
(

CPU

)

Stopped

Peripheral function,
interrupt (

PER

)

Stopped

Clock function,
interrupt (

CLK

)

Stopped

RAM

Retained

Registers/flags

Retained

Reset

Retained

I/O

Retained

High
impedance

Retained

Cancellation method

RESET input,
STOP/SBY
instruction

RESET input,
interrupt
request

RESET input

RESET input,

INT

or timer A

interrupt
request

RESET input,
STOP/SBY
instruction

Notes: OP indicates operating.

1. To reduce current dissipation, stop all oscillation in external circuits.

2. Refer to the Interrupt Frame section for details.

3. Refer to interrupt frame.

4. Subactive mode is an optional function to be specified on the function option list.

5. In the watch and subactive modes, the MCU requires a 32.768-kHz crystal oscillator.

HD404818 Series

Table 16 Operations in Low-Power Dissipation Modes

Function

Stop Mode

Watch Mode

Standby Mode

Subactive Mode

CPU

Reset

Retained

RAM

Retained

Timer A

Reset

Timer B

Reset

Stopped

Timer C

Reset

Stopped

Serial interface

Reset

Stopped

LCD

Reset

I/O

Reset

Retained

Notes: OP indicates operating.

1. Output pins are at high impedance.

2. Subactive mode is an optional function to be specified on the function option list.

3. Transmission/reception is activated if a clock is input in external clock mode. (However,

interrupts are stopped.)

Table 17 I/O Status in Low-Power Dissipation Modes

Output

Input

Standby Mode, Watch Mode

Stop Mode

Active Mode, Subactive Mode

Retained

High impedance

Input enabled

R0R3

Retained

High impedance

Input enabled

System Clock (

CPU

)

Operating

Stopped

Non-time-base peripheral function clock

(

PER

)

Operating

Active mode

Standby mode

Subactive mode

Stopped

Watch mode (TMA3 = 1)

Stop mode (TMA3 = 0)

HD404818 Series

Reset

f :
f :
:
:
:

CPU

CLK

PER

OSC

Operating
Operating
Stopped
f
f

cyc

f :
f :
:
:
:

CPU

CLK

PER

OSC

Operating
Operating
Stopped
f
f

SUB

cyc

f :
f :
:
:
:

CPU

CLK

PER

OSC

Operating
Operating
f
f
f

cyc

f :
f :
:
:
:

CPU

CLK

PER

OSC

Operating
Operating
f
f
f

cyc

SUB

cyc

f :
f :
:
:
:

CPU

CLK

PER

OSC

Stopped
Operating
f
f
f

SUB

f :
f :
:
:
:

CPU

CLK

PER

OSC

Stopped
Operating
Stopped
Stopped
Stopped

f :
f :
:
:
:

CPU

CLK

PER

OSC

Stopped
Operating
Stopped
f
Stopped

SUB

f :
f :
:
:
:

CPU

CLK

PER

OSC

Stopped
Operating
Stopped
f
Stopped

SUB

Standby mode

Stop mode

(TMA3 = 0)

Watch mode

Subactive mode

(TMA3 = 1)

(TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

(TMA3 = 0)

SBY (standby)

Interrupt

Timers A, B, C
Serial,

INT

0 1

SBY (standby)

Interrupt

STOP

INT

Timer A

INT

Timer A

STOP

STOP/SBY

(LSON = 1)

1. Time-base interrupt
2. STOP/SBY (DTON = 1, LSON = 0)
3. STOP/SBY (DTON = 0, LSON = 0)
4. DTON is not affected

f :
f :

f :
f :
:
:
:

LSON:
DTON:

cyc

SUB

OSC

Main oscillation frequency
Suboscillation frequency
for time-base
f /4
f /8
System clock
Clock for time-base
Clock for other
peripheral functions
Low speed on flag
Direct transfer on flag

OSC

CPU

CLK

PER

Active mode

Timers A, B, C
Serial,

INT

0 1

ø
ø
ø

Notes:

ø
ø
ø

Figure 9 MCU Status Transitions

Active Mode: The MCU operates according to the clock generated by the system oscillators OSC

and

OSC

Standby Mode: The MCU enters standby mode when the SBY instruction is executed from active mode.
In this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all
instruction execution-related clocks stop. The stopping of these clocks stops the CPU, retaining all RAM
and register contents and maintaining the current I/O pin status.

Standby mode is terminated by a RESET input oran interrupt request. If it is terminated by a RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and resumes, executing

HD404818 Series

the next instruction after the SBY instruction. If the interrupt enable flag is 1, that interrupt is then
processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A
flowchart of operation in standby mode is shown in figure 10.

Standby

Oscillator: Active
Peripheral clocks:
Active
All other clocks:
Stop

RESET

= 1 ?

Yes

IF0 =

1 ?

Yes

IM0 =

0 ?

IF1 =

1 ?

Yes

IM1 =

0 ?

IFTA =

1 ?

Yes

IMTA =

0 ?

IFTB =

1 ?

Yes

IMTB =

0 ?

IFTC =

1 ?

Yes

IMTC =

0 ?

IFS =

1 ?

Yes

IMS =

0 ?

Yes

(SBY only)

Watch

Oscillator: Stop
Suboscillator: Active
Peripheral clocks: Stop
All other clocks: Stop

Restart

processor clocks

Reset MCU

Execute

next instruction

Accept interrupt

Execute

next instruction

(active mode)

Restart

processor clocks

Yes

IF = 1,

IM = 0, and

IE = 1?

(SBY only)

Figure 10 MCU Operating Flowchart of Watch and Standby Modes

HD404818 Series

Stop Mode: The MCU enters stop mode if the STOP instruction is executed in active mode when TMA3 =
0. In this mode, the system oscillator stops, which stops all MCU functions as well.

Stop mode is terminated by a RESET input as shown in figure 11. RESET must be high for at least one t

to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is
cancelled, all RAM contents are retained, but the accuracy of the contents of the accumulator, B register, W
register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.

Stop mode

Oscillator

Internal clock

RESET

STOP instruction execution

t t (stabilization time)

res

Figure 11 Timing of Stop Mode Cancellation

Watch Mode: The MCU enters watch mode if the STOP instruction is executed in active mode when
TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode.

Watch mode is terminated by a RESET input or a timer-A/

INT

interrupt request. For details on RESET

input, refer to the Stop Mode section. When terminated by a timer-A/

INT

interrupt request, the MCU

enters active mode if LSON is 0, or subactive mode if LSON is 1. After an interrupt request is generated,
the time required to enter active mode is t

for a timer A interrupt, and T

(where T + t

2T + t

)

for an

INT

interrupt, as shown in figure 12.

Operation during mode transition is the same as that at standby mode cancellation (figure 10).

HD404818 Series

Active mode

Watch mode

Active mode

Oscillation
stabilization period

Interrupt strobe

INT

Interrupt request
generation

(During the transition
from watch mode to
active mode only)

T:
t

Interrupt frame length
Oscillation stabilization period

Figure 12 Interrupt Frame

Subactive Mode: The CPU operates with a clock generated by the X1 and X2 oscillation circuits.
Functions that can operate in subactive mode are listed in table 16. When the STOP or SBY instruction is
executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of
LSON and DTON. The DTON flag can only be set in subactive mode; it is automatically reset after a
transition to active mode.

Subactive mode is an optional function that the user must specify on the function option list.

Interrupt Frame: In watch and subactive modes, ø

C L K

is supplied for timer A and the

I NT

circuit.

Prescaler W and timer A operate as time bases to generate interrupt frame timing. Three interrupt frame
cycles (T) can be selected by the settings of the miscellaneous register, as shown in figure 13.

In watch and subactive modes, timer A and

INT

interrupts are generated in synchronism with the interrupt

frame. An interrupt request is generated at an interrupt strobe, except when the MCU enters active mode
from watch mode. The

INT

falling edge is acknowledged regardless of the interrupt frame, but an interrupt

is executed simultaneously with the second interrupt strobe. Timer A generates an overflow and interrupt
request at an interrupt strobe.

HD404818 Series

MIS2

MIS1

MIS0

selection

Refer to
table 20

MIS: $00C

MIS

1 Bit

0 Bit

0.24414 ms

15.625 ms

62.5 ms

Not used

0.12207 ms

0.24414 ms

7.8125 ms

31.25 ms

Oscillation circuit
condition

External clock input

Ceramic or crystal

oscillator

Notes:

1. The value of t applies only when using
a 32.768-kHz oscillator.
2. Only direct transfer.

Figure 13 Miscellaneous Register

Direct Transfer: By controlling the DTON, the MCU can be placed directly from subactive to active
mode. The detailed procedure is as follows:

Set the DTON flag in subactive mode while LSON = 0.

Execute the STOP or SBY instruction.

After the oscillation stabilization time (a fixed value), the MCU will move automatically from subactive
to active mode.

Note that DTON ($020, bit 3) is valid only in subactive mode. When the MCU is in active mode, this flag
is always at reset.

The transition time (t

) from subactive to active mode is t

T + t

Subactive mode

Interrupt
strobe

Direct transfer
timing

Internal
execution
time (< T)

Oscillation
stabilization
time

Active mode

T:
t :

STOP/SBY
execution

(LSON = 0, DTON = 1)

Interrupt frame period
Oscillation stabilization period

Figure 14 Direct Transfer Timing

MCU Operating Sequence: The MCU operates in the sequence shown in figures 15 to 17. It is reset by an
asynchronous RESET input, regardless of its state.

HD404818 Series

Low-power mode

operation cycle

IF = 1 and

IM = 0 ?

Hardware NOP

execution

PC next

Iocation

MCU operation

cycle

Standby/watch

mode

IF = 1 and

IM = 0 ?

Hardware NOP

execution

PC next

Iocation

Instruction

execution

Stop mode

Yes

For specific IF and IM, see figure 10, MCU Operating Flowchart

Figure 17 MCU Operating Sequence (low-power mode operation)

Notes on Use:

In subactive mode, a timer A interrupt request or an external interrupt request (

INT

) occurs in

synchronism with an interrupt strobe.

If the STOP or SBY instruction is executed at the same time with an interrupt strobe, these interrupt
requests will be cancelled and the corresponding interrupt request flags (IFTA, IF0) will not be set.

In subactive mode, do not use the STOP or SBY instruction at the time of an interrupt strobe.

HD404818 Series

When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of
INT

is shorter than the interrupt frame,

INT

is not be detected. Also, if the low level period after the

falling edge of

INT

is shorter than the interrupt frame,

INT

is not be detected.

Edge detection is shown in figure 18. The level of the

INT

signal is sampled by a sampling clock.

When this sampled value changes to low from high, a falling edge is detected.

In figure 19, the level of the

INT

signal is sampled by an interrupt frame. In (a) the sampled value is

low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled
value is high at point A, and also high at point B. A falling edge is not detected in this case either.

When the MCU is in watch mode or subactive mode, keep the high level and low level period of

INT

longer than the interrupt frame.

High

Low

INT

Sampling

Low

Figure 18 Edge Detection

A: Low

B: Low

INT

Interrupt
frame

A: High

B: High

INT

Interrupt
frame

(a) High level period

(b) Low level period

Figure 19 Sampling Example

HD404818 Series

Internal Oscillator Circuit

Figure 20 shows the block diagram of the internal oscillator circuit. A ceramic oscillator can be connected
to OSC

and OSC

. A 32.768-kHz crystal oscillator can be connected to X1 and X2. External clock

operation is available for the system oscillator.

OSC

Subsystem

oscillator

1/4

divider

circuit

1/8

divider

circuit

Mode

control

circuit

Timing

generator

circuit

OSC

cyc

SUB

Timing

generator

circuit

System clock
(

CPU

)

System clock
(

PER

)

Timer-base
clock (

CLK

)

OSC

System

oscillator

Figure 20 Internal Oscillator Circuit

RESET

OSC

NUMG

COMP

TEST

GND

SCK

/R0

GND

Figure 21 Layout of Crystal and Ceramic Oscillators

HD404818 Series

Table 18 Examples of Oscillator Circuits

Circuit Configuration

Circuit Constants

External clock operation

Oscillator

OSC

Open

OSC

Ceramic oscillator

OSC

Ceramic

GND

HD404812, HD404814, HD404816,
HD404818, HD4074818
Ceramic oscillator: CSA4.00MG
(Murata)
R

20%

30 pF

20%

HD40L4812, HD40L4814,
HD40L4816, HD40L4818,
HD407L4818
Ceramic oscillator: CSB400P
(Murata)
CSB400P22 (Murata)
R

1 M

20%

= 220 pF

CSB800J (Murata)
CSB800J122 (Murata)
R

20%

220 pF

Crystal oscillator

OSC

Crystal

GND

HD404812, HD404814, HD404816,
HD404818, HD4074818
C

: 10 to 22 pF

20%

: 10 to 22 pF

20%

1 M

20%

Crystal: Equivalent to circut shown
at bottom left.
C

: 7 pF max.

: 100

max

HD404818 Series

Table 18 Examples of Oscillator Circuits (cont)

Circuit Configuration

Circuit Constants

Crystal oscillator

Crystal

GND

C R

Crystal: 32.768 kHz: MX38T
(Nippon Denpa Kogyo)
C

20 pF

20%

20 pF

20%

14 k

1.5 pF

Notes: 1.

The circuit parameters above are recommended by the crystal or ceramic oscillator
manufacturer. The circuit parameters are affected by the crystal or ceramic oscillator and floating
capacitance when designing the board. When using the oscillator, consult with the crystal or
ceramic oscillator manufacturer to determine the circuit parameters.

2. Writing among OSC

and OSC

or X1 and X2, and other elements should be as short as

possible, and should not cross other wires. Refer to figure 21.

3. When the 32.768-kHz crystal oscillator is not used, pin X1 must be fixed to V

and pin X2 must

be left open.

HD404818 Series

Table 19 I/O Pin Circuit Types

I/O Pins

Circuit

Pin Name

I/O common pins
(wint pull-up MOS)

Input control signal

Input data

Output data

PDR

DCR

Pull-up control signal

-D

-R0

-R1

-R2

-R3

SCK

Output data

SCK

(internal)

DCR

Pull-up control signal

SCK

Output pins
(with pull-up MOS)

Output data

SO or TIMO

DCR

Pull-up control signal

SO
TIMO

Input pins

PDR

Pull-up control signal

INT

Input control signal

Input data

/VC

ref

Analog input

Input control

Input data

Mode select signal

/COMP

(Multiplexed with
analog inputs)

Note: For RO

/SO, refer to table 20, note 3.

HD404818 Series

D Port: Consists of ten 1-bit I/O ports and four input ports. Pins D

to D

are high-current I/O pins (15 mA

max.). The sum of the current for all D-port pins is up to 100 mA. D port can be set/reset by the SED/RED
and SEDD/REDD instructions, and can be tested by the TD/TDD instruction. Output data is stored in the
port data register. The output buffer for port D can be turned on/off by the D-port data control registers
(DCRB, DCRC, DCRD). The DCR is located in the memory address area. Pins D

to D

are input-only

pins.

Two operation modes are available for pins D

and D

: digital input mode and analog input mode. The

operation modes can be selected by port mode register B (PMRB; bits 1, 0). In the digital input mode, these
pins can be used as input with the same characteristics as other I/O pins. In the analog input mode, users
can read the result of the comparison between the reference voltage as input data. The reference voltage is
input through D

/VC

ref

R Port: Consists of four 4-bit I/O ports and can receive/transmit data by the LAR/LRA and LBR/LRB
instructions. Output data is stored in the port data register (PDR) of each pin.

The output buffers of the R ports can be turned on/off by the R-port data control registers (DCR0DCR3).

The DCR is located in the memory address area.

Pins R0

, R0

, and R0

are multiplexed with

SCK, SI, and SO, respectively.

Pins R3

, R3

, and R3

are multiplexed with TIMO,

INT

, and

INT

, respectively. Refer to figure 23.

Pull-Up MOS Transfer Control: All I/O ports, except for pins D

, contain programmable pull-up

MOS.

Bit 3 of port mode register B (PMRB3) controls the activation of all pull-up MOS simultaneously. Pull-up
MOS is controlled by the port data register (PDR) of each pin. Therefore, each bit of pull-up MOS can be
individually turned on or off. Refer to table 20.

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

Unused I/O Pins: If unused pins are left floating, the LSI may malfunction because of noise. The I/O pins
should be fixed as follows to prevent this: pull-up to V

through internal pull-up MOS, or pull-up to V

through a resistor of approximately 100 k

HD404818 Series

PMRA (port mode register A) ADR: $004

R0 /SO pin mode selection

R0 /SI pin mode selection

R3 /

INT

pin mode selection

R3 /

INT

pin mode selection

Port
select

Bit 3

INT

PMRA

Bit 2

PMRA

INT

Port
select

Bit 1

PMRA

Port
select

Bit 0

PMRA

Port
select

Pull-up MOS

on/off

Bit 3

Off

PMRB

Bit 2

PMRB

TIMO

Port
select

Bit 1

PMRB

COMP

Port
select

Bit 0

PMRB

COMP

Port
select

D /COMP

pin mode selection

PMRB (port mode register B) ADR: $012

D /COMP

pin mode selection

R3 /TIMO pin mode selection
Pull-up MOS on/off selection

Port
select

Bit 3

SCK

SMR

SMR (serial mode register) ADR: $005

R0 /

SCK

pin mode selection

Figure 23 I/O Select Mode Registers

HD404818 Series

Table 20 Input/Output by Program Control

PMRB Bit 3

DCR

PDR

PMOS (A)

NMOS (B)

Pull-up MOS

Notes: -- indicates off status.

1. Combine the values of the above mode registers (PMRB3, DCR, and PDR) to select the

input/output for PMOS (A), NMOS (B), and the pull-up MOS, individually.

The DCR and PDR control each pin. Also, PMRB3 controls the on/off of all pull-up MOSs.

2. The second bit of the miscellaneous register (MIS2) controls R0

/SO. When MIS2 is 1, PMOS

(A) is off.

MIS2

/SO

PMOS (A)

Off

3. Each bit of DCR corresponds to each port as follows:

DCR

Bit 3

Bit 2

Bit 1

Bit 0

DCR0

DCR1

DCR2

DCR3

DCRB

DCRC

DCRD

HD404818 Series

Timers

The MCU provides prescalers S and W (each with a different input clock source), and three timer/ counters
(timers A, B, and C). Figures 25, 26 and 27 show their diagrams.

Prescaler S: The input to prescaler S is the system clock signal. The prescaler is initialized to $000 by
MCU reset, and starts to count up with the system clock signal as soon as the RESET input goes low. The
prescaler keeps counting up except at MCU reset and in the stop and watch modes. The prescaler provides
input clock signals to timers A to C and the transmit clock of the serial interface. They can be selected by
timer mode registers A (TMA), B (TMB), C (TMC), and the serial mode register (SMR), respectively.

Prescaler W: The input to prescaler W is a clock which divides the X1 input clock by 8. The output of
prescaler W is available as an input clock for timer A by controlling timer mode register A (TMA).

Timer A Operation: After timer A is initialized to $00 by MCU reset, it counts up at every clock input
signal. When the next clock signal is applied after timer A has counted up to $FF, timer A is set to $00
again, and an overflow output is generated. This sets the timer A interrupt request flag (IFTA: $001, bit 2)
to 1. Therefore, timer A can function as an interval timer periodically generating overflow output at every
256th clock signal input (figure 25).

To use timer A as a watch time base, set TMA3 to 1. Timer counter A receives prescaler W output, and
timer A generates interrupts with accurate timing (reference clock = 32-kHz crystal oscil lator). When
using timer A as a watch time base, prescaler W and the timer counter can be initialized to $0 by setting
timer mode register A.

The clock input signals to timer A are selected by timer mode register A (TMA: $008).

HD404818 Series

Timer B Operation: Timer mode register B (TMB: $009) selects the auto-reload function, input clock
source, and prescaler divide ratio for timer B. When an external event input is used as an input clock signal
to timer B, select R3

INT

by port mode register A (PMRA: $004) to prevent an external interrupt

request from occurring (figure 26)

Timer B is initialized according to the data written into timer load register B by software. Timer B counts
up at every clock input signal. When the next clock signal is applied to timer B after it is set to $FF, it will
generate an overflow output. In this case, if the auto-reload function is selected, timer B is initialized
according to the value of timer load register B. If it is not selected, timer B goes to $00. The timer B
interrupt request flag (IFTB: $002, bit 0) will be set as this overflow is output.

System
clock

INT

Selector

Prescaler S (PSS)

Clock

Timer latch

(TLBL)

Timer counter B

(TCB)

Timer load

(TLRU)

Timer load

(TLRL)

Timer mode

(TMB)

Timer B interrupt

request flag

(IFTB)

Internal data bus

128

512

2048

÷ ÷ ÷ ÷ ÷ ÷

Free-running
control

Overflow

cyc

SUB

cyc

subcyc

)

Timer latch register BU (TLBU)

Figure 26 Timer B Block Diagram

Timer C Operation: Timer mode register C (TMC: $00D) selects the auto-reload function and the
prescaler divide ratio for timer C.

Timer C is initialized according to the data written into timer load register C by software. Timer C counts
up at every clock input signal. When the next clock signal is applied to timer C after it is set to $FF, it will
generate an overflow output. In this case, if the auto-reload function is selected, timer C is initialized

HD404818 Series

according to the value of timer load register C. If it is not selected, timer C goes to $00. The timer C
interrupt request flag (IFTC: $002, bit 2) will be set as this overflow is output.

Timer C is also available as a watchdog timer for detecting runaway programs. MCU reset occurs when the
watchdog on flag (WDON) is 1 and the counter overflow output is generated by a runaway program. If
timer C stops, the watchdog timer function also stops. In the standby mode, this function is enabled.

Timer C provides a variable duty-cycle pulse output function (PWM). The output waveform differs
depending on the contents of the timer mode register and timer load register C (figure 28). When selecting
the pulse output function, set R3

/TIMO to TIMO by controlling port mode register B.

When timer C stops, this functions also stops.

Watchdog on

flag (WDON)

System
reset signal

Timer C interrupt

request flag

(IFTC)

Timer output

control logic

Timer latch register CU (TLCU)

Timer latch
register CL

(TLCL)

Clock

Timer counter C

(TCC)

Selector

System
clock

Prescaler S (PSS)

Overflow

Internal data bus

Timer load

(TCRU)

Timer load

(TCRL)

Timer mode

(TMC)

Free-running/
reload control

Watchdog timer

control logic

TIMO

128

512

1024

2048

cyc

SUB

cyc

subcyc

)

Figure 27 Timer C Block Diagram

HD404818 Series

Registers for Timers

Timer Mode Register A (TMA: $008): Timer mode register A is a 4-bit write-only register which
controls the timer A operation as table 21 shows. Timer mode register A is initialized to $0 at MCU reset.

Timer Mode Register B (TMB: $009): Timer mode register B (TMB) is a 4-bit write-only register which
selects the auto-reload function, the prescaler divide ratio, and the source of the clock input signal, as
shown in table 22. Timer mode register B is initialized to $0 by MCU reset.

The data of timer B changes at the second instruction cycle of a write instruction. Initialization of timer B
by writing data into timer load register B should be performed after the contents of TMB are changed.

Table 21 Timer Mode Register A

TMA

Bit 3

Bit 2

Bit 1

Bit 0

Source Prescaler, Input Clock Period,
Operating Mode

PSS, 2048 t

cyc

Timer A mode

PSS, 1024 t

cyc

PSS, 512 t

cyc

PSS, 128 t

cyc

PSS, 32 t

cyc

PSS, 8 t

cyc

PSS, 4 t

cyc

PSS, 2 t

cyc

PSW, 32 t

subcyc

Time-base mode

PSW, 16 t

subcyc

PSW, 8 t

subcyc

PSW, 2 t

subcyc

PSW, 1/2 t

subcyc

Do not use

PSW, TCA reset

Notes: 1. t

subcyc

= 244.14

s (when a 32.768-kHz crystal oscillator is used)

2. Timer counter overflow output period (s) = input clock period (s)

256

3. If PSW or TCA reset is selected while the LCD is operating, LCD operation halts (power switch

goes off).

When the LCD is connected for display, the PSW and TCA reset periods must be set in the
program to the minimum.

4. In time base mode, the timer counter overflow output cycle must be greater than half of the

interrupt frame period (T/2 = t

If 1/2 t

subcyc

is selected, t

must be 7.8125 ms ((MIS1, MIS0) = (0, 1), see figure 13).

HD404818 Series

5. The division ratio must not be modified during time base mode operation, otherwise an overflow

cycle error will occur.

Timer Mode Register C (TMC: $00D): Timer mode register C is a 4-bit write-only register which selects
the auto-reload function, input clock source, and prescaler divide ratio, as table 23 shows. Timer mode
register C is initialized to $0 at MCU reset.

The contents of timer mode register C will change in the second instruction cycle after a write instruction to
TMC. Therefore, it is required to initialize timer C after the contents of timer mode register C have been
changed completely.

Timer B (TCBL: $00A, TCBU: $00B, TLRL: $00A, TLRU: $00B): Timer B consists of an 8-bit write-
only timer load register, and an 8-bit read-only timer counter. Each of them has low-order digits (TCBL:
$00A, TLRL: $00A) and high-order digits (TCBU: $00B, TLRU: $00B). (Refer to figure 26.)

Timer counter B can be initialized by writing data into timer load register B. In this case, write the low-
order digits first, and then the high-order digits. The timer counter is initialized when the high-order digit
is written. The timer load register is initialized to $00 by MCU reset.

The counter value of timer B can be obtained by reading timer counter B. In this case, read the high-order
digits first, and then the low-order digits. The count value of the low-order digit is obtained when the high-
order digit is read.

Timer C (TCCL: $00E, TCCU: $00F, TCRL: $00E, TCRU: $00F): Timer C consists of the 8-bit write-
only timer load register and the 8-bit read-only timer counter. These individually consist of low-order digits
(TCCL: $00E, TCRL: $00E) and high-order digits (TCCU: $00F, TCRU: $00F). The operation mode of
timer C is the same as that of timer B.

Table 22 Timer Mode Register B

TMB3

Auto-Reload Function

Yes

TMB2

TMB1

TMB0

Prescaler Divide Ratio, Clock Input Source

2048

512

128

INT

(external event input)

HD404818 Series

Table 23 Timer Mode Register C

TMC3

Auto-Reload Function

Yes

TMC2

TMC1

TMC0

Prescaler Divide Ratio, Clock Input Source

2048

1024

512

128

Notes on Use

When using the timer output as variable duty-cycle pulse (PWM) output, note the following point. From
the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs
from the period and duty settings, as shown in table 24. The PWM output should therefore not be used until
after the overflow interrupt following the update of the timer write register. After the overflow, the PWM
output will have the set period and duty cycle.

HD404818 Series

Serial Interface

The serial interface transmits/receives 8-bit data serially. It consists of the serial data register, the serial
mode register, port mode register A, the octal counter, and the selector (figure 29). Pin R0

SCK and the

transmit clock signal are controlled by the serial mode register. The data of the serial data register can be
written and read by software. The data in the serial data register can be shifted synchronously with the
transmit clock signal.

The STS instruction starts serial interface operations and resets the octal counter to $0. The octal counter
starts to count at the falling edge of the transmit clock signal (

SCK) and increments by one at the rising

edge of the

S C K. When the octal counter is reset to $0 after eight transmit clock signals, or when a

transmit/receive operation is discontinued by resetting the octal counter, the serial interrupt request flag will
be set.

Internal data bus

128

512

2048

Port mode

(PMRA)

SCK

Selector

System

clock

Prescaler S (PSS)

I/O

control

logic

Serial mode

(SMR)

Clock

Serial data

Serial interrupt

request flag

(IFS)

Selector

1/2

Octal

counter (OC)

I/O

control

logic

Transfer
control
signal

cyc

sub

cyc

subcyc

)

Figure 29 Serial Interface Block Diagram

HD404818 Series

Selection and Change of the Operation Mode: Table 25 shows the serial interface operation modes
which are determined by a combination of the value in the port mode register and in the serial mode
register.

Initialize the serial interface by writing to the serial mode register to change the operation mode of the
serial interface.

Table 25 Serial Interface Operation Mode

SMR3

PMRA1

PMRA0

Serial Interface Operating Mode

Clock continuous output mode

Transmit mode

Receive mode

Transmit/receive mode

Operating State of Serial Interface: The serial interface has three operating states: the STS waiting state,
transmit clock wait state, and transfer state (figure 30).

The STS waiting state is the initialization state of the serial interface internal state. The serial interface
enters this state in one of two ways: either by changing the operation mode through a change in the data in
the port mode register, or by writing data into the serial mode register. In this state, the serial interface does
not operate even if the transmit clock is applied. If the STS instruction is executed then, the serial interface
shifts to the transmit clock wait state.

In the transmit clock wait state, the falling edge of the first transmit clock causes the serial interface to shift
to the transfer state, while the octal counter counts up and the serial data register shifts simultaneously. As
an exception, if the clock continuous output mode is selected, the serial interface stays in transmit clock
wait state while the transmit clock outputs continuously. The octal counter becomes 000 again after 8
external transmit clocks or by the execution of the STS instruction, the serial interface then returns to the
transmit clock wait state, and the serial interrupt request flag is set simultaneously. In the transfer state the
octal counter becomes 000 after 8 internal transmit clocks, the serial interface then enters the STS
instruction waiting state, and the serial interrupt request flag is set simultaneously.

When the internal transmit clock is selected, the transmit clock output is triggered by the execution of the
STS instruction, and stops after 8 clocks.

Program the SMR again to initialize the internal state of the serial interface when the PMRA is
programmed in the transfer state or in the transmit clock wait state. Then the serial interface goes into the
STS waiting state.

HD404818 Series

(IFS

Octal counter = 000
transmit clock disable

STS waiting state

Transmit clock

8 external transmit clocks

STS instruction

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter

000)

Write to SMR

STS instruction

SMR write

8 internal transmit clocks

(IFS

Figure 30 Serial Interface Operation States

Example of Transmit Clock Error Detection: The serial interface malfunctions when the transmit clock
is disturbed by external noise. In this case, transmit clock errors can be detected by the procedure shown in
figure 31.

If more than 8 transmit clocks are applied in the transmit clock wait state, the state of the serial interface
shifts in the following sequence: transfer state, transmit clock wait state, and transfer state again. The serial
interrupt request flag should be reset before entering into the STS waiting state by writing data to SMR.
This procedure causes the serial interface request flag to be set again.

HD404818 Series

Registers for Serial Interface

Serial Mode Register (SMR: $005): The 4-bit write-only serial mode register controls the R0

SCK,

prescaler divide ratio, and transmit clock source (table 26, figure 32).

A write signal to the serial mode register controls the internal state of the serial interface.

A write signal to the serial mode register stops the serial data register and octal counter from applying the
transmit clock, and it also resets the octal counter to $0 simultaneously. Therefore, when the serial interface
is in the transfer state, a write signal causes the serial mode register to cease the data transfer and to set the
serial interrupt request flag.

Data in the serial mode register will change in the second instruction cycle after a write instruction to the
serial mode register. Therefore, it is required to execute the STS instruction after the data in the serial mode
register has been changed completely. The serial mode register will be reset to $0 by MCU reset.

Serial Data Register (SRL: $006, SRU: $007): The 8-bit read/write serial data register consists of low-
order digits (SRL: $006) and high-order digits (SRU: $007).

The data in the serial data register will be output from the SO pin LSB first synchronously with the falling
edge of the transmit clock signal. At the same time, external data will be input from the SI pin to the serial
data register synchronously with the rising edge of the transmit clock. Figure 33 shows the I/O timing chart
for the transmit clock signal and the data.

The read/write operation of the serial data register should be performed after the completion of data
transmit/receive. Otherwise, data accuracy cannot be guaranteed.

Table 26 Serial Mode Register

SMR3

SCK

Used as R0

port input/output pin

Used as

SCK

input/output pin

Transmit Clock

SMR2 SMR1 SMR0 R0

SCK

Port Clock Source Prescaler Divide Ratio System Clock Divide Ratio

SCK

/output

Prescaler

2048

4096

SCK

/output

Prescaler

512

1024

SCK

/output

Prescaler

128

256

SCK

/output

Prescaler

SCK

/output

Prescaler

SCK

/output

Prescaler

SCK

/output

System clock

SCK

/input

External clock --

HD404818 Series

LCD Controller/Driver

The MCU contains four common signal pins, the controller, and the driver. The controller and the driver
drive 32 segment signal pins. The controller consists of display data RAM, the LCD control register (LCR),
and the LCD duty-cycle/clock control register (LMR) (figure 34). Four programmable duty cycles and
LCD clocks are available. Since the MCU contains a dual port RAM, display data can be transferred to
segment signal pins automatically without program control. When selecting the 32-kHz oscillation clock as
the LCD clock source, the system allows the LCD to display even in watch mode, in which the system
clock halts.

Power switch

GND

LCD

common

driver

Display on/off

LCD duty-

cycle/clock

control register

Display

control

LCD

segment

driver

LCD
clock

$050

$06F

RAM area

Duty selection
Clock selection

LCD
clock

SEG32

SEG2

SEG1

COM4

COM3

COM2

COM1

System clock dividing
output (CL1CL3)
32-kHz clock dividing
output (CL0)

Display

area

(dual port

RAM)

LMR: $014

LCR: $013

LCD

power

supply

control

circuit

Figure 34 LCD Controller/Driver Configuration

LCD Data Area and Segment Data ($050 to $06F): Figure 35 shows the configuration of the LCD RAM
area. Each bit of this area, corresponding to four types of duty cycles, can be transmitted to the segment
driver as display data by programming the area corresponding to the duty cycle.

HD404818 Series

Bit 3

Bit 2

Bit 1

Bit 0

$050

$051

$052

$053

$054

$055

$056

$057

$058

$059

$05A

$05B

$05C

$05D

$05E

$05F

COM4

COM3

COM2

COM1

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

Bit 3

Bit 2

Bit 1

Bit 0

100

101

102

103

104

105

106

107

108

109

110

111

$060

$061

$062

$063

$064

$065

$066

$067

$068

$069

$06A

$06B

$06C

$06D

$06E

$06F

COM4

COM3

COM2

COM1

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

Figure 35 Configuration of LCD RAM Area (dual port RAM)

LCD Control Register (LCR: $013): The LCD control register is a 3-bit write-only register which
controls the blanking of the LCD, activation of the power switch, and display in watch mode/subactive
mode (table 27, figure 36).

Blank/display

Blank: Segment signal is faded regardless of the LCD RAM data.

Display: LCD RAM data is transmitted as a segment signal.

Power switch on/off

Off: Power switch is off.

On: Power switch is on and V

is V

Watch mode/subactive mode display

Off: In the watch mode/subactive mode, all common/segment pins are fixed to GND, and the power
switch is off.

On: In the watch mode/subactive mode, LCD RAM data is transmitted as a segment signal.

LCD Duty-Cycle/Clock Control Register (LMR: $014): The LCD duty-cycle/clock control register is a
write-only register which specifies four display duty cycles and the reference clock for the LCD (table 28,
figure 36).

HD404818 Series

Table 27 LCD Control Register

LCR
BIT 2

Watch Mode/ Subactive Mode
Display

LCR
BIT 1

Power Switch On/Off

LCR
BIT 0

Blank/ Display

Off

Blank

Display

Note:

With the LCD in watch mode, use the divider output of the 32-kHz oscillator as an LCD clock and set
LCR bit 2 to 1. When the system oscillator divider output is used as an LCD clock, set LCR bit 2 to
0.

Table 28 LCD Duty-Cycle/Clock Control Register

LMR

Bit 3

Bit 2

Bit 1

Bit 0

Duty Cycle Select/Input Clock Select

1/4 duty cycle

1/3 duty cycle

1/2 duty cycle

Static

CL0 (32.768 kHz/64; when 32.768-kHz oscillator is used)

CL1 (f

cyc

/256)

CL2 (f

cyc

/2048)

CL3 (Refer to table 29)

Note: f

cyc

is the system oscillator divider output.

LCR (LCD control register) ADR = $013

Blank/display
Power switch on/off

(not used)

Display on/off in watch mode

Duty cycle selection

Input clock selection

LMR (LCD mode register) ADR = $014

Figure 36 LCD Control Register

HD404818 Series

Table 29 LCD Frame Frequency

LMR

Static

Bit 3

Bit 2

Bit 3

Bit 2

Bit 3

Bit 2

Bit 3

Bit 2

Instruction
cycle time

CL0

CL1

CL2

CL3

512 Hz

390.6 Hz

48.8 Hz

24.4 Hz/64 Hz

512 Hz

3906 Hz

488Hz

244 Hz/64 Hz

LMR

1/2 Duty Cycle

Bit 3

Bit 2

Bit 3

Bit 2

Bit 3

Bit 2

Bit 3

Bit 2

Instruction
cycle time

CL0

CL1

CL2

CL3

256 Hz

195.3 Hz

24.4 Hz

12.2 Hz/32 Hz

256 Hz

1953 Hz

244 Hz

122 Hz/32 Hz

LMR

1/3 Duty Cycle

Bit 3

Bit 2

Bit 3

Bit 2

Bit 3

Bit 2

Bit 3

Bit 2

Instruction
cycle time

CL0

CL1

CL2

CL3

170.6 Hz

130.2 Hz

16.3 Hz

8.1 Hz/21.3 Hz

170.6 Hz

1302 Hz

162.6 Hz

81.3 Hz/21.3 Hz

LMR

1/4 Duty Cycle

Bit 3

Bit 2

Bit 3

Bit 2

Bit 3

Bit 2

Bit 3

Bit 2

Instruction
cycle time

CL0

CL1

CL2

CL3

128 Hz

97.7 Hz

12.2 Hz

6.1 Hz/16 Hz

128 Hz

977 Hz

122 Hz

61 Hz/16 Hz

Note:

Division ratio differs depending on the value of bit 3 of timer mode register A

(TMA3 = 0/TMA3 = 1).

If TMA3 = 0, CL3 = fcyc x duty cycle/4096; if TMA3 = 1, CL3 = 32.768 kHz x duty cycle/512.

HD404818 Series

Large LCD Panel Driving and Driving Voltage (V

LCD

): When using a large LCD panel, lower the

dividing resistance by attaching external resistors in parallel with the internal dividing resistors (figure 37).

Since the liquid crystal display board is of a matrix configuration, the path of the charge/discharge current
through the load capacitors is very complicated. Moreover, since it varies depending on display conditions,
the value of resistance cannot be determined by simply referring to the load capacitance of the liquid crystal
display. The value of resistance must be experimentally determined according to the demand for power
consumption of the equipment in which the liquid crystal display is implemented. Capacitor C (0.1 to 0.3

F) is recommended to be attached. In general, R is 1 k

to 10 k

Figure 37 shows a connection when changing the liquid crystal driving voltage (V

LCD

). In this case, the

power supply switch for the dividing resistors (power switch) must be turned off. (Bit 1 of the LCR register
is 0.)

HD404818 Series

Pin Description in PROM Mode

The HD4074818 and HD407L4818 are ZTAT

microcomputers incorporating a PROM. In the PROM

mode, the MCU does not operate and the HD4074818 and HD407L4818 can program the on-chip PROM.

Pin Number

MCU Mode

PROM Mode

Pin Number

MCU Mode

PROM Mode

FP-
80B

FP-80A
TFP-80 Pin Name

I/O Pin Name

I/O

FP-80B

FP-80A
TFP-80

Pin Name

I/O Pin Name

I/O

I/O O

I/O

I/O A

I/O O

I/O

I/O A

I/O O

I/O

/TIMO

I/O A

I/O O

I/O

INT

I/O

I/O O

I/O

INT

I/O

I/O O

I/O

SEG1

I/O

SEG2

I/O

SEG3

SEG4

/VC

ref

SEG5

/COMP

SEG6

/COMP

SEG7

TEST

SEG8

GND

SEG9

SEG10

GND

SEG11

SCK

I/O A

SEG12

/SI

I/O A

SEG13

/SO

I/O A

SEG14

I/O A

SEG15

I/O A

SEG16

I/O A

SEG17

I/O A

SEG18

I/O A

SEG19

I/O A

SEG20

I/O A

SEG21

I/O A

SEG22

HD404818 Series

Pin Number

MCU Mode

PROM Mode

Pin Number

MCU Mode

PROM Mode

FP-
80B

FP-80A
TFP-80 Pin Name

I/O Pin Name

I/O

FP-80B

FP-80A
TFP-80

Pin Name

I/O Pin Name

I/O

SEG23

COM4

SEG24

SEG25

SEG26

SEG27

NUMO

SEG28

NUMO

SEG29

NUMG

SEG30

SEG31

OSC

SEG32

OSC

COM1

RESET

COM2

I/O O

I/O

COM3

I/O O

I/O

Note: I/O: Input/output pin, I: Input pin, O: Output pin

HD404818 Series

Programmable ROM Operation

The MCU on-chip PROM is programmed in PROM mode. PROM mode is set by pulling

TEST, M

, and

low, and RESET high, as shown in figure 38. In PROM mode, the MCU does not operate. It can be

programmed like a standard 27256 EPROM using a standard PROM programmer and an 80-to-28-pin
socket adapter. Table 31 lists the recommended PROM programmers and socket adapters.

Since an instruction of the HMCS400 series consists of 10 bits, the HMCS400 series microcomputer
incorporates a conversion circuit to enable the use of a general-purpose PROM programmer. By this circuit,
an instruction is read or programmed using two addresses, a lower 5 bits and upper 5 bits. For example, if 8
kwords of on-chip PROM are programmed by a general-purpose PROM pro-grammer, 16 kbytes of
addresses ($0000$3FFF) should be specified.

Programming and Verification

The MCU can be programmed at high speed without causing voltage stress or affecting data reliability.

Table 30 shows how programming and verification modes are selected.

Precautions

1. Addresses $0000 to $3FFF must be specified if the PROM is programmed by a PROM programmer. If

addresses of $4000 or higher are accessed, the PROM may not be programmed or verified. Note that
plastic package types cannot be erased and reprogrammed. Data in unused addresses must be set to $FF.

2. Ensure that the PROM programmer, socket adapter, and LSI match. Using the wrong programmer for

the socket adapter may cause an overvoltage and damage the LSI. Make sure that the LSI is firmly fixed
in the socket adapter, and that the socket adapter is firmly fixed onto the programmer.

3. The PROM should be programmed with V

= 12.5 V. Other PROMs use 21 V. If 21 V is applied to the

MCU, the LSI may be permanently damaged. 12.5 V is the Intel 27256 setting.

Table 30 PROM Mode Selection

Pin

Mode

Programming

Low

High

Data input

Verify

High

Low

Data output

Programming inhibited

High

High impedance

HD404818 Series

Addressing Modes

RAM Addressing Modes

As shown in figure 39, the MCU has three RAM addressing modes: register indirect addressing, direct
addressing, and memory register addressing.

Register Indirect Addressing Mode: The W register, X register, and Y register contents (10 bits total) are
used as the RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words, with the word (10 bits)
following the opcode used as the RAM address.

Memory Register Addressing Mode: The memory registers (16 digits from $040 to $04F) are accessed
by executing the LAMR and XMRA instructions.

ROM Addressing Modes and the P Instruction

The MCU has four kinds of ROM addressing modes as shown in figure 40.

Direct Addressing Mode: The program can branch to any address in ROM memory space by executing
the JMPL, BRL, or CALL instruction. These instructions replace the 14 program counter bits (PC

to PC

)

with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 32 pages of ROM with 256 words per page. By executing
the BR instruction, the program can branch to an address in the current page. This instruction replaces the
lower eight bits of the program counter (PC

to PC

) with 8-bit immediate data.

When the BR instruction is on a page boundary (256n + 255) (figure 41), executing it transfers the PC
contents to the next page according to the hardware architecture. Consequently, the program branches to
the next page when the BR instruction is used on a page boundary. The HMCS400 series cross
macroassembler has an automatic paging facility for ROM pages.

Zero-Page Addressing Mode: By executing the CAL instruction, the program can branch to the zero-page
subroutine area, which is located at $0000$003F. When the CAL instruction is executed, 6-bit immediate
data is placed in the lower six bits of the program counter (PC

to PC

) and 0s are placed in the higher eight

bits (PC

to PC

Table Data Addressing Mode: By executing the TBR instruction, the program can branch to the address
determined by the contents of the 4-bit immediate data, accumulator, and B register.

P Instruction: ROM data addressed by table data addressing can be referenced by the P instruction (figure
42). When bit 8 in the referred ROM data is 1, eight bits of ROM data are written into the accumulator and
B register. When bit 9 is 1, eight bits of ROM data is written into the R1 and R2 port output registers.
When both bits 8 and 9 are 1, ROM data is written into the accumulator and B register, and also to the R1
and R2 port output registers at the same time.

HD404818 Series

Instruction 2nd word

Opcode

Instruction 1st word

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 40 ROM Addressing Modes

HD404818 Series

Absolute Maximum Ratings

HD404812, HD404814, HD404816, HD404818, and HD4074818 Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to V

+0.3

Total permissible input current

100

Total permissible output current

Maximum input current

4, 5

4, 6

Maximum output current

7, 8

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

should be under the conditions of the electrical characteristics. If these conditions are exceeded, it
may cause a malfunction or affect the reliability of the LSI.

1. D

) of the HD4074818.

2. Total permissible input current is the sum of the input currents which flow in from all I/O pins to

GND simultaneously.

3. Total permissible output current is the sum of the output currents which flow out from V

to all

I/O pins simultaneously.

4. Maximum input current is the maximum amount of input current from each I/O pin to GND.

5. R0R3.

6. D

7. Maximum output current is the maximum amount of output current from V

to each I/O pin.

8. D

and R0R3.

HD404818 Series

HD40L4812, HD40L4814, HD40L4816, HD40L4818, and HD407L4818 Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to V

+ 0.3

Total permissible input current

100

Total permissible output current

Maximum input current

4, 5

4, 6

Maximum output current

7, 8

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

should be under the conditions of the electrical characteristics. If these conditions are exceeded, it
may cause a malfunction or affect the reliability of the LSI.

1. D

) of the HD407L4818.

2. Total permissible input current is the sum of the input currents which flow in from all I/O pins to

GND simultaneously.

3. Total permissible output current is the sum of the output currents which flow out from V

to all

I/O pins simultaneously.

4. Maximum input current is the maximum amount of input current from each I/O pin to GND.

5. R0R3.

6. D

7. Maximum output current is the maximum amount of output current from V

to each I/O pin.

8. D

and R0R3.

HD404818 Series

Electrical Characteristics for Standard-Voltage

HD404812, HD404814, HD404816, HD404818, and HD4074818 Electrical Characteristics

DC Characteristics (HD404812, HD404814, HD404816, HD404818: V

= 4 to 6 V; HD4074818: V

= 4 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

RESET,

SCK

INT

, SI,

INT

0.8V

0.3

OSC

0.5

0.3

Input low
voltage

RESET,

SCK

INT

, SI,

INT

0.3

0.2V

OSC

0.3

0.5

Output high
voltage

SCK

, TIMO,SO

1.0

= 1.0 mA

Output low
voltage

SCK

, TIMO,SO

0.4

= 1.6 mA

Input/output
leakage
current

RESET,

SCK

INT

SI, SO, TIMO,
OSC

= 0 V to V

Stop mode
retaining
voltage

STOP

Without 32-kHz
oscillator

Current
dissipation in
active mode

CC1

3.5

= 5 V,

OSC

= 4 MHz

CC2

= 5 V,

OSC

= 4 MHz

Current
dissipation in
standby
mode

SBY

= 5 V,

OSC

= 4 MHz

Current
dissipation in
subactive
mode

SUB

150

300

= 5 V,

LCD: On

150

HD404818 Series

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Current
dissipation in
watch mode
(1)

WTC1

= 5 V,

LCD: Off

Current
dissipation in
watch mode
(2)

WTC2

= 5 V,

LCD: On

Current
dissipation in
stop mode

STOP

= 5 V,

Without 32-kHz
oscillator

Notes: 1. Excluding output buffer current.

2. The MCU is in the reset state. Input/output current does not flow.

MCU in reset state

RESET,

TEST

: V

3. The timer operates and input/output current does not flow.

MCU in standby mode

Input/output in reset state

Serial interface: Stop

RESET: GND

TEST

: V

, D

: Digital input mode

4. RAM data retention.

5. D

is in the analog input mode.

Input/output current does not flow. VC

ref

, D

: GND

6. Applies to the HD404812, HD404814, HD404816, and HD404818.

HD404818 Series

Input/Output Characteristics for Standard Pins (HD404812, HD404814, HD404816, HD404818: V

= 4 to 6 V; HD4074818: V

= 4 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise

specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

R0 R3

0.7V

0.3

Input low
voltage

R0R3

0.3

0.3V

Output high
voltage

R0R3

1.0

= 1.0 mA

Pull-up MOS
current

R0R3

100

180

= 5 V,

= 0 V

Output low
voltage

R0R3

0.4

= 1.6 mA

Input/output
leakage
current

R0 R3

= 0 V to V

Input high
voltage

IHA

, D

(analog compare
mode)

ref

+ 0.1

Input low
voltage

ILA

, D

(analog compare
mode)

ref

0.1

Analog input
voltage

Cref

1.2

Notes: 1. Output buffer current is excluded.

2. Applies to HD404812, HD404814, HD404816, and HD404818.

3. Applies to HD4074818.

HD404818 Series

Input/Output Characteristics for High-Current Pins (HD404812, HD404814, HD404816, HD404818:

= 4 to 6 V; HD4074818: V

C C

= 4 to 5.5 V; GND = 0V, T

= 20

C to +75

C, unless otherwise

specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Input high
voltage

0.7V

+ 0.3

Input low
voltage

0.3

0.3V

Output high
voltage

1.0

= 1.0 mA

Pull-up MOS
current

100

180

= 5 V,

= 0 V

Output low
voltage

2.0

= 15 mA,

= 4.5 to 6 V

0.4

= 1.6 mA

Input/output
leakage
current

= 0 V to V

Note:

Output buffer current is excluded.

Liquid Crystal Circuit Characteristics (HD404812, HD404814, HD404816, HD404818: V

= 4 to 6

V; HD4074818: V

= 4 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Note

Segment
driver voltage
drop

SEG1 to SEG32

0.6

= 3

Common
driver voltage
drop

COM1 to COM4

0.3

= 3

LCD power
supply
dividing
resistance

100

300

900

LCD voltage

LCD

Notes: 1. Voltage drops from pins V

, V

, and GND to each segment and common pin.

2. Keep the relationship V

GND when V

LCD

is supplied by an external power

supply.

HD404818 Series

AC Characteristics (HD404812, HD404814, HD404816, HD404818: V

= 4 to 6 V; HD4074818: V

= 4 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Oscillation
frequency

OSC

, OSC

1.6

4.0

4.2

MHz

X1, X2

32.768

kHz

Oscillation
frequency

OSC

, OSC

(without 32 kHz)

0.25

4.0

4.2

MHz

Instruction
cycle time

cyc

0.95

2.5

0.95

Without 32 kHz

Oscillator
stabilization
time

OSC

, OSC

Crystal

7.5

Ceramic
f

OSC

= 4 MHz

X1, X2

= 10

to 60

External
clock
frequency

OSC

1.6

4.2

MHz

0.25

4.2

MHz

Without 32 kHz

External
clock high
width

CPH

OSC

110

External
clock low
width

CPL

OSC

110

External
clock rise
time

CPr

OSC

External
clock fall time

CPf

OSC

INT

high

width

INT

cyc

subcyc

4, 6

INT

low

width

INT

cyc

subcyc

4, 6

INT

high

width

INT

cyc

INT

low

width

INT

cyc

HD404818 Series

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

RESET high
width

RSTH

RESET

cyc

Input
capacitance

f = 1 MHz, V

= 0 V 8

f = 1 MHz, V

= 0 V 9

All pins except D

f = 1 MHz, V

= 0 V

RESET fall
time

RSTf

Analog
comparator
stabilization
time

CSTB

, D

cyc

Notes: 1. The oscillator stabilization time is the period up until the time the oscillator stabilizes after V

reaches 4.0 V at power-on, or after RESET goes high. At power-on or stop mode release,
RESET must be kept high for at least t

. Since t

depends on the ceramic oscillator's circuit

constant and stray capacitance, consult with the manufacturer when designing the reset circuit.

2. The oscillator stabilization time is the period up until the time the oscillator stabilizes after V

reaches 4.0 V at power-on. The time required to stabilize the oscillator (t

) must be obtained.

Since t

depends on the crystal circuit constant and stray capacitance, consult with the

manufacturer.

3. See figure 43.

4. See figure 44. The unit t

cyc

is applied when the MCU is in standby mode or active mode.

5. See figure 45.

6. See figure 44. The unit t

subcyc

is applied when the MCU is in watch mode or subactive mode.

subcyc

= 244.14

s (when a 32.768-kHz crystal oscillator is used)

7. The analog comparator stabilization time is the period up until the analog comparator stabilizes

and correct data can be read after placing D

into analog input mode.

8. Applies to HD404812, HD404814, HD404816, and HD404818.

9. Applies to HD4074818.

HD404818 Series

Serial Interface Timing Characteristics

During Transmit Clock Output (HD404812, HD404814, HD404816, HD404818: V

= 4 to 6 V;

HD4074818: V

= 4 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time t

Scyc

SCK

cyc

subcyc

1, 2, 4

Transmit clock high and
low widths

SCKH,

SCKL

SCK

0.5

Scyc

1, 2

Transmit clock rise and
fall times

SCKr,

SCKf

SCK

100

1, 2

Serial output data delay
time

DSO

300

1, 2

Serial input data setup
time

SSI

200

Serial input data hold time t

HSI

150

During Transmit Clock Input

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time t

Scyc

SCK

cyc

subcyc

1, 4

Transmit clock high and
low widths

SCKH,

SCKL

SCK

0.5

Scyc

Transmit clock rise and
fall times

SCKr,

SCKf

SCK

100

Serial output data delay
time

DSO

300

1, 2

Serial input data setup
time

SSI

200

Serial input data hold time t

HSI

150

Transmit clock completion
detect time

SCKHD

SCK

cyc

subcyc

1,2, 3, 4

Notes: 1. See figure 46.

2. See figure 47.

3. The transmit clock completion detect time is the high level period after 8 pulses of transmit

clocks are input. The serial interrupt request flag is not set if the next transmit clock is input
before the transmit clock completion detect time has passed.

4. The unit t

subcyc

is applied when the MCU is in subactive mode. t

subcyc

= 244.14

s (for a 32.768-

kHz crystal oscillator).

HD404818 Series

Electrical Characteristics for Low-Voltage Versions

HD40L4812, HD40L4814, HD40L4816, HD40L4818, and HD407L4818 Electrical Characteristics

DC Characteristics (HD40L4812, HD40L4814, HD40L4816, HD40L4818: V

C C

= 2.7 to 6 V;

HD407L4818: V

= 3 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

RESET,

SCK

INT

, SI,

INT

0.9V

0.3

OSC

0.3

Input low
voltage

RESET,

SCK

INT

, SI,

INT

0.3

0.1V

OSC

0.3

Output high
voltage

SCK

, TIMO, SO

1.0

= 0.5 mA

Output low
voltage

SCK

, TIMO, SO

0.4

= 0.4 mA

Input/output
leakage
current

RESET,

SCK

INT

SI, SO, TIMO,
OSC

= 0 V to V

Stop mode
retaining
voltage

STOP

Without 32-kHz
oscillator

Current
dissipation in
active mode

CC1

400

1000

= 3V,

OSC

= 400 kHz

CC2

= 3 V,

OSC

= 400 kHz,

analog input mode
(D

)

Current
dissipation in
standby
mode

SBY

200

500

= 3 V

OSC

= 400 kHz

Current
dissipation in
subactive
mode

SUB

100

= 3 V,

LCD: On

HD404818 Series

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Current
dissipation in
watch mode
(1)

WTC1

= 3 V,

LCD: Off

Current
dissipation in
watch mode
(2)

WTC2

= 3 V,

LCD: On

Current
dissipation in
stop mode

STOP

= 3 V,

Without 32-kHz
oscillator

Notes: 1. Excluding output buffer current.

2. The MCU is in the reset state. Input/output current does not flow.

MCU in reset state

RESET,

TEST

: V

3. The timer operates and input/output current does not flow.

MCU in standby mode

Input/output in reset state

Serial interface: Stop

RESET: GND

TEST

: V

, R0R3: V

, D

: Digital input mode

4. RAM data retention.

5. D

is in the analog input mode.

Input/output current does not flow. VC

ref

, D

: GND

6. Applies to HD40L4812, HD40L4814, HD40L4816, and HD40L4818.

HD404818 Series

Input/Output Characteristics for Standard Pins (HD40L4812, HD40L4814, HD40L4816,

HD40L4818: V

= 2.7 to 6 V; HD407L4818: V

= 3 to 5.5 V; GND = 0 V, T

= 20

C to +75

unless otherwise specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

R0R3

0.7V

0.3

Input low
voltage

R0R3

0.3

0.3V

Output high
voltage

R0R3

1.0

= 0.5 mA

Pull-up MOS
current

R0R3

= 3 V,

= 0 V

Output low
voltage

R0R3

0.4

= 0.4 mA

Input/output
leakage
current

R0R3

= 0 V to V

Input high
voltage

IHA

, D

(Analog compare
mode)

ref

0.1

Input low
voltage

ILA

, D

(Analog compare
mode)

ref

0.1

Analog input
voltage

Cref

1.2

Notes: 1

Output buffer current is excluded.

2. Applies to HD40L4812, HD40L4814, HD40L4816, and HD40L4818.

3. Applies to HD407L4818.

HD404818 Series

Input/Output Characteristics for High-Current Pins (HD40L4812, HD40L4814, HD40L4816,

HD40L4818: V

= 2.7 to 6 V; HD407L4818: V

= 3 to 5.5 V; GND = 0 V, T

= 20

C to +75

unless otherwise specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Input high
voltage

0.7V

+ 0.3

Input low
voltage

0.3

0.3V

Output high
voltage

1.0

= 0.5 mA

Pull-up MOS
current

= 3 V,

= 0 V

Output low
voltage

2.0

= 15 mA,

= 4.5 to 6 V

0.4

= 0.4 mA

Input/output
leakage
current

= 0 V V

Note:

Output buffer current is excluded.

Liquid Crystal Circuit Characteristics (HD40L4812, HD40L4814, HD40L4816, HD40L4818: V

2.7 to 6 V; HD407L4818: V

= 3 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise

specified)

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Notes

Segment driver voltage
drop

SEG1 to
SEG32

0.6

= 3

Common driver voltage
drop

COM1 to
COM4

0.3

= 3

LCD power supply
dividing resistance

100

300

900

LCD voltage

LCD

2.7

2, 3

Notes: 1. Voltage drops from pins V

, V

, and GND to each segment and common pin.

2. Keep the relation V

GND when V

LCD

is supplied by an external power supply.

3. V

LCD

min. = 2.7 V (HD40L4812, HD40L4814, HD40L4816, HD40L4818)

LCD

min. = 3 V (HD407L4818)

HD404818 Series

AC Characteristics (HD40L4812, HD40L4814, HD40L4816, HD40L4818: V

C C

= 2.7 to 6 V;

HD407L4818: V

= 3 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Oscillation
frequency

OSC

, OSC

250

800

900

kHz

X1, X2

32.768

kHz

Instruction cycle
time

cyc

4.45

Oscillator
stabilization time

OSC

, OSC

7.5

OSC

= 400 kHz

7.5

OSC

= 800 kHz

X1, X2

= 10

to 60

External clock
frequency

OSC

250

900

kHz

External clock high
width

CPH

OSC

525

External clock low
width

CPL

OSC

525

External clock rise
time

CPr

OSC

External clock fall
time

CPf

OSC

INT

high width

INT

cyc/

subcyc

4, 6

INT

low width

INT

cyc/

subcyc

4, 6

INT

high width

INT

cyc

INT

low width

INT

cyc

RESET high width t

RSTH

RESET

cyc

Input capacitance

f = 1 MHz, V

= 0 V 8

f = 1 MHz, V

= 0 V 9

All pins except D

f = 1 MHz, V

= 0 V

Reset fall time

RSTf

Analog
comparator
stabilization time

CSTB

, D

cyc

Notes: 1. The oscillator stabilization time is the period from when V

reaches 2.7 V (HD407L4818: V

3.0 V) at power-on until the oscillator stabilizes, or after RESET goes high. At power-on or when
recovering from stop mode, RESET must be kept high for more than t

. Since t

depends on

the ceramic oscillator's circuit constant and stray capacitance, consult with the ceramic oscillator
manufacturer when designing the reset circuit.

HD404818 Series

2. The oscillator stabilization time is the period from when V

reaches 2.7 V (HD407L4818: V

3.0 V) at power-on until the oscillator stabilizes. The time required to stabilize the oscillator (t

)

must be obtained. Since t

depends on the ceramic oscillator's circuit constant and stray

capacitance, consult with the ceramic oscillator manufacturer.

3. See figure 48.

4. See figure 49. The unit t

cyc

is applied when the MCU is in standby mode or active mode.

5. See figure 50.

6. See figure 49. The unit t

subcyc

is applied when the MCU is in watch mode or subactive mode.

subcyc

= 244.14

s (when a 32.768-kHz crystal oscillator is used)

7. The analog comparator stabilization time is the period from when D

is placed in analog

input mode until the analog comparator stabilizes and correct data can be read.

8. Applies to HD40L4812, HD40L4814, HD40L4816, and HD40L4818.

9. Applies to HD407L4818.

Serial Interface Timing Characteristics

During Transmit Clock Output (HD40L4812, HD40L4814, HD40L4816, HD40L4818: V

= 2.7 to 6

V; HD407L4818: V

= 3 to 5.5 V; GND = 0 V, T

= 20

C to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time

Scyc

SCK

cyc

subcyc

1, 2, 4

Transmit clock high and low
widths

SCKH

SCKL

SCK

0.5

Scyc

1, 2

Transmit clock rise and fall
times

SCKr

SCKf

SCK

200

1, 2

Serial output data delay time t

DSO

500

1, 2

Serial input data setup time

SSI

300

Serial input data hold time

HSI

300

HD404818 Series

During Transmit Clock Input

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Transmit clock cycle time

Scyc

SCK

cyc

subcyc

1, 4

Transmit clock high and low
widths

SCKH

SCKL

SCK

0.5

Scyc

Transmit clock rise and fall
times

SCKr

SCKf

SCK

200

Serial output data delay time t

DSO

500

1, 2

Serial input data setup time

SSI

300

Serial input data hold time

HSI

300

Transmit clock completion
detect time

SCKHD

SCK

cyc

subcyc

1, 2,
3, 4

Notes: 1. See figure 51.

See figure 52.

3. The transmit clock completion detect time is the high level period after 8 pulses of transmit

clocks are input. The serial interrupt request flag is not set if the next transmit clock is input
before the transmit clock completion detect time has passed.

4. t

subcyc

is applied when the MCU is in subactive mode. t

subcyc

= 244.14

s (for a 32.768-kHz crystal

oscillator).

CPr

CPf

0.3 V

OSC

CPH

CPL

1/f

Figure 48 Oscillator Timing

0.9V

0.1V

INT

Figure 49 Interrupt Timing

RESET

RSTf

RSTH

0.9V

0.1V

Figure 50 Reset Timing

HD404818 Series

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size as an 8-kword version
(HD404818 and HD40L4818). An 8-kword data size is required to change ROM data to mask
manufacturing data since the program used is for an 8-kword version.

This limitation applies when using an EPROM or a data base.

Vector address

Zero-page
subroutine

(64 words)

Pattern & program

(2,048 words)

Not used

Vector address

Zero-page
subroutine

(64 words)

Pattern

(4,096 words)

Not used

ROM 2-kword version:
HD404812, HD40L4812
Address $0800$1FFF

ROM 6-kword version:
HD404816, HD40L4816
Address $1800$1FFF

$0000

$000F
$0010

$003F
$0040

$07FF
$0800

$0000

$000F
$0010

$003F
$0040

$17FF
$1800

$1FFF

Fill this area with 1s

Vector address

Zero-page
subroutine

(64 words)

Pattern & program

(4,096 words)

Not used

ROM 4-kword version:
HD404814, HD40L4814
Address $1000$1FFF

$0000

$000F
$0010

$003F
$0040

$0FFF
$1000

$1FFF

Program

(6,144 words)

$0FFF
$1000

HD404818 Series

HD404812, HD404814, HD404816, HD404818, HD40L4812, HD40L4814,
HD40L4816, HD40L4818 Option List

5-V operation

Low-voltage operation

5-V operation

Low-voltage operation

5-V operation

Low-voltage operation

5-V operation

Low-voltage operation

1. ROM Size

3. ROM Code Media

EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are

programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are

programmed to different EPROMs.

With 32-kHz CPU operation and with watch time base

Without 32-kHz CPU operation and with watch time base

Without 32-kHz CPU operation and without watch time base

2. Optional Functions

Date of order

Customer

Department

Name

ROM code name

LSI type number
(Hitachi's entry)

/ /

4. Oscillator

Ceramic oscillator

Crystal oscillator

External clock

f =

MHz

FP-80A

FP-80B

TFP-80

6. Package

Note:

Used

Not used

5. Stop mode

Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).

Please check off the appropriate applications and
enter the necessary information.

HD404812

HD40L4812

HD404814

HD40L4814

HD404816

HD40L4816

HD404818

HD40L4818

2-kword

4-kword

6-kword

8-kword

Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTATTM version).

HD404818 Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404816TF

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404816TF