Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.

Notes regarding these materials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas

Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.

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third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.

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algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corporation
or an authorized Renesas Technology Corporation product distributor for the latest product information
before purchasing a product listed herein.
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or system that is used under circumstances in which human life is potentially at stake. Please contact
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8. Please contact Renesas Technology Corporation for further details on these materials or the products

contained therein.

HD404849 Series

4-Bit Single-Chip Microcomputer

Rev. 6.0

Sept. 1998

Description

The HD404849 series of HMCS400-series microcomputers is designed to increase program productivity
and also incorporate large-capacity memory. Each microcomputer has an LCD controller/driver, A/D
converter, input capture circuit, 32-kHz oscillator for clock use, and four low-power dissipation modes.

The HD404849 series includes the HD404848 with an 8-kword on-chip ROM, the HD4048412 with a 12-
kword on-chip ROM, the HD404849 with a 16-kword on-chip ROM, and the HD4074849 with a 16-kword
on-chip PROM.

On-chip ROM is available in a PROM (ZTAT

microcomputer) version and a mask ROM version. A

program can be written to the PROM by a PROM writer, which can dramatically shorten system
development periods and smooth the process from debugging to mass production. PROM programming
specifications are the same as for the 27256.

ZTAT

: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

35 I/O pins, including nine high-current pins (15 mA, max.), eight pins multiplexed with LCD segment
pins, and four pins multiplexed with analog input pins

Four timer/counters

Eight-bit input capture circuit

Three timer outputs (including two PWM outputs)

Two event counter inputs (including one in which the detection edge is programmable)

Clock-synchronous 8-bit serial interface

A/D converter (8 channels

8 bits)

Operation voltage 2.7 V to 6.0 V

LCD driver (32 segments

4 commons)

Built-in oscillators

Main clock: Can be driven by ceramic oscillator, crystal oscillator, or external clock.

Subclock: 32.768-kHz crystal

Ten interrupt sources

Four by external sources, including two in which the detection edge is programmable

HD404849 Series

Six by internal sources

Subroutine stack up to 16 levels, including interrupts

Four low-power dissipation modes

Standby mode

Stop mode

Watch mode

Subactive mode

One external input for transition from stop mode to active mode

Instruction cycle time: 0.89

s (f

OSC

= 4.5 MHz)

Operation voltage

= 2.7 V to 6.0 V (subactive mode: 2.2 V to 6.0 V) (HD404848, HD404849)

= 2.7 V to 5.5 V (HD4074849)

Two operating modes

MCU mode (HD404848, HD4048412, HD404849)

MCU/PROM mode (HD4074849 only)

Ordering Information

Type

Product Name

Model Name

ROM (words)

RAM (digits)

Package

Mask ROM

HD404848

HD404848H

8,192

512

80-pin plastic QFP
(FP-80A)

HD404848FS

80-pin plastic QFP
(FP-80B)

HD404848TF

80-pin plastic
TQFP (TFP-80C)

HD4048412

HD4048412H

12,288

1,184

80-pin plastic QFP
(FP-80A)

HD4048412FS

80-pin plastic QFP
(FP-80B)

HD4048412TF

80-pin plastic
TQFP (TFP-80C)

HD404849

HD404849H

16,384

1,184

80-pin plastic QFP
(FP-80A)

HD404849FS

80-pin plastic QFP
(FP-80B)

HD404849TF

80-pin plastic
TQFP (TFP-80C)

ZTAT

HD4074849

HD4074849H

16,384

1,184

80-pin plastic QFP
(FP-80A)

HD4074849FS

80-pin plastic QFP
(FP-80B)

HD4074849TF

80-pin plastic
TQFP (TFP-80C)

HD404849 Series

Pin Arrangement

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

/AN

TEST
OSC

OSC

RESET

X1
X2

GND

STOPC

INT

/INT

/TOB

/TOC

/TOD

EVNB

/EVND

SCK

/SI

/SO

/SEG13

/SEG14

/SEG15

/SEG16

/SEG17

/SEG18

/SEG19

/AN

COM4

COM3

COM2

COM1

SEG44

SEG43

SEG42

SEG41

SEG40

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
R7

/SEG20

FP-80A

TFP-80C

(top view)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

/AN

TEST
OSC

OSC

RESET

X1
X2

GND

/INT

/TOB

/TOC

/TOD

EVNB

/EVND

SCK

/SI

/SO

/SEG13

/SEG14

/SEG15

/SEG16

/SEG17

COM4

COM3

COM2

COM1

SEG44

SEG43

SEG42

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45

SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22

FP-80B

(top view)

SEG21

STOPC

/SEG20

INT

/SEG19

INT

/SEG18

HD404849 Series

Pin Description

Pin Number

Item

Symbol

FP-80A ,TFP-80C FP-80B

I/O

Function

Power supply

Applies power voltage

GND

Connected to ground

Test

TEST

Used for factory testing only: Connect
this pin to GND

Reset

RESET

Resets the MCU

Oscillator

OSC

Input/output pins for the internal
oscillator circuit:
Connect them to a ceramic oscillator
or connect OSC1 to an external
oscillator circuit.

OSC

Used for a 32.768-kHz crystal for
clock purposes. If not to be used, fix
the X1 pin to VCC and leave the X2
pin open.

Port

1119

1321

I/O

Input/output pins addressed by
individual bits; pins D

are high-

current pins that can each supply up
to 15 mA

, D

20, 21

22, 23

Input pins addressable by individual
bits

R0R3, R6,
R7

2233, 79, 80,
1, 2, 3441

2435, 14,
3643

I/O

Input/output pins addressable in 4-bit
units

Interrupt

INT

, INT

2124

2326

Input pins for external interrupts

Stop clear

STOPC

Input pin for transition from stop mode
to active mode

Serial

SCK

I/O

Serial clock input/output pin

Serial receive data input pin

Serial transmit data output pin

Timer

TOB, TOC,
TOD

2628

2830

Timer output pins

EVNB

EVND

29, 30

31, 32

Event count input pins

HD404849 Series

Pin Number

Item

Symbol

FP-80A, TFP-80C FP-80B

I/O

Function

LCD

, V

7072

7274

Power pins for LCD driver. The LCD
power supply division resistors can be
connected and disconnected as
controlled by software.
Voltage conditions are:
V

GND

COM1
COM4

6669

6871

Common signal pins for LCD

SEG13
SEG44

3465

3667

Segment signal pins for LCD

A/D converter

Power pin for A/D converter: Connect
it to the same potential as V

, as

physically close to the V

pin as

possible

Ground for AV

: Connect it to the

same potential as GND, as physically
close to the GND pin as possible

7580, 1, 2

7780, 14

Analog input pins for A/D converter

HD404849 Series

Block Diagram

System control circuit

1,184

4-bit RAM

W (2)

X (4)

SPX (4)

Y (4)

SPY (4)

A (4)

B (4)

SP (10)

Program

counter (14)

Instruction

decoder

ALU

ST (1)

CA (1)

LCD

display

circuit

A/D

converter

Serial

interface

Timer D

Timer C

Timer B

Timer A

External
interrupt

control

cricuit

Internal data bus

Internal address bus

Internal data bus

: Data bus

: Signal lines

RESET

TEST

STOPC

OSC

GND

INT

TOB

EVNB

TOC

TOD

EVND

SCK

V1
V2
V3

COM1
COM2
COM3
COM4

SEG13

SEG44

INT

/INT

STOPC

INT

/TOB
/TOC
/TOD
/

EVNB

/EVND
/

SCK

/SI
/SO

/AN

/SEG13
/SEG14
/SEG15
/SEG16

/SEG17
/SEG18
/SEG19
/SEG20

/INT

High-
current
pins

512

4-bit,

8,192

10-bit, 12,288

10-bit,

16,384

10-bit ROM

HD404849 Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.

Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000$1FFF: HD404848; $0000$2FFF: HD4048412; $0000$3FFF: HD404849,
HD4074849): Used for program coding.

4095

8191

12287

16383

$0000

$000F

$003F

$0FFF

$1FFF

$2FFF

$3FFF

HD404849/
HD4074849
program area
(16,384 words)

HD4048412
program area
(12,288 words)

HD404848
program area
(8,192 words)

Pattern area
(4,096 words)

Zero-page
subroutine area
(64 words)

Vector address area
(16 words)

$0000

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

JMPL instruction

(jump to

RESET

STOPC

routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B, INT routine)

JMPL instruction

(jump to timer C, INT routine)

JMPL instruction

(jump to timer D routine)

JMPL instruction

(jump to A/D, serial routine)

Figure 1 ROM Memory Map

HD404849 Series

RAM Memory Map

The MCU contains a RAM area consisting of a memory register area, an LCD data area, a data area, and a
stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped
onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM
memory map is shown in figure 2 and described below.

RAM-Mapped Register Area ($000$03F):

Interrupt Control Bits Area ($000$003)

This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

Special Function Register Area ($004$01F, $024$03F)

This area is used as mode registers and data registers for external interrupts, serial interface,
timer/counters, LCD, and A/D converter, and is used as data control registers for I/O ports. The
structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W),
read-only (R), and read/write (R/W). The SEM, SEMD, REM, and REMD instructions can be used for
the LCD control register (LCR: $01B), but RAM bit manipulation instructions cannot be used for other
registers.

This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.

Memory Register (MR) Area ($040$04F): Consisting of 16 addresses, this area (MR0MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.

LCD Data Area ($05C$07B): Used for storing 32-digit LCD data which is automatically output to LCD
segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Refer to
the LCD description for details.

Data Area ($090$21F: HD404848; $090$2EF: HD4048412, HD404849, HD4074849): 464 digits
from $090 to $25F have two banks, which can be selected by setting the bank register (V: $03F). Before
accessing this area, set the bank register to the required value (figure 7). The area from $260 to $2EF is
accessed without setting the bank register.

Stack Area ($3C0$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404849 Series

Interrupt control bits area

V register

Port R7 DCR

Port R6 DCR

Port R3 DCR

Port R2 DCR

Port R1 DCR

Port R0 DCR

Port D8 DCR

Port D4 to D7 DCR

Port D0 to D3 DCR

System clock select register

Serial mode register B

Edge sense select register 2

Edge sense select register 1

Port mode register C

Port mode register B

LCD output register 3

LCD mode register

LCD control register

A/D data register upper

A/D data register lower

A/D mode register

Timer mode register D2

Timer mode register C2

Timer mode register B2

Timer-D

Timer mode register D1

Timer-C

Timer mode register C1

Miscellaneous register

Timer-B

Timer mode register B1

Timer mode register A

Serial data register upper

Serial data register lower

Serial mode register A

Port mode register A

$03F

$037

$036

$033

$032

$031

$030

$02E

$02D

$02C

$029

$028

$027

$026

$025

$024

$023

$020

$01F

$01C

$01B

$018

$017

$016

$015

$014

$013

$012

$011

$010

$00F

$00E

$00D

$00C

$00B

$00A

$009

$008

$007

$006

$005

$004

$003

$000

(V)

(DCR7)

(DCR6)

(DCR3)

(DCR2)

(DCR1)

(DCR0)

(DCD2)

(DCD1)

(DCD0)

(SSR)

(SMRB)

(ESR2)

(ESR1)

(PMRC)

(PMRB)

(LOR3)

(LMR)

(LCR)

(ADRU)

(ADRL)

(AMR)

(TMD2)

(TMC2)

(TMB2)

(TRDU/TWDU)

(TRDL/TWDL)

(TMD1)

(TRCU/TWCU)

(TRCL/TWCL)

(TMC1)

(MIS)

(TRBU/TWBU)

(TRBL/TWBL)

(TMB1)

(TMA)

(SRU)

(SRL)

(SMRA)

(PMRA)

R/W

Timer read register B lower
Timer read register B upper

Timer write register B lower
Timer write register B upper

$00A
$00B

10
11

Timer read register C lower
Timer read register C upper

Timer write register C lower
Timer write register C upper

$00E
$00F

14
15

Timer read register D lower
Timer read register D upper

Timer write register D lower
Timer write register D upper

(TRBL)

(TRBU)

R
R

(TWBL)

(TWBU)

W
W

(TRCL)

(TRCU)

R
R

(TWCL)

(TWCU)

W
W

(TRDL)

(TRDU)

R
R

(TWDL)

(TWDU)

W
W

$011
$012

17
18

RAM mapped register

$000

Memory register (16 digits)

LCD display area (32 digits)

Data (144 digits)

Stack (64 digits)

Data (464 digits

V = 0 (bank 0)
V = 1 (bank 1)

$050

$05C

124

$07C

144

$090

608

$260

752

$2F0

960

$3C0

1023

$3FF

Data

(464 digits)

V = 0

(bank = 0)

Data

(464 digits)

V = 1

(bank = 1)

$090

$25F

The data area has two banks:
bank 0 (V = 0) and bank 1 (V = 1)

$040

Not used

Read only
Write only
Read/write

R:
W:
R/W:

Notes:

HD4048412, HD404849, HD4074849

RAM mapped register

$000

Memory register (16 digits)

LCD display area (32 digits)

Stack (64 digits)

Data (400 digits)

$050

$05C

$07C

$090

$220

$3C0

$3FF

$040

Not used

HD404848

Not used

124

144

544

960

1023

Two registers are mapped to the
same address (at $00A, $00B,
$00E, $00F, $011, and $012)

Figure 2 RAM Memory Map

HD404849 Series

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

IMAD

(IM of A/D)

IFAD

(IF of A/D)

IMTD

(IM of timer D)

IFTD

(IF of timer D)

$000

$001

$002

$003

(a) Interrupt control bits area

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

IM3

(IM of INT

)

IF3

(IF of INT

)

IM2

(IM of INT

)

IF2

(IF of INT

)

IMS

(IM of serial

interface)

IFS

(IF of serial

interface)

$020

$021

$022

$023

(b) Register flag area

DTON

(Direct transfer

on flag)

ADSF

(A/D start flag)

WDON

(Watchdog

on flag)

LSON

(Low speed

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

IF:
IM:
IE:
SP:

Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

IAOF

(A/D current off

flag)

Not used

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

HD404849 Series

LSON

IAOF

ICSF
ICEF

RAME

RSP

WDON

ADSF

Not used

DTON

SEM/SEMD

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Allowed

Inhibited

Allowed

Not executed in active mode

Allowed

Used in subactive mode

Not executed

Inhibited

Note: WDON is reset by MCU reset or by

STOPC

enable for stop mode cancellation.

The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST cannot be guaranteed.

Bits in the interrupt control bits area and register flag area can be set and reset by the
SEM/SEMD and REM/REMD instructions, and tested with the TM/TMD instructions.
Other instructions have no effect on these bits. Note the following restrictions for each
bit.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404849 Series

bit3

bit2

bit1

bit0

Interrupt control bits area

$000

$003

SMRA $005

SRL $006

SRU $007

TMB1 $009

TRBL/TWBL $00A

TRBU/TWBU $00B

MIS $00C

TMC1 $00D

TRCL/TWCL $00E

TRCU/TWCU $00F

TMD1 $010

TRDL/TWDL $011

TRDU/TWDU $012

TMB2 $013

TMC2 $014
TMD2 $015

AMR $016

ADRL $017

ADRU $018

LCR $01B

LMR $01C

LOR3 $01F

$020

PMRB $024

PMRC $025

ESR1 $026
ESR2 $027

SMRB $028

SSR $029

DCD0 $02C
DCD1 $02D

DCD2 $02E

DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033

DCR6 $036
DCR7 $037

V $03F

PMRA $004

TMA $008

$023

/SI

/SO

SCK

Serial transmit clock speed selection 1

Timer A/time base

Clock source selection (timer A)

Auto reload

on/off

Clock source selection (timer B)

Timer B register (upper digit)

Pull-up MOS control

PMOS SO control

Timer C output mode selection

Analog channel selection

A/D conversion period

LCD power switch

LCD display on/off

R7/SEG1720

R6/SEG1316

/INT

STOPC

/EVND

EVNB

INT

detection edge selection

32-kHz oscillation stop

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port D

DCR

Port R0

DCR

Port R0

DCR

Port R0

DCR

Port R0

DCR

Port R1

DCR

Port R1

DCR

Port R1

DCR

Port R1

DCR

Port R2

DCR

Port R2

DCR

Port R2

DCR

Port R2

DCR

Port R3

DCR

Port R3

DCR

Port R3

DCR

Port R3

DCR

Port R6

DCR

Port R6

DCR

Port R6

DCR

Port R6

DCR

Port R7

DCR

Port R7

DCR

Port R7

DCR

Port R7

DCR

Bank selection

Auto reload

on/off

Input capture

selection

Serial data register (lower digit)

Serial data register (upper digit)

Timer B register (lower digit)

Interrupt frame period selection

Clock source selection (timer C)

Timer C register (lower digit)

Timer C register (upper digit)

Clock source selection (timer D)

Timer D register (lower digit)

Timer D register (upper digit)

Timer B output mode selection

Timer D output mode selection

A/D data register (lower digit)

A/D data register (upper digit)

LCD input clock source selection

LCD duty cycle selection

INT

detection edge selection

EVND detection edge selection

INT

4.
5.
6.

Transmit clock source selection
32-kHz oscillation division ratio
System oscillation frequency selection

1.
2.
3.

LCD display division resistor switch
Display on/off in watch mode
SO output level control in idle states

Notes:

Auto reload

on/off

Not used

Figure 5 Special Function Register Area

HD404849 Series

Memory registers

65
66
67
68
69
70
71

73
74
75
76
77
78
79

$040

$041
$042

$043

$044

$045
$046

$047
$048
$049

$04A
$04B
$04C
$04D
$04E
$04F

960

$3C0

1023

$3FF

MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)

Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1

MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)

Bit 3

Bit 2

Bit 1

Bit 0

$3FC

$3FD

$3FE

$3FF

1020

1021

1022

1023

PC PC :
ST: Status flag
CA: Carry flag

Program counter

Stack area

Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

Bit

Initial value

Read/Write

Bit name

Not used

R/W

Not used

Bank area selection

Bank 0 is selected

Bank 1 is selected

Note: After reset, the value in the bank register is 0, and therefore bank 0 is

selected.

Bank register (V: $03F)

Figure 7 Bank Register (V)

HD404849 Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described
below.

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter
Initial value: 0,
no R/W

Stack pointer
Initial value: $3FF, no R/W

Initial value: Undefined, R/W

Initial value: 1, no R/W

Figure 8 Registers and Flags

Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.

W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.

HD404849 Series

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare
instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the
BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic,
compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is
read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the
stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN
instruction.

Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.

The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.

Reset

The MCU is reset by inputting a low-level voltage to the

RESET pin. At power-on or when stop mode is

cancelled,

RESET must be low for at least one t

to enable the oscillator to stabilize. During operation,

RESET must be low for at least two instruction cycles.

Initial values after MCU reset are listed in table 1.

HD404849 Series

Table 1 Initial Values After MCU Reset

Item

Abbr.

Initial
Value

Contents

Program
counter

(PC)

$0000

Indicates program execution point from start
address of ROM area

Status flag

(ST)

Enables conditional branching

Stack pointer

(SP)

$3FF

Stack level 0

Interrupt
flags/mask

Interrupt enable flag

(IE)

Inhibits all interrupts

Interrupt request flag

(IF)

Indicates there is no interrupt request

Interrupt mask

(IM)

Prevents (masks) interrupt requests

I/O

Port data register

(PDR)

All bits 1

Enables output at level 1

Data control register

(DCD0,
DCD1)

All bits 0

Turns output buffer off (to high impedance)

(DCD2)

- - - 0

(DCR0
DCR3,
DCR6,
DCR7)

All bits 0

Port mode register A

(PMRA)

- - 00

Refer to description of port mode register A

Port mode register B

(PMRB)

- 000

Refer to description of port mode register B

Port mode register C
bits 3, 1, 0

(PMRC3,
PMRC1,
PMRC0)

000

Refer to description of port mode register C

Detection edge select
register 1

(ESR1)

0000

Disables edge detection

Detection edge select
register 2

(ESR2)

00 - -

Disables edge detection

Timer/
counters,
serial
interface

Timer mode register A

(TMA)

0000

Refer to description of timer mode register A

Timer mode register B1 (TMB1)

0000

Refer to description of timer mode register B1

Timer mode register B2 (TMB2)

- - 00

Refer to description of timer mode register B2

Timer mode register C1 (TMC1)

0000

Refer to description of timer mode register
C1

Timer mode register C2 (TMC2)

- 000

Refer to description of timer mode register
C2

Timer mode register D1 (TMD1)

0000

Refer to description of timer mode register
D1

Timer mode register D2 (TMD2)

0000

Refer to description of timer mode register
D2

HD404849 Series

Item

Abbr.

Initial
Value

Contents

Timer/

Serial mode register A

(SMRA)

0000

Refer to description of serial mode register A

counters,

Serial mode register B

(SMRB)

- - X0

Refer to description of serial mode register B

serial

Prescaler S

(PSS)

$000

interface

Prescaler W

(PSW)

$00

Timer counter A

(TCA)

$00

Timer counter B

(TCB)

$00

Timer counter C

(TCC)

$00

Timer counter D

(TCD)

$00

Timer write register B

(TWBU,
TWBL)

$X0

Timer write register C

(TWCU,
TWCL)

$X0

Timer write register D

(TWDU,
TWDL)

$X0

Octal counter

000

A/D

A/D mode register

(AMR)

0000

Refer to description of A/D mode register

A/D data register

(ADRU,
ADRL)

$80

Refer to description of A/D mode register

LCD

LCD control register

(LCR)

0000

Refer to description of LCD control register

LCD mode register

(LMR)

0000

Refer to description of LCD duty-cycle/clock
control register

LCD output register 3

(LOR3)

- 00 -

Sets R-port/LCD segment pins to R port
mode

Bit registers

Low speed on flag

(LSON)

Refer to description of operati ng modes

Watchdog timer on flag (WDON)

Refer to description of timer C

A/D start flag

(ADSF)

Refer to description of A/D converter

A/D current off flag

(IAOF)

Direct transfer on flag

(DTON)

Refer to description of operati ng modes

Input capture status
flag

(ICSF)

Refer to description of timer D

Input capture error flag (ICEF)

Refer to description of timer D

Others

Miscellaneous register

(MIS)

0000

Refer to description of operati ng modes, I/O,
and serial interface

System clock select
register bits 2, 1

(SSR2,
SSR1)

00 -

Refer to description of operati ng modes and
oscillation circuits

Bank register

(V)

- - - 0

Refer to description of RAM memory map

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. indicates that the bit does not exist.

HD404849 Series

Interrupts

The MCU has ten interrupt sources: four external signals (

INT

, INT

), four timer/counters

(timers A, B, C, and D), serial interface, and A/D converter.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.

Some vector addresses are shared by two different interrupts. They are timer B and INT

, timer C and

INT

, and A/D converter and serial interface interrupts. So the type of request that has occurred must be

checked at the beginning of interrupt processing.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the ten interrupt sources are listed in
table 3.

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.

The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.

Table 2 Vector Addresses and Interrupt Priorities

Reset/Interrupt

Priority

Vector Address

RESET

STOPC*

$0000

INT

$0002

INT

$0004

Timer A

$0006

Timer B, INT

$0008

Timer C, INT

$000A

Timer D

$000C

A/D, Serial

$000E

Note:

The

STOPC

interrupt request is valid only in stop mode.

HD404849 Series

Table 3 Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt Control Bit

INT

Timer A

Timer B
or INT

Timer C
or INT

Timer D

A/D or
Serial

IF0

IM0

IF1

IM1

IFTA

IMTA

IFTB

IMTB

+ IF2

IM2 *

IFTC

IMTC

+ IF3

IM3 *

IFTD

IMTD

IFAD

IMAD

+ IFS

IMS *

Note:

Bits marked

can be either 0 or 1. Their values have no effect on operation.

Instruction cycles

Instruction

execution

IE reset

Interrupt

acceptance

Execution of JMPL

instruction at vector address

Execution of

instruction at

start address

of interrupt

routine

Vector address

generation

Note:

Stacking

The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.

Figure 10 Interrupt Processing Sequence

HD404849 Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.

Table 4 Interrupt Enable Flag (IE: $000, Bit 0)

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

, INT

): There are four external interrupt signals.

External Interrupt Request Flags (IF0IF3: $000, $001, $022): IF0 and IF1 are set when the signals
input to

INT

and

INT

are falling, and IF2 and IF3 are set when the signals input to INT

and INT

are

rising or falling, as listed in table 5. The INT

and INT

interrupt edges are selected by the detection edge

select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13.

Table 5 External Interrupt Request Flags (IF0IF3: $000, $001, $022)

IF0IF3

Interrupt Request

Yes

Bit

Initial value

Read/Write

Bit name

ESR13

ESR12

ESR10

ESR11

Detection edge selection register 1 (ESR1: $026)

ESR11

ESR10

INT

detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

ESR13

ESR12

INT

detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

Figure 12 Detection Edge Selection Register 1 (ESR1)

HD404849 Series

Bit

Initial value

Read/Write

Bit name

ESR23

ESR22

Not used

Detection edge selection register 2 (ESR2: $027)

ESR23

ESR22

EVND detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

Figure 13 Detection Edge Selection Register 2 (ESR2)

External Interrupt Masks (IM0IM3: $000, $001, $022): Prevent (mask) interrupt requests caused by
the corresponding external interrupt request flags, as listed in table 6.

Table 6 External Interrupt Masks (IM0IM3: $000, $001, $022)

IM0IM3

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.

Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)

IFTA

Interrupt Request

Yes

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the
timer A interrupt request flag, as listed in table 8.

HD404849 Series

Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)

IMTA

Interrupt Request

Enabled

Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.

Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)

IFTB

Interrupt Request

Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as listed in table 10.

Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1)

IMTB

Interrupt Request

Enabled

Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.

Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)

IFTC

Interrupt Request

Yes

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 12.

Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3)

IMTC

Interrupt Request

Enabled

Disabled (masked)

HD404849 Series

Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
13.

Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)

IFTD

Interrupt Request

Yes

Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 14.

Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1)

IMTD

Interrupt Request

Enabled

Disabled (masked)

Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 15.

Table 15 Serial Interrupt Request Flag (IFS: $023, Bit 2)

IFS

Interrupt Request

Yes

Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 16.

Table 16 Serial Interrupt Mask (IMS: $023, Bit 3)

IMS

Interrupt Request

Enabled

Disabled (masked)

A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as listed in
table 17.

HD404849 Series

Operating Modes

The MCU has five operating modes as shown in table 19. The operations in each mode are listed in tables
20 and 21. Transitions between operating modes are shown in figure 14.

Table 19 Operating Modes and Clock Status

Mode Name

Active

Standby

Stop

Watch

Subactive

Activation
method

Reset
cancellation,
interrupt
request

STOPC

cancellation in
stop mode,
STOP/SBY
instruction in
subactive
mode (when
direct transfer
is selected)

SBY
instruction

STOP
instruction
when
TMA3 = 0

STOP
instruction
when
TMA3 = 1

INT

or timer A

interrupt
request from
watch mode

Status

System
oscillator

Stopped

Subsystem
oscillator

Cancellation
method

RESET

input,

STOP/SBY
instruction

RESET

input,

interrupt
request

RESET

input,

STOPC

input

in stop mode

RESET

input

INT

or timer A

interrupt
request

RESET

input,

STOP/SBY
instruction

Notes: OP implies in operation.

1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select

2. Subactive mode is an optional function; specify it on the function option list.

HD404849 Series

Table 20 Operations in Low-Power Dissipation Modes

Function

Stop Mode

Watch Mode

Standby Mode

Subactive Mode

CPU

Reset

Retained

RAM

Retained

Timer A

Reset

Timer B

Reset

Stopped

Timer C

Reset

Stopped

Timer D

Reset

Stopped

Serial

Reset

Stopped

A/D

Reset

Stopped

LCD

Reset

I/O

Reset

Retained

Notes: OP implies in operation.

1. Output pins are at high impedance.

2. Subactive mode is an optional function specified on the function option list.

3. Transmission/reception is activated if a clock is input in external clock mode. However,

interrupts stop.

4. When a 32-kHz clock source is used.

Table 21 I/O Status in Low-Power Dissipation Modes

Output

Input

Standby Mode, Watch Mode

Stop Mode

Active Mode, Subactive Mode

Retained

High impedance

Input enabled

, D

Input enabled

R0R3, R6, R7

Retained or output of peripheral
functions

High impedance

Input enabled

HD404849 Series

Reset by

RESET

input or

by watchdog timer

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
Stop
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Oscillate
Oscillate
f

cyc

OSC

CPU

CLK

PER

Stop
Oscillate
f

SUB

OSC

CPU

CLK

PER

Stop
Stop
Stop
Stop
Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
f

Stop

Standby mode

Stop mode

(TMA3 = 0, SSR3 = 1)

Watch mode

Subactive
mode

(TMA3 = 1)

(TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

SBY

Interrupt

SBY

Interrupt

STOP

INT

timer A

STOP

1. Interrupt source
2. STOP/SBY (DTON = 1, LSON = 0)
3. STOP/SBY (DTON = 0, LSON = 0)
4. STOP/SBY (DTON = Don't care, LSON = 1)

OSC

cyc

SUB

LSON:
DTON:

Main oscillation frequency
Suboscillation frequency
for time-base
f

OSC

/8 or f

(software selectable)
f

System clock
Clock for time-base
Clock for other
peripheral functions
Low speed on flag
Direct transfer on flag

Active
mode

Notes:

CPU

CLK

PER

OSC

CPU

CLK

PER

Stop
Oscillate
Stop
Stop
Stop

(TMA3 = 0, SSR3 = 0)

RESET1

RESET2

RAME = 0

RAME = 1

INT

timer A

(TMA3 = 0)

STOP

STOPC

STOP

Figure 14 MCU Status Transitions

HD404849 Series

Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC

and OSC

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.

The MCU enters standby mode when the SBY instruction is executed in active mode.

Standby mode is terminated by a

RESET input or an interrupt request. If it is terminated by RESET input,

the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of
operation in standby mode is shown in figure 15.

HD404849 Series

Standby

Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop

Yes

(SBY
only)

Watch

Oscillator: Stop
Suboscillator: Active
Peripheral clocks: Stop
All other clocks: Stop

Restart

processor clocks

Reset MCU

Execute

next instruction

Accept interrupt

Restart

processor clocks

Yes

IF = 1,

IM = 0, and

IE = 1?

IF0 ·

IM0

= 1?

IF1 ·

IM1

= 1?

IFTA ·

IMTA

= 1?

IFTB ·

IMTB

+ IF2 ·

IM2

= 1?

IFTC ·

IMTC

+ IF3 ·

IM3

= 1?

IFTD ·

IMTD

= 1?

Yes

IFAD ·

IMAD + IFS ·

IMS

= 1?

Stop

Oscillator: Stop
Suboscillator: Active/Stop
Peripheral clocks: Stop
All other clocks: Stop

RESET

= 0?

STOPC

= 0?

RAME = 1

RAME = 0

Yes

Execute

next instruction

(SBY
only)

RESET

= 0?

Figure 15 MCU Operation Flowchart

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC

and OSC

oscillator stops. The X1 and X2

oscillator can be selected to operate by setting bit 3 of the system clock select register (SSR: $029;
operating: SSR3 = 0, stop: SSR3 = 1) (figure 26). The MCU enters stop mode if the STOP instruction is
executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure
41).

Stop mode is terminated by a

RESET input or a STOPC input as shown in figure 16. RESET or STOPC

must be applied for at least one t

to stabilize oscillation (refer to the AC Characteristics section). When

the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,

HD404849 Series

but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.

Stop mode

Oscillator

Internal

clock

STOP instruction execution

res

(stabilization period)

res

RESET

STOPC

Figure 16 Timing of Stop Mode Cancellation

Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator and the LCD
function operate, but other function operations stop. Therefore, the power dissipation in this mode is the
second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the
OSC

and OSC

oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the

STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is
executed in subactive mode.

Watch mode is terminated by a

RESET input or a timer-A/INT

interrupt request. For details of

RESET

input, refer to the Stop Mode section. When terminated by a timer-A/

INT

interrupt request, the MCU

enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated,
the time required to enter active mode is t

for a timer A interrupt, and T

(where T + t

< T

< 2T + t

)

for an INT

interrupt, as shown in figures 17 and 18.

Operation during mode transition is the same as that at standby mode cancellation (figure 15).

HD404849 Series

Active mode

Watch mode

Active mode

Oscillation
stabilization period

Interrupt strobe

INT

Interrupt request
generation

(During the transition
from watch mode to
active mode only)

T:
t :

Interrupt frame length
Oscillation stabilization period

Figure 17 Interrupt Frame

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1

MIS0

0.24414 ms

0.12207 ms

0.24414 ms

7.8125 ms

31.25 ms

Oscillation circuit conditions

External clock input

Ceramic oscillator

Crystal oscillator

15.625 ms

62.5 ms

Not used

Notes: 1.

The values of T and t

are applied when a 32.768-kHz crystal oscillator is used.

The value is applied only when direct transfer operation is used.

Buffer control.

Refer to figure 38.

MIS3

MIS2

Figure 18 Miscellaneous Register (MIS)

Subactive Mode: The OSC

and OSC

oscillator stops and the MCU operates with a clock generated by

the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because
the operating clock slows down, power dissipation is reduced, next least to watch mode.

HD404849 Series

The CPU instruction execution speed can be selected as 244

s or 122

s by setting bit 2 (SSR2) of the

system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the
value is changed in subactive mode, the MCU may malfunction.

When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).

Interrupt Frame: In watch and subactive modes,

CLK

is applied to timer A and the

INT

circuit. Prescaler

W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three
interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18).

In watch and subactive modes, a timer-A/

INT

interrupt is generated synchronously with the interrupt

frame. An interrupt request is generated synchronously with an interrupt strobe except during transition to
active mode. The falling edge of the

INT

signal is input asynchronously with the interrupt frame timing,

but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An
overflow and interrupt request in timer A is generated synchronously with the interrupt strobe.

Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on
flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described
below:

Set LSON to 0 and DTON to 1 in subactive mode.

Execute the STOP or SBY instruction.

The MCU automatically enters active mode from subactive mode after waiting for the MCU internal
processing time and oscillation stabilization time (figure 19).

Notes: 1. The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active

mode.

2. The transition time (T

) from subactive mode to active mode:

< T

< T + t

Subactive mode

Interrupt strobe

Direct transfer
completion timing

MCU internal
processing period

Oscillation
stabilization
time

Active mode

T:
t :

STOP/SBY instruction execution

(Set LSON = 0, DTON = 1)

Interrupt frame length
Oscillation stabilization period

Figure 19 Direct Transition Timing

HD404849 Series

Stop Mode Cancellation by

STOPC : The MCU enters active mode from stop mode by inputting STOPC

RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the

program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by
STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC,
RAME = 1.

RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored

in other modes. Therefore, when the program needs to confirm that stop mode has been cancelled by
STOPC (for example, when the RAM contents before entering stop mode are used after transition to active
mode), execute the TEST instruction on the RAM enable flag (RAME) at the beginning of the program.

MCU Operation Sequence: The MCU operates in the sequence shown in figures 20 to 22. It is reset by
an asynchronous

RESET input, regardless of its status.

The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.

Power on

RESET

= 0 ?

RAME = 0

Reset MCU

MCU

operation

cycle

Yes

Figure 20 MCU Operating Sequence (Power On)

HD404849 Series

Low-power mode

operation cycle

IF = 1 and

IM = 0?

Hardware NOP

execution

PC Next

Iocation

MCU operation

cycle

Standby/watch

mode

IF = 1 and

IM = 0?

Hardware NOP

execution

PC Next

Iocation

Instruction

execution

Stop mode

Yes

For IF and IM operation, refer to figure 15.

STOPC

= 0?

RAME = 1

Reset MCU

Yes

Figure 22 MCU Operating Sequence (Low-Power Mode Operation)

Notes on Use:

When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of
INT

is shorter than the interrupt frame,

INT

will not be detected. Also, if the low level period after the

falling edge of

INT

is shorter than the interrupt frame,

INT

will not be detected.

Edge detection is shown in figure 23. The level of the

INT

signal is sampled by a sampling clock.

When this sampled value changes from high to low, a falling edge is detected.

HD404849 Series

Internal Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 25. As shown in table 22, a ceramic or
crystal oscillator can be connected to OSC

and OSC

, and a 32.768-kHz oscillator can be connected to X1

and X2. The system oscillator can also be operated by an external clock. Bit 1 (SSR1) of the system clock
select register (SSR: $029) must be set according to the fre quency of the oscillator connected to OSC

and

OSC

(figure 26).

Note:

If the system clock select register (SSR: $029) setting does not match the oscillator frequency,

subsystems using the 32.768-kHz oscillation will malfunction.

OSC

System

oscillator

Sub-

system

oscillator

1/4

division

circuit

Timing

generator

circuit

System

clock

selection

CPU with ROM,

RAM, registers,

flags, and I/O

Peripheral

function

interrupt

Time-base

interrupt

Time-base

clock

selection

1/8 or 1/4

division

circuit

Timing

generator

circuit

Timing

generator

circuit

1/8

division

circuit

SUB

subcyc

LSON

TMA3

cyc

OSC

Wcyc

CPU

PER

CLK

Note:

1/8 or 1/4 division ratio can be selected by setting bit 2 of the system
clock select register (SSR: $029).

Figure 25 Clock Generation Circuit

HD404849 Series

Table 22 Oscillator Circuit Examples

Circuit Configuration

Circuit Constants

External clock
operation

External
oscillator

OSC

Open

OSC

Ceramic
oscillator
(OSC

, OSC

)

OSC

Ceramic

oscillator

GND

Ceramic oscillator:
CSA4.00MG (Murata)
R

= 1 M

20%

= C

= 30 pF

20%

Crystal oscillator
(OSC

,OSC

)

OSC

Crystal

oscillator

GND

= 1 M

20%

= C

= 10 to 22 pF

20%

Equivalent circuit of crystal
oscillator shown at left.
C

: 7 pF max

: 100

max

Crystal oscillator
(X1, X2)

Crystal

oscillator

GND

Crystal: 32.768 kHz: MX38T
(Nippon Denpa)
C

= C

= 20 pF

20%

: 14 k

: 1.5 pF

Notes: 1. Circuit constants differ by the different types of crystal oscillators and ceramic oscillators, and

with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine
the circuit parameters.

2. The wiring between the OSC

and OSC

pins (X1 and X2 pins) and the other elements should be

as short as possible, and must not cross other wiring. Refer to figure 27.

3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to V

and leave the X2 pin open.

HD404849 Series

Input/Output

The MCU has 33 input/output pins (D

, R0R3, R6, and R7) and two input pins (D

, D

). The

features are described below.

Nine pins (D

) are high-current input/output pins.

The D

, D

, R0

, R1R3, R6, and R7 input/output pins are multiplexed with peripheral function

pins such as for the timers or serial interface. For these pins, the peripheral function setting is done
prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin
function and input/output selection are automatically switched according to the setting.

Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.

Peripheral function output pins are CMOS output pins. Only the R2

/SO pin can be set to NMOS open-

drain output by software.

In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. The data
control register (DCD, DCR) is also reset, so input/output pins go to the high-impedance state.

Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by
software.

I/O buffer configuration is shown in figure 28, programmable I/O circuits are listed in table 23, and I/O pin
circuit types are shown in table 24.

Table 23 Programmable I/O Circuits

MIS3 (bit 3 of MIS)

DCD, DCR

PDR

CMOS buffer

PMOS

NMOS

Pull-up MOS

Note:

-- indicates off status.

HD404849 Series

Table 24 Circuit Configurations of I/O Pins

I/O Pin Type

Circuit

Pins

Input/output
pins

Pull-up control signal

Buffer control

signal

Output data

Input data

MIS3

DCD, DCR

PDR

Input control signal

Pull-up control signal

Buffer control

signal

Output data

Input data

MIS3

DCR

PDR

Input control signal

MIS2

Input pins

Input data

Input control signal

, D

Peripheral
function pins

Input/
output
pins

Pull-up control signal

Output data

Input data

MIS3

SCK

Output
pins

Pull-up control signal

PMOS control

signal

Output data

MIS3

MIS2

Pull-up control signal

Output data

MIS3

TOB, TOC,
TOD

HD404849 Series

I/O Pin Type

Circuit

Pins

Peripheral
function pins

Input
pins

Input data

INT

STOPC

INT

STOPC

HLT

MIS3

PDR

SI, etc.

SI,

INT

, INT

INT

EVNB

EVND

A/D input

Input control

HLT

MIS3

PDR

A/D input

Input control

Note: The MCU is reset in stop mode, and an peripheral function selections are cancelled. The I/O control

D Port: Consist of nine input/output pins and two input pins addressed by one bit. D

are high-current

I/O pins, and D

and D

are input-only pins.

Pins D

are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. All pins of the D port are tested by the TD
and TDD instructions.

The on/off statuses of the output buffers are controlled by D port data control registers (DCD0DCD2:
$02C$02E) that are mapped to memory addresses (figure 29).

Pins D

and D

are multiplexed with peripheral function pins

STOPC and I

, respectively. The

peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 34).

R Ports: 24 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR
instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data
register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R
port data control registers (DCR0DCR3, DCR6, DCR7: $030$033, $036, $037) that are mapped to
memory addresses (figure 29).

HD404849 Series

Pins R0

are multiplexed with peripheral pins

I NT

INT

, respectively. The peripheral function modes

of these pins are selected by bits 02 (PMRB0PMRB2) of port mode register B (PMRB: $024) (figure
30).

Pins R1

are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral

function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2
(TMB2: $013), bits 02 (TMC20TMC22) of timer mode register C2 (TMC2: $014), and bits 03
(TMD20TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 31, and 33).

Pins R1

and R2

are multiplexed with peripheral pins

EVNB and EVND, respectively. The peripheral

function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C
(PMRC: $025) (figure 34).

Pins R2

are multiplexed with peripheral pins

SCK, SI, and SO, respectively. The peripheral function

modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and
1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 35 and 36.

Ports R6 and R7 are multiplexed with segment pins SEG13SEG20, respectively. The function modes of
these pins can be selected in 4-pin units by setting LCD output register 3 (LOR3: $01F) (figure 37).

HD404849 Series

Bit

Initial value

Read/Write

Bit name

DCD03,

DCD02,

DCD00,

DCD01,

DCD0, DCD1

Data control register

(DCD0 to DCD2: $02C to $02E)
(DCR0 to DCR7: $030 to $037)

DCD13

DCD12

DCD10

DCD11

Bit

Initial value

Read/Write

Bit name

Not used

DCD20

Not used

DCD2

Bit

Initial value

Read/Write

Bit name

DCR03

DCR02

DCR00

DCR01

DCR0 to DCR3, DCR6, DCR7

DCR33

DCR32

DCR30

DCR31

DCR73

DCR72

DCR70

DCR71

DCR63 DCR62

DCR60

DCR61

Correspondence between ports and DCD/DCR bits

DCD0

DCD1

DCD2

DCR0

DCR1

DCR2

DCR3

DCR6

DCR7

Off (high-impedance)

All Bits

CMOS Buffer On/Off Selection

Register Name

Bit 3

Bit 2

Bit 1

Bit 0

Figure 29 Data Control Registers (DCD, DCR)

HD404849 Series

Bit

Initial value

Read/Write

Bit name

Not used

PMRB2

PMRB0

PMRB1

Port mode register B (PMRB: $024)

PMRB2

/INT

mode selection

INT

PMRB0

INT

mode selection

INT

PMRB1

/INT

mode selection

INT

Figure 30 Port Mode Register B (PMRB)

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMC22

R/W

TMC20

R/W

TMC21

Timer mode register C2 (TMC2: $014)

TMC22

TMC20

TMC21

/TOC mode selection

TOC

port

Toggle output

0 output

1 output

Inhibited

PWM output

Figure 31 Timer Mode Register C2 (TMC2)

HD404849 Series

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMB20

R/W

TMB21

Timer mode register B2 (TMB2: $013)

TMB21

TMB20

/TOB mode selection

TOB

port

Toggle output

0 output

1 output

Figure 32 Timer Mode Register B2 (TMB2)

Bit

Initial value

Read/Write

Bit name

R/W

TMD23

R/W

TMD22

R/W

TMD20

R/W

TMD21

Timer mode register D2 (TMD2: $015)

TMD22

TMD20

TMD21

/TOD mode selection

TOD

port

Toggle output

0 output

1 output

Inhibited

PWM output

Input capture (R1

port)

TMD23

Don't care

Figure 33 Timer Mode Register D2 (TMD2)

HD404849 Series

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

PMRC0

PMRC1

Port mode register C (PMRC: $025)

PMRC0

EVNB

mode selection

EVNB

PMRC2

STOPC

PMRC3

INT

mode selection

INT

STOPC

mode selection

Note:

PMRC2 is reset to 0 only by

RESET

input. When

STOPC

is input in stop

mode, PMRC2 is not reset but retains its value.

PMRC1

/EVND mode selection

EVND

Figure 34 Port Mode Register C (PMRC)

Bit

Initial value

Read/Write

Bit name

SMRA3

SMRA2

SMRA0

SMRA1

Serial mode register A (SMRA: $005)

Output

Input

Prescaler

System clock

External clock

2048

512

128

Prescaler
division
ratio

SMRA2

SMRA0

SMRA1

Clock source

SMRA3

SCK

mode selection

SCK

Figure 35 Serial Mode Register A (SMRA)

HD404849 Series

Bit

Initial value

Read/Write

Bit name

Not used

PMRA0

PMRA1

PMRA0

/SO mode selection

Port mode register A (PMRA: $004)

PMRA1

/SI mode selection

Figure 36 Port Mode Register A (PMRA)

Bit

Initial value

Read/Write

Bit name

Not used

LOR32

Not used

LOR31

LCD output register 3 (LOR3: $01F)

LOR31

R6/SEG13SEG16 mode selection

SEG13SEG16

LOR32

R7/SEG17SEG20 mode selection

SEG17SEG20

Figure 37 LCD Output Register 3 (LOR3)

Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin other than input-only pins D

and D

. The on/off status of all these transistors is

controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual
transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off
control of that pin alone (table 23 and figure 38).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

HD404849 Series

Prescalers

The MCU has two prescalers, S and W.

The prescaler operating conditions are listed in table 25, and the prescalers output supply is shown in figure
39. The timer AD input clocks except external events, the serial transmit clock except the external clock,
and the LCD controller/driver operating clock are selected from the prescaler outputs, depending on
corresponding mode registers.

Prescaler Operation

Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and
at MCU reset.

Prescaler W: Five-bit counter that inputs the divided X1 input clock signal (32-kHz crystal oscillation).
After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by
software.

Table 25 Prescaler Operating Conditions

Prescaler

Input Clock

Reset Conditions

Stop Conditions

Prescaler S

System clock (in active and standby
mode), subsystem clock (in subactive
mode)

MCU reset

MCU reset, stop mode,
watch mode

Prescaler W

32-kHz crystal oscillation

MCU reset, software

MCU reset, stop mode

Subsystem

clock

Prescaler W

LCD

Timer A

Timer B

Timer C

Timer D

System

clock

Prescaler S

Serial

interface

Clock

selector

/4 or f

Figure 39 Prescaler Output Supply

HD404849 Series

Timers

The MCU has four timer/counters (A to D).

Timer A: Free-running timer

Timer B: Multifunction timer

Timer C: Multifunction timer

Timer D: Multifunction timer

Timer A is an 8-bit free-running timer. Timers BD are 8-bit multifunction timers, whose functions are
listed in table 26. The operating modes are selected by software.

Table 26 Timer Functions

Functions

Timer A

Timer B

Timer C

Timer D

Clock source

Prescaler S

Available

Prescaler W

Available

External event

Available

Timer functions

Free-running

Available

Time-base

Available

Event counter

Available

Reload

Available

Watchdog

Available

Input capture

Available

Timer outputs

Toggle

Available

0 output

Available

1 output

Available

PWM

Available

Note:

-- implies not available.

Timer A

Timer A Functions: Timer A has the following functions.

Free-running timer

Clock time-base

The block diagram of timer A is shown in figure 40.

HD404849 Series

1/4

1/2

32.768-kHz
oscillator

System
clock

Prescaler W

(PSW)

Selector

Prescaler S (PSS)

Selector

Internal data bus

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

2 f

1/2 tw

cyc

PER

128

512

1024

2048

÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷

÷ ÷ ÷ ÷

Figure 40 Block Diagram of Timer A

Timer A Operations:

Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).

Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.

Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer
mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A
generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case,
prescaler W and timer A can be reset to $00 by software.

Registers for Timer A Operation: Timer A operating modes are set by the following registers.

Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode
and input clock source as shown in figure 41.

HD404849 Series

Bit

Initial value

Read/Write

Bit name

TMA3

TMA2

TMA0

TMA1

Timer mode register A (TMA: $008)

PSS

PSW

Operating mode

Timer A mode

TMA3

TMA1

TMA2

TMA0

Source
prescaler

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

Input clock
frequency

32t

Wcyc

16t

Wcyc

1/2t

Wcyc

Time-base
mode

Inhibited

PSW and TCA reset

Don't

care

Note: 1.

2.
3.

Wcyc

= 244.14

s (when a 32.768-kHz crystal oscillator is used)

Timer counter overflow output period (seconds) = input clock period (seconds) 256.
If PSW or TCA reset is selected while the LCD is operating, LCD operation halts
(power switch goes off and all SEG and COM pins are grounded).
When an LCD is connected for display, the PSW and TCA reset periods must be
set in the program to the minimum.
The division ratio must not be modified during time-base mode operation,
otherwise an overflow cycle error will occur.

Figure 41 Timer Mode Register A (TMA)

HD404849 Series

Timer B

Timer B Functions: Timer B has the following functions.

Free-running/reload timer

External event counter

Timer output operation (toggle, 0, and 1 outputs)

The block diagram of timer B is shown in figure 42.

System
clock

EVNB

TOB

Timer output control

Selector

Prescaler S (PSS)

Clock

Timer read register BU (TRBU)

Timer read
register BL

(TRBL)

Timer counter B

(TCB)

Timer write
register BU

(TWBU)

Timer write

(TWBL)

Timer mode

(TMB1)

Timer mode

(TMB2)

Timer B interrupt

request flag

(IFTB)

PER

Internal data bus

128

512

2048

÷ ÷ ÷ ÷ ÷ ÷

Free-running/
Reload control

Overflow

Timer output

control logic

Figure 42 Block Diagram of Timer B

HD404849 Series

Timer B Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).

Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer B is used as an external event counter by selecting external
event input as the input clock source. In this case, pin R1

EVNB must be set to EVNB by port mode

Timer B is incremented by one at each falling edge of signals input to pin

EVNB. The other operations

are basically the same as the free-running/reload timer operation.

Timer output operation: The following three output modes can be selected for timer B by setting timer
mode register B2 (TMB2: $013).

Toggle

0 output

1 output

By selecting the timer output mode, pin R1

/TOB is set to TOB. The output from TOB is reset low by

MCU reset.

Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input

after timer B has reached $FF. By using this function and reload timer function, clock signals can
be output at a required frequency for the buzzer. The output waveform is shown in figure 43 (1).

0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after

timer B has reached $FF. Note that this function must be used only when the output level is high.

1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer

B has reached $FF. Note that this function must be used only when the output level is low.

HD404849 Series

(N + 1)

256

(256 N)

TMC13 = 0

The waveform is always fixed low when N = $FF.
T:

TMC13 = 1

Input clock period to counter (the clock source and frequency
division ratio are controlled in timer mode registers B1, C1, and D1)
The value in timer write registers C and D

Note:

TMD13 = 0

(free-running timer setting)

256 clock cycles

Free-running timer

(1) Toggle output waveform (timers B, C, and D)

(2) PWM output waveform (timers C and D)

(256 N)

clock cycles

(256 N)

clock cycles

Reload timer

TMD13 = 1

(reload timer setting)

Figure 43 Timer Output Waveform

Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.

Timer mode register B1 (TMB1: $009)

Timer mode register B2 (TMB2: $013)

Timer write register B (TWBL: $00A, TWBU: $00B)

Timer read register B (TRBL: $00A, TRBU: $00B)

Port mode register C (PMRC: $025)

Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and prescaler division ratio as shown in figure 44. It is reset to $0 by
MCU reset.

HD404849 Series

Bit

Initial value

Read/Write

Bit name

TMB13

TMB12

TMB10

TMB11

Timer mode register B1 (TMB1: $009)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMB12

TMB10

TMB11

Input clock period and input
clock source

EVNB

(external event input)

TMB13

Free-running/reload
timer selection

Free-running timer

Reload timer

Figure 44 Timer Mode Register B1 (TMB1)

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. A timer B initialization by writing to timer write
register B (TWBL: $00A, TWBU: $00B) must be programmed to occur after a mode change becomes
valid.

Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output
mode as shown in figure 45. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMB20

R/W

TMB21

Timer mode register B2 (TMB2: $013)

TMB21

TMB20

/TOB mode selection

TOB

port

Toggle output

0 output

1 output

Figure 45 Timer Mode Register B2 (TMB2)

Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of a lower digit
(TWBL) and upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value cannot be guaranteed. See figures 46 and 47.

HD404849 Series

Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.

Bit

Initial value

Read/Write

Bit name

TWBL3

TWBL2

TWBL0

TWBL1

Timer write register B (lower digit) (TWBL: $00A)

Figure 46 Timer Write Register B Lower Digit (TWBL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWBU3

Undefined

TWBU2

Undefined

TWBU0

Undefined

TWBU1

Timer write register B (upper digit) (TWBU: $00B)

Figure 47 Timer Write Register B Upper Digit (TWBU)

Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of a lower digit
(TRBL) and upper digit (TRBU) that holds the count of the timer B upper digit. See figures 48 and 49.

The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is
obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by
reading TRBL, the count of timer B when TRBU was read can be obtained.

Bit

Initial value

Read/Write

Bit name

Undefined

TRBL3

Undefined

TRBL2

Undefined

TRBL0

Undefined

TRBL1

Timer read register B (lower digit) (TRBL: $00A)

Figure 48 Timer Read Register B Lower Digit (TRBL)

HD404849 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TRBU3

Undefined

TRBU2

Undefined

TRBU0

Undefined

TRBU1

Timer read register B (upper digit) (TRBU: $00B)

Figure 49 Timer Read Register B Upper Digit (TRBU)

Port mode register C (PMRC: $025): Write-only register that selects R1

EVNB pin function as shown

in figure 50. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

PMRC0

PMRC1

/EVND mode selection

EVND

Port mode register C (PMRC: $025)

PMRC0

EVNB

mode selection

EVNB

PMRC3

INT

mode selection

INT

PMRC2

STOPC

mode selection

STOPC

Figure 50 Port Mode Register C (PMRC)

Timer C

Timer C Functions: Timer C has the following functions.

Free-running/reload timer

Watchdog timer

Timer output operation (toggle, 0, 1, and PWM outputs)

The block diagram of timer C is shown in figure 51.

HD404849 Series

Timer C Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).

Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program runaway can be controlled by
initializing timer C by software before it reaches $FF.

Timer output operation: The following four output modes can be selected for timer C by setting timer
mode register C2 (TMC2: $014).

Toggle

0 output

1 output

PWM output

By selecting the timer output mode, pin R1

/TOC is set to TOC. The output from TOC is reset low by

MCU reset.

Toggle output: The operation is basically the same as that of timer-B's toggle output.

0 output: The operation is basically the same as that of timer-B's 0 output.

1 output: The operation is basically the same as that of timer-B's 1 output.

PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output

function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 43 (2).

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.

Timer mode register C1 (TMC1: $00D)

Timer mode register C2 (TMC2: $014)

Timer write register C (TWCL: $00E, TWCU: $00F)

Timer read register C (TRCL: $00E, TRCU: $00F)

Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and prescaler division ratio as shown in figure 52. It is reset to $0 by
MCU reset.

HD404849 Series

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C1 write instruction. A timer C initialization by writing to timer write
register C (TWCL: $00E, TWCU: $00F) must be programmed to occur after a mode change becomes
valid.

Bit

Initial value

Read/Write

Bit name

TMC13

TMC12

TMC10

TMC11

Timer mode register C1 (TMC1: $00D)

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

TMC12

TMC10

TMC11

TMC13

Free-running/reload timer selection

Free-running timer

Reload timer

Input clock period

Figure 52 Timer Mode Register C1 (TMC1)

Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output
mode as shown in figure 53. It is reset to $0 by MCU reset.

HD404849 Series

Bit

Initial value

Read/Write

Bit name

Not used

R/W

TMC22

R/W

TMC20

R/W

TMC21

Timer mode register C2 (TMC2: $014)

TMC22

TMC21

/TOC mode selection

TOC

port

Toggle output

0 output

1 output

Inhibited

PWM output

TMC20

Figure 53 Timer Mode Register C2 (TMC2)

Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit
(TWCL) and upper digit (TWCU). See figures 54 and 55. The operation of timer write register C is
basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).

Bit

Initial value

Read/Write

Bit name

TWCL3

TWCL2

TWCL0

TWCL1

Timer write register C (lower digit) (TWCL: $00E)

Figure 54 Timer Write Register C Lower Digit (TWCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWCU3

Undefined

TWCU2

Undefined

TWCU0

Undefined

TWCU1

Timer write register C (upper digit) (TWCU: $00F)

Figure 55 Timer Write Register C Upper Digit (TWCU)

HD404849 Series

Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit
(TRCL) and upper digit (TRCU) that holds the count of the timer C upper digit. See figures 56 and 57.
The operation of timer read register C is basically the same as that of timer read register B (TRBL:
$00A, TRBU: $00B).

Bit

Initial value

Read/Write

Bit name

Undefined

TRCL3

Undefined

TRCL2

Undefined

TRCL0

Undefined

TRCL1

Timer read register C (lower digit) (TRCL: $00E)

Figure 56 Timer Read Register C Lower Digit (TRCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRCU3

Undefined

TRCU2

Undefined

TRCU0

Undefined

TRCU1

Timer read register C (upper digit) (TRCU: $00F)

Figure 57 Timer Read Register C Upper Digit (TRCU)

Timer D

Timer D Functions: Timer D has the following functions.

Free-running/reload timer

External event counter

Timer output operation (toggle, 0, 1, and PWM outputs)

Input capture timer

The block diagram for each operation mode of timer D is shown in figures 58-1 and 58-2.

HD404849 Series

Timer D Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register D1 (TMD1: $010).

Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by
software and incremented by one at each clock input. If an input clock is applied to timer D after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is
initialized to its initial value set in timer write register D; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer D is used as an external event counter by selecting the
external event input as an input clock source. In this case, pin R2

/EVND must be set to EVND by port

mode register C (PMRC: $025).

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and
falling edges detection is selected, the time between the falling edge and rising edge of input signals
must be 2t

cyc

or longer.

Timer D is incremented by one at each detection edge selected by detection edge select register 2
(ESR2: $027). The other operations are basically the same as the free-running/reload timer operation.

Timer output operation: The following four output modes can be selected for timer D by setting timer
mode register D2 (TMD2: $015).

Toggle

0 output

1 output

PWM output

By selecting the timer output mode, pin R1

/TOD is set to TOD. The output from TOD is reset low by

MCU reset.

Toggle output: The operation is basically the same as that of timer-B's toggle output.

0 output: The operation is basically the same as that of timer-B's 0 output.

1 output: The operation is basically the same as that of timer-B's 1 output.

PWM output: The operation is basically the same as that of timer-C's PWM output.

Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVND.

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by detection edge select register 2 (ESR2: $027).

When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.

HD404849 Series

By selecting the input capture operation, pin R1

/TOD is set to R1

and timer D is reset to $00.

Registers for Timer D Operation: By using the following registers, timer D operation modes are selected
and the timer D count is read and written.

Timer mode register D1 (TMD1: $010)

Timer mode register D2 (TMD2: $015)

Timer write register D (TWDL: $011, TWDU: $012)

Timer read register D (TRDL: $011, TRDU: $012)

Port mode register C (PMRC: $025)

Detection edge select register 2 (ESR2: $027)

Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and prescaler division ratio as shown in figure 59. It is reset to $0 by
MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. A timer D initialization by writing to
timer write register D (TWDL: $011, TWDU: $012) must be programmed to occur after a mode change
becomes valid.

When selecting the input capture timer operation, select the internal clock as the input clock source.

HD404849 Series

Bit

Initial value

Read/Write

Bit name

R/W

TMD23

R/W

TMD22

R/W

TMD20

R/W

TMD21

Timer mode register D2 (TMD2: $015)

TMD22

TMD20

TMD21

/TOD mode selection

TOD

port

Toggle output

0 output

1 output

Inhibited

PWM output

Input capture (R1

port)

TMD23

Don't care

Figure 60 Timer Mode Register D2 (TMD2)

Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit
(TWDL) and upper digit (TWDU). See figures 61 and 62. The operation of timer write register D is
basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).

Bit

Initial value

Read/Write

Bit name

TWDL3

TWDL2

TWDL0

TWDL1

Timer write register D (lower digit) (TWDL: $011)

Figure 61 Timer Write Register D Lower Digit (TWDL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWDU3

Undefined

TWDU2

Undefined

TWDU0

Undefined

TWDU1

Timer write register D (upper digit) (TWDU: $012)

Figure 62 Timer Write Register D Upper Digit (TWDU)

HD404849 Series

Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit
(TRDL) and upper digit (TRDU). See figures 63 and 64. The operation of timer read register D is
basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).

When the input capture timer operation is selected and if the count of timer D is read after a trigger is
input, either the lower or upper digit can be read first.

Bit

Initial value

Read/Write

Bit name

Undefined

TRDL3

Undefined

TRDL2

Undefined

TRDL0

Undefined

TRDL1

Timer read register D (lower digit) (TRDL: $011)

Figure 63 Timer Read Register D Lower Digit (TRDL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRDU3

Undefined

TRDU2

Undefined

TRDU0

Timer read register D (upper digit) (TRDU: $012)

Undefined

TRDU1

Figure 64 Timer Read Register D Upper Digit (TRDU)

Port mode register C (PMRC: $025): Write-only register that selects R2

/EVND pin function as shown

in figure 50. It is reset to $0 by MCU reset.

Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of
signals input to pin EVND as shown in figure 65. It is reset to $0 by MCU reset.

HD404849 Series

Bit

Initial value

Read/Write

Bit name

ESR23

ESR22

Not used

Detection edge register 2 (ESR2: $027)

ESR23

ESR22

EVND detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection

Note: Both falling and rising edges are detected.

Figure 65 Detection Edge Select Register 2 (ESR2)

Notes on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 27. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

HD404849 Series

Internal data bus

128

512

2048

Serial mode

(SMRB)

SCK

Selector

System

clock

PER

Prescaler S (PSS)

Idle

controller

Serial mode

(SMRA)

Clock

Serial data

Serial interrupt

request flag

(IFS)

Selector

1/2

Octal

counter (OC)

I/O

controller

Transfer
control
signal

Figure 66 Block Diagram of Serial Interface

Serial Interface Operation

Selecting and Changing the Operating Mode: Table 28 lists the serial interface's operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial
mode register A (SMRA: $005) settings; to change the operating mode, always initialize the serial interface
internally by writing data to serial mode register A. Note that the serial interface is initialized by writing
data to serial mode register A. Refer to the following Serial Mode Register A section for details.

Table 28 Serial Interface Operating Modes

SMRA

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Clock continuous output mode

Transmit mode

Receive mode

Transmit/receive mode

HD404849 Series

Pin Setting: The R2

SCK pin is controlled by writing data to serial mode register A (SMRA: $005). The

/SI and R2

/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the

following Registers for Serial Interface section for details.

Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register A
(SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following Registers for Serial
Interface section for details.

Data Setting: Serial data is set by writing data to the serial data register (SRL: $006, SRU, $007).
Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the
transmit clock and is input from or output to an external system.

The output level of the SO pin remains unsettled until the first data is output after MCU reset, or until the
output level control in idle states is performed.

Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to
000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $023, bit 2) is set, and the transfer stops.

When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t

cyc

to 8192t

cyc

by setting bits 0 to 2 (SMRA0 SMRA2) of serial mode register A (SMRA: $005) and bit 0

(SMRB0) of serial mode register B (SMRB: $028) as listed in table 29.

Table 29 Serial Transmit Clock (Prescaler Output)

SMRB

SMRA

Bit 0

Bit 2

Bit 1

Bit 0

Prescaler Division Ratio

Transmit Clock Frequency

2048

4096t

cyc

512

1024t

cyc

128

256t

cyc

64t

cyc

16t

cyc

4096

8192t

cyc

1024

2048t

cyc

256

512t

cyc

128t

cyc

32t

cyc

HD404849 Series

Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 67.

STS wait state

Transmit clock wait state

Transfer state

Continuous clock output state (only in internal clock mode)

STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.

Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts the serial data register, and puts the serial interface in transfer state.
However, note that if clock continuous output mode is selected in internal clock mode, the serial
interface does not enter transfer state but enters clock continuous output state (17).

The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04,
14) in transmit clock wait state.

Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge
of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction
sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is
executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait
state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode.
In internal clock mode, the transmit clock stops after outputting eight clocks.

In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.

If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 2) is set
by the octal counter that is reset to 000.

Clock continuous output state (only in internal clock mode): Clock continuous output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the

SCK pin.

When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters clock continuous output state.
If serial mode register A (SMRA: $005) is written to in clock continuous output mode (18), STS wait
state is entered.

HD404849 Series

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

MCU reset

SMRA write

STS instruction

Transmit clock

8 transmit clocks

STS instruction (IFS 1)

SMRA write (IFS 1)

External clock mode

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

SMRA write

STS instruction

Transmit clock

STS instruction (IFS 1)

8 transmit clocks

Internal clock mode

Clock continuous output state

(PMRA 0, 1 = 00)

SMRA write

Transmit clock

Note: Refer to the Operating States section for the corresponding encircled numbers.

MCU reset

SMRA write (IFS 1)

Figure 67 Serial Interface State Transitions

Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB:
$028) to 0 or 1. The output level control example is shown in figure 68. Note that the output level cannot
be controlled in transfer state.

HD404849 Series

State

MCU reset

PMRA write

SMRA write

SMRB write

SRL, SRU write

STS instruction

SCK

pin (input)

SO pin

IFS

STS wait state

Transmit clock
wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

External clock selection

Output level control in

idle states

Dummy write for
state transition

Output level control in

idle states

Data write for transmission

Undefined

LSB

MSB

Flag reset at transfer completion

External clock mode

State

MCU reset

PMRA write

SMRA write

SMRB write

SRL, SRU write

STS instruction

SCK

pin (output)

SO pin

IFS

STS wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

Internal clock selection

Output level control in

idle states

Data write for transmission

Output level control in

idle states

Undefined

LSB

MSB

Flag reset at transfer completion

Internal clock mode

Figure 68 Example of Serial Interface Operation Sequence

HD404849 Series

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 69.

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to serial mode
register A (SMRA: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.

HD404849 Series

Notes on Use:

Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register A (SMRA: $005) again.

Setting the serial interrupt request flag (IFS: $023, bit 2): If the state is changed from transfer to another
by writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register A write or STS instruction execution must be programmed to be executed after
confirming that the

SCK pin is at 1, that is, after executing the input instruction to port R2.

Registers for Serial Interface

The serial interface operation is selected, and serial data is read and written by the following registers.

Serial Mode Register A (SMRA: $005)

Serial Mode Register B (SMRB: $028)

Serial Data Register (SRL: $006, SRU: $007)

Port Mode Register A (PMRA: $004)

Miscellaneous Register (MIS: $00C)

Serial Mode Register A (SMRA: $005): This register has the following functions (figure 70).

SCK pin function selection

Transfer clock selection

Prescaler division ratio selection

Serial interface initialization

Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.

A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to
the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is
performed during data transfer, the data transfer is discontinued and the serial interrupt request flag (IFS:
$023, bit 2) is set.

Written data is valid from the second instruction execution cycle after a write operation, so the STS
instruction must be executed at least two cycles after a write operation.

HD404849 Series

Bit

Initial value

Read/Write

Bit name

SMRA3

SMRA2

SMRA0

SMRA1

Serial mode register A (SMRA: $005)

SMRA2

SMRA0

SMRA1

SMRA3

/SCK

mode selection

SCK

Output

Input

Clock source

Prescaler
division ratio

Refer to
table 29

SCK

Prescaler

System clock

External clock

Figure 70 Serial Mode Register A (SMRA)

Serial Mode Register B (SMRB: $028): This register has the following functions (figure 71).

Prescaler division ratio selection

Output level control in idle states

Serial mode register B (SMRB: $028) is a 2-bit write-only register. It cannot be written during data
transfer.

By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can
be reset to 0 by MCU reset. Bit 1 (SMRB1) is used to control the output level of the SO pin in idle states.
The output level changes at the same time that SMRB1 is written to.

HD404849 Series

Bit

Initial value

Read/Write

Bit name

Not used

SMRB0

Undefined

SMRB1

SMRB0

Transmit clock division ratio

Prescaler output divided by 2

Prescaler output divided by 4

Serial mode register B (SMRB: $028)

SMRB1

Output level control in idle states

Low level

High level

Figure 71 Serial Mode Register B (SMRB)

Serial Data Register (SRL: $006, SRU: $007): The serial data register configuration is shown in figures
72 and 73. This register has the following functions.

Transmission data write and shift

Receive data shift and read

Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 74.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR3

Undefined

R/W

SR2

Undefined

R/W

SR0

Undefined

R/W

SR1

Serial data register (lower digit) (SRL: $006)

Figure 72 Serial Data Register (SRL)

HD404849 Series

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR7

Undefined

R/W

SR6

Undefined

R/W

SR4

Undefined

R/W

SR5

Serial data register (upper digit) (SRU: $007)

Figure 73 Serial Data Register (SRU)

LSB

MSB

Transmit clock

Serial output
data

Serial input data
latch timing

Figure 74 Serial Interface Input/Output Timing

Port Mode Register A (PMRA: $004): This register has the following functions (figure 75).

/SI pin function selection

/SO pin function selection

Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

Not used

PMRA0

PMRA1

PMRA0

/SO mode selection

Port mode register A (PMRA: $004)

PMRA1

/SI mode selection

Figure 75 Port Mode Register A (PMRA)

HD404849 Series

A/D Converter

The MCU has a built-in A/D converter that uses successive approximations with a resistor ladder. It can
measure eight analog inputs with 8-bit resolution. As shown in the block diagram of figure 77, the A/D
converter has a 4-bit A/D mode register, a 4-bit plus 4-bit A/D data register, a 1-bit A/D start flag, and a 1-
bit A/D current off flag.

COMP

Selector

Reference
voltage

Reference voltage control

A/D control

logic

A/D start flag

(ADSF)

A/D current

off flag
(IAOF)

Conversion time control

HLT

(1 in stop, watch, and

subactive modes)

A/D mode

(AMR)

A/D data

(ADRU, ADRL)

Interrupt flag

(IFAD)

Encoder

Internal data bus

/AN

D/A

Figure 77 Block Diagram of A/D Converter

HD404849 Series

A/D Data Register (ADRL: $017, ADRU: $018): 8-bit read-only register consisting of a 4-bit lower
digit and 4-bit upper digit. This register is not cleared by reset. Any data read during A/D conversion is
not guaranteed. After the completion of A/D conversion, the resultant eight-bit data is held in this register
until the start of the next conversion (figures 79, 80, and 81).

MSB

LSB

Bit 0

Bit 7

ADRU: $018

ADRL: $017

RESULT

Figure 79 A/D Data Registers

Bit

Initial value

Read/Write

Bit name

ADRL3

ADRL2

ADRL0

ADRL1

A/D data register (lower digit) (ADRL: $017)

Figure 80 A/D Data Register Lower Digit (ADRL)

Bit

Initial value

Read/Write

Bit name

A/D data register (upper digit) (ADRU: $018)

ADRU2

ADRU1

ADRU0

ADRU3

Figure 81 A/D Data Register Upper Digit (ADRU)

HD404849 Series

A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the
completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 82.

Bit

Initial value

Read/Write

Bit name

R/W

DTON

R/W

ADSF

R/W

LSON

R/W

WDON

A/D start flag (ADSF: $020, bit 2)

ADSF (A/D start flag)

A/D conversion started

A/D conversion completed

Refer to the description of operating
modes

DTON

Refer to the description of timers

WDON

Refer to the description of operating
modes

LSON

Figure 82 A/D Start Flag (ADSF)

A/D Current Off Flag (IAOF: $021, Bit 2): By setting this 1-bit flag to 1, the current flowing through the
ladder resistor of the A/D converter is cut off during standby and active modes. See figure 83.

HD404849 Series

Bit

Initial value

Read/Write

Bit name

R/W

RAME

R/W

IAOF

R/W

ICSF

R/W

ICEF

A/D current off flag (IAOF: $021, bit 2)

Refer to description of operating modes

RAME

Refer to description of timers

ICEF

Refer to description of timers

ICSF

IAOF (A/D current off flag)

Current I is cut off.

Current I flows.

Figure 83 A/D Current Off Flag (IAOF)

Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2),
but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data
register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed.

The A/D converter does not operate in the stop, watch, and subactive modes because it relies on the clock
from OSC, which is stopped in these modes. During these low-power dissipation modes, current through
the resistor ladder is cut off to decrease the power input.

The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as
active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to V

. When using a shared

R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and
PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain pulled up.

HD404849 Series

LCD Data Area and Segment Data ($05C$07B): As shown in figure 85, each bit of the storage area
corresponds to one of four duty cycles. If data is written to an area corresponding to a certain duty cycle, it
is automatically output to the corresponding segments as display data.

Bit 3

Bit 2

Bit 1

Bit 0

100

101

102

103

104

105

$060

$061

$062

$063

$064

$065

$066

$067

$068

$069

COM4

COM3

COM2

COM1

Bit 3

Bit 2

Bit 1

Bit 0

$05C

$05D

$05E

$05F

SEG13

SEG14

SEG15

SEG16

SEG13

SEG14

SEG15

SEG16

SEG13

SEG14

SEG15

SEG16

SEG13

SEG14

SEG15

SEG16

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

$06B

$06C

$06D

$06E

$06F

$070

$071

$072

$073

$074

$075

$076

$077

$078

$079

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

122

123

$07A

$07B

COM4

COM3

COM2

COM1

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG43

SEG44

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG17

SEG18

SEG19

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

$06A

106

Figure 85 Configuration of LCD RAM Area (for Dual-Port RAM)

HD404849 Series

100

LCD Control Register (LCR: $01B): Four-bit write-only register which controls LCD blanking, on/off
switching of the liquid-crystal display's power supply division resistor, display in watch and subactive
modes, and connection of the LCD division resistor, as shown in figure 86.

Blank/display

Blank: Segment signals are turned off, regardless of LCD RAM data setting.

Display: LCD RAM data is output as segment signals.

Power switch on/off

Off: The power switch is off.

On: The power switch is on and V

is V

Watch/subactive mode display

Off: In watch and subactive modes, all common and segment pins are grounded and the liquid-crystal
power switch is turned off.

On: In watch and subactive modes, LCD RAM data is output as segment signals.

LCD power supply division resistor switch

Off: Division resistor is disconnected.

On: Division resistor is connected.

Bit

Initial value

Read/Write

Bit name

LCR3

LCR2

LCR0

LCR1

LCD display control register (LCR: $01B)

LCR1

Power switch on/off

Off

LCR0

Blank/display

Blank

Display

LCD power supply division
resistor switch

LCR3

Off

Display on/off selection in
watch and subactive modes

LCR2

Off

Figure 86 LCD Control Register (LCR)

HD404849 Series

101

LCD Duty-Cycle/Clock Control Register (LMR: $01C): Four-bit write-only register which selects the
display duty cycle and LCD clock source, as shown in figure 87. The dependence of frame frequency on
duty cycle is listed in table 30.

Bit

Initial value

Read/Write

Bit name

LMR3

LMR2

LMR0

LMR1

LCD duty cycle/clock control register (LMR: $01C)

LMR3

LMR2

Input clock source selection

LMR1

LMR0

Duty cycle selection

1/4 duty

1/3 duty

1/2 duty

Static

CL0 (32.768

duty/64: when

32.768-kHz oscillation is used)

CL1 (f

OSC

duty cycle/1024)

CL2 (f

OSC

duty cycle/8192)

CL3 (refer to table 29)

Figure 87 LCD Duty-Cycle/Clock Control Register (LMR)

HD404849 Series

102

Table 30 LCD Frame Frequencies for Different Duty Cycles

Frame Frequencies

Duty Cycle

LMR3

LMR2

OSC

= 400 kHz f

OSC

= 800 kHZ f

OSC

= 2 MHz

OSC

= 4 MHz

Static

CL0

512 Hz

CL1

390.6 Hz

781.3 Hz

1953 Hz

3906 Hz

CL2

48.8 Hz

97.7 Hz

244.1 Hz

488.3 Hz

CL3

24.4 Hz

48.8 Hz

122.1 Hz

244.1 Hz

64 Hz

1/2

CL0

256 Hz

CL1

195.3 Hz

390.6 Hz

976.6 Hz

1953 Hz

CL2

24.4 Hz

48.8 Hz

122.1 Hz

244.1 Hz

CL3

12.2 Hz

24.4 Hz

61 Hz

122.1 Hz

32 Hz

1/3

CL0

170.7 Hz

CL1

130.2 Hz

260.4 Hz

651 Hz

1302 Hz

CL2

16.3 Hz

32.6 Hz

81.4 Hz

162.8 Hz

CL3

8.1 Hz

16.3 Hz

40.7 Hz

81.4 Hz

21.3 Hz

1/4

CL0

128 Hz

CL1

97.7 Hz

195.3 Hz

488.3 Hz

976.6 Hz

CL2

12.2 Hz

24.4 Hz

61 Hz

122.1 Hz

CL3

6.1 Hz

12.2 Hz

30.5 Hz

61 Hz

16 Hz

Note:

The division ratio depends on the value of bit 3 of timer mode register A (TMA).

Upper value: When TMA3 = 0, CL3 = f

OSC

duty cycle/16384.

Lower value: When TMA3 = 1, CL3 = 32.768 kHz

duty cycle/512.

LCD Output Register 3 (LOR3: $01F): Write-only register used to specify ports R6 and R7 as pins
SEG13SEG20 in 4-pin units (figure 88).

HD404849 Series

103

Bit

Initial value

Read/Write

Bit name

Not used

LOR32

Not used

LOR31

LCD output register 3 (LOR3: $01F)

LOR31

R6/SEG13SEG16 mode selection

SEG13SEG16

LOR32

R7/SEG17SEG20 mode selection

SEG17SEG20

Figure 88 LCD Output Register 3 (LOR3)

Large Liquid-Crystal Panel Drive and V

LCD

: If the capacitance of the LCD is very large while being

driven, decrease the capacitance by attaching external resistors in parallel, as shown in figure 89.

The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix
configuration of the LCD complicates the paths of charge/discharge currents flowing through the
capacitors--the resistance will also vary with lighting conditions. This size must be determined by trial-
and-error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 to 10
k

is usually suitable. (Another effective method is to attach capacitors of 0.1 to 0.3

F.)

Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid-crystal drive
voltage (V

LCD

HD404849 Series

105

Programmable ROM (HD4074849)

The HD4074849 is a ZTAT

microcomputer with built-in PROM that can be programmed in PROM

mode.

Pin Description by Mode

Pin No.

MCU Mode

PROM Mode

Pin No

MCU Mode

PROM Mode

FP-80A,
TFP- 80C FP-80B Pin Name I/O

Pin Name I/O

FP- 80A,
TFP-80C

FP-80B Pin Name

I/O

Pin
Name

I/O

/AN

I/O

/TOD

I/O

/AN

I/O

EVNB

I/O

GND

/EVND

I/O

TEST

SCK

I/O

OSC

/SI

I/O

OSC

/SO

I/O

RESET

/SEG13

I/O

GND

/SEG14

I/O

/SEG15

I/O

GND

/SEG16

I/O

/SEG17

I/O

/SEG18

I/O

/SEG19

I/O

/SEG20

I/O

SEG21

I/O

SEG22

I/O

SEG23

I/O

SEG24

I/O

SEG25

STOPC

SEG26

INT

SEG27

INT

I/O

SEG28

/INT

I/O

SEG29

/INT

I/O

SEG30

I/O

SEG31

/TOB

I/O

SEG32

/TOC

I/O

SEG33

HD404849 Series

106

Pin No.

MCU Mode

PROM Mode

Pin No

MCU Mode

PROM Mode

FP-80A,
TFP- 80C FP-80B Pin Name I/O

Pin Name I/O

FP- 80A,
TFP-80C

FP-80B Pin Name

I/O

Pin
Name

I/O

SEG34

COM3

SEG35

COM4

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

AN0

SEG42

AN1

SEG43

AN2

SEG44

AN3

COM1

/AN

I/O

COM2

/AN

I/O

Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin

2. Each of O

has two pins; before using, each pair must be connected together.

PROM Mode Pin Functions

: Applies the programming voltage (12.5 V

0.3 V) to the built-in PROM.

CE : Inputs a control signal to enable PROM programming and verification.

OE : Inputs a data output control signal for verification.

: Act as address input pins of the built-in PROM.

: Act as data bus input pins of the built-in PROM. Each of O

has two pins; before using these

pins, connect each pair together.

RESET, TEST: Used to set PROM mode. The MCU is set to PROM mode by pulling M

and

RESET low, and TEST high.

Other Pins: Connect pins AV

, OSC

, D

, R7

/SEG20, and V

to V

. Connect pins AV

and X1 to

GND. Leave other pins open.

Programming the Built-In PROM

The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling

RESET, M

and

low, and TEST high. In PROM mode, the MCU does not operate, but it can be programmed in the

HD404849 Series

107

same way as any other commercial 27256-type EPROM using a standard PROM programmer and an 80-to-
28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table 31.

Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. As shown in figure 90, this circuit splits
each instruction into five lower bits and five upper bits that are read from or written to consecutive
addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a
general-purpose PROM programmer, a 32-kbyte address space ($0000$7FFF) must be specified.

Table 31 Recommended PROM Programmers and Socket Adapters

PROM Programmer

Manufacturer

Model name

DATA I/O Corp.

121B
29B

AVAL Corp.

PKW1000

Socket Adapter

Package

Model Name

Manufacturer

FP-80A

HS4849ESH01H

Hitachi

FP-80B

HS4849ESF01H

TFP-80C

HS4849ESN01H

Warnings

1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address

$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.

Note that the plastic-package version cannot be erased and reprogrammed.

2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1

positions match), otherwise overcurrents may damage the LSI. Before starting programming, make
sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.

3. PROM programmers have two voltages (V

): 12.5 V and 21 V. Remember that Hitachi devices require

a V

of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.

Programming and Verification

The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.

HD404849 Series

108

Programming and verification modes are selected as listed in table 32, the memory map in PROM mode is
shown in figure 90.

Table 32 PROM Mode Selection

Pin

Mode

Programming

Low

High

Data input

Verification

High

Low

Data output

Programming inhibited

High

High impedance

$0000

Vector address

Zero-page subroutine
(64 words)

Pattern
(4,096 words)

Program
(16,384 words)

$0001

$001F

$0080

$007F

$2000

$1FFF

$0020

$7FFF

Bit 4

Bit 8

Bit 3

Bit 7

Bit 2

Bit 6

Bit 1

Bit 5

1
1

Bit 0

Bit 9

Upper three bits are not to be used
(fill them with 111)

Upper 5 bits

Lower 5 bits

$0000

$000F
$0010

$003F
$0040

$3FFF

$0FFF
$1000

Figure 90 Memory Map in PROM Mode

HD404849 Series

109

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes, as shown in figure 91 and described below.

W register

X register

Y register

RAM address

Register Indirect Addressing

RAM address

Direct Addressing

2nd word of Instruction

Opcode

1st word of Instruction

RAM address

Memory Register Addressing

Opcode

Instruction

Figure 91 RAM Addressing Modes

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address. When the area from $090 to $25F is used, a bank must be selected by the bank register
(V: $03F).

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

HD404849 Series

110

Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses
from $040 to $04F, are accessed with the LAMR and XMRA instructions.

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes, as shown in figure 92 and described below.

2nd word of instruction

Opcode

1st word of instruction

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 92 ROM Addressing Modes

HD404849 Series

111

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC

) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC

) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 94. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.

Accumulator

Referenced ROM address

Address Designation

B register

[P]

Instruction

Opcode

If RO = 1

Accumulator, B register

ROM data

Pattern Output

ROM data

If RO = 1

Output registers R1, R2

Figure 93 P Instruction

HD404849 Series

112

BR AAA

AAA NOP

256 (n 1) + 255

256n

BR AAA
BR BBB

256n + 254
256n + 255
256 (n + 1)

BBB NOP

Figure 94 Branching when the Branch Destination is on a Page Boundary

Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC

), and 0s are placed in the eight high-

order bits (PC

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-
bit immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 93. If bit 8 of the ROM data is 1, the lower eight bits of ROM data are written to the
accumulator and the B register. If bit 9 is 1, the lower eight bits of ROM data are written to the R1 and R2
port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register,
and also to the R1 and R2 port output registers at the same time.

The P instruction has no effect on the program counter.

HD404849 Series

113

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to V

+ 0.3

Total permissible input current

100

Total permissible output current

Maximum input current

4, 5

4, 6

Maximum output current

7, 8

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.

1. Applies to D

) of the HD4074849.

2. The total permissible input current is the total of input currents simultaneously flowing in from all

the I/O pins to ground.

3. The total permissible output current is the total of output currents simultaneously flowing out from

to all I/O pins.

4. The maximum input current is the maximum current flowing from each I/O pin to ground.

5. Applies to R0R3, R6, and R7.

6. Applies to D

7. The maximum output current is the maximum current flowing out from V

to each I/O pin.

8. Applies to D

, R03, R6, and R7.

HD404849 Series

114

Electrical Characteristics

DC Characteristics (HD404848/HD4048412/HD404849: V

= 2.7 to 6.0 V, GND = 0 V,

= 20

C to +75

C; HD4074849: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

C, unless

otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Input high
voltage

RESET

SCK

SI,

INT

, INT

STOPC

EVNB

EVND

0.9V

0.3

OSC

0.3 --

0.3

External clock
operation

Input low
voltage

RESET

SCK

SI,

INT

, INT

STOPC

EVNB

EVND

0.3

0.1V

OSC

0.3

External clock
operation

Output high
voltage

SCK

, SO, TOB,

TOC, TOD

1.0 --

= 0.5 mA

Output low
voltage

SCK

, SO, TOB,

TOC, TOD

0.4

= 0.4 mA

I/O leakage
current

RESET

SCK

SI,

INT

, INT

STOPC

EVNB

EVND,
OSC

, TOB,

TOC, TOD, SO

1.0

= 0 V to V

Current
dissipation in
active mode

CC1

= 5.0 V,

OSC

= 4 MHz

CC2

0.6

1.8

= 3.0 V,

OSC

= 800 kHz

Current
dissipation in
standby
mode

SBY1

1.0

2.0

= 5.0 V,

OSC

= 4 MHz,

LCD on

SBY2

0.2

0.7

= 3.0 V,

OSC

= 800 kHz

LCD on

HD404849 Series

115

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Notes

Current
dissipation in
subactive
mode

SUB

= 3.0 V, LCD on 4, 7, 8

= 3.0 V, LCD on 5, 7, 8

150

= 3.0 V, LCD on 6, 7, 8

Current
dissipation in
watch mode

WTC1

= 3.0 V, LCD on 8

WTC2

= 3.0 V, LCD off 8

Current
dissipation in
stop mode

STOP

= 3.0 V

no 32-kHz oscillator

Stop mode
retaining
voltage

STOP

1.5

No 32-kHz oscillator 9

Notes: 1. Output buffer current is excluded.

2. I

CC1

and I

CC2

are the source currents when no I/O current is flowing while the MCU is in reset

state.

Test conditions: MCU: Reset

Pins:

RESET

and TEST at GND

3. I

SBY1

and I

SBY2

are the source currents when no I/O current is flowing while the MCU timer is

operating.

Test conditions: MCU: I/O reset

Standby mode

Pins:

RESET

at V

TEST at GND

, D

, R0R3, R6, R7 at V

4. Applies to HD404848.

5. Applies to HD4048412 and HD404849.

6. Applies to HD4074849.

7. When the LCD power supply division resistor is connected (LCR3 = 0).

8. These are the source currents when no I/O current is flowing.

Test conditions: Pins:

RESET

at V

TEST at GND

, D

, R0R3, R6, R7 at V

9. Test condition voltage necessary for RAM data retention.

HD404849 Series

116

I/O Characteristics for Standard Pins (HD404848/HD4048412/HD404849: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20

C to +75

C; HD4074849: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit Test Condition

Notes

Input high
voltage

, D

R0R3, R6, R7

0.7V

+ 0.3 V

Input low
voltage

R0R3, R6, R7

0.3

0.3V

Output high
voltage

R0R3, R6, R7

1.0 --

= 0.5 mA

Output low
voltage

R0R3, R6, R7

0.4

= 0.4 mA

I/O leakage
current

, R0R3,

R6, R7

= 0 V to V

1, 2

= V

0.3 V to V

1, 3

= 0 V to 0.3 V

1, 3

Pull-up MOS
current

R0R3,

R6, R7

150

= 3.0 V,

= 0 V

Notes: 1. Output buffer current is excluded.

2. Applies to HD404848, HD4048412, and HD404849.

3. Applies to HD4074849.

HD404849 Series

117

I/O Characteristics for High-Current Pins (HD404848/HD4048412/HD404849: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20

C to +75

C; HD4074849: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

unless otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit Test Condition

Note

Input high
voltage

0.7V

+ 0.3 V

Input low
voltage

0.3

0.3V

Output high
voltage

1.0 --

= 0.5 mA

Output low
voltage

0.4

= 0.4 mA

2.0

= 15 mA,

= 4.5 V to 6.0 V

I/O leakage
current

= 0 V to V

Pull-up MOS
current

150

= 3 V,

= 0 V

Note:

1. The test condition of HD4074849 is V

= 4.5 V to 5.5 V.

2. Output buffer current is excluded.

LCD Circuit Characteristics (HD404848/HD4048412/HD404849: V

= 2.7 to 6.0 V, GND = 0 V, T

20

C to +75

C; HD4074849: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

C, unless otherwise

specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit Test Condition

Note

Segment
driver voltage
drop

SEG13SEG44 --

0.6

= 3

Common
driver voltage
drop

COM1COM4

0.3

= 3

LCD power
supply
division
resistance

300

900

Between V

and GND

LCD voltage

LCD

2.7

Notes: 1. V

and V

are the voltage drops from power supply pins V1, V2, V3, and GND to each segment

pin and each common pin, respectively.

2. When V

LCD

is supplied from an external source, the following relations must be retained:

GND

HD404849 Series

118

A/D Converter Characteristics (HD404848/HD4048412/HD404849: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20

C to +75

C; HD4074849: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

C, unless

otherwise specified)

Item

Symbol

Pin(s)

Min

Typ

Max

Unit

Test Condition

Note

Analog power
voltage

0.3 V

+ 0.3 V

Analog input
voltage

Current between
AV

and AV

200

= AV

= 5.0 V

Analog input
capacitance

Resolution

Bit

Number of inputs

Channel

Absolute accuracy --

2.0

LSB

Conversion time

cyc

Input impedance

Note: 1. Connect to V

when the A/D converter is not used.

HD404849 Series

119

AC Characteristics (HD404848/HD4048412/HD404849: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20

C to

+75

C; HD4074849: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

C, unless otherwise specified)

Item

Symbol

Pin(s)

Min Typ

Max

Unit

Test Condition

Note

Clock oscillation
frequency

OSC

, OSC

0.4

4.5

MHz

1/4 division

X1, X2

32.768 --

kHz

Instruction cycle time

cyc

0.89 --

subcyc

244.14 --

32-kHz oscillator,
1/8 division

122.07 --

32-kHz oscillator,
1/4 division

Oscillation stabilization
time
(ceramic oscillator)

OSC

, OSC

7.5

Oscillation stabilization
time
(crystal oscillator)

OSC

, OSC

X1, X2

= 10

C to+60

C 3

External clock high
width

CPH

OSC

105 --

OSC

= 4 MHz

External clock low width t

CPL

OSC

105 --

OSC

= 4 MHz

External clock rise time

CPr

OSC

= 4 MHz

External clock fall time

CPf

OSC

= 4 MHz

INT

EVNB

EVND high widths

INT

EVNB

, EVND

cyc

subcyc

INT

EVNB

EVND low widths

INT

EVNB

, EVND

cyc

subcyc

RESET

low width

RSTL

RESET

cyc

STOPC

low width

STPL

STOPC

RESET

rise time

RSTr

RESET

STOPC

rise time

STPr

STOPC

Input capacitance

All pins except
D

f = 1 MHz, V

= 0 V

180

f = 1 MHz, V

= 0 V 8

Notes: 1. When the subsystem oscillator (32.768-kHz crystal oscillator) is used, f

OSC

must operate under

one of the following conditions: 0.4 MHz

OSC

1.0 MHz or 1.6 MHz

OSC

4.5 MHz. Set bit 1

of the system clock select register (SSR: $029) to 0 for the former, and 1 for the latter.

2. For the HD404848, HD4048412, and HD404849, instructions can be executed during subactive

mode if V

= 2.2 V to 6.0 V.

3. The oscillation stabilization time is defined as the time required for the oscillator to stabilize in the

following three cases:

After V

reaches 2.7 V at power-on

After

RESET

input goes low when stop mode is cancelled

HD404849 Series

120

After

STOPC

input goes low when stop mode is cancelled

At power-on or when stop mode is cancelled,

RESET

STOPC

must be input for at least t

ensure the oscillation stabilization time. If using a ceramic or crystal oscillator, contact its
manufacturer to determine what stabilization time is required since it will depend on the circuit
constants and stray capacitances.

4. See figure 95.

5. See figure 96.

6. See figure 97.

7. See figure 98.

8. The max value for the HD404848, HD4048412, HD404849 is 15 pF.

Serial Interface Timing Characteristics (HD404848/HD4048412/HD404849: V

= 2.7 to 6.0 V, GND

= 0 V, T

= 20

C to +75

C; HD4074849: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20

C to +75

C, unless

otherwise specified)

During Transmit Clock Output

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Note

Transmit clock cycle time

Scyc

SCK

1.0

cyc

Load shown in figure
100

Transmit clock high width

SCKH

SCK

0.4

Scyc

Load shown in figure
100

Transmit clock low width

SCKL

SCK

0.4

Scyc

Load shown in figure
100

Transmit clock rise time

SCKr

SCK

100

Load shown in figure
100

Transmit clock fall time

SCKf

SCK

100

Load shown in figure
100

Serial output data delay time t

DSO

300

Load shown in figure
100

Serial input data setup time

SSI

200

Serial input data hold time

HSI

200

Note: 1. Refer to figure 99.

HD404849 Series

121

During Transmit Clock Input

Item

Symbol

Pin

Min

Typ

Max

Unit

Test Condition

Note

Transmit clock cycle time

Scyc

SCK

1.0

cyc

Transmit clock high width

SCKH

SCK

0.4

Scyc

Transmit clock low width

SCKL

SCK

0.4

Scyc

Transmit clock rise time

SCKr

SCK

100

Transmit clock fall time

SCKf

SCK

100

Transmit output data delay
time

DSO

300

Load shown in figure
100

Serial input data setup time

SSI

200

Serial input data hold time

HSI

200

Note: 1. Refer to figure 99.

CPr

CPf

0.3 V

OSC

CPH

CPL

1/f

Figure 95 External Clock Timing

0.9V

0.1V

INT

to INT

EVNB

, EVND

Figure 96 Interrupt Timing

RSTr

RSTL

0.9V

0.1V

RESET

Figure 97 Reset Timing

STPr

STPL

0.9V

0.1V

STOPC

Figure 98

STOPC Timing

HD404849 Series

123

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version
(HD404849). A 16-kword data size is required to change ROM data to mask manufacturing data since the
program used is for a 16-kword version.

This limitation applies when using an EPROM or a data base.

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(8,192 words)

Not used

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(12,288 words)

Not used

8-kword ROM version:
HD404848
Write all-1 data to addresses
$2000 to $3FFF

12-kword ROM version:
HD4048412
Write all-1 data to addresses
$3000 to $3FFF

$0000

$000F
$0010

$003F
$0040

$1FFF
$2000

$3FFF

$0000

$000F
$0010

$003F
$0040

$2FFF
$3000

$3FFF

Write all-1 data in shaded areas

HD404849 Series

124

HD404848/HD4048412/HD404849 Option List

HD404848

HD4048412

HD404849

1. ROM Size

3. ROM Code Media

EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are

programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are

programmed to different EPROMs.

With 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, without time-base

2. Optional Functions

Date of order

Customer

Department

Name

ROM code name

LSI number

/ /

4. Oscillator for OSC1 and OSC2

Ceramic oscillator

Crystal oscillator

External clock

f =

MHz

FP-80A

FP-80B

TFP-80C

6. Package

Note:

Used

Not used

5. Stop mode

Options marked with an asterisk require a subsystem
crystal oscillator (X1, X2).

Please check off the appropriate applications and
enter the necessary information.

8-kword

12-kword

16-kword

Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTATTM version).

HD404849 Series

125

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404849

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD404849