Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

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Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
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Remember to give due consideration to safety when making your circuit designs, with appropriate
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Notes regarding these materials

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contained therein.

HD404358 Series

Rev. 6.0

Sept. 1998

Description

The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to increase program
productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input
capture timer, and two low-power dissipation modes.

The HD404358 Series includes seven chips: the HD404354, HD40A4354 with 4-kword ROM; the
HD404356, HD40A4356 with 6-kword ROM; the HD404358, HD40A4358 with 8-kword ROM; the
HD407A4359 with 16-kword PROM.

The HD40A4354, HD40A4356, HA40A4358, and HD407A4359 are high speed versions (minimum
instruction cycle time: 0.47

The HD407A4359 is a PROM version (ZTAT

microcomputer). A program can be written to the PROM

by a PROM writer, which can dramatically shorten system development periods and smooth the process
from debugging to mass production. (The ZTAT

version is 27256-compatible.)

ZTAT

: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

34 I/O pins

One input-only pin

33 input/output pins: 4 pins are intermediate-voltage NMOS open drain with high-current pins (15

mA, max.)

On-chip A/D converter (8-bit

8-channel)

Low power voltage 2.7 V to 6.0 V

Three timers

One event counter input

One timer output

One input capture timer

Eight-bit clock-synchronous serial interface (1 channel)

Alarm output

HD404358 Series

Built-in oscillators

Ceramic oscillator or crystal

External clock drive is also possible

Seven interrupt sources

Two by external sources

Three by timers

One by A/D converter

One by serial interface

Two low-power dissipation modes

Standby mode

Stop mode

Instruction cycle time

0.47

s (f

OSC

= 8.5 MHz, 1/4 division ratio):

HD40A4354, HD40A4356, HD40A4358,

HD407A4359

0.8

s (f

OSC

= 5 MHz, 1/4 division ratio):

HD404354, HD404356, HD404358

Ordering Information

Type

Instruction Cycle
Time

Product Name

Model Name

ROM
(Words)

RAM
(Digit)

Package

Mask ROM Standard versions

HD404354

HD404354S

4,096

384

DP-42S

OSC

= 5 MHz)

HD404354H

FP-44A

HD404356

HD404356S

6,144

DP-42S

HD404356H

FP-44A

HD404358

HD404358S

8,192

DP-42S

HD404358H

FP-44A

High speed versions HD40A4354

HD40A4354S

4,096

384

DP-42S

OSC

= 8.5 MHz)

HD40A4354H

FP-44A

HD40A4356

HD40A4356S

6,144

DP-42S

HD40A4356H

FP-44A

HD40A4358

HD40A4358S

8,192

DP-42S

HD40A4358H

FP-44A

ZTAT

OSC

= 8.5 MHz)

HD407A4359

HD407A4359S

16,384

512

DP-42S

HD407A4359H

FP-44A

HD404358 Series

Pin Arrangement

1
2
3
4
5
6
7
8
9
10
11

33
32
31
30
29
28
27
26
25
24
23

FP-44A

TEST

RESET

OSC

GND

/AN

SCK

/SI

/SO

/TOC

/AN

INT

/EVNB

/BUZZ

STOPC

/AN

SCK

/SI

/SO

/TOC

TEST

RESET

OSC

STOPC

/BUZZ

/EVNB

INT

/INT

DP-42S

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

20
21

29
28
27
26
25
24
23
22

42
41
40
39
38
37
36
35
34
33
32
31
30

/AN

GND

HD404358 Series

Pin Description

Pin Number

Item

Symbol

DP-42S FP-44A I/O

Function

Power
supply

Applies power voltage

GND

Connected to ground

Test

TEST

Cannot be used in user applications. Connect this pin
to GND.

Reset

RESET

Resets the MCU

Oscillator

OSC

Input/output pin for the internal oscillator. Connect
these pins to the ceramic oscillator or crystal oscillator,
or OSC

to an external oscillator circuit.

OSC

Port

2230

1721,

2326

I/O

Input/output pins addressed individually by bits; D

are all standard-voltage I/O pins.

One-bit standard-voltage input port pin

25,

1219,

3138

4043,

714

2734

I/O

Four-bit input/output pins consisting of standard-voltage
pins

3942

3538

I/O

Four-bit input/output pins consisting of intermediate
voltage pins

Interrupt

INT

22, 23

17, 18

Input pins for external interrupts

Stop clear

STOPC

Input pin for transition from stop mode to active mode

Serial
Interface

SCK

I/O

Serial interface clock input/output pin

Serial interface receive data input pin

Serial interface transmit data output pin

Timer

TOC

Timer output pin

EVNB

Event count input pin

Alarm

BUZZ

Square waveform output pin

A/D
converter

Power supply for the A/D converter. Connect this pin
as close as possible to the V

pin and at the same

voltage as V

. If the power supply voltage to be used

for the A/D converter is not equal to V

, connect a 0.1-

F bypass capacitor between the AV

and AV

pins.

(However, this is not necessary when the AV

pin is

directly connected to the V

pin.)

Ground for the A/D converter. Connect this pin as
close as possible to GND at the same voltage as GND.

1219

714

Analog input pins for the A/D converter

HD404358 Series

Block Diagram

D port

R0 port

R1 port

R2 port

R3 port

R4 port

R8 port

(14 bits)

Instruction

decoder

(10 bits)

(4 bits)

(1 bit)

ALU

SPY

(4 bits)

SPX

(4 bits)

(2 bits)

RAM

(384 4 bits)
(512 4 bits)

System control

Interrupt

control

Timer A

Timer B

Timer C

Serial

interface

A/D

converter

Buzzer

Internal data bus

Internal address bus

BUZZ

·
·
·

SCK

TOC

EVNB

INT

Data bus

Intermediate

voltage pin

Directional

signal line

GND

OSC

STOPC

TEST

RESET

RA port

ROM

(4,096 10 bits) (6,144 10 bits)
(16,384 10 bits)(8,192 10 bits)

HD404358 Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

Vector Address Area ($0000$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.

Zero-Page Subroutine Area ($0000$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000-$0FFF (HD404354, HD40A4354), $0000$17FF (HD404356, HD40A4356),
$0000$1FFF (HD404358, HD40A4358), $0000$3FFF (HD407A4359)): The entire ROM area can be
used for program coding.

$000F

$0FFF

$1800

$0010

$003F

$0040

Vector address

(16 words)

Zero-page subroutine

(64 words)

Pattern (4,096 words)

Program (4,096 words)

Program

(8,192 words)

$0000

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007

$0008
$0009

$000A
$000B

$000C
$000D

$000E

$000F

JMPL instruction

(jump to

RESET

STOPC

routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B routine)

JMPL instruction

(jump to timer C routine)

JMPL instruction

(jump to A/D converter routine)

JMPL instruction

(jump to

INT

routine)

JMPL instruction

(jump to serial routine)

For HD404358, HD40A4358

Program

(16,384 words)

HD407A4359

$1FFF

$2000

$3FFF

For HD404354, HD40A4354

$1000

Program

(6,144 words)

For HD404356, HD40A4356

$17FF

Note: Since the ROM address areas between $0000$0FFF overlap, the user can

determine how these areas are to be used.

Figure 1 ROM Memory Map

HD404358 Series

RAM Memory Map

The HD404354, HD40A4354, HD404356, HD40A4356, HD404358 and HD40A4358 MCUs contain 384-
digit

4-bit RAM areas. The HD407A4359 MCU contain 512-digit

4-bit RAM areas. Both of these

RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control
bits area, special function register area, and register flag area are mapped onto the same RAM memory
space labeled as a RAM-mapped register area. The RAM memory map is shown in figure 2 and described
below.

RAM-Mapped Register Area ($000$03F):

Interrupt Control Bits Area ($000$003)

This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

Special Function Register Area ($004$01F, $024$03F)

This area is used as mode registers and data registers for external interrupts, serial interface,
timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.

This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD,
and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on
using the instructions are shown in figure 4.

Memory Register (MR) Area ($040$04F): Consisting of 16 addresses, this area (MR0MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.

Data Area ($050$17F for HD404354/HD40A4354/HD404356/HD40A4356/HD404358/HD40A4358,
$050$1FF for HD407A4359)

Stack Area ($3C0$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404358 Series

RAM Memory Map

A/D channel register (ACR)

$000

$040

$050

$003

$004

$005

$006

$007

$008
$009

$00A
$00B

$00C

$00D

$00E

$00F

$020
$023

$033

$00A

$00B

$00E

$00F

R/W

W
W

R/W

R/W
R/W

$3C0

RAM-mapped registers

Memory registers (MR)

Stack (64 digits)

Interrupt control bits area

Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)

Timer B (TRBL/TWBL)
(TRBU/TWBU)

Miscellaneous register (MIS)

Timer mode register C (TMC)
Timer C (TRCL/TWCL)
(TRCU/TWCU)

Port R0 DCR (DCR0)

Port R3 DCR (DCR3)

Not used

1. Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).

2. Undefined.

Timer read register B lower (TRBL)

Timer read register B upper (TRBU)

Timer read register C lower (TRCL)

Timer read register C upper (TRCU)

Timer write register B lower (TWBL)

Timer write register B upper (TWBU)

Timer write register C lower (TWCL)

Timer write register C upper (TWCU)

R: Read only
W: Write only
R/W: Read/write

$200

Notes:

$016

A/D data register lower (ADRL)

$017

$024
$025
$026

$018

$019

$01A

$3FF

A/D data register upper (ADRU)
A/D mode register 1 (AMR1)
A/D mode register 2 (AMR2)

W
W

Port mode register B (PMRB)
Port mode register C (PMRC)

Timer mode register B2 (TMB2)

Not used

W
W

$030

Not used

-000

0000
0000

Undefined

-000

0000

/0000

00--

0000

0000
1000
0000

--00

0000

00-0
-000

Undefined

/0000

Undefined

Initial values

after reset

$03F

HD404354, HD40A4354,
HD404356, HD40A4356,

HD404358, HD40A4358

Data (304 digits)

HD407A4359

Data (432 digits)

0000

---0

Port D

Port D DCR

Port R1 DCR (DCR1)
Port R2 DCR (DCR2)

W
W

0000

Port R8 DCR (DCR8)

DCR

(DCD0)

(DCD1)

(DCD2)

$02C

$02D

$02E

$02F

$031
$032

$038

Not used

$180

$034

Port R4 DCR (DCR4)

0000

Figure 2 RAM Memory Map

HD404358 Series

Bit 3

Bit 2

Bit 1

Bit 0

IMTA

(IM of timer A)

IFTA

(IF of timer A)

IM1

(IM of

INT

)

IF1

(IF of

INT

)

IMTC

(IM of timer C)

IFTC

(IF of timer C)

IMTB

(IM of timer B)

IFTB

(IF of timer B)

IMS

(IM of serial)

IFS

(IF of serial)

IMAD

(IM of A/D)

IFAD

(IF of A/D)

$000

$001

$002

$003

Interrupt control bits area

IM0

(IM of

INT

)

IF0

(IF of

INT

)

RSP

(Reset SP bit)

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

$020

$021

$022

$023

ADSF

(A/D start flag)

WDON

(Watchdog

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag)

IAOF

off flag)

IF:
IM:
IE:
SP:

Interrupt request flag
Interrupt mask
Interrupt enable flag
Stack pointer

Bit 3

Bit 2

Bit 1

Bit 0

Not used

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

IAOF

ICSF
ICEF

RAME

RSP

WDON

ADSF

Not used

SEM/SEMD

REM/REMD

TM/TMD

Allowed

Not executed

Allowed

Not executed

Allowed

Inhibited

Allowed

Not executed

Inhibited

Allowed

Inhibited

Allowed

Not executed

Inhibited

Note: WDON is reset by MCU reset or by

STOPC

enable for stop mode cancellation.

The REM or REMD instuction must not be executed for ADSF during A/D conversion.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404358 Series

$000

$003

PMRA $004

SMR $005

SRL $006

SRU $007

TMA $008

TMB1 $009

TRBL/TWBL $00A

TRBU/TWBU $00B

MIS $00C

TMC $00D

TRCL/TWCL $00E

TRCU/TWCU $00F

ACR $016

ADRL $017

ADRU $018

AMR1$019

AMR2 $01A

$020

$023

PMRB $024

PMRC $025

TMB2 $026

DCD0 $02C

DCD1 $02D

DCD2 $02E

DCR0 $030

DCR1 $031

DCR2 $032

DCR3 $033

DCR4 $034

DCR8 $038

$03F

Bit 3

Bit 2

Bit 1

Interrupt control bits area

/BUZZ

/TOC

/SO

Serial transmit clock speed selection

Serial data register (lower digit)

Serial data register (upper digit)

Clock source selection (timer A)

Clock source selection (timer B)

Timer B register (lower digit)

Timer B register (upper digit)

SO PMOS control

Clock source selection (timer C)

Timer C register (lower digit)

Timer C register (upper digit)

Analog channel selection

A/D data register (lower digit)

A/D data register (upper digit)

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port D

DCD

Port R0

DCR

Port R2

DCR

Port R4

DCR

Port R0

DCR

Port R2

DCR

Port R4

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R4

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R4

DCR

1.
2.
3.
4.
5.
6.

SCK

Bit 0

Auto-reload on/off
Pull-up MOS control
A/D conversion time
SO output level control in idle states
Serial clock source selection
Input capture selection

Notes:

/SI

/AN

R4/AN

Port R8

DCR Port R8

DCR

STOPC

Buzzer output

/EVNB

INT

EVNB detection edge selection

INT

Port R1

DCR

Port R3

DCR

Port R1

DCR

Port R3

DCR Port R3

DCR

Not used

Figure 5 Special Function Register Area

HD404358 Series

Memory registers

65
66
67
68
69
70
71

73
74
75
76
77
78
79

$040

$041
$042

$043

$044

$045
$046

$047
$048
$049

$04A
$04B
$04C
$04D
$04E
$04F

960

$3C0

1023

$3FF

MR(0)
MR(1)
MR(2)
MR(3)
MR(4)
MR(5)
MR(6)
MR(7)
MR(8)
MR(9)

Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1

MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)

Bit 3

Bit 2

Bit 1

Bit 0

$3FC

$3FD

$3FE

$3FF

1020

1021

1022

1023

PC PC :
ST: Status flag
CA: Carry flag

Program counter

Stack area

Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

HD404358 Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter
Initial value: 0,
no R/W

Stack pointer
Initial value: $3FF, no R/W

Initial value: Undefined, R/W

Initial value: 1, no R/W

Figure 7 Registers and Flags

Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.

W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.

HD404358 Series

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction,
not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL,
CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or
bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read,
regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack
during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction.

Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.

The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.

Reset

The MCU is reset by inputting a high-level voltage to the

RESET pin. At power-on or when stop mode is

cancelled,

RESET must be high for at least one t

to enable the oscillator to stabilize. During operation,

RESET must be high for at least two instruction cycles.

Initial values after MCU reset are listed in table 1.

Interrupts

The MCU has 7 interrupt sources: two external signals (

INT

and

INT

), three timer/counters (timers A, B,

and C), serial interface, and A/D converter.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the
interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE)
and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in
table 3.

HD404358 Series

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.

The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.

HD404358 Series

Table 1

Initial Values After MCU Reset

Item

Abbr.

Initial Value

Contents

Program counter

(PC)

$0000

Indicates program execution point
from start address of ROM area

Status flag

(ST)

Enables conditional branching

Stack pointer

(SP)

$3FF

Stack level 0

Interrupt
flags/mask

Interrupt enable flag

(IE)

Inhibits all interrupts

Interrupt request flag

(IF)

Indicates there is no interrupt
request

Interrupt mask

(IM)

Prevents (masks) interrupt requests

I/O

Port data register

(PDR)

All bits 1

Enables output at level 1

Data control register

(DCD0
DCD1)

All bits 0

Turns output buffer off (to high
impedance)

(DCD2)

- - - 0

(DCR0
DCR4,
DCR8)

All bits 0

Port mode register A

(PMRA)

0000

Refer to description of port mode
register A

Port mode register B bits
20

(PMRB2
PMRB0)

000

Refer to description of port mode
register B

Port mode register C

(PMRC)

00 - 0

Refer to description of port mode
register C

Timer/
counters,
serial
interface

Timer mode register A

(TMA)

- 000

Refer to description of timer mode
register A

Timer mode register B1

(TMB1)

0000

Refer to description of timer mode
register B1

Timer mode register B2

(TMB2)

- 000

Refer to description of timer mode
register B2

Timer mode register C

(TMC)

0000

Refer to description of timer mode
register C

Serial mode register

(SMR)

0000

Refer to description of serial mode
register

Prescaler S

(PSS)

$000

Timer counter A

(TCA)

$00

Timer counter B

(TCB)

$00

Timer counter C

(TCC)

$00

Timer write register B

(TWBU,
TWBL)

$X0

Timer write register C

(TWCU,
TWCL)

$X0

Octal counter

000

HD404358 Series

Item

Abbr.

Initial
Value

Contents

A/D

A/D mode register 1

(AMR1)

0000

Refer to description of A/D mode register

A/D mode register 2

(AMR2)

- - 00

A/D channel register

(ACR)

- 000

Refer to description of A/D channel register

A/D data register

(ADRL)

0000

Refer to description of A/D data register

(ADRU)

1000

Bit registers

Watchdog timer on flag

(WDON)

Refer to description of timer C

A/D start flag

(ADSF)

Refer to description of A/D converter

off flag

(IAOF)

Refer to the description of A/D converter

Input capture status flag

(ICSF)

Refer to description of timer B

Input capture error flag

(ICEF)

Refer to description of timer B

Others

Miscellaneous register

(MIS)

00 - -

Refer to description of operati ng modes, I/O,
and serial interface

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. indicates that the bit does not exist.

Item

Abbr.

Status After Cancellation of
Stop Mode by

STOPC

Input

Status After all Other Types of
Reset

Carry flag

(CA)

Pre-stop-mode values are not
guaranteed; values must be
initialized by program

Pre-MCU-reset values are not
guaranteed; values must be
initialized by program

Accumulator

(A)

B register

(B)

W register

(W)

X/SPX register

(X/SPX)

Y/SPY register

(Y/SPY)

Serial data register

(SRL, SRU)

RAM

Pre-stop-mode values are
retained

RAM enable flag

(RAME)

Port mode register
B bit 3

(PMRB3)

Pre-stop-mode values are
retained

HD404358 Series

Table 3

Interrupt Processing and Activation Conditions

Interrupt Source

INT

Timer A

Timer B

Timer C

A/D

Serial

IF0 ·

IM0

IF1 ·

IM1

IFTA ·

IMTA

IFTB ·

IMTB

IFTC ·

IMTC

IFAD ·

IMAD

IFS ·

IMS

Note:

Bits marked

can be either 0 or 1. Their values have no effect on operation.

Instruction cycles

Instruction

execution

IE reset

Interrupt

acceptance

Execution of JMPL

instruction at vector address

Execution of

instruction at

start address

of interrupt

routine

Vector address

generation

Note:

The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.

Stacking

Figure 9 Interrupt Processing Sequence

HD404358 Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.

Table 4

Interrupt Enable Flag (IE: $000, Bit 0)

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

): Two external interrupt signals.

External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising
edge of signals input to

INT

and

INT

, as listed in table 5.

Table 5

External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0)

IF0, IF1

Interrupt Request

Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.

Table 6

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1)

IM0, IM1

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.

Table 7

Timer A Interrupt Request Flag (IFTA: $001, Bit 2)

IFTA

Interrupt Request

Yes

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as listed in table 8.

HD404358 Series

Table 8

Timer A Interrupt Mask (IMTA: $001, Bit 3)

IMTA

Interrupt Request

Enabled

Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.

Table 9

Timer B Interrupt Request Flag (IFTB: $002, Bit 0)

IFTB

Interrupt Request

Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer
B interrupt request flag, as listed in table 10.

Table 10

Timer B Interrupt Mask (IMTB: $002, Bit 1)

IMTB

Interrupt Request

Enabled

Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.

Table 11

Timer C Interrupt Request Flag (IFTC: $002, Bit 2)

IFTC

Interrupt Request

Yes

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as listed in table 12.

Table 12

Timer C Interrupt Mask (IMTC: $002, Bit 3)

IMTC

Interrupt Request

Enabled

Disabled (masked)

HD404358 Series

Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 13.

Table 13

Serial Interrupt Request Flag (IFS: $003, Bit 2)

IFS

Interrupt Request

Yes

Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 14.

Table 14

Serial Interrupt Mask (IMS: $003, Bit 3)

Mask IMS

Interrupt Request

Enabled

Disabled (masked)

A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in
table 15.

Table 15

A/D Interrupt Request Flag (IFAD: $003, Bit 0)

IFAD

Interrupt Request

Yes

A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 16.

Table 16

A/D Interrupt Mask (IMAD: $003, Bit 1)

IMAD

Interrupt Request

Enabled

Disabled (masked)

HD404358 Series

Operating Modes

The MCU has three operating modes as shown in table 17. The operations in each mode are listed in tables
18 and 19. Transitions between operating modes are shown in figure 11.

Table 17

Operating Modes and Clock Status

Mode Name

Active

Standby

Stop

Activation method

RESET

cancellation,

interrupt request,

STOPC

cancellation in stop mode

SBY instruction

STOP instruction

Status

System
oscillator

Stopped

Cancellation
method

RESET

input, STOP/ SBY

instruction

RESET

input, interrupt

request

RESET

input,

STOPC

input in stop mode

Note:

OP implies in operation

Table 18

Operations in Low-Power Dissipation Modes

Function

Stop Mode

Standby Mode

CPU

Reset

Retained

RAM

Retained

Timer A

Reset

Timer B

Reset

Timer C

Reset

Serial

Reset

A/D

Reset

I/O

Reset

Retained

Note:

OP implies in operation

Table 19

I/O Status in Low-Power Dissipation Modes

Output

Input

Standby Mode

Stop Mode

Active Mode

Input enabled

, R0R4,

R8,

Retained or output of
peripheral functions

High impedance

Input enabled

HD404358 Series

Reset by

RESET

input or

by watchdog timer

Standby mode

Stop mode

SBY

instruction

Interrupt

Active
mode

RESET 1

RESET 2

RAME = 0

RAME = 1

STOP

instruction

STOPC

Oscillate

Stop

cyc

OSC

CPU

PER

Oscillate

cyc

OSC

CPU

PER

Stop

OSC

CPU

PER

Main oscillation frequency

OSC

System clock

Clock for other peripheral
functions

OSC

cyc

CPU

PER

Figure 11 MCU Status Transitions

Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC

and OSC

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.

The MCU enters standby mode when the SBY instruction is executed in active mode.

Standby mode is terminated by a

RESET input or an interrupt request. If it is terminated by RESET input,

the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation
in standby mode is shown in figure 12.

HD404358 Series

Standby

Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop

Yes

Restart

processor clocks

Reset MCU

Execute

next instruction

Accept interrupt

Restart

processor clocks

Yes

IF = 1,

IM = 0, and

IE = 1?

RESET

= 0?

IF0 ·

IMO

= 1?

IF1 ·

IM1

= 1?

IFTA ·

IMTA

= 1?

IFTB ·

IMTB

= 1?

IFTC ·

IMTC

= 1?

IFAD ·

IMAD

= 1?

Yes

IFS ·

IMS

= 1?

Stop

Oscillator: Stop
Peripheral clocks: Stop
All other clocks: Stop

RESET

= 0?

STOPC

= 0?

RAME = 1

RAME = 0

Yes

Execute

next instruction

Figure 12 MCU Operation Flowchart

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC

and OSC

oscillator stops.

Stop mode is terminated by a

RESET input or a STOPC input as shown in figure 13. RESET or STOPC

must be applied for at least one t

to stabilize oscillation (refer to the AC Characteristics section). When

the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.

HD404358 Series

Stop mode

Oscillator

Internal

clock

STOP instruction execution

res

(stabilization period)

res

RESET

STOPC

Figure 13 Timing of Stop Mode Cancellation

Stop Mode Cancellation by

STOPC: The MCU enters active mode from stop mode by inputting STOPC

as well as by

R E SE T . In either case, the MCU starts instruction execution from the starting address

(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by

STOPC and by RESET. When stop mode is cancelled by R E SE T , RAME = 0;

when cancelled by

STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop

mode;

STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop

mode has been cancelled by

STOPC (for example, when the RAM contents before entering stop mode is

used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the
beginning of the program.

MCU Operation Sequence: The MCU operates in the sequence shown in figure 15. It is reset by an
asynchronous

RESET input, regardless of its status.

The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.

Power on

RESET

= 0 ?

RAME = 0

Reset MCU

MCU

operation

cycle

Yes

Figure 14 MCU Operating Sequence (Power On)

HD404358 Series

Table 20

Oscillator Circuit Examples

Circuit Configuration

Circuit Constants

External clock
operation

External
oscillator

OSC

Open

OSC

Ceramic oscillator
(OSC

, OSC

)

OSC

Ceramic

GND

Ceramic oscillator:

CSA4.00MG

(Murata)

= 1 M

20%

= C

= 30 pF

20%

Crystal oscillator
(OSC

, OSC

)

OSC

Crystal

GND

OSC

= 1 M

20%

= C

= 10 to 22 pF

20%

Crystal: Equivalent to circuit
shown below

= 7 pF max.

= 100

max.

Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray

capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.

2. Wiring among OSC

, OSC

, and elements should be as short as possible, and must not cross

other wiring (see figure 18).

HD404358 Series

Input/Output

The MCU has 33 input/output pins (D

, R0R4, R8) and an input pin (RA

). The features are described

below.

Four pins (R2

) are high-current (15 mA max) input/output with intermediate voltage NMOS open

drain pins.

The D

, R0, R3R4 input/output pins are multiplexed with peripheral function pins such as for the

timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port
setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output
selection are automatically switched according to the setting.

Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.

Peripheral function output pins are CMOS output pins. Only the R0

/SO pin can be set to NMOS open-

drain output by software.

In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.

Each input/output pin except for R2 has a built-in pull-up MOS, which can be individually turned on or
off by software.

I/O buffer configuration is shown in figure 19, programmable I/O circuits are listed in table 21, and I/O pin
circuit types are shown in table 22.

Table 21

Programmable I/O Circuits

MIS3 (bit 3 of MIS)

DCD, DCR

PDR

CMOS buffer

PMOS

NMOS

Pull-up MOS

Note:

-- indicates off status.

HD404358 Series

Table 22

Circuit Configurations of I/O Pins

I/O Pin Type

Circuit

Pins

Input/output
pins

Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

PDR

Input control signal

DCR, DCD

, R0

Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

DCR

PDR

Input control signal

MIS2

HLT

DCR

PDR

Input data

Output data

Input control signal

Input pins

Input data

Input control signal

Peripheral
function pins

Input/output
pins

Pull-up control signal

Output data

Input data

HLT

MIS3

SCK

Notes on next page.

HD404358 Series

Evaluation Chip Set and

ZTAT

/Mask ROM Product Differences

As shown in figure 20, the NMOS intermediate breakdown voltage open drain pin circuit in the evaluation
chip set differs from that used in the ZTAT

microcomputer and built-in mask ROM microcomputer

products.

Please note that although these outputs in the ZTAT

microcomputer and built-in mask ROM

microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs
cannot be set to high impedance in the evaluation chip set.

Table 23

Program Control of High Impedance States

Register

Set Value

DCR

PDR

Notes:

An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation.

This applies to the ZTAT

and built-in mask ROM microcomputer NMOS open drain pins.

HLT

MIS3

DCR

PDR

CPU input

Input control signal

Evaluation Chip Set Circuit Structure

Input control signal

ZTAT and Built-in Mask ROM Microcomputer Circuit Structure

HLT

DCR

PDR

CPU input

Figure 20 NMOS Intermediate Breakdown Voltage Open Drain Pin Circuits

HD404358 Series

D Port (D

): Consist of 9 input/output pins addressed by one bit.

Pins D

are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. All pins D

are tested by the TD and

TDD instructions.

The on/off statuses of the output buffers are cont rol l ed by D-port dat a control regis t ers (DC D0DC D2: $02C
$02E) that are mapped to memory addresses (figure 21).

Pins D0D2, D4 are multiplexed with peripheral function pins

INT0, INT1, EVNB, and STOPC,

respectively. The peripheral function modes of these pins are selected by bits 03 (PMRB0PMRB3) of
port mode register B (PMRB: $024) (figure 22).

Pin D

is multiplexed with peripheral function pin BUZZ. The peripheral function mode of this pin is

selected by bit 3 (PMRA3) of port mode register A (PMRA: $004) (figure 23).

R Ports (R0

R4

, R8): 24 input/output pins addressed in 4-bit units. Data is input to these ports by the

LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored
in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are
controlled by R-port data control registers (DCR0DCR4: $030$034, DCR8: $038) that are mapped to
memory addresses (figure 21).

Pin R0

is multiplexed with peripheral function pin

SCK. The peripheral function mode of this pin is

selected by bit 3 (SMR3) of serial mode register (SMR: $005) (figure 24).

Pins R0

are multiplexed with peripheral pins SI, SO and TOC, respectively. The peripheral function

modes of these pins are selected by bits 02 (PMRA0PMRA2) of port mode register A (PMRA: $004), as
shown in figures 23.

Port R3 is multiplexed with peripheral function pins AN

, respectively. The peripheral function

modes of these pins can be selected by individual pins, by setting A/D mode register 1 (AMR1: $019)
(figure 25).

Ports R4 is multiplexed with peripheral function pins AN

, respectively. The peripheral function

modes of these pins can be selected in 4-pin units by setting bit 1 (AMR21) of A/D mode register 2
(AMR2: $01A) (figure 26).

Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous
register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data
register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 21 and figure 27).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to V

to prevent LSI malfunctions due to noise. These pins must either be pulled up to V

their pull-up MOS transistors or by resistors of about 100 k

HD404358 Series

Bit

Initial value

Read/Write

Bit name

DCD0, DCD2, DCR0 to DCR4, DCR8

Data control register

(DCD0 to 2: $02C to $02E)
(DCR0 to 4: $030 to $034, DCR8: $038)

Correspondence between ports and DCD/DCR bits

DCD0

DCD1

DCD2

DCR0

DCR1

DCR2

DCR3

DCR4

DCR8

Off (high-impedance)

Bits 0 to 3

CMOS Buffer On/Off Selection

Register Name

Not used

Bit 3

Not used

Bit 2

Not used

Bit 1

Bit 0

DCD03,
DCD13,
DCR03
DCR43,
DCR83

DCD02,
DCD12,
DCR02
DCR42,
DCR82

DCD01,
DCD11,
DCR01
DCR41,
DCR81

DCD00
DCD20,
DCR00
DCR40,
DCR80

Figure 21 Data Control Registers (DCD, DCR)

HD404358 Series

Bit

Initial value

Read/Write

Bit name

PMRB3

PMRB2

PMRB0

PMRB1

PMRB0

INT

Mode Selection

INT

Port mode register B (PMRB: $024)

PMRB1

INT

Mode Selection

INT

PMRB2

/EVNB Mode Selection

EVNB

PMRB3

STOPC

Mode Selection

STOPC

Note:

PMRB3 is reset to 0 only by

RESET

input. When

STOPC

is input in stop mode, PMRB3 is not

reset but retains its value.

Figure 22 Port Mode Register B (PMRB)

Bit

Initial value

Read/Write

Bit name

PMRA3

PMRA2

PMRA0

PMRA1

PMRA0

/SO Mode Selection

Port mode register A (PMRA: $004)

PMRA1

/SI Mode Selection

PMRA2

/TOC Mode Selection

TOC

PMRA3

/BUZZ Mode Selection

BUZZ

Figure 23 Port Mode Register A (PMRA)

HD404358 Series

Bit

Initial value

Read/Write

Bit name

SMR3

SMR2

SMR0

SMR1

Serial mode register (SMR: $005)

SMR2

SMR0

SMR1

SMR3

SCK

Mode Selection

SCK

Transmit clock selection.
Refer to figure 55 in the
serial interface section.

Figure 24 Serial Mode Register (SMR)

Bit

Initial value

Read/Write

Bit name

AMR13

AMR12

AMR10

AMR11

AMR10

A/D mode register 1 (AMR1: $019)

AMR11

AMR12

/AN

Mode Selection

AMR13

/AN

Mode Selection

/AN

Mode Selection

/AN

Mode Selection

Figure 25 A/D Mode Register 1 (AMR1)

HD404358 Series

Prescalers

The MCU has a built-in prescaler labeled as prescaler S (PSS).

The prescalers operating conditions are listed in table 24, and the prescalers output supply is shown in
figure 28. The timers AC input clocks except external events, the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.

Prescaler Operation

Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock.

Table 24

Prescaler Operating Conditions

Prescaler

Input Clock

Reset Conditions

Stop Conditions

Prescaler S

System clock

MCU reset

MCU reset, stop mode

Timer A

Timer B

Timer C

Serial

System

clock

Prescaler S

Clock

selector

Alarm output

circuit

Figure 28 Prescaler Output Supply

HD404358 Series

Timers

The MCU has four timer/counters (A to C).

Timer A: Free-running timer

Timer B: Multifunction timer

Timer C: Multifunction timer

Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunction timers, whose functions are
listed in table 25. The operating modes are selected by software.

Table 25

Timer Functions

Functions

Timer A

Timer B

Timer C

Clock source

Prescaler S

Available

External event

Available

Timer functions

Free-running

Available

Event counter

Available

Reload

Available

Watchdog

Available

Input capture

Available

Timer output

PWM

Available

Note:

-- implies not available.

HD404358 Series

Timer A

Timer A Functions: Timer A has the following functions.

Free-running timer

The block diagram of timer A is shown in figure 29.

System
clock

Selector

Prescaler S (PSS)

Internal data bus

Timer A interrupt

request flag

(IFTA)

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

PER

128

512

1024

2048

÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷

Clock

Figure 29 Timer A Block Diagram

Timer A Operations:

Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).

Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.

Registers for Timer A Operation: Timer A operating modes are set by the following registers.

Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode
and input clock source as shown in figure 30.

HD404358 Series

Timer B

Timer B Functions: Timer B has the following functions.

Free-running/reload timer

External event counter

Input capture timer

The block diagram for each operation mode of timer B is shown in figures 31 and 32.

Timer counter B

(TCB)

128

512

2048

Timer mode

(TMB2)

EVNB

Selector

System

clock

PER

Prescaler S (PSS)

Edge

detector

Edge detection control signal

Timer write

(TWBL)

Timer mode

(TMB1)

Timer write

(TWBU)

Clock

Free-running

timer control

signal

Timer read

(TRBL)

Interrupt request

flag of timer B

(IFTB)

Timer read

(TRBU)

Overflow

Internal data bus

Figure 31 Timer B Free-Running and Reload Operation Block Diagram

HD404358 Series

Timer B Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).

Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

External event counter operation: Timer B is used as an external event counter by selecting the external
event input as an input clock source. In this case, pin D

/EVNB must be set to EVNB by port mode

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling
edges detection is selected, the time between the falling edge and rising edge of input signals must be
2t

cyc

or longer.

Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026).
The other operation is basically the same as the free-running/reload timer operation.

Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVNB.

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by timer mode register 2 (TMB2: $026).

When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL:
$00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF
is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture
error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0.

Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.

Timer mode register B1 (TMB1: $009)
Timer mode register B2 (TMB2: $026)
Timer write register B (TWBL: $00A, TWBU: $00B)
Timer read register B (TRBL: $00A, TRBU: $00B)
Port mode register B (PMRB: $024)

Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 33. It is reset to $0
by MCU reset.

HD404358 Series

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.

When selecting the input capture timer operation, select the internal clock as the input clock source.

Bit

Initial value

Read/Write

Bit name

TMB13

TMB12

TMB10

TMB11

Timer mode register B1 (TMB1: $009)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMB12

TMB10

TMB11

Input Clock Period and Input
Clock Source

/EVNB (external event input)

TMB13

Free-Running/Reload
Timer Selection

Free-running timer

Reload timer

Figure 33 Timer Mode Register B1 (TMB1)

HD404358 Series

Timer mode register B2 (TMB2: $026): Three-bit write-only register that selects the detection edge of
signals input to pin EVNB and input capture operation as shown in figure 34. It is reset to $0 by MCU
reset.

Bit

Initial value

Read/Write

Bit name

Not used

TMB22

TMB20

TMB21

Timer mode register B2 (TMB2: $026)

TMB21

TMB20

EVNB Edge Detection Selection

No detection

Falling edge detection

Rising edge detection

Rising and falling edge detection

TMB22

Free-Running/Reload and Input Capture Selection

Free-running/reload

Input capture

Figure 34 Timer Mode Register B2 (TMB2)

Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value is invalid (figures 35 and 36).

Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.

Bit

Initial value

Read/Write

Bit name

TWBL3

TWBL2

TWBL0

TWBL1

Timer write register B (lower digit) (TWBL: $00A)

Figure 35 Timer Write Register B Lower Digit (TWBL)

HD404358 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWBU3

Undefined

TWBU2

Undefined

TWBU0

Undefined

TWBU1

Timer write register B (upper digit) (TWBU: $00B)

Figure 36 Timer Write Register B Upper Digit (TWBU)

Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 37 and 38).

The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained,
and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading
TRBL, the count of timer B when TRBU is read can be obtained.

When the input capture timer operation is selected and if the count of timer B is read after a trigger is
input, either the lower or upper digit can be read first.

Bit

Initial value

Read/Write

Bit name

Undefined

TRBL3

Undefined

TRBL2

Undefined

TRBL0

Undefined

TRBL1

Timer read register B (lower digit) (TRBL: $00A)

Figure 37 Timer Read Register B Lower Digit (TRBL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRBU3

Undefined

TRBU2

Undefined

TRBU0

Undefined

TRBU1

Timer read register B (upper digit) (TRBU: $00B)

Figure 38 Timer Read Register B Upper Digit (TRBU)

HD404358 Series

Timer C

Timer C Functions: Timer C has the following functions.

Free-running/reload timer

Watchdog timer

Timer output operation (PWM output)

The block diagram of timer C is shown in figure 40.

Timer counter C

(TCC)

Port mode

Selector

System

clock

Prescaler S (PSS)

Timer write

(TWCL)

Timer mode

Timer write

(TWCU)

Clock

Free-running
timer control
signal

Timer read

(TRCL)

Interrupt request

flag of timer C

(IFTC)

Timer read register C upper (TRCU)

Overflow

TOC

Timer

output

control

signal

Watchdog timer

controller

Watchdog on

flag (WDON)

System reset signal

Internal data bus

Timer output

control logic

128

512

1024

2048

PER

Figure 40 Timer C Block Diagram

HD404358 Series

Timer C Operations:

Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C (TMC: $00D).

Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.

Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. The watchdog timer operation flowchart is
shown in figure 41. Program run can be controlled by initializing timer C by software before it reaches
$FF.

$FF + 1

$00

Timer C

count value

Overflow

Time

CPU

operation

Normal

operation

Timer C

clear

Normal

operation

Timer C

clear

Program
runaway

Normal

operation

Reset

Figure 41 Watchdog Timer Operation Flowchart

Timer output operation: The PWM output modes can be selected for timer C by setting port mode
register A (PMRA: $004).

By selecting the timer output mode, pin R0

/TOC is set to TOC. The output from TOC is reset low by

MCU reset.

PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C (TMC:
$00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in
figure 42.

HD404358 Series

T (N + 1)

T 256

T (256 N)

TMC3 = 0
(free-running
timer)

TMC3 = 1
(reload timer)

Notes:

T: Input clock period supplied to counter. (The clock source and system clock division

N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.)

ratio are determined by timer mode register C.)

Figure 42 PWM Output Waveform

Notes on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 26. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

In this case, the lower digit (TWCL) must be written to first, bit writing only to the lower digit does not
change the timer C value. Timer C is changed to the value in timer write register B at the same time the
upper digit (TWCU) is written to.

Table 26

PWM Output Following Update of Timer Write Register

PWM Output

Mode

Timer Write Register is Updated
during High PWM Output

Timer Write Register is Updated
during Low PWM Output

Reload

Timer write
register
updated to
value N

Interrupt
request

(255 N)

Timer write
register
updated to
value N

Interrupt
request

(255 N)

HD404358 Series

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.

Timer mode register C (TMC: $00D)
Port mode register A (PMRA: $004)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)

Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 43. It is reset to $0
by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C write instruction. Setting timer C's initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.

Bit

Initial value

Read/Write

Bit name

TMC3

TMC2

TMC0

TMC1

Timer mode register C (TMC: $00D)

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

TMC2

TMC0

TMC1

Input Clock Period

TMC3

Free-Running/Reload
Timer Selection

Free-running timer

Reload timer

1024t

cyc

Figure 43 Timer Mode Register C (TMC)

HD404358 Series

Port mode register A (PMRA: $004): Write-only register that selects R0

/TOC pin function as shown in

figure 44. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

PMRA3

PMRA2

PMRA0

PMRA1

PMRA0

/SO Mode Selection

Port mode register A (PMRA: $004)

PMRA1

/SI Mode Selection

PMRA2

/TOC Mode Selection

TOC

PMRA3

/BUZZ Mode Selection

BUZZ

Figure 44 Port Mode Register A (PMRA)

Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit
(TWCL) and the upper digit (TWCU) as shown in figures 45 and 46. The operation of timer write
register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).

Bit

Initial value

Read/Write

Bit name

TWCL3

TWCL2

TWCL0

TWCL1

Timer write register C (lower digit) (TWCL: $00E)

Figure 45 Timer Write Register C Lower Digit (TWCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TWCU3

Undefined

TWCU2

Undefined

TWCU0

Undefined

TWCU1

Timer write register C (upper digit) (TWCU: $00F)

Figure 46 Timer Write Register C Upper Digit (TWCU)

HD404358 Series

Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit
(TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit (figures 47 and 48).
The operation of timer read register C is basically the same as that of timer read register B (TRBL:
$00A, TRBU: $00B).

Bit

Initial value

Read/Write

Bit name

Undefined

TRCL3

Undefined

TRCL2

Undefined

TRCL0

Undefined

TRCL1

Timer read register C (lower digit) (TRCL: $00E)

Figure 47 Timer Read Register C Lower Digit (TRCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRCU3

Undefined

TRCU2

Undefined

TRCU0

Undefined

TRCU1

Timer read register C (upper digit) (TRCU: $00F)

Figure 48 Timer Read Register C Upper Digit (TRCU)

HD404358 Series

Alarm Output Function

The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the
prescaler S's outputs, and the output frequency depends on the state of port mode register C (PMRC: $025).
The duty cycle of the pulse output is fixed at 50%.

Internal data bus

256

512

1024

2048

Selector

System

clock

PER

Prescaler S (PSS)

Alarm output

control signal

BUZZ

Alarm output

controller

Port mode

(PMRC)

Port mode

(PMRA)

Figure 49 Alarm Output Function Block Diagram

Port Mode Register C (PMRC: $025): Four-bit write-only register that selects the alarm frequencies as
shown in figure 50. It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

PMRC0

Undefined

PMRC1

Port mode register C (PMRC: $025)

PMRC1

Output Level Control in Idle States

Low level

High level

PMRC0

Serial Clock Division Ratio

Prescaler output divided by 2

Prescaler output divided by 4

PMRC3

PMRC2

System Clock Divisor

2048

1024

512

256

Figure 50 Port Mode Register C (PMRC)

HD404358 Series

Port Mode Register A (PMRA: $004): Four-bit write-only register that selects D

/BUZZ pin function as

shown in figure 44. It is reset to $0 by MCU reset.

Serial Interface

The serial interface serially transfers and receives 8-bit data, and includes the following features.

Multiple transmit clock sources

External clock

Internal prescaler output clock

System clock

Output level control in idle states

Five registers, an octal counter, and a selector are also configured for the serial interface as follows.

Serial data register (SRL: $006, SRU: $007)
Serial mode register (SMR: $005)
Port mode register A (PMRA: $004)
Port mode register C (PMRC: $025)
Miscellaneous register (MIS: $00C)
Octal counter (OC)
Selector

The block diagram of the serial interface is shown in figure 51.

HD404358 Series

Internal data bus

128

512

2048

Port mode

(PMRC)

SCK

Selector

System

clock

PER

Prescaler S (PSS)

Idle

controller

Serial mode

(SMR)

Clock

Serial data

Serial interrupt

request flag

(IFS)

Selector

1/2

Octal

counter (OC)

I/O

controller

Transfer
control
signal

Figure 51 Serial Interface Block Diagram

Serial Interface Operation

Selecting and Changing the Operating Mode: Table 27 lists the serial interface's operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and the
serial mode register (SMR: $005) settings; to change the operating mode, always initialize the serial
interface internally by writing data to the serial mode register. Note that the serial interface is initialized by
writing data to the serial mode register. Refer to the following Serial Mode Register section for details.

Table 27

Serial Interface Operating Modes

SMR

PMRA

Bit 3

Bit 1

Bit 0

Operating Mode

Continuous clock output mode

Transmit mode

Receive mode

Transmit/receive mode

HD404358 Series

Pin Setting: The R0

SCK pin is controlled by writing data to the serial mode register (SMR: $005). The

/SI and R0

/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the

following Registers for Serial Interface section for details.

Transmit Clock Source Setting: The transmit clock source is set by writing data to the serial mode
register (SMR: $005) and port mode register C (PMRC: $025). Refer to the following Registers for Serial
Interface section for details.

Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU, $007).
Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the
transmit clock and is input from or output to an external system.

The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.

Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000
by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops.

When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t

cyc

to 8192t

cyc

by setting bits 0 to 2 (SMR0 SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0)

of port mode register C (PMRC: $025) as listed in table 28.

Table 28

Serial Transmit Clock (Prescaler Output)

PMRC

SMR

Bit 0

Bit 2

Bit 1

Bit 0

Prescaler Division Ratio

Transmit Clock Frequency

2048

4096t

cyc

512

1024t

cyc

128

256t

cyc

64t

cyc

16t

cyc

4096

8192t

cyc

1024

2048t

cyc

256

512t

cyc

128t

cyc

32t

cyc

HD404358 Series

Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 52.

STS wait state
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)

STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.

Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However,
note that if continuous clock output mode is selected in internal clock mode, the serial interface does not
enter transfer state but enters continuous clock output state (17).

The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04,
14) in transmit clock wait state.

Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.

In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.

If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set
by the octal counter that is reset to 000.

Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the

SCK pin.

When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait
state is entered.

HD404358 Series

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

MCU reset

SMR write

STS instruction

Transmit clock

8 transmit clocks

STS instruction (IFS 1)

SMR write (IFS 1)

External clock mode

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000)

Transfer state

(Octal counter = 000)

SMR write

STS instruction

Transmit clock

STS instruction (IFS 1)

8 transmit clocks

Internal clock mode

Continuous clock output state

(PMRA 0, 1 = 0, 0)

SMR write

Transmit clock 17

Note: Refer to the Operating States section for the corresponding encircled numbers.

MCU reset

SMR write (IFS 1)

Figure 52 Serial Interface State Transitions

Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC:
$025) to 0 or 1. The output level control example is shown in figure 53. Note that the output level cannot be
controlled in transfer state.

HD404358 Series

State

MCU reset

PMRA write

SMR write

PMRC write

SRL, SRU write

STS instruction

SCK

pin (input)

SO pin

IFS

STS wait state

Transmit clock
wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

External clock selection

Output level control in

idle states

Dummy write for
state transition

Output level control in

idle states

Data write for transmission

Undefined

LSB

MSB

Flag reset at transfer completion

External clock mode

State

MCU reset

PMRA write

SMR write

PMRC write

SRL, SRU write

STS instruction

SCK

pin (output)

SO pin

IFS

STS wait state

Transfer state

Transmit clock
wait state

STS wait state

Port selection

Internal clock selection

Output level control in

idle states

Data write for transmission

Output level control in

idle states

Undefined

LSB

MSB

Flag reset at transfer completion

Internal clock mode

Figure 53 Example of Serial Interface Operation Sequence

HD404358 Series

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 54.

Transfer completion

(IFS 1)

Interrupts inhibited

IFS 0

SMR write

IFS = 1

Transmit clock
error processing

Normal
termination

Yes

Transmit clock error detection flowchart

Transmit clock error detection procedure

State

SCK

pin (input)

Transmit clock
wait state

Transfer state

Transmit clock wait state

Noise

Transfer state has been
entered by the transmit clock
error. When SMR is written,
IFS is set.

Flag set because octal
counter reaches 000

Flag reset at
transfer completion

SMR write

IFS

Figure 54 Transmit Clock Error Detection

HD404358 Series

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode
register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.

Notes on Use:

Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode
register (SMR: $005) again.

Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by
writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register write or STS instruction execution must be programmed to be executed after
confirming that the

SCK pin is at 1, that is, after executing the input instruction to port R0.

Registers for Serial Interface

The serial interface operation is selected, and serial data is read and written by the following registers.

Serial Mode Register (SMR: $005)
Serial Data Register (SRL: $006, SRU: $007)
Port Mode Register A (PMRA: $004)
Port Mode Register C (PMRC: $025)
Miscellaneous Register (MIS: $00C)

Serial Mode Register (SMR: $005): This register has the following functions (figure 55).

SCK pin function selection

Transmit clock selection

Prescaler division ratio selection

Serial interface initialization

Serial mode register (SMR: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.

A write signal input to serial mode register (SMR: $005) discontinues the input of the transmit clock to the
serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed
during data transfer, the serial interrupt request flag (IFS: $003, bit 2) is set.

Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.

HD404358 Series

Bit

Initial value

Read/Write

Bit name

SMR3

SMR2

SMR0

SMR1

Serial mode register (SMR: $005)

SMR2

SMR0

SMR1

SMR3

SCK

Mode Selection

SCK

Output

Input

Clock Source

External clock

Prescaler
Division Ratio

Refer to
table 28

Prescaler

System clock

Figure 55 Serial Mode Register (SMR)

Port Mode Register C (PMRC: $025): This register has the following functions (figure 56).

Prescaler division ratio selection

Output level control in idle states

Port mode register C (PMRC: $025) is a 4-bit write-only register. It cannot be written during data transfer.

By setting bit 0 (PMRC0) of this register, the prescaler division ratio is selected. Bit 0 (PMRC0) can be
reset to 0 by MCU reset. By setting bit 1 (PMRC1), the output level of the SO pin is controlled in idle
states. The output level changes at the same time that PMRC1 is written to.

HD404358 Series

Bit

Initial value

Read/Write

Bit name

PMRC3

PMRC2

PMRC0

Undefined

PMRC1

Port mode register C (PMRC: $025)

PMRC1

Output Level Control in Idle States

Low level

High level

PMRC0

Serial Clock Division Ratio

Prescaler output divided by 2

Prescaler output divided by 4

Alarm output function.
Refer to figure 50.

Figure 56 Port Mode Register C (PMRC)

Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 57 and
58).

Transmission data write and shift

Receive data shift and read

Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 59.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR3

Undefined

R/W

SR2

Undefined

R/W

SR0

Undefined

R/W

SR1

Serial data register (lower digit) (SRL: $006)

Figure 57 Serial Data Register (SRL)

HD404358 Series

Bit

Initial value

Read/Write

Bit name

PMRA3

PMRA2

PMRA0

PMRA1

PMRA0

/SO Mode Selection

Port mode register A (PMRA: $004)

PMRA1

/SI Mode Selection

PMRA2

/TOC Mode Selection

TOC

PMRA3

/BUZZ Mode Selection

BUZZ

Figure 60 Port Mode Register A (PMRA)

Miscellaneous Register (MIS: $00C): This register has the following functions (figure 61).

/SO pin PMOS control

Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

Not used

MIS2

CMOS Buffer
On/Off Selection
for Pin R0

/SO

Miscellaneous register (MIS: $00C)

PMOS active

PMOS off

MIS3

Pull-Up MOS
On/Off Selection

Pull-up MOS off

Pull-up MOS on
(refer to table 21)

Figure 61 Miscellaneous Register (MIS)

HD404358 Series

Registers for A/D Converter Operation

A/D Mode Register 1 (AMR1: $019): Four-bit write-only register which selects digital or analog ports, as
shown in figure 63.

Bit

Initial value

Read/Write

Bit name

AMR13

AMR12

AMR10

AMR11

AMR10

A/D mode register 1 (AMR1: $019)

AMR11

AMR12

/AN

Mode Selection

AMR13

/AN

Mode Selection

/AN

Mode Selection

/AN

Mode Selection

Figure 63 A/D Mode Register 1 (AMR1)

A/D Mode register 2 (AMR2: $01A): Two-bit write-only register which is used to set the A/D conversion
period and to select digital or analog ports. Bit 0 of the A/D mode register selects the A/D conversion
period, and bit 1 selects port R4 as pins AN

in 4-pin units (figure 64).

Bit

Initial value

Read/Write

Bit name

Not used

AMR20

AMR21

AMR20

67 t

cyc

A/D mode register 2 (AMR2: $01A)

AMR21

Conversion Time

34 t

cyc

R4/AN

Pin Selection

Figure 64 A/D Mode Register 2 (AMR2)

HD404358 Series

A/D Channel Register (ACR: $016): Three-bit write-only register which indicates analog input pin
information, as shown in figure 65.

Bit

Initial value

Read/Write

Bit name

Not used

ACR2

ACR0

ACR1

A/D channel register (ACR: $016)

Analog Input Selection

ACR1

ACR2

ACR0

Figure 65 A/D Channel Register (ACR)

A/D Start Flag (ADSF: $02C, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the
completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 66.

Bit

Initial value

Read/Write

Bit name

Not used

R/W

ADSF

WDON

A/D start flag (ADSF: $020, bit 2)

Refer to the description of timers

WDON

A/D conversion completed

A/D conversion started

A/D Start Flag (ADSF)

Not used

Figure 66 A/D Start Flag (ADSF)

HD404358 Series

Off Flag (IAOF: $021, Bit 2): By setting the I

A D

off flag to 1, the current flowing through the

resistance ladder can be cut off even while operating in standby or active mode, as shown in figure 67.

Bit

Initial value

Read/Write

Bit name

R/W

RAME

R/W

IAOF

R/W

ICSF

R/W

ICEF

off flag (IAOF: $021, bit 2)

Refer to the description of operating
modes

RAME

Refer to the description of timers

ICEF

Refer to the description of timers

ICSF

current flows

current is cut off

Off Flag (IAOF)

Figure 67 I

Off Flag (IAOF)

A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower
digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the
resultant eight-bit data is held in this register until the start of the next conversion (figures 68, 69, and 70).

MSB

LSB

Bit 0

Bit 7

ADRU: $018

ADRL: $017

Figure 68 A/D Data Registers (ADRU, ADRL)

HD404358 Series

Bit

Initial value

Read/Write

Bit name

ADRL3

ADRL2

ADRL0

ADRL1

A/D data register (lower digit) (ADRL: $017)

Figure 69 A/D Data Register Lower Digit (ADRL)

Bit

Initial value

Read/Write

Bit name

A/D data register (upper digit) (ADRU: $018)

ADRU2

ADRU1

ADRU0

ADRU3

Figure 70 A/D Data Register Upper Digit (ADRU)

Notes on Usage

Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)

Do not write to the A/D start flag during A/D conversion

Data in the A/D data register during A/D conversion is undefined

Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power while in these modes, all current
flowing through the converter's resistance ladder is cut off.

If the power supply for the A/D converter is to be different from V

, connect a 0.1-

F bypass capacitor

between the AV

and AV

pins. (However, this is not necessary when the AV

pin is directly

connected to the V

pin.)

The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D
converter oparates stably, do not execute port output instructions during A/D convention.

The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to V

. When using a

shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by A/D mode register 1 or 2 (AMR1 or AMR2) as an analog
pin will remain pulled up (figure 71).

HD404358 Series

Pin Description in PROM Mode

The HD4074359 is a PROM version of a ZTAT

microcomputer. In PROM mode, the MCU stops

operating, thus allowing the user to program the on-chip PROM.

Pin Number

MCU Mode

PROM Mode

DP-42S

FP-44A

Pin

I/O

Pin

I/O

I/O

SCK

I/O

/SI

I/O

/SO

I/O

/TOC

I/O

TEST

RESET

OSC

GND

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

/AN

I/O

INT

I/O

INT

I/O

/EVNB

I/O

/BUZZ

I/O

STOPC

I/O

HD404358 Series

Programming the Built-In PROM

The MCU's built-in PROM is programmed in PROM mode. PROM mode is set by pulling

RESET, M

and

low, as shown in figure 72. In PROM mode, the MCU does not operate, but it can be programmed

in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a
100-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table
29.

Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if,
for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer,
a 32-kbyte address space ($0000$7FFF) must be specified.

Table 29

Recommended PROM Programmers and Socket Adapters

PROM Programmer

Socket Adapter

Manufacture

Model Name

Package

Manufacture

Model Name

DATA I/O corp

121 B

DP-42S

Hitachi

HS4359ESS01H

FP-44A

HS4359ESH01H

AVAL corp

PKW-1000

DP-42S

Hitachi

HS4359ESS01H

FP-44A

HS4359ESH01H

Control signals

Address bus

Data bus

GND
V

RESET

GND

HD407A4359

PROM mode pins

Socket adapter

PROM programmer

Figure 72 PROM Mode Connections

HD404358 Series

Warnings

1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address

$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.

Note that the plastic-package version cannot be erased and reprogrammed.

2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1

positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure
that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.

3. PROM programmers have two voltages (V

): 12.5 V and 21 V. Remember that ZTAT

devices

require a V

of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.

Programming and Verification

The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.

Programming and verification modes are selected as listed in table 30.

For details of PROM programming, refer to the following Notes on PROM Programming section.

Table 30

PROM Mode Selection

Pin

Mode

Programming

Low

High

Data input

Verification

High

Low

Data output

Programming inhibited

High

High impedance

HD404358 Series

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes, as shown in figure 73 and described below.

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.

W register

X register

Y register

RAM address

Register Direct Addressing

RAM address

Direct Addressing

2nd word of Instruction

Opcode

1st word of Instruction

RAM address

Memory Register Addressing

Opcode

Instruction

Figure 73 RAM Addressing Modes

HD404358 Series

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes, as shown in figure 74 and described below.

Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC

) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC

) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 76. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.

Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC

), and 0s are placed in the eight high-

order bits (PC

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 75. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.

The P instruction has no effect on the program counter

HD404358 Series

2nd word of instruction

Opcode

1st word of instruction

[JMPL]
[BRL]
[CALL]

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL]

Opcode

Program counter

Accumulator

Program counter

Table Data Addressing

B register

[TBR]

Instruction

Opcode

Instruction

Program counter

Current Page Addressing

[BR]

Figure 74 ROM Addressing Modes

HD404358 Series

Absolute Maximum Ratings

Item

Symbol

Value

Unit

Notes

Supply voltage

0.3 to +7.0

Programming voltage

0.3 to +14.0

Pin voltage

0.3 to V

+ 0.3 V

0.3 to +15.0

Total permissible input current

105

Total permissible output current

Maximum input current

6, 7

6, 8

Maximum output current

7, 9

Operating temperature

opr

20 to +75

Storage temperature

stg

55 to +125

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.

1. Applies to pin TEST (V

) of HD407A4359.

2. Applies to all standard voltage pins.

3. Applies to intermediate-voltage pins.

4. The total permissible input current is the total of input currents simultaneously flowing in from all

the I/O pins to GND.

5. The total permissible output current is the total of output currents simultaneously flowing out from

to all I/O pins.

6. The maximum input current is the maximum current flowing from each I/O pin to GND.

7. Applies to ports D

to D

, R0, R1, R3, R4, and R8.

8. Applies to port R2.

9. The maximum output current is the maximum current flowing from V

to each I/O pin.

HD404358 Series

Electrical Characteristics

DC Characteristics (HD407A4359: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

C; HD404354/

HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20

to +75

unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition Notes

Input high
voltage

RESET

SCK

INT

STOPC

, EVNB

0.8V

+ 0.3 V

0.7 V

+ 0.3 V

OSC

0.5

+ 0.3 V

Input low
voltage

RESET

SCK

INT

STOPC

, EVNB

0.3

0.2V

0.3

0.3V

OSC

0.3

0.5

Output high
voltage

SCK

, SO, TOC

0.5

= 0.5 mA

Output low
voltage

SCK

, SO, TOC

0.4

= 0.4 mA

I/O leakage
current

RESET

SCK

, SI,

SO,TOC,OSC

INT

STOPC

, EVNB

= 0 V to V

Current
dissipation in
active mode

5.0

= 5 V,

OSC

= 4 MHz

Current
dissipation in
standby mode

SBY

2.0

= 5 V,

OSC

= 4 MHz

Current
dissipation in
stop mode

STOP

= 5 V

Stop mode
retaining
voltage

STOP

Notes: 1. Excludes current flowing through pull-up MOS and output buffers.

2. I

is the source current when no I/O current is flowing while the MCU is in reset state.

Test conditions:

MCU:

Reset

Pins:

RESET

, TEST at GND

HD404358 Series

3. I

SBY

is the source current when no I/O current is flowing while the MCU timer is operating.

Test conditions:

MCU:

I/O reset

Standby mode

Pins:

RESET

at V

TEST at GND

, R0R4, R8, RA

at V

4. This is the source current when no I/O current is flowing.

Test conditions:

Pins:

RESET

at V

TEST at GND

, R0R4, R8, RA

at V

I/O Characteristics for Standard Pins (HD407A4359: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to

+75

C; HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20 to +75

C, unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Input high
voltage

R0, R1, R3,

R4, R8, RA

0.7V

+ 0.3

Input low
voltage

R0, R1, R3,

R4, R8, RA

0.3

0.3V

Output high
voltage

R0, R1, R3,

R4, R8

0.5

= 0.5 mA

Output low
voltage

R0, R1, R3,

R4, R8

0.4

= 1.6 mA

Input leakage
current

R0, R1, R3,

R4, R8, RA

= 0 V to V

Pull-up MOS
current

R0, R1, R3,

R4, R8

150

300

= 5 V,

= 0 V

Note:

1. Output buffer current is excluded.

HD404358 Series

I/O Characteristics for Intermediate-Voltage Pins (HD407A4359: V

= 2.7 to 5.5 V, GND = 0 V, T

20 to +75

C;HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD 40A4358: V

= 2.7 to

6.0 V, GND = 0 V, T

= 20 to +75

unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Input high
voltage

0.7V

Input low
voltage

0.3

0.3V

Output high
voltage

11.5

500 k

at 12 V

Output low
voltage

0.4

= 0.4 mA

2.0

= 15 mA,

= 4.5 to 5.5 V

I/O leakage
current

= 0 V to 12 V

Note:

1. Excludes output buffer current.

HD404358 Series

A/D Converter Characteristics (HD407A4359: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to +75

HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: V

= 2.7 to 6.0 V, GND = 0

V, T

= 20 to +75

unless otherwise specified)

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Analog supply
voltage

0.3 V

+ 0.3 V

Analog input
voltage

Current flowing
between AV

and AV

200

= AV

= 5.0

Analog input
capacitance

Resolution

Bit

Number of input
channels

Channel

Absolute
accuracy

2.0

LSB

Conversion
time

cyc

Input
impedance

Note:

1. Connect this to V

if the A/D converter is not used.

HD404358 Series

Standard f

OSC

= 5.0 MHz Version AC Characteristics (HD404354/HD404356/HD404358: V

= 2.7 to

6.0 V, GND = 0 V, T

= 20 to +75

Item

Symbol Pins

Min

Typ

Max

Unit

Test Condition

Note

Clock oscillation
frequency

OSC

, OSC

0.4

5.0

MHz 1/4 system clock

division ratio

Instruction cycle time

cyc

0.8

Oscillation stabilization
time (ceramic oscillator)

OSC

, OSC

7.5

Oscillation stabilization
time (crystal oscillator)

OSC

, OSC

External clock high
width

CPH

OSC

External clock low width t

CPL

OSC

External clock rise time

CPr

OSC

External clock fall time

CPf

OSC

INT

, EVNB high

widths

INT

EVNB

cyc

INT

, EVNB low

widths

INT

EVNB

cyc

RESET

low width

RSTL

RESET

cyc

STOPC

low width

STPL

STOPC

RESET

rise time

RSTr

RESET

STOPC

rise time

STPr

STOPC

Input capacitance

All input pins
except and R2

f = 1 MHz, V

= 0 V

f = 1 MHz, V

= 0 V

Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the

following situations:

After V

reaches 2.7 V at power-on.

After

RESET

input goes low when stop mode is cancelled.

After

STOPC

input goes low when stop mode is cancelled.

To ensure the oscillation stabilization time at power-on or when stop mode is cancelled,

RESET

STOPC

must be input for at least a duration of t

When using a crystal or ceramic oscillator, consult with the manufacturer to determine what

stabilization time is required, since it will depend on the circuit constants and stray capacitance.

2. Refer to figure 77.

3. Refer to figure 78.

4. Refer to figure 79.

5. Refer to figure 80.

HD404358 Series

High-Speed f

OSC

= 8.5 MHz Version AC Characteristics (HD407A4359: V

= 2.7 to 5.5 V, GND = 0

V, T

= 20 to +75

C; HD40A4354/HD40A4356/HD40A4358: V

= 2.7 to 6.0 V, GND = 0 V, T

= 20

to +75

Item

Symbol Pins

Min

Typ

Max

Unit

Test Condition

Note

Clock oscillation
frequency

OSC

, OSC

0.4

5.0

MHz

1/4 system clock
division ratio

0.4

8.5

MHz

1/4 system clock
division ratio,
V

= 4.5 to 5.5 V

Instruction cycle time

cyc

0.8

0.47

= 4.5 to 5.5 V

Oscillation
stabilization time
(ceramic oscillator)

OSC

, OSC

7.5

Oscillation
stabilization time
(crystal oscillator)

OSC

, OSC

External clock high
width

CPH

OSC

= 4.5 to 5.5 V

External clock low
width

CPL

OSC

= 4.5 to 5.5 V

External clock rise
time

CPr

OSC

= 4.5 to 5.5 V

External clock fall time t

CPf

OSC

= 4.5 to 5.5 V

INT

, EVNB high

widths

INT

, EVNB

cyc

INT

, EVNB low

widths

INT

, EVNB

cyc

RESET

low width

RSTL

RESET

cyc

STOPC

low width

STPL

STOPC

RESET

rise time

RSTr

RESET

STOPC

rise time

STPr

STOPC

Input capacitance

All input pins
except TEST and
R2

f = 1 MHz, V

= 0 V

TEST

f = 1 MHz, V

= 0 V 6

180

f = 1 MHz, V

= 0 V 7

f = 1 MHz, V

= 0 V

HD404358 Series

Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the

following situations:

a. After V

reaches 2.7 V at power-on.

b. After

RESET

input goes low when stop mode is cancelled.

c. After

STOPC

input goes low when stop mode is cancelled.

To ensure the oscillation stabilization time at power-on or when stop mode is cancelled,

RESET

STOPC

must be input for at least a duration of t

When using a crystal or ceramic oscillator, consult with the manufacturer to determine what

stabilization time is required, since it will depend on the circuit constants and stray capacitance.

2. Refer to figure 77.

3. Refer to figure 78.

4. Refer to figure 79.

5. Refer to figure 80.

6. Applies to the HD40A4354, HD40A4356, HD40A4358.

7. Applies to the HD407A4359.

HD404358 Series

Serial Interface Timing Characteristics (HD407A4359: V

= 2.7 to 5.5 V, GND = 0 V, T

= 20 to

+75

C; HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: V

= 2.7 to 6.0 V,

GND = 0 V, T

= 20 to +75

unless otherwise specified)

During Transmit Clock Output

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Transmit clock cycle
time

Scyc

SCK

cyc

Load shown in figure 82

Transmit clock high
width

SCKH

SCK

0.4

Scyc

Load shown in figure 82

Transmit clock low
width

SCKL

SCK

0.4

Scyc

Load shown in figure 82

Transmit clock rise time t

SCKr

SCK

Load shown in figure 82

Transmit clock fall time

SCKf

SCK

Load shown in figure 82

Serial output data delay
time

DSO

300

Load shown in figure 82

Serial input data setup
time

SSI

100

Serial input data hold
time

HSI

200

During Transmit Clock Input

Item

Symbol

Pins

Min

Typ

Max

Unit

Test Condition

Note

Transmit clock cycle
time

Scyc

SCK

cyc

Transmit clock high
width

SCKH

SCK

0.4

Scyc

Transmit clock low
width

SCKL

SCK

0.4

Scyc

Transmit clock rise time t

SCKr

SCK

Transmit clock fall time

SCKf

SCK

Serial output data delay
time

DSO

300

Load shown in figure 82

Serial input data setup
time

SSI

100

Serial input data hold
time

HSI

200

Note:

1. Refer to figure 81.

HD404358 Series

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404354,
HD40A4354, HD404356 and HD40A4356 as an 8-kword version (HD404358, HD40A4358). The 8-kword
and 16-kword data sizes are required to change ROM data to mask manu facturing data since the program
used is for an 8-k or 16-kword version.

This limitation applies when using an EPROM or a data base.

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(4,096 words)

Not used

ROM 4-kword version:
HD404354, HD40A4354

$0000

$000F
$0010

$003F
$0040

$0FFF
$1000

$1FFF

Fill this area with 1s

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(6,144 words)

Not used

ROM 6-kword version:
HD404356, HD40A4356

$0000

$000F
$0010

$003F
$0040

$17FF
$1800

$1FFF

HD404358 Series

HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358

Please check off the appropriate applications and enter the necessary information.

2. ROM code media

Date of order

Customer

Department

Name

ROM code name

LSI number

EPROM:

Ceramic oscillator

Crystal oscillator

External clock

f = MHz

3. System Oscillator (OSC1, OSC2)

The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are

programmed to different EPROMS.

5 MHz operation

8.5 MHz operation

5 MHz operation

8.5 MHz operation

5 MHz operation

8.5 MHz operation

HD404354

HD40A4354

HD404356

HD40A4356

HD404358

HD40A4358

4-kword

6-kword

8-kword

1. ROM size

DP-42S

FP-44A

5. Package

Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTATTM version).

Used

Not used

4. Stop mode

HD404358 Series

100

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent,

copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party's rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi's sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor

products.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD40A4358R

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HD40A4358R