Rev.1.0, Feb.25.2004, page 1 of 29

HD49335F/HF

CDS/PGA & 10-bit A/D TG Converter

REJ03F0100-0100Z

Rev.1.0

Feb.25.2004

Description

The HD49335F/HF is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip.

There are address map and timing generator charts besides this specification. May be contacted to our sales department
if examining the details.

Functions

· Correlated double sampling
· PGA
· Serial interface control
· 10-bit ADC
· Timing generator
· Operates using only the 3 V voltage
· Corresponds to switching mode of power dissipation and operating frequency

Power dissipation: 220 mW (Typ), maximum frequency: 36 MHz (HD49335HF)
Power dissipation: 150 mW (Typ), maximum frequency: 25 MHz (HD49335F)

· ADC direct input mode
· QFP 64-pin package

Features

· Suppresses low-frequency noise, which output from CCD by the correlated double sampling.
· The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and

registers.

· High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier.
· PGA, pulse timing, standby mode, etc., is achieved via a serial interface.
· High precision is provided by a 10-bit-resolution A/D converter.
· Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization

(wave pattern). It is patented by Renesas.

· Timing generator generates the all of pulse which are needed for CCD driving.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 2 of 29

Pin Arrangement

48 47

46 45 44 43 42 41 40

36 35 34

1 2

3 4 5 6 7 8 9

11 12 13 14 15

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

(Top view)

BLKC

CDS_in

BLKFB

BLKSH

Test2
Test1

DLL_C

MON

41cont

SDATA

SCK

XV3
XV2
XV1
DV

1/4clk_o
H2A
DV

1/2clk_o
H1A
DV

RG
Reset
VD_in

VRM

VRT

VRB

BIAS

ADC_in

STROB

SUB_PD

SUB_SW

XSUB

CH4

CH3

CH2

CH1

XV4

1,2

CLK_in

HD_in

Pin Description

Pin No.

Symbol

Description

I/O

Analog(A) or
Digital(D)

Remarks

Odd/even number line detecting pulse output pin

2 mA/10 pF

2 DV

1,2

CDS Digital ground + ADC output buffer ground (0 V)

3 to 12

D0 to D9

Digital output (D0; LSB, D9; MSB)

2 mA/10 pF

13 DV

ADC output buffer power supply (3 V)

14 DV

General ground for TG (0 V)

CLK_in

CLK input (max 72 MHz)

16 HD_in

input

I/O

17 VD_in

input

I/O

Reset

Hardware reset (for DLL reset)

Schmitt trigger

Reset gate pulse output

3 mA/10 pF

20 DV

General power supply for TG (3 V)

21 DV

H1 buffer power supply (3 V)

H1A

H.CCD transfer pulse output-1A

30 mA/165 pF

1/2clk_o

CLK_in 2 divided output. 3 divided output at 3 divided mode

2 mA/10 pF

24 DV

H1 buffer ground (0 V)

25 DV

H1 buffer ground (0 V)

H2A

H.CCD transfer pulse output-2A

30 mA/165 pF

1/4clk_o

CLK_in 4 divided output. 6 divided output at 3 divided mode

2 mA/10 pF

28 DV

H2 buffer power supply (3 V)

29 DV

General power supply for TG (3 V)

HD49335F/HF

Rev.1.0, Feb.25.2004, page 3 of 29

Pin Description (cont.)

Pin No.

Symbol

Description

I/O

Analog(A) or
Digital(D)

Remarks

XV1

V.CCD transfer pulse output-1

2 mA/10 pF

XV2

V.CCD transfer pulse output-2

2 mA/10 pF

XV3

V.CCD transfer pulse output-3

2 mA/10 pF

XV4

V.CCD transfer pulse output-4

2 mA/10 pF

CH1

Read out pulse output-1

2 mA/10 pF

CH2

Read out pulse output-2

2 mA/10 pF

CH3

Read out pulse output-3

2 mA/10 pF

CH4

Read out pulse output-4/XV6 at stripe mode

2 mA/10 pF

XSUB

Pulse output for electronic shutter

2 mA/10 pF

SUB_SW

SUB voltage control output-1. ADCK input

I/O

2 mA/10 pF

SUB_PD

SUB voltage control output-2/ XV5 at stripe mode

2 mA/10 pF

STROB

Flash control output. Input Vgate at Hi of pin 61

I/O

2 mA/10 pF

42 DV

General ground for TG (0 V)

43 AV

Analog

ground

44 ADC_in

converter

input

BIAS

Bias standard resistance

VRB

ADC bottom standard voltage (0.1

F for GND)

VRT

ADC top standard voltage (0.1

F for GND)

VRM

ADC middle standard voltage (0.1

F for GND)

49 AV

Analog power supply (3 V)

BLKC

Black level C pin (1000 pF for GND)

CDS_in

CDS input pin

52 AV

Analog power supply (3 V)

BLKFB

Black level FB pin (1

F between BLKFB and BLKSH)

54 BLKSH

Black

level

S/H

55 AV

Analog

ground

56 Test2

H: Normal operation, L: CDS single operation mode
Input 36; PBLK at testing, Input 37; OBP, Input 38; CPDM,
Input 39; ADCK, Input 40; SP2, Input 41; SP1

I D

Test1

L: Slave mode, H: Master mode

DLL_C

Analog delay DLL external C pin (100 pF for GND)

59 DV

Digital power supply (3 V) CDS, PAG, ADC part

MON

Pulse monitor (SP1, SP2, ADCK, OBP, CPDM, PBLK input)

2 mA/10 pF

61 41cont

Input STROB = pin 41, Input SUB_SW = pin 39 at Low
Input Vgate = pin 41, Input ADCK = pin 39 at Hi

I D

Serial data CS at CDS part

63 SDATA

Input

serial

data

SCK

Input serial clock

HD49335F/HF

Rev.1.0, Feb.25.2004, page 6 of 29

Internal Functions

Functional Description

· CDS input

CCD low-frequency noise is suppressed by CDS (correlated double sampling).
The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *

Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from 2.36 dB to 31.40 dB. *

· ADC input

The center level of the input signal is clamped at 512 LSB (Typ).
Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57

times (4.86 dB) to 5.14 times (14.22 dB). *

· Automatic offset calibration of PGA and ADC
· DC offset compensation feedback for CCD and CDS
· Pre-blanking

Digital output is fixed at clamp level

· Digital outputs enable function

Note: 1. It is not

covered by warranty when 14LSB settings

2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

Operating Description

Figure 1 shows CDS/PGA + ADC function block.

DAC

CDS
AMP

PG
AMP

CDS_in

BLKFB

BLKSH

SH
AMP

VRT

SP1

SP2

10bit
ADC

D0 to D9

BLKC

OBP

ADC_in

Offset

calibration

logic

DC offset

feedback

logic

Gain setting

(register)

Clamp data

(register)

Current

DAC

Figure 1 CDS/PGA Functional Block Diagram

1. CDS (Correlated Double Sampling) Circuit

The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1).
The difference between these two signal levels is extracted by the CDSAMP, which also operates as a
programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK
period, the above sampling and bias operation are paused.

2. PGA Circuit

The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 8 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 255.

In CDSIN mode: Gain = (2.36 dB + 0.033 dB)

× N (LOG linear).

In ADCIN mode: Gain = (0.57 times + 0.001784 times)

× N (linear).

Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 7 of 29

3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings

The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data
(14 LSB to 76 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).

4. DC Offset Compensation Feedback Function

Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (

Gain/H) per 1 H of the feedback loop is given by the following equation. 1H is

the one cycle of the OBP.

Gain/

H = 0.078/(fclk

C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)

Example: When fclk = 20 MHz and C3 = 1.0

Gain/

H = 0.0039

When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8
times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain
(

Gain/H) must be one or lower. If it is two or more, oscillation occurs.

The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the high-speed lead-in operation continues,
and when the offset error is 16 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. (Refer to table 2.)

Table 1

Loop Gain Multiplication Factor during
High-Speed Lead-In Operation

Table 2

High-Speed Lead-In Operation
Cancellation Time

HGain-Nsel

(register settings)

Multiplication

Factor N

HGstop-Hsel

(register settings)

Cancellation

Time

[0]

[1]

[0]

[1]

1 H

8 H

4 H

2 H

5. Pre-Blanking Function

During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (14 to 76 LSB).

HD49335F/HF

Rev.1.0, Feb.25.2004, page 8 of 29

6. ADC Digital Output Control Function

The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.

Table 3

ADC Digital Output Functions

L
L

H
H

L
L

H
H

L
L

H
H

L
L

H
H

L
L

H
H

L
L
L
L

H
X
X
X
X

H
X

L
L

H
H
X

L
L

H
H
X

L
L

H
H

STBY

TEST0

PBLK

MINV

TEST1

LINV

Hi-Z
Same as in table 4.
D9 is inverted in table 4.
D8 to D0 are inverted in table 4.
D9 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D9 is inverted in table 5.
D8 to D0 are inverted in table 5.
D9 to D0 are inverted in table 5.
Output code is set up to Clamp Level.

Low-power wait state
Normal operation

Pre-blanking
Normal operation

Pre-blanking
Test mode

Operating Mode

ADC Digital Output

Note:

1. STBY, TEST, LINV, and MINV are set by register.

Table 4

ADC Output Code (Binary)

L
L

H
H

H
H
H

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

L
L
L
L

H
H
H
H

3
4
5
6

511
512

1020
1021
1022
1023

Output Pin

Output
codes

Steps

Table 5

ADC Output Code (Gray)

L
L
L
L

H
H

L
L
L
L

H
H
H
H

3
4
5
6

511
512

1020
1021
1022
1023

H
H
H

L
L

H
H

L
L

H
H

L
L

H
H

H
H
H

L
L

L
L
L
L

L
L

L
L
L
L

L
L

L
L
L
L

L
L

L
L
L
L

L
L

L
L
L
L

L
L

L
L
L
L

Output Pin

Output
codes

Steps

HD49335F/HF

Rev.1.0, Feb.25.2004, page 9 of 29

7. Adjustment of Black-Level S/H Response Frequency Characteristics

The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the
register settings, as shown in table 6.

Table 6

SHSW CR Time Constant Setting

BLKC

Recommendation value of C is 1000 pF

The SHAMP frequency characteristics can be adjusted by changing the register settings
and the C4 value of the external pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.

2.20 nsec
(72 MHz)

2.30 nsec
(69 MHz)

2.51 nsec
(63 MHz)

2.64 nsec
(60 MHz)

2.93 nsec
(54 MHz)

3.11 nsec
(51 MHz)

3.52 nsec
(45 MHz)

3.77 nsec
(42 MHz)

[3]

[0]

4.40 nsec
(36 MHz)

4.80 nsec
(33 MHz)

[1]

[2]

5.87 nsec
(27 MHz)

6.60 nsec
(24 MHz)

8.80 nsec
(18 MHz)

10.6 nsec
(15 MHz)

17.6 nsec
(9 MHz)

26.4 nsec
(6 MHz)

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

SHSW-fsel (Register setting)

CR Time Constant (Typ)
(cutoff frequency conversion)

Table 7

SHAMP Frequency Characteristics Setting

230 MHz

6800 pF

(240 pF)

56 MHz

18000 pF

(360 pF)

116 MHz

10000 pF

(270 pF)

100 MHz

10000 pF

(560 pF)

"Lo"

"Hi"

24 MHz

27000 pF

(820 pF)

75 MHz

13000 pF

(300 pF)

32 MHz

22000 pF

(750 pF)

49 MHz

15000 pF

(620 pF)

[0]

[1]

[0]

[1]

[0]

[1]

SHA-fsel (Register setting)

LoPwr

(Register setting)

Note: Upper line

Middle line
Lower line

: SHAMP cutoff frequency (Typ)
: Standard value of C4 (maximum value is not defined)
: Minimum value of C4 (do not set below this value)

HD49335F/HF

Rev.1.0, Feb.25.2004, page 11 of 29

Detailed Timing Specifications

Detailed Timing Specifications when CDSIN Input Mode is Used

Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.

CDS_in

SP1

Vth

(2)

(3)

SP2

ADCLK

(7)

Vth

(8)

(9)

(10)

(4)

(1)

(5)

(11)

(6)

(13)

(12)

D0 to D9

Black

level

Signal

level

Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used

Table 8

Timing Specifications when the CDSIN Input Mode is Used

No. Timing

Symbol

Min

Typ Max

Unit

(1)

Black-level signal fetch time

CDS1

-- (1.5)

-- ns

(2) SP1

`Hi'

period

CDS2

Typ

0.8

1/4f

CLK

Typ

1.2

(3)

Signal-level fetch time

CDS3

-- (1.5)

-- ns

(4) SP2

`Hi'

period

CDS4

Typ

0.8

1/4f

CLK

Typ

1.2

(5)

SP1 falling to SP2 falling time

CDS5

Typ

0.85

1/2f

CLK

Typ

1.15

(6)

SP1 falling to ADCLK rising inhibit time

CDS6

-- (5)

-- ns

(7), (8) ADCLK t

min./t

min

CDS7, 8

(9)

ADCLK rising to digital output

holding time

CHLD9

-- (7)

-- ns

(10)

ADCLK rising to digital output delay time

COD10

-- (16)

-- ns

(11)

H1 rising to ADCLK rising time

CDS11

(1/4f

CLK

) --

(12)

H1 rising to SPSIG falling time

CDS12

(1/f

CLK

) --

(13)

H1 rising to SPBLK falling time

CDS13

(1/2f

CLK

) --

OBP Detailed Timing Specifications

Figure 4 shows the OBP detailed timing specifications.

The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black
signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).

CDS_in

OBP

N+1

N+5

N+12

N+13

Note:

OB pulse > 2 clock cycles

OB period *

1. Shifts

±1 clock cycle depending on the OBP input timing.

Figure 4 OBP Detailed Timing Specifications

HD49335F/HF

Rev.1.0, Feb.25.2004, page 12 of 29

Detailed Timing Specifications at Pre-Blanking

Figure 5 shows the pre-blanking detailed timing specifications.

Digital output

(D0 to D9)

ADC

data

Clamp Level

ADC

data

PBLK

ADCLK

× 2 clock

ADCLK

× 10 clock

Vth

Figure 5 Detailed Timing Specifications at Pre-Blanking

Detailed Timing Specifications when ADCIN Input Mode is Used

Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.

ADC_in

(1)

ADCLK

D0 to D9

(2)

Vth

(3)

(5)

(4)

Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used

Table 9

Timing Specifications when ADCIN Input Mode is Used

No. Timing

Symbol

Min

Typ Max

Unit

(1)

Signal fetch time

ADC1

-- (6)

-- ns

(2), (3)

ADCLK t

min./t

min.

ADC2, 3

Typ

0.85

1/2f

ADCLK

Typ

1.15

(4)

ADCLK rising to digital output hold time

AHLD4

-- (14.5)

-- ns

(5)

ADCLK rising to digital output delay time

AOD5

-- (23.5)

-- ns

HD49335F/HF

Rev.1.0, Feb.25.2004, page 13 of 29

Dummy Clamp

It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it
woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes
to clamp processing by dummy bit level. Resister settings are follows.

D12, D11, D10 of address H'F7 (Dummy CP)

0, 0, 0 ; OFF

0, 0, 1 ; +32

0, 1, 0 ; +64

0, 1, 1 ; +96

1, 1, 1 ; +224

The amount of offset are changes automatically
depends on PGA gain in the LSI.

D8, D8 of address H'F7 (DMCG)
The amount of feed back current can be
reduced with only dummy clamp.
Data = 0:1/4
1:1/8
2:1/16
3:1/32

D10 to D12 of address H'F7

Note: OB/Dummy switching part has 1/8 hysteresis of threshold value.

D8 to D9 of address H'F7

Digital output

CDS
AGC

CDS_in

BLKFB

BLKSH

SH
AMP

VRT

SP1

SP2

SP1

on/off

Clamp level

(+)

(

ADC

DET

Current

cell

Dummy

DET

Detect 4clk
from OPDM edge

Detect 8clk
from OBP edge

Figure 7 Internal Bias Circuitry

HD49335F/HF

Rev.1.0, Feb.25.2004, page 14 of 29

Absolute Maximum Ratings

(Ta = 25

°C)

Item Symbol

Ratings

Unit

Power supply voltage

4.1

Analog input voltage

0.3 to AV

+0.3

Digital input voltage

0.3 to DV

+0.3

Operating temperature range

20 to +85

°C

Power dissipation

590

Storage temperature

Tstg

55 to +125

°C

Power supply voltage

Vopr

2.70 to 3.30

Note: AV

, AV

are analog power

source systems

of CDS, PGA, and ADC.

1, DV

1 are digital power source systems of CDS, PGA and ADC.

2, DV

2 are buffer power source systems of ADC output.

3, DV

3 are general digital power source systems of TG.

4, DV

4 are buffer power source systems of H1 and H2.

Pin 2 multi bonds the DV

1 and DV

When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output

When Hi, pin 41 = Vgate input, pin 39 = ADCK input

Electrical Characteristics

(Unless othewide specified, Ta = 25°C, AV

= 3.0 V, DV

= 3.0 V, and R

BIAS

= 33 k

)

· Items Common to CDSIN and ADCIN Input Modes

Item Symbol

Min

Typ

Max

Unit

Test

Conditions

Remarks

Power supply voltage
range

2.70 3.00

3.30 V

CLK

MHz

LoPwr = low *

HD49335HF

Conversion frequency

CLK

low

5.5

MHz

LoPwr = high *

HD49335F

IH2

3.0

2.25

-- DV

Digital input voltage

IL2

3.0

0.6

CS, SCK, SDATA

0.5

= 1 mA

Digital output voltage

-- 0.5

V I

= +1 mA

-- 50

A V

= 3.0 V

Digital input current

50 -- --

A V

= 0 V

ADC

resolution RES

10 10

10 bit

ADC integral linearity

INL

(2)

LSBp-p

CLK

= 25 MHz

ADC differential linearity+ DNL+

0.3

0.99

LSB

CLK

= 25 MHz

ADC differential linearity DNL

0.99

0.3

LSB

CLK

= 25 MHz

Sleep current

SLP

100 0 100

Digital input pin is
set to 0 V, output
pin is open

Standby current

STBY

mA Digital I/O pin is set

to 0 V

Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.

2. 2 divided mode: f

CLK

= 1/2CLK_in

3 divided mode: f

CLK

= 1/3CLK_in

3. Values within parentheses ( ) are for reference.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 15 of 29

Electrical Characteristics (cont.)

(Unless othewide specified, Ta = 25°C, AV

= 3.0 V, DV

= 3.0 V, and R

BIAS

= 33 k

)

· Items for CDSIN Input Mode

Item Symbol

Min

Typ

Max

Unit

Test

Conditions

Remarks

Consumption current (1)

DD1

-- 84 96.6 mA

CLK

= 36 MHz

CDSIN mode
LoPwr = low

Consumption current (2)

DD2

-- 58 66.7 mA

CLK

= 20 MHz

CDSIN mode
LoPwr = high

CCD offset tolerance range V

CCD

(100)

-- (100) mV

Timing specifications (1)

CDS1

-- (1.5) -- ns

Timing specifications (2)

CDS2

Typ

0.8

1/4f

CLK

Typ

1.2

Timing specifications (3)

CDS3

-- (1.5) -- ns

Timing specifications (4)

CDS4

Typ

0.8

1/4f

CLK

Typ

1.2

Timing specifications (5)

CDS5

Typ

0.85 1/2f

CLK

Typ

1.15 ns

Timing specifications (6)

CDS6

1 5 9 ns

Timing specifications (7)

CDS7

-- 1/2f

CLK

Timing specifications (8)

CDS8

-- 1/2f

CLK

Timing specifications (9)

CHLD9

(7) --

= 10 pF

Timing specifications (10)

COD10

(16) --

= 10 pF

Timing specifications (11)

CDS11

(1/4f

CLK

) --

Timing specifications (12)

CDS12

(1/f

CLK

) --

Timing specifications (13)

CDS13

(1/2f

CLK

) --

Refer to table 8

CLP(00) --

(14)

LSB

CLP(09) --

(32)

LSB

Clamp level

CLP(31) --

(76)

LSB

AGC(0)

4.4 2.4 0.4 dB

AGC(63)

4.1 6.1 8.1 dB

AGC(127)

12.5 14.5 16.5 dB

AGC(191)

21.0 23.0 25.0 dB

PGA gain at CDS input

AGC(255)

29.4 31.4 33.4 dB

DLL_2 11

MHz

DLL_3 7

MHz

DLL operation frequency

DLL_4 5.5

MHz

T/G 3/1divided operation
frequency range

CLK_in3 28.6

28.6

MHz

CLK

= 1/3CLK_in3

2.94 2.97 -- V

Buff,

= 5 mA

30 mA Buff, I

= +5 mA

2.89 2.94 -- V

Buff,

= 5 mA

112

14 mA Buff, I

= +5 mA

2.91 2.96 -- V

Buff,

= 3 mA

10 mA Buff, I

= +3 mA

2.85 2.93 -- V

Buff,

= 2 mA

129

4 mA Buff, I

= +2 mA

2.69 2.86 -- V

Buff,

= 2 mA

H Buffer output voltage

115

262

2 mA Buff, I

= +2 mA

2.81 2.90 -- V

= 2 mA

RG output voltage

-- 78 141 mV

= +2 mA

Notes: 1. Define digital output full scall with 1 V input as 0 dB.

2. Number of master steps: 60 steps, DLL current High

3. Number of master steps: 40 steps, DLL current Low

4. Number of master steps: 60 steps, DLL current Low

5. Values within parentheses ( ) are for reference.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 16 of 29

Electrical Characteristics (cont.)

(Unless othewide specified, Ta = 25°C, AV

= 3.0 V, DV

= 3.0 V, and R

BIAS

= 33 k

)

· Items for ADCIN Input Mode

Item Symbol

Min

Typ

Max

Unit

Test

Conditions

Remarks

Consumption current (3)

DD3

-- 32 38.4 mA

CLK

= 36 MHz

ADCIN mode
LoPwr = low

Consumption current (4)

DD4

-- 22 27.5 mA

CLK

= 25 MHz

ADCIN mode
LoPwr = high

Timing specifications (14)

ADC1

-- (6) -- ns

Timing specifications (15)

ADC2

Typ

0.85 1/2f

ADCLK

Typ

1.15 ns

Timing specifications (16)

ADC3

Typ

0.85 1/2f

ADCLK

Typ

1.15 ns

Timing specifications (17)

AHLD4

-- (14.5)

-- ns

= 10 pF

Timing specifications (18)

AOD5

-- (23.5)

-- ns

= 10 pF

Refer to table 9

Input current at ADC input

IIN

CIN

110 --

110

A V

= 1.0 to 2.0 V

Clamp level at ADC input

OF2

(512)

LSB

GSL(0)

0.45 0.57 0.72 Times

GSL(63)

1.36 1.71 2.16 Times

GSL(127)

2.27 2.86 3.60 Times

GSL(191)

3.18 4.00 5.04 Times

PGA gain at ADC input

GSL(255)

4.08 5.14 6.47 Times

Note : Values within parentheses ( ) are for reference.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 17 of 29

Serial Interface Specifications

Timing Specifications

SDATA

STD2(Upper data)

STD1(Lower data)

address(address)

SCK

D11

D10

D13

D12

D15

D14

INT1

INT2

Latches SDATA
at SCK rising edge

Data is determined
at CS rising edge

Figure 8 Serial Interface Timing Specifications

Item Min Max
f

SCK

-- 5

MHz

INT1,2

ns --

Notes: 1. 3 byte continuous communications.

2. Input SCK with 24 clock when CS is Low.

3. It becomes invalid when data communications are stopped on the way.

4. Data becomes a default with hardware reset.

5. Input more than double frequency of SCK to the CLK_in when transfer

the serial data.

The Kind of Data

Data address has 256 type. H'00 to H'FF

H'00
:
:
H'EF

Data at timing generator part

H'F0
:
:
H'FF

Data at CDS part

Address map of each data referred to other sheet.
Details of timing generator refer to the timing chart on the other sheet together with this specification.
This specification only explains about the data of CDS part.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 18 of 29

Explanation of Serial Data of CDS Part

Serial data of CDS part are assigned to address H'F0 to H'F8. Functions are follows.

Address

STD1[7:0] (L)

PGA gain

STD2[15:8] (H)

D0 D15 D14 D13

test_I1

· PGA gain (D0 to D7 of address H'F0)

Details are referred to page 5 block diagram.

At CDS_in mode: 2.36 dB + 0.132 dB

N (Log linear)

At ADC_in mode: 0.57 times + 0.01784 times

N (Times linear)

: Full-scale digital output is defined as 0 dB when 1 V is input.

Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.

(1) Level dia explain

CDS

PGA

0 dB when set N = 18 which correspond to 2.36 dB

ADC

(2) Level dia on the circuit

CDS

PGA

3.64 dB + 0.132 dB

× N

(CDS = 0 dB)

ADC

2 V

1023

(1.0 V)

(2.0 V)

(1023)

Figure 9 Level Dia of PGA

· Test_I1 (D13 to D15 of address H'F0)

It controls the standard current of analog amplifier systems of CDS, PGA. Use data = 4 (D15 = 1) normally.

When data = 0, 50% current value with default
When data = 4, default
When data = 7, 150% current value with default

Address

STD1[7:0] (L)

STD2[15:8] (H)

D0 D15 D14 D13 D12 D11 D10 D9

SHA_fsel

test_I2

SHSW_fsel

test0

MINV

LINV

STBY

SLP

· SLP and STBY (D0, D1 of address H'F1)

SLP:

Stop the all circuit. Consumption current of CDS part is less than 10

µA.

Start up from offset calibration when recover is needed.

STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.

Allow 50 H time for feedback clamp is stabilized until recover.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 19 of 29

· Output mode (D2 to D4 of address H'F1 and address H'F4 of D6)

It is a test mode. Combination details are table 3 to 5. Normally set to all 0.

· SHA-fsel (D8 to D9 of address H'F1)

It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 8. To get rough idea, set the
double cut off frequency point with using.

· SHSW-fsel (D10 to D13 of address H'F1)

It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page
8. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.

· Test_I2 (D14 to D15 of address H'F1)

Current of ADC analog part can be set minutely. Normally use data = 0.

0: Default (100%)
1: 150%
2: 50%
3: 80%

Address

STD1[7:0] (L)

HGain-Nsel

STD2[15:8] (H)

D0 D15 D14 D13 D12 D11 D10 D9

Clamp level

Reset

AD_sel

CDS_buff

Low_pwr

HGstop-Hsel

· Clamp (D0 to D4 of address H'F2)

Determine the OB part level with digital code of ADC output.

Clamp level = setting data

2 + 14

Default data is 9 = 32 LSB.

· HGstop-Hsel, HGain-Nsel (D8 to D11 of address H'F2)

Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/1 to previous field, its switch to high speed leading mode.

· Low_PWR (D12 of address H'F2)

Switch circuit current and frequency characteristic.

Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee

· ADSEL (D14 of address H'F2)

Data = 0: Select CDS_in
Data = 1: Select ADC_in

· Reset (D15 of address H'F2)

Software reset.

Data = 1: Normal
Data = 0: Reset

Offset calibration should be done when starting up with using this bit. Details are referred to page 23.

Address

STD1[7:0] (L)

STD2[15:8] (H)

D0 D15 D14 D13 D12 D11 D10 D9

· Address H'F3 are all testing data.

Normally set to all 0., or do not transfer the data.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 20 of 29

Address

STD1[7:0] (L)

STD2[15:8] (H)

D12 D11 D10 D9

Gray_test

VD latch

MON

Gray code

H12_Buff

· MON (D0 to D2 of address H'F4)

Select the pulse which output to pin MON (pin 60).

When D0 to D2: 0, Fix to Low

When 1, ADCLK

When 2, SP1

When 3, SP2

When 4, OBP

When 5, PBLK

When 6, CPDM

When 7, DLL_test

· H12Baff (D3 to D6 of address H'F4)

Select the buffer size which output to pin H1A, H2A (pin 22, 26).

D3: 2 mA buffer
D4: 4 mA buffer
D5: 10 mA buffer
D6: 14 mA buffer

Above data can be on/off individually. Default is D6 can be on only. (18 mA buffer)

· VD latch (D7 of address H'F4)

Data = 0: Gain data is determined when CS rising
Data = 1: Gain data is determined when VD falling

Differential Code and Gray Code (D8 to D12 of address H'F4)

· Gray code (D8 to D9 of address H'F4)

DC output code can be change to following type.

Gray Code [1]

Gray Code [0]

Output Code

0 0 Binary

code

0 1 Gray

code

Differential encoded binary

Differential encoded gray

· Serial data setting items (D10 to D12 of address H'F4)

Setting Bit

Setting Contents

Gray_test[0]
Gray_test[1]

Standard data output timing control signal
(Refer to the following table)

Gray_test[2]

ADCLK polar with OBP. (Lo

Positive edge, HI

Negative edge)

· Standard data output timing

Gray_test[1] Gray_test[0] Standard Data Output Timing
Low Low Third

and

fourth

Low

High

Fourth and fifth

High

Low

Fifth and sixth

High High Sixth

and

seventh

HD49335F/HF

Rev.1.0, Feb.25.2004, page 21 of 29

Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in
parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC output.
Figure 11 indicates the timing specifications.

ADC

Differential SW(D9)

Carry bit
round

+
-

Gray SW(D8)

Standard data
control signal
(D12,D11,D10)

Standard
data
selector

10-bit
output

2clk_DL

Gray

Binary

conversion

Figure 10 Differential Code, Gray Code Circuit

ADCLK

OBP

Digital output

(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)

(In case of select the positive edge of ADCLK with D12)

(In case of select the positive polar)

Differential data

Standard

data

Differential data

Figure 11 Differential Code Timing Specifications

To use differential code, complex circuit is necessary at DSP side.

(1) Differential coded

From ADC

Standard data
control signal

Carry bit
round

2clk_DL

Standard
data
selector

D11

D11
D10

D10

Gray

Binary

(2) Gray

Binary conversion

Figure 12 Complex Circuit Example

Address

STD1[7:0] (L)

STD2[15:8] (H)

D12 D11 D10 D9

P_SP1

P_SP2

P_ADCLK

P_RG

DLL

steps

DLL

current

2,3 divided

select

Address

STD1[7:0] (L)

STD2[15:8] (H)

D12

D10

D15 D14 D13

P_SP2

P_SP1

P_ADCLK

P_RG

HD49335F/HF

Rev.1.0, Feb.25.2004, page 22 of 29

· Address H'F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address

H'F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.

D15 of address H'F8 = 0

D15 of address H'F8 = 1

Divided mode

2 divided, 1/4 phase select

3 divided, 1/6 phase select

D0 to D7 of address H'F5

Valid

Invalid

D0 to D14 of address H'F8

Invalid

Valid

· Phase settings of high speed pulse (address H'F5 to H'F8)

(1) Select the 1/4 phase from figure 13 at 2 divided mode (D15 = 0 of address H'F8).

Select the 1/6 phase from figure 14 at 3 divided mode (D15 = 1 of address H'F8).
·····P_SP1, P_SP2, P_ADCLK, P_RG

(2) Then select the necessary delay time from figure 15.

·····DL_SP1, DL_SP2, DL_RG, DL_ADCLK
RG can be set both of rising / falling edge optionally.

Data = 0

Data = 1

Data = 3

Data = 2

P_SP1
P_SP2

Data = 0

Data = 1

Data = 3

Data = 2

P_ADCLK
P_RG

Figure 13 2 Divided Mode, 1/4 Phase Select (Valid at D15 = 0 of address H'F8)

Data = 5

Data = 2

Data = 3

Data = 4

Data = 1

Data = 0

P_SP1
P_SP2

Data = 0

Data = 3

Data = 4

Data = 5

Data = 2

Data = 1

P_ADCLK
P_RG

Figure 14 3 Divided Mode, 1/6 Phase Select (Valid at D15 = 1 of address H'F8)

Default Value of Each Phases

P_SP1

P_SP2

P_ADCLK P_RG

divided

mode

1 2 1 0

divided

mode

0 3 1 5

Note: 50% of duty pulse makes tr, tf of RG by DLL.

Address

STD1[7:0] (L)

STD2[15:8] (H)

D12 D11 D10 D9

DL_SP2

DL_SP1

DL_RG_f

DL_RG_r

DL_ADCLK

CDS_test

Address

STD1[7:0] (L)

STD2[15:8] (H)

D12 D11 D10 D9

Dummy

clamp th

Dummy

clamp current

HD49335F/HF

Rev.1.0, Feb.25.2004, page 23 of 29

(3) Setting method of DLL

Default

DLL step decides the how many divide the 1
cycle of sensor CLK. For reference,
set 1 ns(when 2 ns DLL_current bit = 0,
when 1 set to 1 ns)
Can be set 16 to 64 steps by 4 steps.
Steps = 4 + (4

× N); possible to set N = 3 to 15

Recommended steps is clk_in = when 11 to 14 MHz: H'0E(60 steps)

when 14 to 22MHz: H'09(40 steps)

when 22 to 50MHz: H'1E(60 steps)

when 50 to 72MHz: H'19(40 steps)

Can be change each 4 type of pulse 0 to 15 steps with
1 step. (1 ns or 2 ns divide)
Select the 2 ns divide when sensor CLK is less than
15 MHz.

DL_RG

DL_SP1

DL_ADCLK

DL_SP2

DL_ADCLK

DLL_C

Control voltage

P_ADCLK

AND

DLL = 64 steps

ADCLK(0)

(In phase with H1)

DLL = 15 steps

DL_SP1

P_SP1

DLL = 15 steps

DL_SP2

(Falling)

(Rising)

P_SP2

DLL = 15 steps

ADCLK

(0, 0)

DL_RG

DLL = 15 steps

Figure 15 Analog Delay (DLL) Circuit Block.

· CDS_test (D12 of address H'F6)

It is testing data. Normally set to 0.

· Dummy clamp current (D9 to 8 of address H'F7)

Data = When 0, 1/4

When 1, 1/8

When 2, 1/16

When 3, 1/32

Details are refer to page 12.

· Dummy clamp threshold (D12 to 10 of address H'F7)

Data = When 0, off

When 1, +32

When 2, +64

When 3, +96

When 4, +128

When 5, +160

When 6, +192

When 7, +224

Details are refer to page 12.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 24 of 29

Operation Sequence at Power On

(1) Resistor transfer of TG part

(2) DLL data transfer of CDS part
(3) Reset=L of CDS part
(4) Reset=H of CDS part
(5) Other data of CDS part

: Wait more than 6clk after release the hardware Reset and then transfer
the necessary data to TG part.
: Transfer the phase data of RG, SP1, SP2, ADCLK of CDS part.
: Transfer Reset bit = 0 of address H'F2.
: Transfer Reset bit = 1 of address H'F2. (Reset release)
: Transfer the SH_SW_fsel and other PGA.

CLK_in

Hardware
Reset

3clk or more

6clk or more

(1)

2ms or more

(Charge of external C)

40,000ADCLK or more

(offset calibration)

(2) (3)

(4)

CDS_Reset = Low

(5)

Note: At 2 divided mode: ADCLK = 1/2CLK_in

At 3 divided mode: ADCLK = 1/3CLK_in

SP1
SP2
ADCLK
OBP
etc.

RESET bit

Automatic adjustment taking
40,000ADCLK period after
Reset cancellation

Before transfer the Reset bit = 0, TG series pulse need to be settled, so address

H'00 to H'EF of TG part and H'F4 to H7F7 of CDS part should transfer in advance.

HD49335
serial data transfer

Must be stable within the operating
power supply voltage range

Start control
of TG and
camera DSP

Automatic offset
calibration

The following describes the above serial data transfer. For details of resistor settings are referred to serial data
function table.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 26 of 29

Notice for Use

1. Careful handling is necessary to prevent damage due to static electricity.
2. This product has been developed for consumer applications, and should not be used in non-consumer applications.
3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to

prevent latchup, a ceramic capacitor of 0.1 µF or more and an electrolytic capacitor of 10 µF or more should be
inserted between the ground and power supply.

4. Common connection of AV

and DV

should be made off-chip. If AV

and DV

are isolated by a noise filter,

the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.

5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure

below.

HD49335

1 to 4

Noise filter

Analog
+3.0V

HD49335

1 to 4

100

µH

0.01

µF

Noise filter

Example of noise filter

Digital
+3.0V

0.01

µF

6. Connect AV

and DV

off-chip using a common ground. If there are separate analog system and digital system

set grounds, connect to the analog system.

7. When V

is specified in the data sheet, this indicates AV

and DV

8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power

supply or ground pins or left open to prevent crosstalk in adjacent analog pins.

9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of

bending than Fe-type lead material, careful handling is necessary.

10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as

solder dipping cannot be used.

11. Serial communication should not be performed during the effective video period, since this will result in degraded

picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the
HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked.

12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in

accordance with the power-on operating sequence (see page 24).

13. Ripple noise of DC/DC converter which generates the voltage of analog part should set under 50 dB with power

supply voltage.

HD49335F/HF

Rev.1.0, Feb.25.2004, page 27 of 29

Example of Recommended External Circuit

· Slave mode
Pin 57(Test1 = Low)

24 23 22 21 20 19 18 17

57 58 59 60 61 62 63 64

HD49335

0.1

47/6

1000p

100p

XV4

CH1

CH2

CH3

CH4

XSUB

SUB_SW/ADCK_in

SUB_PD

STROB/Vgate

ADC_in

BIAS

VRB

VRT

VRM

HD_in

CLK_in

1,2

XV2

XV1

1/4clk_o

H2A

1/2clk_o

H1A

Reset

BLKC

CDS_in

BLKFB

BLKSH

Test2

Test1

DLL_C

MON

41pin_cont

Sdata

XV3

VD_in

SCK

0.1

47/6

0.1

3.0V

Reset(Normally Hi)

to CCD

0.1

33k

to CCD

ID pulse

to V.Baff

· Master mode
Pin 57(Test1 = Hi)

24 23 22 21 20 19 18 17

57 58 59 60 61 62 63 64

HD49335

0.1

47/6

1000p

100p

XV4

CH1

CH2

CH3

CH4

XSUB

SUB_SW/ADCK_in

SUB_PD

STROB/Vgate

ADC_in

BIAS

VRB

VRT

VRM

HD_in

CLK_in

1,2

XV2

XV1

1/4clk_o

H2A

1/2clk_o

H1A

Reset

BLKC

CDS_in

BLKFB

BLKSH

Test2

Test1

DLL_C

MON

41pin_cont

Sdata

Unit: R:

C: F

XV3

VD_in

SCK

0.1

47/6

0.1

CCD signal input

3.0V

to CCD

0.1

33k

61pin = Low: Pin 41 is STROB output

Pin 39 is SUB_SW output

61pin = Hi: Pin 41 is Vgate output

Pin 39 is Hiz

61pin = Low: Pin 41 is STROB output

Pin 39 is SUB_SW output

61pin = Hi: Pin 41 is Vgate output

Pin 39 is Hiz

to V.Baff

Pin 56 = Low: TESTIN mode. Please do not use.

Low

Pin 57

Slave mode

Master mode

Mode

CLK, HD, VD input from SSG.

HD, VD output

Specification

Serial data input

from
Pulse generator

to
Camera
signal
processor

HD49335F/HF

Rev.1.0, Feb.25.2004, page 28 of 29

· CDS single operating mode
Pin 56(Test2 = Low)

Pin 57 is "Don't care" in this mode.

Serial data when CDS single operation mode are following resister specifications.

(Latch timing specification is same as normal mode)

24 23 22 21 20 19 18 17

57 58 59 60 61 62 63 64

HD49335

0.1

47/6

1000p

100p

PBLK

OBP

CP_DM

ADCK

SP2

SP1

ADC_in

BIAS

VRB

VRT

VRM

1,2

Reset

BLKC

CDS_in

BLKFB

BLKSH

Test2

Test1

DLL_C

MON

41pin_cont

Sdata

Unit: R:

C: F

SCK

0.1

47/6

0.1

3.0V

Reset(Normally Hi)

0.1

33k

Pin changes are not effective with pin61.

ADC_in

INT2

fsck

tsu

SCK

tho

INT1

SDATA

D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15

D00

D01

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Resister 4

Resister 3

Resister 0

Resister 1

Resister 7

Resister 5

Resister 6

Resister 2

D02

Test_I1 (0)

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15 Test_I1 (2)

Test_I1 (1)

PGA(0) LSB

SLP

Reset

ADSEL

Low:CDSin
High:ADin

LoPwr

STBY

PGA(1)

PGA(2)

PGA(3)

PGA(4)

PGA(5)

PGA(6)

PGA(7) MSB

SHSW-fsel(3)

Test_I2 (1)

Test_I2 (0)

Output mode(LINV)

Output mode(MINV)

Output mode(Test0)

SHA-fsel(0)

SHA-fsel(1)

SHSW-fsel(0)

SHSW-fsel(1)

SHSW-fsel(2)

MON(0)

MON(1)

Gray_ts(0)

Gray_ts(2)

Gray_ts(1)

MON(2)

H12Baff(0)

H12Baff(1)

H12Baff(2)

H12Baff(3)

VD latch

Gray1

Gray2

P_SP1(0)

P_SP1(1)

DLL_CK(2)

DLL_current

DLL_CK(3)

P_SP2(0)

P_SP2(1)

P_ADCLK(0)

P_ADCLK(1)

P_RG(0)

P_RG(1)

DLL_CK(0)

DLL_CK(1)

DL_SP1(0)

DL_SP1(1)

DL_ADCLK(2)

CDS_test

DL_ADCLK(3)

DL_SP1(2)

DL_SP1(3)

DL_SP2(0)

DL_SP2(1)

DL_SP2(2)

DL_SP2(3)

DL_ADCLK(0)

DL_ADCLK(1)

DL_RG_r(0)

DL_RG_r(1)

Dummy CP(0)

Dummy CP(2)

Dummy CP(1)

DL_RG_r(2)

DL_RG_r(3)

DL_RG_f(0)

DL_RG_f(1)

DL_RG_f(2)

DL_RG_f(3)

DMCG(0)

DMCG(1)

Clamp(0)

Clamp(1)

Clamp(2)

Clamp(3)

Clamp(4)

HGstop-Hsel(0)

HGstop-Hsel(1)

HGain-Nsel(0)

HGain-Nsel(1)

test

CCD signal input

Serial data input

to
Camera
signal
processor

Low: Normal
High: Sleep
Low: Normal
High: Standby

Low: Normal
High: Low power

Low: Reset
High: Normal

Keep safety first in your circuit designs!

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble

may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's

application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,

diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of

publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.

The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor

home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to

evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life

is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and

cannot be imported into a country other than the approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

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http://www.renesas.com

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