Rev.1.0, Apr 20, 2004, page 1 of 22

HD49338F/HF

CDS/PGA & 12-bit A/D Converter

REJ03F0107-0100Z

Rev.1.0

Apr 20, 2004

Description

The HD49338F/HF is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera
digital signal processing systems together with a 12-bit A/D converter in a single chip.

Functions

Correlated double sampling
PGA
Offset compensation
Serial interface control
12-bit ADC
Operates using only the 3 V voltage
Corresponds to switching mode of power dissipation and operating frequency

Power dissipation: 150 mW (Typ), maximum frequency: 36 MHz
Power dissipation: 100 mW (Typ), maximum frequency: 25 MHz

ADC direct input mode
Y-IN direct input mode
QFP 48-pin package

Features

Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling.
The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and

registers.

High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier.
Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change and

the CCD offset in the CDS (correlated double sampling) amplifier input.

PGA, standby mode, etc., is achieved via a serial interface.
High precision is provided by a 12-bit-resolution A/D converter.

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 2 of 22

Pin Arrangement

ADCIN

Y IN

BIAS

BLKC

CDSIN

BLKFB

BLKSH

D10

D11

36 35

34 33 32 31 30 29 28

26 25

1 2

3 4 5 6 7 8 9

11 12

(Top view)

(NC)

SPSIG

SPBLK

OBP

PBLK

ADCLK

DRDV

VRM

VRT

VRB

OEB

SDATA

SCK

Pin Description

Pin No.

Symbol

Description

I/O

Analog(A) or
Digital(D)

Digital output (LSB)

2 to 11

D1 to D10

Digital output

D11

Digital output (MSB)

13 DRDV

Output buffer power supply (3 V)

14 DV

Digital ground (0 V)

15 DV

Digital ground (0 V)

ADCLK

ADC conversion clock input pin

17 DV

Digital power supply (3 V)

18 DV

Digital power supply (3 V)

PBLK

Preblanking input pin

OBP

Optical black pulse input pin

SPBLK

Black level sampling clock input pin

SPSIG

Signal level sampling clock input pin

No connection pin

24 DV

Output power supply (3 V)

25 AV

Analog ground (0 V)

26 AV

Analog ground (0 V)

27 AV

Analog power supply (3 V)

BLKSH

Black level S/H pin

BLKFB

Black level FB pin

30 CDSIN

CDS

input

BLKC

Black level C pin

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 3 of 22

Pin Description (cont.)

Pin No.

Symbol

Description

I/O

Analog(A) or
Digital(D)

BIAS

Internal bias pin
Connect a 33 k

resistor between BIAS and AV

-- A

33 AV

Analog power supply (3 V)

Y IN

Y input pin

35 AV

Analog ground (0 V)

36 ADCIN

ADC

input

VRM

Reference voltage pin 1
Connect a 0.1

�

F ceramic capacitor between VRM and AV

-- A

VRT

Reference voltage pin 3
Connect a 0.1

�

F ceramic capacitor between VRT and AV

-- A

VRB

Reference voltage pin 2
Connect a 0.1

�

F ceramic capacitor between VRB and AV

-- A

40 DV

Digital power supply (3 V)

41 DV

Digital ground (0 V)

42 OEB

Digital output enable pin

43 DV

Digital power supply (3 V)

44 DV

Digital power supply (3 V)

45 DV

Digital ground (0 V)

Serial interface control input pin

SDATA

Serial data input pin

SCK

Serial clock input pin

Note: 1. With pull-down resistor.

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 6 of 22

Internal Functions

Functional Description

CDS input

CCD low-frequency noise is suppressed by CDS (correlated double sampling).
The signal level is clamped at 56 LSB to 304 LSB by resister during the OB period.
Gain can be adjusted using 10 bits of register (0.033 dB steps) within the range from �2.36 dB to 31.40 dB. *

ADC input

The center level of the input signal is clamped at 2048 LSB (Typ).
Gain can be adjusted using 10 bits of register (0.00446 times steps) within the range from 0.57 times (�4.86 dB) to

5.14 times (14.22 dB). *

Y-IN input

The input signal is clamped at 280 LSB (Typ) by SYNC Tip clamp.

Automatic offset calibration of PGA and ADC
DC offset compensation feedback for CCD and CDS
Pre-blanking

CDS input operation is protected by separating it from the large input signal.
Digital output is fixed at 32 LSB.

Digital output enable function

Note: 1. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

Operating Description

Figure 1 shows CDS/PGA + ADC function block.

Offset

calibration

logic

DC offset

feedback

logic

DAC

CDS
AMP

PG
AMP

ADCIN

CDSIN

BLKFB

BLKSH

Gain setting

(register)

Clamp data

(register)

OBP

SH
AMP

BLKC

VRT

Current

DAC

12-bit

ADC

D0 to D11

Figure 1 HD49338F/HF Functional Block Diagram

1. CDS (Correlated Double Sampling) Circuit

The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation
period. During the PBLK period, the above sampling and bias operation are paused.

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 7 of 22

2. PGA Circuit

The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain
using 10 bits of register.
The equation below shows how the gain changes when register value N is from 0 to 1023.

In CDSIN mode: Gain = (�2.36 dB + 0.033 dB)

� N (LOG linear).

In ADCIN mode: Gain = (0.57 times + 0.00446 times)

� N (linear).

Full-scale digital output is defined as 0 dB (one time) when 1 V is input.

3. Automatic Offset Calibration Function and Black-Level Clamp Data Setting

The DAC DC voltage added to the output of the PGAMP is adjusted by automatic offset calibration.
The data, which cancels the output offset of the PGAMP and the input offset of the ADC, and the clamp data (56
LSB to 304 LSB) set by register are added and input to the DAC.
The automatic offset calibration starts automatically after the RESET mode set by register 1 is cancelled and
terminates after 40000 clock cycles (when fclk = 20 MHz, 2 ms).

4. DC Offset Compensation Feedback Function

Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets
(including the CCD offset and the CDSAMP offset) are compensated for.
The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged
by the current DAC (see figure 1).
The open-loop differential gain (

Gain/H) per 1 H of the feedback loop is given by the following equation. 1H is

the one cycle of the OBP.

Gain/

H = 0.078/(fclk

�

C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor)

Example: When fclk = 20 MHz and C3 = 1.0

�

Gain/

H = 0.0039

When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop
gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 2 times, 4 times, 8
times, or 16 times by changing the register settings (see table 1). Note that the open-loop differential gain
(

Gain/H) must be one or lower. If it is two or more, oscillation occurs.

The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be
selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 64 LSB, the high-speed lead-in operation continues,
and when the offset error is 64 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4
H, or 8 H depending on the register settings. See table 2.

Table 1

Loop Gain Multiplication Factor during
High-Speed Lead-In Operation

Table 2

High-Speed Lead-In Operation
Cancellation Time

HGain-Nsel

(register settings)

Multiplication

Factor N

HGstop-Hsel

(register settings)

Cancellation

Time

[0]

[1]

[0]

[1]

1 H

8 H

4 H

2 H

5. Pre-Blanking Function

During the PBLK input period, the CSD input operation is separated and protected from the large input signal. The
ADC digital output is fixed to clamp data (56 to 304 LSB).

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 8 of 22

6. ADC Digital Output Control Function

The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.

Table 3

ADC Digital Output Functions

Operating Mode

ADC Digital Output

Low-power wait state
Output Hi-Z
Normal operation

Pre-blanking
Normal operation

Pre-blanking
Test mode

Hi-Z
Hi-Z
Same as in table 4.
D11 is inverted in table 4.
D10 to D0 are inverted in table 4.
D11 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D11 is inverted in table 5.
D10 to D0 are inverted in table 5.
D11 to D0 are inverted in table 5.
Output code is set up to Clamp Level.

Notes:

1. STBY, TEST, LINV, and MINV are set by register.
2. Mode setting for the OEB and the PBLK are done by external input pins.
3. The polarity of the PBLK pin when the register setting is SPinv is low.

X
X
H
H
H
H

H
H
H
H

X
X
X
X

H
H

L
L

H
H

L
L

H
H

L
L

H
H

L
L

H
H

L
L

H
H

L
L

H
H

X
X

H
X

X
X

L
L

H
H
X

L
L

H
H
X

L
L

H
H

X
X

X
H

STBY

OEB

D11 D10

PBLK

MINV

LINV

TEST0

TEST1

Table 4

ADC Output Code

Output Pin
Output
codes

Steps

0
1
2
3
4
5
6

2047
2048

4092
4093
4094
4095

L
L

H
H

L
L

H
H

L
L
L
L

H
H
H

H
H
H
H

L
L
L
L
L
L
L

H
H
H
H

L
L
L
L
L
L
L

H
H
H
H

L
L
L
L
L
L
L

H
H
H
H

L
L
L
L
L
L
L

H
H
H
H

L
L
L
L
L
L
L

H
H
H
H

L
L
L
L
L
L
L

H
H
H
H

L
L
L
L
L
L
L

H
H
H
H

D10

L
L
L
L
L
L
L

H
H
H
H

D11

L
L
L
L
L
L
L

H
H
H
H

Table 5

ADC Output Code (TEST1)

Output Pin
Output
codes

Steps

0
1
2
3
4
5
6

2047
2048

4092
4093
4094
4095

L
L

H
H
H
H

L
L

H
H

L
L

H
H

L
L

H
H

L
L

H
H

L
L
L
L

H
H
H

L
L

L
L
L
L

L
L
L
L
L
L
L

L
L

L
L
L
L

L
L
L
L
L
L
L

L
L

L
L
L
L

L
L
L
L
L
L
L

L
L

L
L
L
L

L
L
L
L
L
L
L

L
L

L
L
L
L

L
L
L
L
L
L
L

L
L

L
L
L
L

L
L
L
L
L
L
L

L
L

L
L
L
L

L
L
L
L
L
L
L

L
L

L
L
L
L

D10

L
L
L
L
L
L
L

H
H

L
L
L
L

D11

L
L
L
L
L
L
L

H
H
H
H

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 9 of 22

7. Adjustment of Black-Level S/H Response Frequency Characteristics

The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the
register settings, as shown in table 6.

Table 6

SHSW CR Time Constant Setting

[0]

2.20 nsec
(72 MHz)

2.30 nsec
(69 MHz)

[1]

[2]

2.51 nsec
(63 MHz)

2.64 nsec
(60 MHz)

2.93 nsec
(54 MHz)

3.11 nsec
(51 MHz)

3.52 nsec
(45 MHz)

3.77 nsec
(42 MHz)

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

SHSW-fsel (Register setting)

4.40 nsec
(36 MHz)

4.80 nsec
(33 MHz)

[1]

[2]

CR Time Constant (Typ)
(cutoff frequency conversion)

5.87 nsec
(27 MHz)

6.60 nsec
(24 MHz)

8.80 nsec
(18 MHz)

10.6 nsec
(15 MHz)

17.6 nsec
(9 MHz)

26.4 nsec
(6 MHz)

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

[0]

[1]

[2]

[3]

BLKC

The SHAMP frequency characteristics can be adjusted by changing the register settings
and the C4 value of the external 31st pin.
The settings are shown in table 7.
Values other than those shown in the table 7 cannot be used.

SHSW-fsel (Register setting)

CR Time Constant (Typ)
(cutoff frequency conversion)

Table 7

SHAMP Frequency Characteristics Setting

49 MHz

15000 pF

(620 pF)

24 MHz

27000 pF

(820 pF)

32 MHz

22000 pF

(750 pF)

SHA-fsel (Register setting)

LoPwr

(Register setting)

Note: Upper line

Middle line
Lower line

: SHAMP cutoff frequency (Typ)
: Standard value of C4 (maximum value is not defined)
: Minimum value of C4 (do not set below this value)

56 MHz

18000 pF

(360 pF)

116 MHz

10000 pF

(270 pF)

"Lo"

"Hi"

75 MHz

13000 pF

(300 pF)

[0]

[1]

[0]

[1]

[0]

[1]

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 11 of 22

Detailed Timing Specifications

Detailed Timing Specifications when CDSIN Input Mode is Used

Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing
specification.

CDSIN

Note:

SPBLK

Vth

(2)

(3)

SPSIG

ADCLK

(7)

Vth

(8)

(9)

(10)

Black

level

Signal

level

(4)

(1)

(5)

(6)

D0 to D11

1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high, the polarities

of the SPBLK and the SPSIG are inverted.)

Figure 3 Detailed Timing Chart when CDSIN Input Mode is Used

Table 8

Timing Specifications when the CDSIN Input Mode is Used

No. Timing

Symbol

Min

Typ

Max

Unit

(1)

Black-level signal fetch time

CDS1

(1.5)

(2)

SPBLK low period *

CDS2

Typ

�

0.8

1/4f

CLK

Typ

�

1.2

(3)

Signal-level fetch time

CDS3

(1.5)

(4)

SPSIG low period *

CDS4

Typ

�

0.8

1/4f

CLK

Typ

�

1.2

(5)

SPBLK rising to SPSIG rising time *

CDS5

Typ

�

0.85 1/2f

CLK

�

0.90 Typ

�

1.00 ns

(6)

SPSIG rising to ADCLK rising inhibition time *

CDS6

(7), (8) ADCLK t

min./t

min.

CDS7, 8

(9)

ADCLK rising to digital output hold time

CHLD9

(10)

ADCLK rising to digital output delay time

COD10

Note: 1. SPBLK and SPSIG polarities when serial data Spinv bit is set to low.

OBP Detailed Timing Specifications

Figure 4 shows the OBP detailed timing specifications.

The OB period is from the fifth to the twelfth clock cycle after the OB pulse is input. The average of the black signal
level is taken for eight input cycles during the OB period and becomes the clamp level (DC standard).

CDSIN

OBP

Note:

OB pulse > 2 clock cycles

When serial data OBPinv bit is set to low
(When the OBPinv is set to high, the polarity of the OBP is inverted.)

OB period *

1. Shifts

�1 clock cycle depending on the OBP input timing.

N+1

N+5

N+12

N+13

This edge is used, when OBP pulse-width period is clamp-on.

Figure 4 OBP Detailed Timing Specifications

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 12 of 22

Detailed Timing Specifications at Pre-Blanking

Figure 5 shows the pre-blanking detailed timing specifications.

Digital output

(D0 to D11)

ADC

data

Clamp level

ADC

data

PBLK

ADCLK

� 2 clocks

ADCLK

� 12 clocks

(shifts one clock cycle depending
on the PBLK input timing)

When serial data SPinv bit is set to low
(When the SPinv is set to high, the PBLK polarity is inverted.)

Vth

Figure 5 Detailed Timing Specifications at Pre-Blanking

Detailed Timing Specifications when ADCIN Input Mode is Used

Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.

ADCIN

(1)

ADCLK

D0 to D11

(2)

Vth

(3)

(5)

(4)

Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used

Table 9

Timing Specifications when ADCIN Input Mode is Used

No. Timing

Symbol

Min

Typ Max

Unit

(1)

Signal fetch time

ADC1

-- (6)

-- ns

(2), (3)

ADCLK t

min./t

min.

ADC2, 3

Typ

�

0.85

1/2f

ADCLK

Typ

�

1.15

(4)

ADCLK rising to digital output hold time

AHLD4

14.5 --

(5)

ADCLK rising to digital output delay time

AOD5

23.5 31.5

Detailed Timing Specifications for Digital Output-Enable Control

Figure 7 shows the detailed timing specifications for digital output enable control. When the OEB pin is set to high,
output disable mode is entered, and the output state becomes High-Z.

Digital output

(D0 to D11)

OEB

2 k

10 pF

, t

measurement load

, t

measurement load

Vth

10 pF

2 k

Figure 7 Detailed Timing Specifications for Digital Output Enable Control

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 13 of 22

Serial Interface Specifications

Resister 2

Resister 0

Resister 4 to 7

Test Mode (can not be used)

Resister 3

Resister 1

Low

Low to High

SHA-fsel [0] (LSB)

SHA-fsel [1] (MSB)

SHSW-fsel [0] (LSB)

Low: Normal operation mode
High: Sleep mode

SLP

Low: Normal operation mode
High: Standby mode

STBY

Low: CDSIN input mode
High: YIN input mode

CSEL

Low: CDSIN input mode
High: YIN input mode

YSEL

Timing Specifications

Table 10

Serial Data Function List

SCK

SDATA

Latches SDATA
at SCK rising edge

Data is determined
at CS rising edge

INT

SCK

Figure 8 Serial Interface Timing Specifications

DI 00 (LSB)

DI 01

Low

High

Low

High

Low

High

DI 02

DI 03

DI 04

DI 05

DI 06

DI 07

DI 08

DI 09

DI 10

DI 11

DI 12

DI 13

DI 14

DI 15 (MSB)

PGA gain setting *

PGA gain setting (LSB) *

PGA gain setting *

PGA gain setting (MSB) *

Cannot be used. *

Low

High

Low

INT

1, 2

SCK

50 ns
50 ns

50 ns

Min

5 MHz

Max

Notes: 1.

2.
3.
4.
5.
6.

2 byte continuous communications.
SDATA is latched at SCK rising edge.
Insert 16 clocks of SCK while CS is low.
Data is invalid if data transmission is aborted during transmission.
The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
This bit is used for the IC testing, and cannot be used by the user.
Please do not set up in addition to "ALL Low".
This bit is used for the IC testing, and cannot be used by the user.
It is set to the state on the right of a column when RESET bit is set to low. The register
3 should transmit by setup on the right of a column.

Output mode setting (LINV)

Output mode setting (MINV)

Output mode setting (TEST0)

SHAMP
frequency
character-
istics
switching

SHSW-fsel [1]

SHSW-fsel [2]

SHSW-fsel [3] (MSB)

SHSW
frequency
character-
istics
switching

HGstop-Hsel [1]

HGain-Nsel [0]

Clamp-level [3]

Clamp-level [2]

Gray code [1]

Clamp-level [1]

Clamp-level [0] (LSB)

Clamp-level [4] (MSB)

HGstop-Hsel [0]

Gray_test [2]

Gray_test [0]

Gray_test [1]

HGain-Nsel [1]

Low: Normal mode
High: Low power mode

LoPwr

SPinv,
SPSIG/SPBLK/PBLK inversion

OBPinv, OBP inversion

Low: Reset mode
High: Normal operation mode

RESET

High-speed
lead-in
cancellation
time

High-speed
lead-in
gain
multiplication

YC-Bias off

Gray code [0] (TEST1)

Cannot be used. *

All low

Cannot be used. *

All low

Average4, 4 lines average

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 14 of 22

Explanation of Serial Data of CDS Part

Serial data of CDS part has the following functions.

PGA gain (D5 to D12 of register 0)

Details are referred to page 6 block diagram.

At CDS_in mode: �2.36 dB + 0.132 dB

�

N (Log linear)

At ADC_in mode: 0.57 times + 0.01784 times

�

N (Times linear)

: Full-scale digital output is defined as 0 dB when 1 V is input.

Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB � 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.

(1) Level dia explain

CDS

PGA

0 dB when set N = 18 which correspond to 2.36 dB

ADC

(2) Level dia on the circuit

CDS

PGA

3.64 dB + 0.132 dB

� N

(CDS = 0 dB)

ADC

2 V

1023

(1.0 V)

(2.0 V)

(1023)

Figure 9 Level Dia of PGA

CSEL (D15 of register 0)

Data = 0: Select CDSIN
Data = 1: Select ADCIN

Address

STD1[7:0] (L)

STD2[15:8] (H)

D0 D15 D14 D13 D12 D11 D10 D9

SHA_fsel

test_I2

SHSW_fsel

test0

MINV

LINV

STBY

SLP

SLP and STBY (D3, D4 of register 1)

SLP:

Stop the all circuit. Consumption current of CDS part is less than 10

�A.

Start up from offset calibration when recover is needed.

STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.

Allow 50 H time for feedback clamp is stabilized until recover.

Output mode (D5 to D7 of register 1 and D4 of register 3)

It is a test mode. Combination details are table 3 to 5. Normally set to all 0.

SHA-fsel (D8 to D9 of register 1)

It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the
double cut off frequency point with using.

SHSW-fsel (D10 to D13 of register 1)

It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page
9. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 15 of 22

Clamp (D3 to D7 of register 2)

Determine the OB part level with digital code of ADC output.

Clamp level = setting data

�

2 + 14

Default data is 9 = 32 LSB.

HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2)

Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch
the high speed leading mode. Transfer the gain +1/�1 to previous field, its switch to high speed leading mode.

Low_PWR (D12 of register 2)

Switch circuit current and frequency characteristic.

Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee

SPinv (D13 of register 2)

SPSIG/SPBLK/PBLK input signal inverted switching.

Data = 1: Normal
Data = 0: Inverted

Reset (D15 of register 2)

Software reset.

Data = 1: Normal
Data = 0: Reset

Offset calibration should be done when starting up with using this bit. Details are referred to page 19.

C_Bias_off (D3 of register 3)

Center bias is turned off in ADCIN mode.

Data = 0: Normally on
Data = 1: Off

Ave_4H (D6 of register 3)

Clamp detection data is averaged 4H.

Data = 0: 1H
Data = 1: Averaged 4H

Differential Code and Gray Code (D4 to D5 and D7 to D9 of register 3)

Gray code (D4 to D5 of register 3)

DC output code can be change to following type.

Gray Code [1]

Gray Code [0]

Output Code

0 0 Binary

code

0 1 Gray

code

Differential encoded binary

Differential encoded gray

Serial data setting items (D7 to D9 of register 3)

Setting Bit

Setting Contents

Gray_test[0]
Gray_test[1]

Standard data output timing control signal
(Refer to the following table)

Gray_test[2]

ADCLK polar with OBP. (Lo

Positive edge, HI

Negative edge)

� Standard data output timing

Gray_test[1] Gray_test[0] Standard Data Output Timing
Low Low Third

and

fourth

Low

High

Fourth and fifth

High

Low

Fifth and sixth

High High Sixth

and

seventh

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 16 of 22

Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in
parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC output.
Figure 11 indicates the timing specifications.

ADC

Differential SW(D5)

Carry bit
round

+
-

Gray SW(D4)

Standard data
control signal
(D9,D8,D7)

Standard
data
selector

10-bit
output

2clk_DL

Gray

Binary

conversion

Figure 10 Differential Code, Gray Code Circuit

ADCLK

OBP

Digital output

(Beginning edge of OBP and standard edge of ADCLK should be exept �5 ns)

(In case of select the positive edge of ADCLK with D8)

(In case of select the positive polar)

Differential data

Standard

data

Differential data

Figure 11 Differential Code Timing Specifications

To use differential code, complex circuit is necessary at DSP side.

(1) Differential coded

From ADC

Standard data
control signal

Carry bit
round

2clk_DL

Standard
data
selector

D9
D8

Gray

Binary

(2) Gray

Binary conversion

Figure 12 Complex Circuit Example

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 17 of 22

Absolute Maximum Ratings

(Ta = 25

�C)

Item Symbol

Ratings

Unit

Power supply voltage

(max) 4.1

Analog input voltage

(max)

�0.3 to AV

+0.3

Digital input voltage

(max)

�0.3 to DV

+0.3

Operating temperature

Topr

�10 to +75

�C

Power dissipation

Pt(max)

400

Storage temperature

Tstg

�55 to +125

�C

Power supply voltage range (HD49338HF)

2.85 to 3.3

Power supply voltage range (HD49338F)

Vopr

2.70 to 3.3

Notes: 1. V

indicates AV

and DV

must be commonly connected outside the IC. When they are separated by a noise filter, the

potential difference must be 0.3 V or less at power on, and 0.1 V or less during operation.

Electrical Characteristics

(Unless othewide specified, Ta = 25�C, AV

= 3.0 V, DV

= 3.0 V, and R

BIAS

= 33 k

)

Items Common to CDSIN and ADCIN Input Modes

Item Symbol

Min

Typ

Max

Unit

Test

Conditions

Remarks

Power supply voltage
range

2.85 3.00

3.30 V

LoPwr

low

CLK

low

5.5

MHz

LoPwr = high

Conversion frequency

CLK

25 --

36 MHz

LoPwr

low

3.0

2.0

�

-- DV

3.0

0.8

�

Digital input pins
other than CS,
SCK and SDATA

IH2

3.0

2.25

�

-- DV

Digital input voltage

IL2

3.0

0.6

�

CS, SCK, SDATA

�0.5

= �1 mA

Digital output voltage

-- 0.5

V I

= +1 mA

-- 50

�

A V

= 3.0 V

IH2

-- 250

�

A V

= 3.0 V

Digital input current

�50 -- --

�

A V

= 0 V

OZH

-- 50

�

A V

= V

Digital output current

OZL

�50

-- --

�

A V

= 0 V

ADC

resolution RES

12 12

12 bit

ADC integral linearity

INL

(8)

LSBp-p

CLK

= 20 MHz

ADC differential linearity+ DNL+

0.6

0.95

LSB

CLK

= 20 MHz

ADC differential linearity� DNL�

�0.95

�0.6

LSB

CLK

= 20 MHz

Sleep current

SLP

�100 0 100

�

Digital input pin is
set to 0 V, output
pin is open

Standby current

STBY

mA Digital I/O pin is set

to 0 V

-- 100 ns

Digital output Hi-Z
delay time

-- 100 ns

= 2 k

= 10 pF

See figure 7

Notes: 1. Differential linearity is the calculated difference in linearity errors between adjacent codes.

2. Values within parentheses ( ) are for reference.

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 18 of 22

Electrical Characteristics (cont.)

(Unless othewide specified, Ta = 25�C, AV

= 3.0 V, DV

= 3.0 V, and R

BIAS

= 33 k

)

Items for CDSIN Input Mode

Item Symbol

Min

Typ

Max

Unit

Test

Conditions

Remarks

Consumption current (1)

DD1

-- 57 68 mA

LoPwr

low

CLK

= 36 MHz

Consumption current (2)

DD2

-- 37 46 mA

LoPwr

high

CLK

= 250 MHz

CCD offset tolerance range

CCD

(�100)

(100) mV

Timing specifications (1)

CDS1

-- (1.5) -- ns

Timing specifications (2)

CDS2

Typ

�

0.8

1/4f

CLK

Typ

�

1.2

Timing specifications (3)

CDS3

-- (1.5) -- ns

Timing specifications (4)

CDS4

Typ

�

0.8

1/4f

CLK

Typ

�

1.2

Timing specifications (5)

CDS5

Typ

�

0.85

1/2f

CLK

�

0.90 Typ

�

1.00

Timing specifications (6)

CDS6

1 5

Timing specifications (7)

CDS7

11 --

-- ns

Timing specifications (8)

CDS8

11 --

-- ns

Timing specifications (9)

CHLD9

Timing specifications (10)

COD10

-- 16

= 10 pF

See table 8

CLP(00) --

(56)

LSB

CLP(09) --

(128)

LSB

Clamp level

CLP(31) --

(304)

LSB

AGC(0) �4.4 �2.4

�0.4

AGC(256) 4.1

6.1

8.1

AGC(512) 12.5

14.5

16.5

AGC(768) 21.0

23.0

25.0

PGA gain at CDS input

AGC(1023) 29.4

31.4

33.4

Note : Values within parentheses ( ) are for reference.

Items for ADCIN Input Mode

Item Symbol

Min

Typ

Max

Unit

Test

Conditions

Remarks

Consumption current (3)

DD3

-- 39 49 mA

LoPwr

low

CLK

= 36 MHz

Consumption current (4)

DD4

-- 21 26 mA

LoPwr

high

CLK

= 20 MHz

Timing specifications (11)

ADC1

-- (6) -- ns

Timing specifications (12)

ADC2

Typ

�

0.85

1/2f

ADCLK

Typ

�

1.15

Timing specifications (13)

ADC3

Typ

�

0.85

1/2f

ADCLK

Typ

�

1.15

Timing specifications (14)

AHLD4

-- 14.5 -- ns

Timing specifications (15)

AOD5

-- 23.5 31.5 ns

= 10 pF

See table 9

Input current at ADC input

IIN

CIN

�110 --

110

�

A V

= 1.0 V to 2.0 V

Clamp level at ADC input

OF2

(2048)

LSB

Clamp level at YIN input

OF1

(280)

LSB

GSL(0)

0.45 0.57 0.72 Times

GSL(256)

1.36 1.71 2.16 Times

GSL(512)

2.27 2.86 3.60 Times

GSL(768)

3.18 4.00 5.04 Times

PGA gain at ADC input

GSL(1023)

4.08 5.14 6.47 Times

Note : Values within parentheses ( ) are for reference.

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 19 of 22

Operation Sequence at Power On

RESET bit

RESET = "Low"

(RESET mode)

OBP

High-speed pulse is the right phase

OBP is the right phase

SPBLK
SPSIG
ADCLK
etc.

OBP is started within this period

HD49338F/HF
serial data transfer

RESET = "High"

(RESET cancellation)

Must be stable within the operating
power supply voltage range

Start control
of TG and
camera DSP

(1) Register 2 setting
(2) Register 2 setting

(3) Register 0 and 1 settings
(4) Please perform an offset calibration in the period which avoided PBLK of V.

: Set all bits in register 2 to the usage condition, and set the RESET bit to low.
: Cancel the RESET mode by setting the register 2 RESET bit to high.
Do not change other register 2 settings. Offset calibration starts automatically.
: After the offset calibration is terminated, set registers 0 and 1.

(2) Register 2 setting

(1) Register 2 setting

(3) Registers 0
and 1 settings

0 ms

or more

1 ms or more

2 ms or more

Prohibition

period

Ends after

40000 clock cycles

Automatic offset
calibration

The following describes the above serial data transfer. For details on registers 0, 1, and 2, refer to table 10.

(4)Offset calibration
(automatically starts
after RESET
cancellation)

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 20 of 22

Notice for Use

1. Careful handling is necessary to prevent damage due to static electricity.
2. This product has been developed for consumer applications, and should not be used in non-consumer applications.
3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to

prevent latchup, a ceramic capacitor of 0.1 �F or more and an electrolytic capacitor of 10 �F or more should be
inserted between the ground and power supply.

4. Common connection of AV

and DV

should be made off-chip. If AV

and DV

are isolated by a noise filter,

the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation.

5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure

below.

HD49338F/HF

Noise filter

Analog
+3.0V

HD49338F/HF

100

�H

0.01

�F

Noise filter

Example of noise filter

Digital
+3.0V

0.01

�F

6. Connect AV

and DV

off-chip using a common ground. If there are separate analog system and digital system

set grounds, connect to the analog system.

7. When V

is specified in the data sheet, this indicates AV

and DV

8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power

supply or ground pins or left open to prevent crosstalk in adjacent analog pins.

9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of

bending than Fe-type lead material, careful handling is necessary.

10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as

solder dipping cannot be used.

11. Serial communication should not be performed during the effective video period, since this will result in degraded

picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the
HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked.

12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in

accordance with the power-on operating sequence (see page 16).

HD49338F/HF

Rev.1.0, Apr 20, 2004, page 21 of 22

Example of Recommended External Circuit

R11 100
R12 100
R13 100

R10 100

C20

0.1

C18

0.1

C19

0.1

C17

0.1

�

� At CDS Input

Notes: 1. For C4, see table 5.

2. For C3, see page 8 "DC Offset Compensation Feedback Function".

Unit: R:

C: F

C4*

C14 0.1

R15 33 k

C15 0.1

16 15 14 13

45 46 47 48

Serial data input

GND

from
Timing generator

from CCD out

Note: External circuit is same as above except for ADC/Y input.

3.0 V

to
Camera
signal
processor

C21

0.1

C22

0.1

C20

0.1

C18

0.1

C19

0.1

C17

0.1

C21

0.1

C22

0.1

C13

0.1

� C3*

�

C10
0.1

C11

0.1

C12

0.1

C11

0.1

C12

0.1

R15 33 k

C16

47/6

C21
47/6

�

R14 100

HD49338F/HF

(CDS/PGA+ADC)

�

� At ADC/Yin Input

VRM

VRT

VRB

OEB

SDATA

SCK

D11

D10

(NC)

SPSIG

SPBLK

OBP

PBLK

ADCLK

DRDV

BLKSH

BLKFB

CDSIN

BLKC

BIAS

Y IN

ADCIN

C15 0.1

16 15 14 13

45 46 47 48

Serial data input

GND

from
Timing generator

C14 0.1

C13

0.1

C2 2.2/16

C16

47/6

C21
47/6

�

HD49338F/HF

(CDS/PGA+ADC)

C23 0.47

with Y input

BLKSH

BLKFB

CDSIN

BLKC

BIAS

Y IN

ADCIN

D11

D10

(NC)

SPSIG

SPBLK

OBP

PBLK

ADCLK

DRDV

VRM

VRT

VRB

OEB

SDATA

SCK

with ADC input

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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials
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Электронный компонент: HD49338F