Document Outline

Cover
Preface
Contents
Major Revisions and Additions in This Version
Section 1 Overview
- 1.1 Overview
- 1.2 Block Diagram
- 1.3 Pin Description
- 1.4 Pin Functions
Section 2 CPU
- 2.1 Overview
- 2.2 CPU Operating Modes
- 2.3 Address Space
- 2.4 Register Configuration
- 2.5 Data Formats
- 2.6 Instruction Set
- 2.7 Addressing Modes and Effective Address Calculation
- 2.8 Processing States
- 2.9 Basic Operational Timing
Section 3 MCU Operating Modes
- 3.1 Overview
- 3.2 Mode Control Register (MDCR)
- 3.3 System Control Register (SYSCR)
- 3.4 Operating Mode Descriptions
- 3.5 Pin Functions in Each Operating Mode
- 3.6 Memory Map in Each Operating Mode
Section 4 Exception Handling
- 4.1 Overview
- 4.2 Reset
- 4.3 Interrupts
- 4.4 Trap Instruction
- 4.5 Stack Status after Exception Handling
- 4.6 Notes on Stack Usage
Section 5 Interrupt Controller
- 5.1 Overview
- 5.2 Register Descriptions
- 5.3 Interrupt Sources
- 5.4 Interrupt Operation
- 5.5 Usage Notes
Section 6 Bus Controller
- 6.1 Overview
- 6.2 Register Descriptions
- 6.3 Operation
- 6.4 Usage Notes
Section 7 Refresh Controller
- 7.1 Overview
- 7.2 Register Descriptions
- 7.3 Operation
- 7.4 Interrupt Source
- 7.5 Usage Notes
Section 8 DMA Controller
- 8.1 Overview
- 8.2 Register Descriptions (1) (Short Address Mode)
- 8.3 Register Descriptions (2) (Full Address Mode)
- 8.4 Operation
- 8.5 Interrupts
- 8.6 Usage Notes
Section 9 I/O Ports
- 9.1 Overview
- 9.2 Port 4
- 9.3 Port 5
- 9.4 Port 6
- 9.5 Port 7
- 9.6 Port 8
- 9.7 Port 9
- 9.8 Port A
- 9.9 Port B
- 9.10 Port C
Section 10 16-Bit Integrated Timer Unit (ITU)
- 10.1 Overview
- 10.2 Register Descriptions
- 10.3 CPU Interface
- 10.4 Operation
- 10.5 Interrupts
- 10.6 Usage Notes
Section 11 Programmable Timing Pattern Controller
- 11.1 Overview
- 11.2 Register Descriptions
- 11.3 Operation
- 11.4 Usage Notes
Section 12 Watchdog Timer
- 12.1 Overview
- 12.2 Register Descriptions
- 12.3 Operation
- 12.4 Interrupts
- 12.5 Usage Notes
Section 13 Serial Communication Interface
- 13.1 Overview
- 13.2 Register Descriptions
- 13.3 Operation
- 13.4 SCI Interrupts
- 13.5 Usage Notes
Section 14 A/D Converter
- 14.1 Overview
- 14.2 Register Descriptions
- 14.3 CPU Interface
- 14.4 Operation
- 14.5 Interrupts
- 14.6 Usage Notes
Section 15 RAM
- 15.1 Overview
- 15.2 System Control Register (SYSCR)
- 15.3 Operation
Section 16 Clock Pulse Generator
- 16.1 Overview
- 16.2 Oscillator Circuit
- 16.3 System Clock Divider (Clock-Halving Version)
- 16.4 Duty Adjustment Circuit (1:1 Version)
- 16.5 Prescalers
Section 17 Power-Down State
- 17.1 Overview
- 17.2 Register Configuration
- 17.3 Sleep Mode
- 17.4 Software Standby Mode
- 17.5 Hardware Standby Mode
Section 18 Electrical Characteristics
- 18.1 Absolute Maximum Ratings
- 18.2 Electrical Characteristics
- 18.3 Operational Timing
Appendix A Instruction Set
- A.1 Instruction List
- A.2 Operation Code Map (1)
- A.3 Number of States Required for Execution
Appendix B Register Field
- B.1 Register Addresses and Bit Names
- B.2 Register Descriptions
Appendix C I/O Port Block Diagrams
- C.1 Port 4 Block Diagram
- C.2 Port 5 Block Diagram
- C.3 Port 6 Block Diagrams
- C.4 Port 7 Block Diagram
- C.5 Port 8 Block Diagrams
- C.6 Port 9 Block Diagrams
- C.7 Port A Block Diagrams
- C.8 Port B Block Diagrams
- C.9 Port C Block Diagrams
Appendix D Pin States
- D.1 Port States in Each Mode
- D.2 Pin States at Reset
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix F Package Dimensions

Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but

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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i)

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Preface

The H8/3003 is a high-performance microcontroller that integrates system supporting functions
together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip system supporting functions include RAM, a 16-bit integrated timer unit (ITU), a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, I/O ports, a direct memory access controller (DMAC), a refresh
controller, and other facilities.
The four operating modes offer a choice of data bus width and address space size, enabling the
H8/3003 to adapt quickly and flexibly to a variety of conditions.
This manual describes the H8/3003 hardware. For details of the instruction set, refer to the
H8/300H Programming Manual.

Contents

Section 1

Overview

......................................................................................................

1.1

Overview ........................................................................................................................

1.2

Block Diagram................................................................................................................

1.3

Pin Description ...............................................................................................................

1.3.1

Pin Arrangement .............................................................................................

1.3.2

Pin Functions ..................................................................................................

1.4

Pin Functions .................................................................................................................. 11

Section 2

CPU

............................................................................................................... 17

2.1

Overview ........................................................................................................................ 17
2.1.1

Features........................................................................................................... 17

2.1.2

Differences from H8/300 CPU ....................................................................... 18

2.2

CPU Operating Modes.................................................................................................... 19

2.3

Address Space................................................................................................................. 20

2.4

Register Configuration.................................................................................................... 21
2.4.1

Overview......................................................................................................... 21

2.4.2

General Registers............................................................................................ 22

2.4.3

Control Registers ............................................................................................ 23

2.4.4

Initial CPU Register Values ............................................................................ 24

2.5

Data Formats................................................................................................................... 25
2.5.1

General Register Data Formats....................................................................... 25

2.5.2

Memory Data Formats .................................................................................... 26

2.6

Instruction Set................................................................................................................. 28
2.6.1

Instruction Set Overview ................................................................................ 28

2.6.2

Instructions and Addressing Modes................................................................ 29

2.6.3

Tables of Instructions Classified by Function................................................. 30

2.6.4

Basic Instruction Formats ............................................................................... 40

2.6.5

Notes on Use of Bit Manipulation Instructions .............................................. 41

2.7

Addressing Modes and Effective Address Calculation .................................................. 41
2.7.1

Addressing Modes .......................................................................................... 41

2.7.2

Effective Address Calculation ........................................................................ 44

2.8

Processing States ............................................................................................................ 48
2.8.1

Overview......................................................................................................... 48

2.8.2

Program Execution State ................................................................................ 49

2.8.3

Exception-Handling State ............................................................................... 49

2.8.4

Exception-Handling Sequences ...................................................................... 51

2.8.5

Bus-Released State ......................................................................................... 52

2.8.6

Reset State ...................................................................................................... 52

2.8.7

Power-Down State .......................................................................................... 52

Электронный компонент: HD6413003V

Document Outline