Document Outline

• Cover
• Cautions
• Preface
• Contents
• Section 1 Overview
  • 1.1 Features of SuperH Microcomputer with On-Chip Ethernet Controller
  • 1.2Block Diagram
  • 1.3 Pin Description
    • 1.3.1 Pin Arrangement
    • 1.3.2 Pin Functions
    • 1.3.3 Pin Multiplexing
  • 1.4 Processing States
• Section 2 CPU
  • 2.1 Register Configuration
    • 2.1.1 General Registers
    • 2.1.2 Control Registers
    • 2.1.3 System Registers
    • 2.1.4 DSP Registers
    • 2.1.5 Notes on Guard Bits and Overflow Treatment
    • 2.1.6 Initial Values of Registers
  • 2.2 Data Formats
    • 2.2.1 Data Format in Registers
    • 2.2.2 Data Formats in Memory
    • 2.2.3 Immediate Data Format
    • 2.2.4 DSP Type Data Formats
    • 2.2.5 DSP Type Instructions and Data Formats
  • 2.3 CPU Core Instruction Features
  • 2.4 Instruction Formats
    • 2.4.1 CPU Instruction Addressing Modes
    • 2.4.2 DSP Data Addressing
    • 2.4.3 Instruction Formats for CPU Instructions
    • 2.4.4 Instruction Formats for DSP Instructions
  • 2.5 Instruction Set
    • 2.5.1 CPU Instruction Set
    • 2.5.2 DSP Data Transfer Instruction Set
    • 2.5.3 DSP Operation Instruction Set
    • 2.5.4 Various Operation Instructions
  • 2.6 Usage Notes
    • 2.6.1 When not using DSP instructions
    • 2.6.2 When executing a combination of double-precision multiplication or double-precision product-sum operation (CPU instruc
• Section 3 Oscillator Circuits and Operating Modes
  • 3.1 Overview
  • 3.2 On-Chip Clock Pulse Generator and Operating Modes
    • 3.2.1 Clock Pulse Generator
    • 3.2.2 lock Operating Mode Settings
    • 3.2.3 Connecting a Crystal Resonator
    • 3.2.4 External Clock Input
    • 3.2.5 Operating Frequency Selection by Register
    • 3.2.6 lock Modes and Frequency Ranges
    • 3.2.7 Notes on Board Design
  • 3.3 Bus Width of the CS0 Area
• Section 4 Exception Handling
  • 4.1 Overview
    • 4.1.1 Types of Exception Handling and Priority Order
    • 4.1.2 Exception Handling Operations
    • 4.1.3 Exception Vector Table
  • 4.2 Resets
    • 4.2.1 Types of Resets
    • 4.2.2 Power-On Reset
    • 4.2.3 Manual Reset
  • 4.3 Address Errors
    • 4.3.1 Sources of Address Errors
    • 4.3.2 Address Error Exception Handling
  • 4.4 Interrupts
    • 4.4.1 Interrupt Sources
    • 4.4.2 Interrupt Priority Levels
    • 4.4.3 Interrupt Exception Handling
  • 4.5 Exceptions Triggered by Instructions
    • 4.5.1 Instruction-Triggered Exception Types
    • 4.5.2 Trap Instructions
    • 4.5.3 Illegal Slot Instructions
    • 4.5.4 General Illegal Instructions
  • 4.6 When Exception Sources Are Not Accepted
    • 4.6.1 Immediately after a Delayed Branch Instruction
    • 4.6.2 Immediately after an Interrupt-Disabled Instruction
    • 4.6.3 Instructions in Repeat Loops
  • 4.7 Stack Status after Exception Handling
  • 4.8 Usage Notes
    • 4.8.1 Value of Stack Pointer (SP)
    • 4.8.2 Value of Vector Base Register (VBR)
    • 4.8.3 Address Errors Caused by Stacking of Address Error Exception Handling
    • 4.8.4 Manual Reset during Register Access
• Section 5 Interrupt Controller (INTC)
  • 5.1 Overview
    • 5.1.1 Features
    • 5.1.2 Block Diagram
    • 5.1.3 Pin Configuration
    • 5.1.4 Register Configuration
  • 5.2 Interrupt Sources
    • 5.2.1 NMI Interrupt
    • 5.2.2 User Break Interrupt
    • 5.2.3 H-UDI Interrupt
    • 5.2.4 IRL Interrupts
    • 5.2.5 IRQ Interrupts
    • 5.2.6 On-chip Peripheral Module Interrupts
    • 5.2.7 Interrupt Exception Vectors and Priority Order
  • 5.3 Register Descriptions
    • 5.3.1 Interrupt Priority Level Setting Register A (IPRA)
    • 5.3.2 Interrupt Priority Level Setting Register B (IPRB)
    • 5.3.3 Interrupt Priority Level Setting Register C (IPRC)
    • 5.3.4 Interrupt Priority Level Setting Register D (IPRD)
    • 5.3.5 Interrupt Priority Level Setting Register E (IPRE)
    • 5.3.6 Vector Number Setting Register WDT (VCRWDT)
    • 5.3.7 Vector Number Setting Register A (VCRA)
    • 5.3.8 Vector Number Setting Register B (VCRB)
    • 5.3.9 Vector Number Setting Register C (VCRC)
    • 5.3.10 Vector Number Setting Register D (VCRD)
    • 5.3.11 Vector Number Setting Register E (VCRE)
    • 5.3.12 Vector Number Setting Register F (VCRF)
    • 5.3.13 Vector Number Setting Register G (VCRG)
    • 5.3.14 Vector Number Setting Register H (VCRH)
    • 5.3.15 Vector Number Setting Register I (VCRI)
    • 5.3.16 Vector Number Setting Register J (VCRJ)
    • 5.3.17 Vector Number Setting Register K (VCRK)
    • 5.3.18 Vector Number Setting Register L (VCRL)
    • 5.3.19 Vector Number Setting Register M (VCRM)
    • 5.3.20 Vector Number Setting Register N (VCRN)
    • 5.3.21 Vector Number Setting Register O (VCRO)
    • 5.3.22 Vector Number Setting Register P (VCRP)
    • 5.3.23 Vector Number Setting Register Q (VCRQ)
    • 5.3.24 Vector Number Setting Register R (VCRR)
    • 5.3.25 Vector Number Setting Register S (VCRS)
    • 5.3.26 Vector Number Setting Register T (VCRT)
    • 5.3.27 Vector Number Setting Register U (VCRU)
    • 5.3.28 Interrupt Control Register (ICR)
    • 5.3.29 IRQ Control/Status Register (IRQCSR)
  • 5.4 Interrupt Operation
    • 5.4.1 Interrupt Sequence
    • 5.4.2 Stack State after Interrupt Exception Handling
  • 5.5 Interrupt Response Time
  • 5.6 Sampling of Pins IRL3 �IRL0
  • 5.7 Usage Notes
• Section 6 User Break Controller (UBC)
  • 6.1 Overview
    • 6.1.1 Features
    • 6.1.2 Block Diagram
    • 6.1.3 Register Configuration
  • 6.2 Register Descriptions
    • 6.2.1 Break Address Register A (BARA)
    • 6.2.2 Break Address Mask Register A (BAMRA)
    • 6.2.3 Break Bus Cycle Register A (BBRA)
    • 6.2.4 Break Address Register B (BARB)
    • 6.2.5 Break Address Mask Register B (BAMRB)
    • 6.2.6 Break Bus Cycle Register B (BBRB)
    • 6.2.7 Break Address Register C (BARC)
    • 6.2.8 Break Address Mask Register C (BAMRC)
    • 6.2.9 Break Data Register C (BDRC)
    • 6.2.10 Break Data Mask Register C (BDMRC)
    • 6.2.11 Break Bus Cycle Register C (BBRC)
    • 6.2.12 Break Execution Times Register C (BETRC)
    • 6.2.13 Break Address Register D (BARD)
    • 6.2.14 Break Address Mask Register D (BAMRD)
    • 6.2.15 Break Data Register D (BDRD)
    • 6.2.16 Break Data Mask Register D (BDMRD)
    • 6.2.17 Break Bus Cycle Register D (BBRD)
    • 6.2.18 Break Execution Times Register D (BETRD)
    • 6.2.19 Break Control Register (BRCR)
    • 6.2.20 Branch Flag Registers (BRFR)
    • 6.2.21 Branch Source Registers (BRSR)
    • 6.2.22 Branch Destination Registers (BRDR)
  • 6.3 Operation
    • 6.3.1 User Break Operation Sequence
    • 6.3.2 Instruction Fetch Cycle Break
    • 6.3.3 Data Access Cycle Break
    • 6.3.4 Saved Program Counter (PC)Value
    • 6.3.5 X Memory Bus or Y Memory Bus Cycle Break
    • 6.3.6 Sequential Break
    • 6.3.7 PC Traces
    • 6.3.8 Examples of Use
    • 6.3.9 Usage Notes
• Section 7 Bus State Controller (BSC)
  • 7.1 Overview
    • 7.1.1 Features
    • 7.1.2 Block Diagram
    • 7.1.3 Pin Configuration
    • 7.1.4 Register Configuration
    • 7.1.5 Address Map
  • 7.2 Register Descriptions
    • 7.2.1 Bus Control Register 1 (BCR1)
    • 7.2.2 Bus Control Register 2 (BCR2)
    • 7.2.3 Bus Control Register 3 (BCR3)
    • 7.2.4 Wait Control Register 1 (WCR1)
    • 7.2.5 Wait Control Register 2 (WCR2)
    • 7.2.6 Wait Control Register 3 (WCR3)
    • 7.2.7 Individual Memory Control Register (MCR)
    • 7.2.8 Refresh Timer Control/Status Register (RTCSR)
    • 7.2.9 Refresh Timer Counter (RTCNT)
    • 7.2.10 Refresh Time Constant Register (RTCOR)
  • 7.3 Access Size and Data Alignment
    • 7.3.1 Connection to Ordinary Devices
    • 7.3.2 Connection to Little-Endian Devices
  • 7.4 Accessing Ordinary Space
    • 7.4.1 Basic Timing
    • 7.4.2 Wait State Control
    • 7.4.3 CS Assertion Period Extension
  • 7.5 Synchronous DRAM Interface
    • 7.5.1 Synchronous DRAM Direct Connection
    • 7.5.2 Address Multiplexing
    • 7.5.3 Burst Reads
    • 7.5.4 Single Reads
    • 7.5.5 Single Writes
    • 7.5.6 Burst Write Mode
    • 7.5.7 Bank Active Function
    • 7.5.8 Refreshes
    • 7.5.9 Overlap Between Auto Precharge Cycle (Tap)and Next Access
    • 7.5.10 Power-On Sequence
    • 7.5.11 64 Mbit Synchronous DRAM (2 Mword � 32-bit)Connection
  • 7.6 DRAM Interface
    • 7.6.1 DRAM Direct Connection
    • 7.6.2 Address Multiplexing
    • 7.6.3 Basic Timing
    • 7.6.4 Wait State Control
    • 7.6.5 Burst Access
    • 7.6.6 EDO Mode
    • 7.6.7 DRAM Single Transfer
    • 7.6.8 Refreshing
    • 7.6.9 Power-On Sequence
  • 7.7 Burst ROM Interface
  • 7.8 Idles between Cycles
  • 7.9 Bus Arbitration
    • 7.9.1 Master Mode
  • 7.10 Additional Items
    • 7.10.1 Resets
    • 7.10.2 Access as Viewed from CPU,DMAC or E-DMAC
    • 7.10.3 STATS1 and STATS0 Pins
    • 7.10.4 BUSHiZ Specification
  • 7.11 Usage Notes
    • 7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC
    • 7.11.2 When Using I � :E � Clock Ratio of 1 :1,8-Bit Bus Width,and External Wait Input
    • 7.11.3 When connecting external device to synchronous DRAM
• Section 8 Cache
  • 8.1 Introduction
    • 8.1.1 Register Configuration
  • 8.2 Register Description
    • 8.2.1 Cache Control Register (CCR)
  • 8.3Address Space and the Cache
  • 8.4 Cache Operation
    • 8.4.1 Cache Reads
    • 8.4.2 Write Access
    • 8.4.3 Cache-Through Access
    • 8.4.4 The TAS Instruction
    • 8.4.5 Pseudo-LRU and Cache Replacement
    • 8.4.6 Cache Initialization
    • 8.4.7 Associative Purges
    • 8.4.8 Cache Flushing
    • 8.4.9 Data Array Access
    • 8.4.10 Address Array Access
  • 8.5 Cache Use
    • 8.5.1 Initialization
    • 8.5.2 Purge of Specific Lines
    • 8.5.3 Cache Data Coherency
    • 8.5.4 Two-Way Cache Mode
  • 8.6 Usage Notes
    • 8.6.1 Standby
    • 8.6.2 Cache Control Register
• Section 9 Ethernet Controller (EtherC)
  • 9.1 Overview
    • 9.1.1 Features
    • 9.1.2 Configuration
    • 9.1.3 Pin Configuration
    • 9.1.4 Ethernet Controller Register Configuration
  • 9.2 Register Descriptions
    • 9.2.1 EtherC Mode Register (ECMR)
    • 9.2.2 EtherC Status Register (ECSR)
    • 9.2.3 EtherC Interrupt Permission Register (ECSIPR)
    • 9.2.4 PHY Interface Register (PIR)
    • 9.2.5 MAC Address High Register (MAHR)
    • 9.2.6 MAC Address Low Register (MALR)
    • 9.2.7 Receive Frame Length Register (RFLR)
    • 9.2.8 PHY Interface Status Register (PSR)
    • 9.2.9 Transmit Retry Over Counter Register (TROCR)
    • 9.2.10 Single Collision Detect Counter Register (SCDCR)
    • 9.2.11 Delay Collision Detect Counter Register (CDCR)
    • 9.2.12 Lost Carrier Counter Register (LCCR)
    • 9.2.13 Carrier Not Detect Counter Register (CNDCR)
    • 9.2.14 Illegal Frame Length Counter Register (IFLCR)
    • 9.2.15 CRC Error Frame Counter Register (CEFCR)
    • 9.2.16 Frame Receive Error Counter Register (FRECR )
    • 9.2.17 Too-Short Frame Receive Counter Register (TSFRCR)
    • 9.2.18 Too-Long Frame Receive Counter Register (TLFRCR )
    • 9.2.19 Residual-Bit Frame Counter Register (RFCR)
    • 9.2.20 Multicast Address Frame Counter Register (MAFCR)
  • 9.3 Operation
    • 9.3.1 Transmission
    • 9.3.2 Reception
    • 9.3.3 MII Frame Timing
    • 9.3.4 Accessing MII Registers
    • 9.3.5 Magic Packet Detection
    • 9.3.6 CPU Operating Mode and Ethernet Controller Operation
    • 9.3.7 CAM Match Signal Input Function
  • 9.4 Connection to PHY-LSI
• Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)
  • 10.1 Overview
    • 10.1.1 Features
    • 10.1.2 Configuration
    • 10.1.3 Descriptor Management System
    • 10.1.4 Register Configuration
  • 10.2 Register Descriptions
    • 10.2.1 E-DMAC Mode Register (EDMR)
    • 10.2.2 E-DMAC Transmit Request Register (EDTRR)
    • 10.2.3 E-DMAC Receive Request Register (EDRRR)
    • 10.2.4 Transmit Descriptor List Address Register (TDLAR)
    • 10.2.5 Receive Descriptor List Address Register (RDLAR)
    • 10.2.6 EtherC/E-DMAC Status Register (EESR)
    • 10.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)
    • 10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)
    • 10.2.9 Receive Missed-Frame Counter Register (RMFCR)
    • 10.2.10 Transmit FIFO Threshold Register (TFTR)
    • 10.2.11 FIFO Depth Register (FDR)
    • 10.2.12 Receiver Control Register (RCR)
    • 10.2.13 E-DMAC Operation Control Register (EDOCR)
    • 10.2.14 Receiving-Buffer Write Address Register (RBWAR)
    • 10.2.15 Receiving-Descriptor Fetch Address Register (RDFAR)
    • 10.2.16 Transmission-Buffer Read Address Register (TBRAR)
    • 10.2.17 Transmission-Descriptor Fetch Address Register (TDFAR)
  • 10.3Operation
    • 10.3.1 Descriptor List and Data Buffers
    • 10.3.2 Transmission
    • 10.3.3 Reception
    • 10.3.4 Multi-Buffer Frame Transmit/Receive Processing
• Section 11 Direct Memory Access Controller (DMAC)
  • 11.1 Overview
    • 11.1.1 Features
    • 11.1.2 Block Diagram
    • 11.1.3 Pin Configuration
    • 11.1.4 Register Configuration
  • 11.2 Register Descriptions
    • 11.2.1 DMA Source Address Registers 0 and 1 (SAR0,SAR1)
    • 11.2.2 DMA Destination Address Registers 0 and 1 (DAR0,DAR1)
    • 11.2.3 DMA Transfer Count Registers 0 and 1 (TCR0,TCR1)
    • 11.2.4 DMA Channel Control Registers 0 and 1 (CHCR0,CHCR1)
    • 11.2.5 DMA Vector Number Registers 0 and 1 (VCRDMA0,VCRDMA1)
    • 11.2.6 DMA Request/Response Selection Control Registers 0 and 1 (DRCR0,DRCR1)
    • 11.2.7 DMA Operation Register (DMAOR)
  • 11.3 Operation
    • 11.3.1 DMA Transfer Flow
    • 11.3.2 DMA Transfer Requests
    • 11.3.3 Channel Priorities
    • 11.3.4 DMA Transfer Types
    • 11.3.5 Number of Bus Cycles
    • 11.3.6 DMA Transfer Request Acknowledge Signal Output Timing
    • 11.3.7 DREQn Pin Input Detection Timing
    • 11.3.8 DMA Transfer End
    • 11.3.9 BH Pin Output Timing
  • 11.4 Usage Examples
    • 11.4.1 Example of DMA Data Transfer Between SCIF and External Memory
  • 11.5 Usage Notes
• Section 12 16-Bit Free-Running Timer (FRT)
  • 12.1 Overview
    • 12.1.1 Features
    • 12.1.2 Block Diagram
    • 12.1.3 Pin Configuration
    • 12.1.4 Register Configuration
  • 12.2 Register Descriptions
    • 12.2.1 Free-Running Counter (FRC)
    • 12.2.2 Output Compare Registers A and B (OCRA and OCRB)
    • 12.2.3 Input Capture Register (FICR)
    • 12.2.4 Timer Interrupt Enable Register (TIER)
    • 12.2.5 Free-Running Timer Control/Status Register (FTCSR)
    • 12.2.6 Timer Control Register (TCR)
    • 12.2.7 Timer Output Compare Control Register (TOCR)
  • 12.3 CPU Interface
  • 12.4Operation
    • 12.4.1 FRC Count Timing
    • 12.4.2 Output Timing for Output Compare
    • 12.4.3 FRC Clear Timing
    • 12.4.4 Input Capture Input Timing
    • 12.4.5 Input Capture Flag (ICF)Setting Timing
    • 12.4.6 Output Compare Flag (OCFA,OCFB)Setting Timing
    • 12.4.7 Timer Overflow Flag (OVF)Setting Timing
  • 12.5 Interrupt Sources
  • 12.6 Example of FRT Use
  • 12.7 Usage Notes
    • 12.7.1 Contention between FRC Write and Clear
    • 12.7.2 Contention between FRC Write and Increment
    • 12.7.3 Contention between OCR Write and Compare Match
    • 12.7.4 Internal Clock Switching and Counter Operation
    • 12.7.5 Timer Output (FTOA,FTOB)
• Section 13 Watchdog Timer (WDT)
  • 13.1 Overview
    • 13.1.1 Features
    • 13.1.2 Block Diagram
    • 13.1.3 Pin Configuration
    • 13.1.4 Register Configuration
  • 13.2 Register Descriptions
    • 13.2.1 Watchdog Timer Counter (WTCNT)
    • 13.2.2 Watchdog Timer Control/Status Register (WTCSR)
    • 13.2.3 Reset Control/Status Register (RSTCSR)
    • 13.2.4 Notes on Register Access
  • 13.3 Operation
    • 13.3.1 Operation in Watchdog Timer Mode
    • 13.3.2 Operation in Interval Timer Mode
    • 13.3.3 Operation when Standby Mode is Cleared
    • 13.3.4 Timing of Overflow Flag (OVF)Setting
    • 13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF)Setting
  • 13.4Usage Notes
    • 13.4.1 Contention between WTCNT Write and Increment
    • 13.4.2 Changing CKS2 to CKS0 Bit Values
    • 13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode
    • 13.4.4 System Reset with WDTOVF
    • 13.4.5 Internal Reset in Watchdog Timer Mode
• Section 14 Serial Communication Interface with FIFO (SCIF)
  • 14.1 Overview
    • 14.1.1 Features
    • 14.1.2 Block Diagrams
    • 14.1.3 Pin Configuration
    • 14.1.4 Register Configuration
  • 14.2 Register Descriptions
    • 14.2.1 Receive Shift Register (SCRSR)
    • 14.2.2 Receive FIFO Data Register (SCFRDR)
    • 14.2.3 Transmit Shift Register (SCTSR)
    • 14.2.4 Transmit FIFO Data Register (SCFTDR)
    • 14.2.5 Serial Mode Register (SCSMR)
    • 14.2.6 Serial Control Register (SCSCR)
    • 14.2.7 Serial Status 1 Register (SC1SSR)
    • 14.2.8 Serial Status 2 Register (SC2SSR)
    • 14.2.9 Bit Rate Register (SCBRR)
    • 14.2.10 FIFO Control Register (SCFCR)
    • 14.2.11 FIFO Data Count Register (SCFDR)
    • 14.2.12 FIFO Error Register (SCFER)
    • 14.2.13 IrDA Mode Register (SCIMR)
  • 14.3 Operation
    • 14.3.1 Overview
    • 14.3.2 Operation in Asynchronous Mode
    • 14.3.3 Multiprocessor Communication Function
    • 14.3.4 Operation in Synchronous Mode
    • 14.3.5 Use of Transmit/Receive FIFO Buffers
    • 14.3.6 Operation in IrDA Mode
  • 14.4 SCIF Interrupt Sources and the DMAC
  • 14.5 Usage Notes
• Section 15 Serial I/O with FIFO (SIOF)
  • 15.1 Overview
    • 15.1.1 Features
  • 15.2 Register Configuration
    • 15.2.1 Receive Shift Register (SIRSR)
    • 15.2.2 Receive Data Register (SIRDR)
    • 15.2.3 Transmit Shift Register (SITSR)
    • 15.2.4 Transmit Data Register (SITDR)
    • 15.2.5 Serial Control Register (SICTR)
    • 15.2.6 Serial Status Register (SISTR)
    • 15.2.7 Receive Control Data Register (SIRCDR)
    • 15.2.8 Transmit Control Data Register (SITCDR)
    • 15.2.9 FIFO Control Register (SIFCR)
    • 15.2.10 FIFO Data Count Register (SIFDR)
  • 15.3 Operation
    • 15.3.1 Input when TRMD =0 in SIFCR
    • 15.3.2 Output when TRMD =0 in SIFCR
    • 15.3.3 Output when TRMD =1 in SIFCR
  • 15.4 SIOF Interrupt Sources and DMAC
• Section 16 Serial I/O (SIO)
  • 16.1 Overview
    • 16.1.1 Features
  • 16.2 Register Configuration
    • 16.2.1 Receive Shift Register (SIRSR)
    • 16.2.2 Receive Data Register (SIRDR)
    • 16.2.3 Transmit Shift Register (SITSR)
    • 16.2.4 Transmit Data Register (SITDR)
    • 16.2.5 Serial Control Register (SICTR)
    • 16.2.6 Serial Status Register (SISTR)
  • 16.3 Operation
    • 16.3.1 Input
    • 16.3.2 Output
  • 16.4 SIO Interrupt Sources and DMAC
• Section 17 16-Bit Timer Pulse Unit (TPU)
  • 17.1 Overview
    • 17.1.1 Features
    • 17.1.2 Block Diagram
    • 17.1.3 Pin Configuration
    • 17.1.4 Register Configuration
  • 17.2 Register Descriptions
    • 17.2.1 Timer Control Register (TCR)
    • 17.2.2 Timer Mode Register (TMDR)
    • 17.2.3 Timer I/O Control Register (TIOR)
    • 17.2.4 Timer Interrupt Enable Register (TIER)
    • 17.2.5 Timer Status Register (TSR)
    • 17.2.6 Timer Counter (TCNT)
    • 17.2.7 Timer General Register (TGR)
    • 17.2.8 Timer Start Register (TSTR)
    • 17.2.9 Timer Synchronous Register (TSYR)
  • 17.3Interface to Bus Master
    • 17.3.1 16-Bit Registers
    • 17.3.2 8-Bit Registers
  • 17.4 Operation
    • 17.4.1 Overview
    • 17.4.2 Basic Functions
    • 17.4.3 Synchronous Operation
    • 17.4.4 Buffer Operation
    • 17.4.5 PWM Modes
    • 17.4.6 Phase Counting Mode
  • 17.5 Interrupts
    • 17.5.1 Interrupt Sources and Priorities
    • 17.5.2 DMAC Activation
  • 17.6 Operation Timing
    • 17.6.1 Input/Output Timing
    • 17.6.2 Interrupt Signal Timing
  • 17.7 Usage Notes
  • 17.8 Usage Notes
    • 17.8.1 Clearing Flags in TSR0 to TSR2
    • 17.8.2 DMA Transfer by TPU0
• Section 18 Hitachi User Debug Interface (H-UDI)
  • 18.1 Overview
    • 18.1.1 Features
    • 18.1.2 H-UDI Block Diagram
    • 18.1.3 Pin Configuration
    • 18.1.4 Register Configuration
  • 18.2 External Signals
    • 18.2.1 Test Clock (TCK)
    • 18.2.2 Test Mode Select (TMS)
    • 18.2.3 Test Data Input (TDI)
    • 18.2.4 Test Data Output (TDO)
    • 18.2.5 Test Reset (TRST )
  • 18.3 Register Descriptions
    • 18.3.1 Instruction Register (SDIR)
    • 18.3.2 Status Register (SDSR)
    • 18.3.3 Data Register (SDDR)
    • 18.3.4 Bypass Register (SDBPR)
    • 18.3.5 Boundary scan register (SDBSR)
    • 18.3.6 ID code register (SDIDR)
  • 18.4 Operation
    • 18.4.1 TAP Controller
    • 18.4.2 H-UDI Interrupt and Serial Transfer
    • 18.4.3 H-UDI Reset
  • 18.5 Boundary Scan
    • 18.5.1 Supported Instructions
    • 18.5.2 Notes on Use
  • 18.6 Usage Notes
• Section 19 Pin Function Controller (PFC)
  • 19.1 Overview
  • 19.2 Register Configuration
  • 19.3 Register Descriptions
    • 19.3.1 Port A Control Register (PACR)
    • 19.3.2 Port A I/O Register (PAIOR)
    • 19.3.3 Port B Control Registers (PBCR,PBCR2)
    • 19.3.4 Port B I/O Register (PBIOR)
• Section 20 I/O Ports
  • 20.1 Overview
  • 20.2 Port A
    • 20.2.1 Register Configuration
    • 20.2.2 Port A Data Register (PADR)
  • 20.3 Port B
    • 20.3.1 Register Configuration
    • 20.3.2 Port B Data Register (PBDR)
• Section 21 Power-Down Modes
  • 21.1 Overview
    • 21.1.1 Power-Down Modes
    • 21.1.2 Register
  • 21.2 Register Descriptions
    • 21.2.1 Standby Control Register 1 (SBYCR1)
    • 21.2.2 Standby Control Register 2 (SBYCR2)
  • 21.3 Sleep Mode
    • 21.3.1 Transition to Sleep Mode
    • 21.3.2 Canceling Sleep Mode
  • 21.4 Standby Mode
    • 21.4.1 Transition to Standby Mode
    • 21.4.2 Canceling Standby Mode
    • 21.4.3 Standby Mode Cancellation by NMI Interrupt
    • 21.4.4 Clock Pause Function
    • 21.4.5 Notes on Standby Mode
  • 21.5 Module Standby Function
    • 21.5.1 Transition to Module Standby Function
    • 21.5.2 Clearing the Module Standby Function
• Section 22 Electrical Characteristics
  • 22.1 Absolute Maximum Ratings
  • 22.2 DC Characteristics
  • 22.3 AC Characteristics
    • 22.3.1 Clock Timing
    • 22.3.2 Control Signal Timing
    • 22.3.3 Bus Timing
    • 22.3.4 Direct Memory Access Controller Timing
    • 22.3.5 Free-Running Timer Timing
    • 22.3.6 Serial Communication Interface Timing
    • 22.3.7 Watchdog Timer Timing
    • 22.3.8 Serial I/O with FIFO /Serial I/O Timing
    • 22.3.9 Hitachi User Debug Interface Timing
    • 22.3.10 I/O Port Timing
    • 22.3.11 Ethernet Controller Timing
    • 22.3.12 STATS,BH ,and BUSHiZ Signal Timing
  • 22.4 AC Characteristic Test Conditions
• Appendix A On-Chip Peripheral Module Registers
  • A.1 Addresses
• Appendix B Pin States
  • B.1 Pin States in Reset,Power-Down State,and Bus-Released State
• Appendix C Product Lineup
• Appendix D Package Dimensions
• Colophon