Document Outline

Cover
Cautions
Preface
Revisions and Additions in this Edition
Contents
Section 1 Overview and Pin Functions
- 1.1 SH7708 Series Features
- 1.2 Block Diagram
- 1.3 Pin Description
  - 1.3.1 Pin Arrangement
  - 1.3.2 SH7708 Series Pin Functions
Section 2 CPU
- 2.1 Register Configuration
  - 2.1.1 Privileged Mode and Banks
  - 2.1.2 General Registers
  - 2.1.3 System Registers
  - 2.1.4 Control Registers
- 2.2 Data Formats
  - 2.2.1 Data Format in Registers
  - 2.2.2 Data Format in Memory
- 2.3 Instruction Features
  - 2.3.1 Execution Environment
  - 2.3.2 Addressing Modes
  - 2.3.3 Instruction Formats
- 2.4 Instruction Set
  - 2.4.1 Instruction Set Classified by Function
  - 2.4.2 Instruction Code Map
- 2.5 Processor States and Processor Modes
  - 2.5.1 Processor States
  - 2.5.2 Processor Modes
- 2.6 Usage Note
Section 3 Memory Management Unit (MMU)
- 3.1 Overview
  - 3.1.1 Features
  - 3.1.2 Role of MMU
  - 3.1.3 SH7708 Series MMU
  - 3.1.4 Register Configuration
- 3.2 Register Description
- 3.3 TLB Functions
  - 3.3.1 Configuration of the TLB
  - 3.3.2 TLB Indexing
  - 3.3.3 TLB Address Comparison
  - 3.3.4 Page Management Information
- 3.4 MMU Functions
  - 3.4.1 MMU Hardware Management
  - 3.4.2 MMU Software Management
  - 3.4.3 MMU Instruction (LDLTB)
  - 3.4.4 Avoiding Synonym Problems
- 3.5 MMU Exceptions
  - 3.5.1 TLB Miss Exception
  - 3.5.2 TLB Protection Violation Exception
  - 3.5.3 TLB Invalid Exception
  - 3.5.4 Initial Page Write Exception
  - 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error)
- 3.6 Memory-Mapped TLB
  - 3.6.1 Address Array
  - 3.6.2 Data Array
  - 3.6.3 Usage Examples
- 3.7 Usage Note
Section 4 Exception Handling
- 4.1 Overview
  - 4.1.1 Features
  - 4.1.2 Register Configuration
- 4.2 Exception Handling Function
  - 4.2.1 Exception Handling Flow
  - 4.2.2 Exception Handling Vector Addresses
  - 4.2.3 Acceptance of Exceptions
  - 4.2.4 Exception Codes
  - 4.2.5 Exception Request Masks
  - 4.2.6 Returning from Exception Handling
- 4.3 Register Description
- 4.4 Exception Handler Operation
  - 4.4.1 Reset
  - 4.4.2 Interrupts
  - 4.4.3 General Exceptions
- 4.5 Individual Exception Operations
  - 4.5.1 Resets
  - 4.5.2 General Exceptions
  - 4.5.3 Interrupts
- 4.6 Cautions
Section 5 Cache
- 5.1 Overview
  - 5.1.1 Features
  - 5.1.2 Cache Structure
  - 5.1.3 Register Configuration
- 5.2 Register Description
  - 5.2.1 Cache Control Register (CCR)
- 5.3 Cache Operation
  - 5.3.1 Searching the Cache
  - 5.3.2 Read Access
  - 5.3.3 Write Access
  - 5.3.4 Write-Back Buffer
  - 5.3.5 Coherency of Cache and External Memory
  - 5.3.6 RAM Mode
- 5.4 Memory-Mapped Cache
  - 5.4.1 Address Array
  - 5.4.2 Data Array
- 5.5 Usage Examples
  - 5.5.1 Invalidating Specific Entries
  - 5.5.2 Reading the Data of a Specific Entry
Section 6 Interrupt Controller (INTC)
- 6.1 Overview
  - 6.1.1 Features
  - 6.1.2 Block Diagram
  - 6.1.3 Pin Configuration
  - 6.1.4 Register Configuration
- 6.2 Interrupt Sources
  - 6.2.1 NMI Interrupts
  - 6.2.2 IRL Interrupts
  - 6.2.3 On-Chip Supporting Module Interrupts
  - 6.2.4 Interrupt Exception Handling and Priority
- 6.3 INTC Registers
  - 6.3.1 Interrupt Priority Registers A and B (IPRA,IPRB)
  - 6.3.2 Interrupt Control Register (ICR)
- 6.4 INTC Operation
  - 6.4.1 Interrupt Sequence
  - 6.4.2 Multiple Interrupts
- 6.5 Interrupt Response Time
Section 7 User Break Controller (UBC)
- 7.1 Overview
  - 7.1.1 Features
  - 7.1.2 Block Diagram
  - 7.1.3 Register Configuration
  - 7.1.4 Break Conditions and Register Settings
- 7.2 UBC Register Functions
  - 7.2.1 Break Address Register A (BARA)
  - 7.2.2 Break Address Register B (BARB)
  - 7.2.3 Break ASID Register A (BASRA)
  - 7.2.4 Break ASID Register B (BASRB)
  - 7.2.5 Break Address Mask Register A (BAMRA)
  - 7.2.6 Break Address Mask Register B (BAMRB)
  - 7.2.7 Break Bus Cycle Register A (BBRA)
  - 7.2.8 Break Bus Cycle Register B (BBRB)
  - 7.2.9 Break Data Register B (BDRB)
  - 7.2.10 Break Data Mask Register B (BDMRB)
  - 7.2.11 Break Control Register (BRCR)
- 7.3 UBC Operation
  - 7.3.1 User Break Operation Flow
  - 7.3.2 Instruction Fetch Cycle Break
  - 7.3.3 Data Access Cycle Break
  - 7.3.4 Saved Program Counter (PC)Value
  - 7.3.5 Examples of Use
  - 7.3.6 Cautions
Section 8 Power-Down Modes
- 8.1 Overview
  - 8.1.1 Power-Down Modes
  - 8.1.2 Register Configuration
  - 8.1.3 Pin Configuration
- 8.2 Register Description
  - 8.2.1 Standby Control Register (STBCR)
- 8.3 Sleep Mode
  - 8.3.1 Transition to Sleep Mode
  - 8.3.2 Canceling Sleep Mode
- 8.4 Standby Mode
  - 8.4.1 Transition to Standby Mode
  - 8.4.2 Canceling Standby Mode
  - 8.4.3 Clock Pause Function
- 8.5 Module Standby Function
  - 8.5.1 Transition to Module Standby Function
  - 8.5.2 Clearing the Module Standby Function
- 8.6 Timing of STATUS Pin Changes
  - 8.6.1 Timing for Resets
  - 8.6.2 Timing for Canceling Standbys
  - 8.6.3 Timing for Canceling Sleep Mode
- 8.7 Hardware Standby Mode
  - 8.7.1 Transition to Hardware Standby Mode
  - 8.7.2 Canceling Hardware Standby Mode
  - 8.7.3 Hardware Standby Mode Timing
Section 9 On-Chip Oscillation Circuits
- 9.1 Overview
  - 9.1.1 Features
- 9.2 Overview of the CPG
  - 9.2.1 CPG Block Diagram
  - 9.2.2 CPG Pin Configuration
  - 9.2.3 CPG Register Configuration
- 9.3 Clock Operating Modes
- 9.4 Register Descriptions
  - 9.4.1 Frequency Control Register (FRQCR)
- 9.5 Changing the Frequency
  - 9.5.1 Changing the Multiplication Rate
  - 9.5.2 Changing the Division Ratio
- 9.6 PLL Standby Function
  - 9.6.1 Overview of the PLL Standby Function
  - 9.6.2 Usage
- 9.7 Controlling Clock Output
  - 9.7.1 Clock Modes 0 �2
  - 9.7.2 Clock Modes 3 and 4
- 9.8 Overview of the Watchdog Timer (WDT)
  - 9.8.1 Block Diagram of the WDT
  - 9.8.2 Register Configurations
- 9.9 WDT Registers
  - 9.9.1 Watchdog Timer Counter (WTCNT)
  - 9.9.2 Watchdog Timer Control/Status Register (WTCSR)
  - 9.9.3 Notes on Register Access
- 9.10 Using the WDT
  - 9.10.1 Canceling Standbys
  - 9.10.2 Changing the Frequency
  - 9.10.3 Using Watchdog Timer Mode
  - 9.10.4 Using Interval Timer Mode
  - 9.10.5 Usage Notes
- 9.11 Notes on Board Design
Section 10 Bus State Controller (BSC)
- 10.1 Overview
  - 10.1.1 Features
  - 10.1.2 Block Diagram
  - 10.1.3 Pin Configuration
  - 10.1.4 Register Configuration
  - 10.1.5 Area Overview
  - 10.1.6 PCMCIA Support
- 10.2 BSC Registers
  - 10.2.1 Bus Control Register 1 (BCR1)
  - 10.2.2 Bus Control Register 2 (BCR2)
  - 10.2.3 Wait State Control Register 1 (WCR1)
  - 10.2.4 Wait State Control Register 2 (WCR2)
  - 10.2.5 Individual Memory Control Register (MCR)
  - 10.2.6 DRAM Control Register (DCR)
  - 10.2.7 PCMCIA Control Register (PCR)
  - 10.2.8 Synchronous DRAM Mode Register (SDMR)
  - 10.2.9 Refresh Timer Control/Status Register (RTCSR)
  - 10.2.10 Refresh Timer Counter (RTCNT)
  - 10.2.11 Refresh Time Constant Register (RTCOR)
  - 10.2.12 Refresh Count Register (RFCR)
  - 10.2.13 Cautions on Accessing Refresh Control Related Registers
- 10.3 BSC Operation
  - 10.3.1 Endian/Access Size and Data Alignment
  - 10.3.2 Description of Areas
  - 10.3.3 Basic Interface
  - 10.3.4 DRAM Interface
  - 10.3.5 Synchronous DRAM Interface
  - 10.3.6 Pseudo-SRAM Direct Connection
  - 10.3.7 Burst ROM Interface
  - 10.3.8 PCMCIA Interface
  - 10.3.9 Waits between Access Cycles
  - 10.3.10 Bus Arbitration
- 10.4 Usage Notes
  - 10.4.1 Area 2 and 3 Bus Width Setting
  - 10.4.2 When Area 6 is Designated for PCMCIA,with a 16-Bit Bus Width
  - 10.4.3 Self-Refreshing
  - 10.4.4 PCMCIA Area Access
  - 10.4.5 Note on DRAM Connection for Areas 2 and 3
Section 11 Timer (TMU)
- 11.1 Overview
  - 11.1.1 Features
  - 11.1.2 Block Diagram
  - 11.1.3 Pin Configuration
  - 11.1.4 Register Configuration
- 11.2 TMU Registers
  - 11.2.1 Timer Output Control Register (TOCR)
  - 11.2.2 Timer Start Register (TSTR)
  - 11.2.3 Timer Control Register (TCR)
  - 11.2.4 Timer Constant Register (TCOR)
  - 11.2.5 Timer Counters (TCNT)
  - 11.2.6 Input Capture Register (TCPR2)
- 11.3 TMU Operation
  - 11.3.1 Overview
  - 11.3.2 Basic Functions
- 11.4 Interrupts
  - 11.4.1 Status Flag Set Timing
  - 11.4.2 Status Flag Clear Timing
  - 11.4.3 Interrupt Sources and Priorities
- 11.5 Usage Notes
  - 11.5.1 Writing to Registers
  - 11.5.2 Reading Registers
  - 11.5.3 Clearing UNF in the TCR Register
Section 12 Realtime Clock (RTC)
- 12.1 Overview
  - 12.1.1 Features
  - 12.1.2 Block Diagram
  - 12.1.3 Pin Configuration
  - 12.1.4 RTC Register Configuration
- 12.2 RTC Registers
  - 12.2.1 64-Hz Counter (R64CNT)
  - 12.2.2 Second Counter (RSECCNT)
  - 12.2.3 Minute Counter (RMINCNT)
  - 12.2.4 Hour Counter (RHRCNT)
  - 12.2.5 Day of the Week Counter (RWKCNT)
  - 12.2.6 Date Counter (RDAYCNT)
  - 12.2.7 Month Counter (RMONCNT)
  - 12.2.8 Year Counter (RYRCNT)
  - 12.2.9 Second Alarm Register (RSECAR)
  - 12.2.10 Minute Alarm Register (RMINAR)
  - 12.2.11 Hour Alarm Register (RHRAR)
  - 12.2.12 Day of the Week Alarm Register (RWKAR)
  - 12.2.13 Date Alarm Register (RDAYAR)
  - 12.2.14 Month Alarm Register (RMONAR)
  - 12.2.15 RTC Control Register 1 (RCR1)
  - 12.2.16 RTC Control Register 2 (RCR2)
- 12.3 RTC Operation
  - 12.3.1 Initial Settings of Registers after Power-On
  - 12.3.2 Setting the Time
  - 12.3.3 Reading the Time
  - 12.3.4 Alarm Function
  - 12.3.5 Crystal Oscillator Circuit
- 12.4 Usage Notes
  - 12.4.1 Flag Clearing
  - 12.4.2 Register Writes during RTC Count
  - 12.4.3 Usage Note about Periodic Interrupt on RTC
Section 13 Serial Communication Interface (SCI)
- 13.1 Overview
  - 13.1.1 Features
  - 13.1.2 Block Diagram
  - 13.1.3 Pin Configuration
  - 13.1.4 Register Configuration
- 13.2 Register Descriptions
  - 13.2.1 Receive Shift Register (SCRSR)
  - 13.2.2 Receive Data Register (SCRDR)
  - 13.2.3 Transmit Shift Register (SCTSR)
  - 13.2.4 Transmit Data Register (SCTDR)
  - 13.2.5 Serial Mode Register (SCSMR)
  - 13.2.6 Serial Control Register (SCSCR)
  - 13.2.7 Serial Status Register (SCSSR)
  - 13.2.8 Serial Port Register (SCSPTR)
  - 13.2.9 Bit Rate Register (SCBRR)
- 13.3 Operation
  - 13.3.1 Overview
  - 13.3.2 Operation in Asynchronous Mode
  - 13.3.3 Multiprocessor Communication
  - 13.3.4 Synchronous Operation
- 13.4 SCI Interrupt Sources
- 13.5 Usage Notes
Section 14 Smart Card Interface
- 14.1 Overview
  - 14.1.1 Features
  - 14.1.2 Block Diagram
  - 14.1.3 Pin Configuration
  - 14.1.4 Register Configuration
- 14.2 Register Descriptions
  - 14.2.1 Smart Card Mode Register (SCSCMR)
  - 14.2.2 Serial Status Register (SCSSR)
- 14.3 Operation
  - 14.3.1 Overview
  - 14.3.2 Pin Connections
  - 14.3.3 Data Format
  - 14.3.4 Register Settings
  - 14.3.5 Clock
  - 14.3.6 Data Transmission and Reception
- 14.4 Usage Notes
  - 14.4.1 Receive Data Timing and Receive Margin in Asynchronous Mode
  - 14.4.2 Retransmission (Receive and Transmit Modes)
Section 15 I/O Ports
- 15.1 Overview
  - 15.1.1 Features
  - 15.1.2 Block Diagram
  - 15.1.3 Pin Configuration
  - 15.1.4 Register Configuration
- 15.2 Register Descriptions
  - 15.2.1 Port Control Register (PCTR)
  - 15.2.2 Port Data Register (PDTR)
  - 15.2.3 Serial Port Register (SCSPTR)
Section 16 Electrical Characteristics (-SH7708,SH7708S-)
- 16.1 Absolute Maximum Ratings
- 16.2 DC Characteristics
- 16.3 AC Characteristics
  - 16.3.1 Clock Timing
  - 16.3.2 Control Signal Timing
  - 16.3.3 AC Bus Timing Specifications
  - 16.3.4 Basic Timing
  - 16.3.5 Burst ROM Timing
  - 16.3.6 DRAM Timing
  - 16.3.7 Synchronous DRAM Timing
  - 16.3.8 Pseudo-SRAM Timing
  - 16.3.9 PCMCIA Timing
  - 16.3.10 Peripheral Module Signal Timing
  - 16.3.11 AC Characteristics Test Conditions
Section 17 Electrical Characteristics (-SH7708R-)
- 17.1 Absolute Maximum Ratings
- 17.2 DC Characteristics
- 17.3 AC Characteristics
  - 17.3.1 Clock Timing
  - 17.3.2 Control Signal Timing
  - 17.3.3 AC Bus Timing Specifications
  - 17.3.4 Basic Timing
  - 17.3.5 Burst ROM Timing
  - 17.3.6 DRAM Timing
  - 17.3.7 Synchronous DRAM Timing
  - 17.3.8 Pseudo-SRAM Timing
  - 17.3.9 PCMCIA Timing
  - 17.3.10 Peripheral Module Signal Timing
  - 17.3.11 AC Characteristics Test Conditions
Appendix A Pin Functions
- A.1 Pin States
- A.2 Pin Specifications
- A.3 Handling of Unused Pins
- A.4 Pin States in Access to Each Address Space
Appendix B Control Registers
- B.1 Register Address Map
- B.2 Register Bit List
- B.3 Register States in Reset and Power-Down States
Appendix C Delay Time Variation Due to Load Capacitance
Appendix D Package Dimensions
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Электронный компонент: HD6417708SF60

Document Outline