Document Outline
- Cover
- Cautions
- Preface
- List of Items Revised or Added for This Version
- Contents
- Section 1 Overview
- 1.1 SH7750 Series (SH7750, SH7750S, SH7750R) Features
- 1.2 Block Diagram
- 1.3 Pin Arrangement
- 1.4 Pin Functions
- 1.4.1 Pin Functions (256-Pin BGA)
- 1.4.2 Pin Functions (208-Pin QFP)
- 1.4.3 Pin Functions (264-Pin CSP)
- Section 2 Programming Model
- 2.1 Data Formats
- 2.2 Register Configuration
- 2.2.1 Privileged Mode and Banks
- 2.2.2 General Registers
- 2.2.3 Floating-Point Registers
- 2.2.4 Control Registers
- 2.2.5 System Registers
- 2.3 Memory-Mapped Registers
- 2.4 Data Format in Registers
- 2.5 Data Formats in Memory
- 2.6 Processor States
- 2.7 Processor Modes
- Section 3 Memory Management Unit (MMU)
- 3.1 Overview
- 3.1.1 Features
- 3.1.2 Role of the MMU
- 3.1.3 Register Configuration
- 3.1.4 Caution
- 3.2 Register Descriptions
- 3.3 Address Space
- 3.3.1 Physical Address Space
- 3.3.2 External Memory Space
- 3.3.3 Virtual Address Space
- 3.3.4 On-Chip RAM Space
- 3.3.5 Address Translation
- 3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode
- 3.3.7 Address Space Identifier (ASID)
- 3.4 TLB Functions
- 3.4.1 Unified TLB (UTLB) Configuration
- 3.4.2 Instruction TLB (ITLB) Configuration
- 3.4.3 Address Translation Method
- 3.5 MMU Functions
- 3.5.1 MMU Hardware Management
- 3.5.2 MMU Software Management
- 3.5.3 MMU Instruction (LDTLB)
- 3.5.4 Hardware ITLB Miss Handling
- 3.5.5 Avoiding Synonym Problems
- 3.6 MMU Exceptions
- 3.6.1 Instruction TLB Multiple Hit Exception
- 3.6.2 Instruction TLB Miss Exception
- 3.6.3 Instruction TLB Protection Violation Exception
- 3.6.4 Data TLB Multiple Hit Exception
- 3.6.5 Data TLB Miss Exception
- 3.6.6 Data TLB Protection Violation Exception
- 3.6.7 Initial Page Write Exception
- 3.7 Memory-Mapped TLB Configuration
- 3.7.1 ITLB Address Array
- 3.7.2 ITLB Data Array 1
- 3.7.3 ITLB Data Array 2
- 3.7.4 UTLB Address Array
- 3.7.5 UTLB Data Array 1
- 3.7.6 UTLB Data Array 2
- Section 4 Caches
- 4.1 Overview
- 4.1.1 Features
- 4.1.2 Register Configuration
- 4.2 Register Descriptions
- 4.3 Operand Cache (OC)
- 4.3.1 Configuration
- 4.3.2 Read Operation
- 4.3.3 Write Operation
- 4.3.4 Write-Back Buffer
- 4.3.5 Write-Through Buffer
- 4.3.6 RAM Mode
- 4.3.7 OC Index Mode
- 4.3.8 Coherency between Cache and External Memory
- 4.3.9 Prefetch Operation
- 4.4 Instruction Cache (IC)
- 4.4.1 Configuration
- 4.4.2 Read Operation
- 4.4.3 IC Index Mode
- 4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S)
- 4.5.1 IC Address Array
- 4.5.2 IC Data Array
- 4.5.3 OC Address Array
- 4.5.4 OC Data Array
- 4.6 Memory-Mapped Cache Configuration (SH7750R)
- 4.6.1 IC Address Array
- 4.6.2 IC Data Array
- 4.6.3 OC Address Array
- 4.6.4 OC Data Array
- 4.6.5 Summary of the Memory-Mapping of the OC
- 4.7 Store Queues
- 4.7.1 SQ Configuration
- 4.7.2 SQ Writes
- 4.7.3 Transfer to External Memory
- 4.7.4 SQ Protection
- 4.7.5 Reading the SQs (SH7750R Only)
- 4.7.6 SQ Usage Notes
- Section 5 Exceptions
- 5.1 Overview
- 5.1.1 Features
- 5.1.2 Register Configuration
- 5.2 Register Descriptions
- 5.3 Exception Handling Functions
- 5.3.1 Exception Handling Flow
- 5.3.2 Exception Handling Vector Addresses
- 5.4 Exception Types and Priorities
- 5.5 Exception Flow
- 5.5.1 Exception Flow
- 5.5.2 Exception Source Acceptance
- 5.5.3 Exception Requests and BL Bit
- 5.5.4 Return from Exception Handling
- 5.6 Description of Exceptions
- 5.6.1 Resets
- 5.6.2 General Exceptions
- 5.6.3 Interrupts
- 5.6.4 Priority Order with Multiple Exceptions
- 5.7 Usage Notes
- 5.8 Restrictions
- Section 6 Floating-Point Unit
- 6.1 Overview
- 6.2 Data Formats
- 6.2.1 Floating-Point Format
- 6.2.2 Non-Numbers (NaN)
- 6.2.3 Denormalized Numbers
- 6.3 Registers
- 6.3.1 Floating-Point Registers
- 6.3.2 Floating-Point Status/Control Register (FPSCR)
- 6.3.3 Floating-Point Communication Register (FPUL)
- 6.4 Rounding
- 6.5 Floating-Point Exceptions
- 6.6 Graphics Support Functions
- 6.6.1 Geometric Operation Instructions
- 6.6.2 Pair Single-Precision Data Transfer
- Section 7 Instruction Set
- 7.1 Execution Environment
- 7.2 Addressing Modes
- 7.3 Instruction Set
- Section 8 Pipelining
- 8.1 Pipelines
- 8.2 Parallel-Executability
- 8.3 Execution Cycles and Pipeline Stalling
- Section 9 Power-Down Modes
- 9.1 Overview
- 9.1.1 Types of Power-Down Modes
- 9.1.2 Register Configuration
- 9.1.3 Pin Configuration
- 9.2 Register Descriptions
- 9.2.1 Standby Control Register (STBCR)
- 9.2.2 Peripheral Module Pin High Impedance Control
- 9.2.3 Peripheral Module Pin Pull-Up Control
- 9.2.4 Standby Control Register 2 (STBCR2)
- 9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only)
- 9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only)
- 9.3 Sleep Mode
- 9.3.1 Transition to Sleep Mode
- 9.3.2 Exit from Sleep Mode
- 9.4 Deep Sleep Mode
- 9.4.1 Transition to Deep Sleep Mode
- 9.4.2 Exit from Deep Sleep Mode
- 9.5 Standby Mode
- 9.5.1 Transition to Standby Mode
- 9.5.2 Exit from Standby Mode
- 9.5.3 Clock Pause Function
- 9.6 Module Standby Function
- 9.6.1 Transition to Module Standby Function
- 9.6.2 Exit from Module Standby Function
- 9.7 Hardware Standby Mode (SH7750S, SH7750R Only)
- 9.7.1 Transition to Hardware Standby Mode
- 9.7.2 Exit from Hardware Standby Mode
- 9.7.3 Usage Notes
- 9.8 STATUS Pin Change Timing
- 9.8.1 In Reset
- 9.8.2 In Exit from Standby Mode
- 9.8.3 In Exit from Sleep Mode
- 9.8.4 In Exit from Deep Sleep Mode
- 9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only)
- Section 10 Clock Oscillation Circuits
- 10.1 Overview
- 10.2 Overview of CPG
- 10.2.1 Block Diagram of CPG
- 10.2.2 CPG Pin Configuration
- 10.2.3 CPG Register Configuration
- 10.3 Clock Operating Modes
- 10.4 CPG Register Description
- 10.4.1 Frequency Control Register (FRQCR)
- 10.5 Changing the Frequency
- 10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off)
- 10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On)
- 10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On)
- 10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off)
- 10.5.5 Changing CPU or Peripheral Module Clock Division Ratio
- 10.6 Output Clock Control
- 10.7 Overview of Watchdog Timer
- 10.7.1 Block Diagram
- 10.7.2 Register Configuration
- 10.8 WDT Register Descriptions
- 10.8.1 Watchdog Timer Counter (WTCNT)
- 10.8.2 Watchdog Timer Control/Status Register (WTCSR)
- 10.8.3 Notes on Register Access
- 10.9 Using the WDT
- 10.9.1 Standby Clearing Procedure
- 10.9.2 Frequency Changing Procedure
- 10.9.3 Using Watchdog Timer Mode
- 10.9.4 Using Interval Timer Mode
- 10.10 Notes on Board Design
- Section 11 Realtime Clock (RTC)
- 11.1 Overview
- 11.1.1 Features
- 11.1.2 Block Diagram
- 11.1.3 Pin Configuration
- 11.1.4 Register Configuration
- 11.2 Register Descriptions
- 11.2.1 64 Hz Counter (R64CNT)
- 11.2.2 Second Counter (RSECCNT)
- 11.2.3 Minute Counter (RMINCNT)
- 11.2.4 Hour Counter (RHRCNT)
- 11.2.5 Day-of-Week Counter (RWKCNT)
- 11.2.6 Day Counter (RDAYCNT)
- 11.2.7 Month Counter (RMONCNT)
- 11.2.8 Year Counter (RYRCNT)
- 11.2.9 Second Alarm Register (RSECAR)
- 11.2.10 Minute Alarm Register (RMINAR)
- 11.2.11 Hour Alarm Register (RHRAR)
- 11.2.12 Day-of-Week Alarm Register (RWKAR)
- 11.2.13 Day Alarm Register (RDAYAR)
- 11.2.14 Month Alarm Register (RMONAR)
- 11.2.15 RTC Control Register 1 (RCR1)
- 11.2.16 RTC Control Register 2 (RCR2)
- 11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Register (RYRAR) (SH7750R Only)
- 11.3 Operation
- 11.3.1 Time Setting Procedures
- 11.3.2 Time Reading Procedures
- 11.3.3 Alarm Function
- 11.4 Interrupts
- 11.5 Usage Notes
- 11.5.1 Register Initialization
- 11.5.2 Carry Flag and Interrupt Flag in Standby Mode
- 11.5.3 Crystal Oscillator Circuit
- Section 12 Timer Unit (TMU)
- 12.1 Overview
- 12.1.1 Features
- 12.1.2 Block Diagram
- 12.1.3 Pin Configuration
- 12.1.4 Register Configuration
- 12.2 Register Descriptions
- 12.2.1 Timer Output Control Register (TOCR)
- 12.2.2 Timer Start Register (TSTR)
- 12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only)
- 12.2.4 Timer Constant Registers (TCOR)
- 12.2.5 Timer Counters (TCNT)
- 12.2.6 Timer Control Registers (TCR)
- 12.2.7 Input Capture Register (TCPR2)
- 12.3 Operation
- 12.3.1 Counter Operation
- 12.3.2 Input Capture Function
- 12.4 Interrupts
- 12.5 Usage Notes
- 12.5.1 Register Writes
- 12.5.2 TCNT Register Reads
- 12.5.3 Resetting the RTC Frequency Divider
- 12.5.4 External Clock Frequency
- Section 13 Bus State Controller (BSC)
- 13.1 Overview
- 13.1.1 Features
- 13.1.2 Block Diagram
- 13.1.3 Pin Configuration
- 13.1.4 Register Configuration
- 13.1.5 Overview of Areas
- 13.1.6 PCMCIA Support
- 13.2 Register Descriptions
- 13.2.1 Bus Control Register 1 (BCR1)
- 13.2.2 Bus Control Register 2 (BCR2)
- 13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only)
- 13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only)
- 13.2.5 Wait Control Register 1 (WCR1)
- 13.2.6 Wait Control Register 2 (WCR2)
- 13.2.7 Wait Control Register 3 (WCR3)
- 13.2.8 Memory Control Register (MCR)
- 13.2.9 PCMCIA Control Register (PCR)
- 13.2.10 Synchronous DRAM Mode Register (SDMR)
- 13.2.11 Refresh Timer Control/Status Register (RTCSR)
- 13.2.12 Refresh Timer Counter (RTCNT)
- 13.2.13 Refresh Time Constant Register (RTCOR)
- 13.2.14 Refresh Count Register (RFCR)
- 13.2.15 Notes on Accessing Refresh Control Registers
- 13.3 Operation
- 13.3.1 Endian/Access Size and Data Alignment
- 13.3.2 Areas
- 13.3.3 SRAM Interface
- 13.3.4 DRAM Interface
- 13.3.5 Synchronous DRAM Interface
- 13.3.6 Burst ROM Interface
- 13.3.7 PCMCIA Interface
- 13.3.8 MPX Interface
- 13.3.9 Byte Control SRAM Interface
- 13.3.10 Waits between Access Cycles
- 13.3.11 Bus Arbitration
- 13.3.12 Master Mode
- 13.3.13 Slave Mode
- 13.3.14 Partial-Sharing Master Mode
- 13.3.15 Cooperation between Master and Slave
- 13.3.16 Notes on Usage
- Section 14 Direct Memory Access Controller (DMAC)
- 14.1 Overview
- 14.1.1 Features
- 14.1.2 Block Diagram (SH7750, SH7750S)
- 14.1.3 Pin Configuration (SH7750, SH7750S)
- 14.1.4 Register Configuration (SH7750, SH7750S)
- 14.2 Register Descriptions (SH7750, SH7750S)
- 14.2.1 DMA Source Address Registers 03 (SAR0SAR3)
- 14.2.2 DMA Destination Address Registers 03 (DAR0DAR3)
- 14.2.3 DMA Transfer Count Registers 03 (DMATCR0DMATCR3)
- 14.2.4 DMA Channel Control Registers 03 (CHCR0CHCR3)
- 14.2.5 DMA Operation Register (DMAOR)
- 14.3 Operation
- 14.3.1 DMA Transfer Procedure
- 14.3.2 DMA Transfer Requests
- 14.3.3 Channel Priorities
- 14.3.4 Types of DMA Transfer
- 14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
- 14.3.6 Ending DMA Transfer
- 14.4 Examples of Use
- 14.4.1 Examples of Transfer between External Memory and an External Device with DACK
- 14.5 On-Demand Data Transfer Mode (DDT Mode)
- 14.5.1 Operation
- 14.5.2 Pins in DDT Mode
- 14.5.3 Transfer Request Acceptance on Each Channel
- 14.5.4 Notes on Use of DDT Module
- 14.6 Configuration of the DMAC (SH7750R)
- 14.6.1 Block Diagram of the DMAC
- 14.6.2 Pin Configuration (SH7750R)
- 14.6.3 Register Configuration (SH7750R)
- 14.7 Register Descriptions (SH7750R)
- 14.7.1 DMA Source Address Registers 0-7 (SAR0-SAR7)
- 14.7.2 DMA Destination Address Registers 0-7 (DAR0-DAR7)
- 14.7.3 DMA Transfer Count Registers 0-7 (DMATCR0-DMATCR7)
- 14.7.4 DMA Channel Control Registers 0-7 (CHCR0-CHCR7)
- 14.7.5 DMA Operation Register (DMAOR)
- 14.8 Operation (SH7750R)
- 14.8.1 Channel Specification for a Normal DMA Transfer
- 14.8.2 Channel Specification for DDT-Mode DMA Transfer
- 14.8.3 Transfer Channel Notification in DDT Mode
- 14.8.4 Clearing Request Queues by DTR Format
- 14.8.5 Interrupt-Request Codes
- 14.9 Usage Notes
- Section 15 Serial Communication Interface (SCI)
- 15.1 Overview
- 15.1.1 Features
- 15.1.2 Block Diagram
- 15.1.3 Pin Configuration
- 15.1.4 Register Configuration
- 15.2 Register Descriptions
- 15.2.1 Receive Shift Register (SCRSR1)
- 15.2.2 Receive Data Register (SCRDR1)
- 15.2.3 Transmit Shift Register (SCTSR1)
- 15.2.4 Transmit Data Register (SCTDR1)
- 15.2.5 Serial Mode Register (SCSMR1)
- 15.2.6 Serial Control Register (SCSCR1)
- 15.2.7 Serial Status Register (SCSSR1)
- 15.2.8 Serial Port Register (SCSPTR1)
- 15.2.9 Bit Rate Register (SCBRR1)
- 15.3 Operation
- 15.3.1 Overview
- 15.3.2 Operation in Asynchronous Mode
- 15.3.3 Multiprocessor Communication Function
- 15.3.4 Operation in Synchronous Mode
- 15.4 SCI Interrupt Sources and DMAC
- 15.5 Usage Notes
- Section 16 Serial Communication Interface with FIFO (SCIF)
- 16.1 Overview
- 16.1.1 Features
- 16.1.2 Block Diagram
- 16.1.3 Pin Configuration
- 16.1.4 Register Configuration
- 16.2 Register Descriptions
- 16.2.1 Receive Shift Register (SCRSR2)
- 16.2.2 Receive FIFO Data Register (SCFRDR2)
- 16.2.3 Transmit Shift Register (SCTSR2)
- 16.2.4 Transmit FIFO Data Register (SCFTDR2)
- 16.2.5 Serial Mode Register (SCSMR2)
- 16.2.6 Serial Control Register (SCSCR2)
- 16.2.7 Serial Status Register (SCFSR2)
- 16.2.8 Bit Rate Register (SCBRR2)
- 16.2.9 FIFO Control Register (SCFCR2)
- 16.2.10 FIFO Data Count Register (SCFDR2)
- 16.2.11 Serial Port Register (SCSPTR2)
- 16.2.12 Line Status Register (SCLSR2)
- 16.3 Operation
- 16.3.1 Overview
- 16.3.2 Serial Operation
- 16.4 SCIF Interrupt Sources and the DMAC
- 16.5 Usage Notes
- Section 17 Smart Card Interface
- 17.1 Overview
- 17.1.1 Features
- 17.1.2 Block Diagram
- 17.1.3 Pin Configuration
- 17.1.4 Register Configuration
- 17.2 Register Descriptions
- 17.2.1 Smart Card Mode Register (SCSCMR1)
- 17.2.2 Serial Mode Register (SCSMR1)
- 17.2.3 Serial Control Register (SCSCR1)
- 17.2.4 Serial Status Register (SCSSR1)
- 17.3 Operation
- 17.3.1 Overview
- 17.3.2 Pin Connections
- 17.3.3 Data Format
- 17.3.4 Register Settings
- 17.3.5 Clock
- 17.3.6 Data Transmit/Receive Operations
- 17.4 Usage Notes
- Section 18 I/O Ports
- 18.1 Overview
- 18.1.1 Features
- 18.1.2 Block Diagrams
- 18.1.3 Pin Configuration
- 18.1.4 Register Configuration
- 18.2 Register Descriptions
- 18.2.1 Port Control Register A (PCTRA)
- 18.2.2 Port Data Register A (PDTRA)
- 18.2.3 Port Control Register B (PCTRB)
- 18.2.4 Port Data Register B (PDTRB)
- 18.2.5 GPIO Interrupt Control Register (GPIOIC)
- 18.2.6 Serial Port Register (SCSPTR1)
- 18.2.7 Serial Port Register (SCSPTR2)
- Section 19 Interrupt Controller (INTC)
- 19.1 Overview
- 19.1.1 Features
- 19.1.2 Block Diagram
- 19.1.3 Pin Configuration
- 19.1.4 Register Configuration
- 19.2 Interrupt Sources
- 19.2.1 NMI Interrupt
- 19.2.2 IRL Interrupts
- 19.2.3 On-Chip Peripheral Module Interrupts
- 19.2.4 Interrupt Exception Handling and Priority
- 19.3 Register Descriptions
- 19.3.1 Interrupt Priority Registers A to D (IPRAIPRD)
- 19.3.2 Interrupt Control Register (ICR)
- 19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)
- 19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only)
- 19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only)
- 19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only)
- 19.3.7 Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only)
- 19.4 INTC Operation
- 19.4.1 Interrupt Operation Sequence
- 19.4.2 Multiple Interrupts
- 19.4.3 Interrupt Masking with MAI Bit
- 19.5 Interrupt Response Time
- Section 20 User Break Controller (UBC)
- 20.1 Overview
- 20.1.1 Features
- 20.1.2 Block Diagram
- 20.2 Register Descriptions
- 20.2.1 Access to UBC Control Registers
- 20.2.2 Break Address Register A (BARA)
- 20.2.3 Break ASID Register A (BASRA)
- 20.2.4 Break Address Mask Register A (BAMRA)
- 20.2.5 Break Bus Cycle Register A (BBRA)
- 20.2.6 Break Address Register B (BARB)
- 20.2.7 Break ASID Register B (BASRB)
- 20.2.8 Break Address Mask Register B (BAMRB)
- 20.2.9 Break Data Register B (BDRB)
- 20.2.10 Break Data Mask Register B (BDMRB)
- 20.2.11 Break Bus Cycle Register B (BBRB)
- 20.2.12 Break Control Register (BRCR)
- 20.3 Operation
- 20.3.1 Explanation of Terms Relating to Accesses
- 20.3.2 Explanation of Terms Relating to Instruction Intervals
- 20.3.3 User Break Operation Sequence
- 20.3.4 Instruction Access Cycle Break
- 20.3.5 Operand Access Cycle Break
- 20.3.6 Condition Match Flag Setting
- 20.3.7 Program Counter (PC) Value Saved
- 20.3.8 Contiguous A and B Settings for Sequential Conditions
- 20.3.9 Usage Notes
- 20.4 User Break Debug Support Function
- 20.5 Examples of Use
- 20.6 User Break Controller Stop Function
- 20.6.1 Transition to User Break Controller Stopped State
- 20.6.2 Cancelling the User Break Controller Stopped State
- 20.6.3 Examples of Stopping and Restarting the User Break Controller
- Section 21 Hitachi User Debug Interface (H-UDI)
- 21.1 Overview
- 21.1.1 Features
- 21.1.2 Block Diagram
- 21.1.3 Pin Configuration
- 21.1.4 Register Configuration
- 21.2 Register Descriptions
- 21.2.1 Instruction Register (SDIR)
- 21.2.2 Data Register (SDDR)
- 21.2.3 Bypass Register (SDBPR)
- 21.2.4 Interrupt Source Register (SDINT) (SH7750R Only)
- 21.2.5 Boundary Scan Register (SDBSR) (SH7750R Only)
- 21.3 Operation
- 21.3.1 TAP Control
- 21.3.2 H-UDI Reset
- 21.3.3 H-UDI Interrupt
- 21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) (SH7750R Only)
- 21.4 Usage Notes
- Section 22 Electrical Characteristics
- 22.1 Absolute Maximum Ratings
- 22.2 DC Characteristics
- 22.3 AC Characteristics
- 22.3.1 Clock and Control Signal Timing
- 22.3.2 Control Signal Timing
- 22.3.3 Bus Timing
- 22.3.4 Peripheral Module Signal Timing
- 22.3.5 AC Characteristic Test Conditions
- 22.3.6 Delay Time Variation Due to Load Capacitance
- Appendix A Address List
- Appendix B Package Dimensions
- Appendix C Mode Pin Settings
- Appendix D CKIO2ENB Pin Configuration
- Appendix E Pin Functions
- E.1 Pin States
- E.2 Handling of Unused Pins
- Appendix F Synchronous DRAM Address Multiplexing Tables
- Appendix G Prefetching of Instructions and its Side Effects
- Appendix H Power-On and Power-Off Procedures
- Appendix I Product Code Lineup
- Index
- Colophon
Regarding the change of names mentioned in the document, such as Hitachi
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April 1, 2003
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Hitachi SuperH
TM
RISC engine
SH7750 Series
SH7750, SH7750S, SH7750R
Hardware Manual
ADE-602-124E
Rev. 6.0
7/10/2002
Hitachi, Ltd.
Cautions
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However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 6.0, 07/02, page iii of I
Preface
The SH-4 (SH7750 Series: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit
SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system.
The SH7750 Series is built in with a variety of peripheral functions such as cache memory,
memory management unit (MMU), interrupt controller, timers, two serial communication
interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller
(BSC) and smart card interface. This series can be used in a wide range of multimedia equipment.
The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA,
as well as 64-bit synchronous DRAM 4-bank system and 64-bit data bus.
Target Readers: This manual is designed for use by people who design application systems using
the SH7750, SH7750S, or SH7750R.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
Purpose: This manual provides the information of the hardware functions and electrical
characteristics of the SH7750, SH7750S, and SH7750R.
The SH-4 Programming Manual contains detailed information of executable instructions. Please
read the Programming Manual together with this manual.
How to Use the Book:
To understand general functions
Read the manual from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.
To understanding CPU functions
Refer to the separate SH-4 Programming Manual.
Explanatory Note: Bit sequence: upper bit at left, and lower bit at right
List of Related Documents: The latest documents are available on our Web site. Please make
sure that you have the latest version.
(http://www.hitachisemiconductor.com/)
User manuals for SH7750, SH7750S, and SH7750R
Name of Document
Document No.
SH7750 Series Hardware Manual
This manual
SH-4 Programming Manual
ADE-602-156