SH7751 Series Hardware Manual
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April 1, 2003
To all our customers
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Hitachi SuperH
TM
RISC engine
SH7751 Series
SH7751, SH7751R
Hardware Manual
ADE-602-201B
Rev. 3.0
4/11/2002
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party's
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi's sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
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5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi's sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 3.0, 04/02, page iii of xxxviii
Preface
The SH-4 (SH7751 Series (SH7751, SH7751R)) microprocessor incorporates the 32-bit SH-4
CPU and is also equipped with peripheral functions necessary for configuring a user system.
The SH7751 Series is built in with a variety of peripheral functions such as cache memory,
memory management unit (MMU), interrupt controller, floating-point unit (FPU), timers, two
serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC),
bus state controller (BSC) and PCI controller (PCIC). This series can be used in a wide range of
multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous
DRAM and PCMCIA.
Target Readers: This manual is designed for use by people who design application systems using
the SH7751 or SH7751R.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
This hardware manual contains revisions related to the addition of R-mask functionality. Be sure
to check the text for the updated content.
Purpose: This manual provides the information of the hardware functions and electrical
characteristics of the SH7751 and SH7751R.
The SH-4 Programming Manual contains detailed information of executable instructions. Please
read the Programming Manual together with this manual.
How to Use the Book:
To understand general functions
Read the manual from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.
To understanding CPU functions
Refer to the separate SH-4 Programming Manual.
Explanatory Note: Bit sequence: upper bit at left, and lower bit at right
List of Related Documents: The latest documents are available on our Web site. Please make
sure that you have the latest version.
(http://www.hitachisemiconductor.com/)
Rev. 3.0, 04/02, page iv of xxxviii
User manuals for SH7751 and SH7751R
Name of Document
Document No.
SH7751 Series Hardware Manual
This manual
SH-4 Programming Manual
ADE-602-156
User manuals for development tools
Name of Document
Document No.
C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual
ADE-702-246
Simulator/Debugger User's Manual
ADE-702-186
Hitachi Embedded Workshop User's Manual
ADE-702-201
Rev. 3.0, 04/02, page v of xxxviii
Contents
Section 1
Overview
......................................................................................................
1
1.1
SH7751 Series Features................................................................................................
1
1.2
Block Diagram.............................................................................................................
10
1.3
Pin Arrangement ..........................................................................................................
11
1.4
Pin Functions ...............................................................................................................
13
1.4.1
Pin Functions (256-Pin QFP) ...........................................................................
13
1.4.2
Pin Functions (256-Pin BGA) ..........................................................................
24
Section 2
Programming Model
..................................................................................
35
2.1
Data Formats ...............................................................................................................
35
2.2
Register Configuration .................................................................................................
36
2.2.1
Privileged Mode and Banks .............................................................................
36
2.2.2
General Registers ............................................................................................
39
2.2.3
Floating-Point Registers...................................................................................
41
2.2.4
Control Registers.............................................................................................
43
2.2.5
System Registers .............................................................................................
44
2.3
Memory-Mapped Registers ..........................................................................................
46
2.4
Data Format in Registers..............................................................................................
47
2.5
Data Formats in Memory..............................................................................................
47
2.6
Processor States ...........................................................................................................
48
2.7
Processor Modes..........................................................................................................
49
Section 3
Memory Management Unit (MMU)
......................................................
51
3.1
Overview .....................................................................................................................
51
3.1.1
Features...........................................................................................................
51
3.1.2
Role of the MMU ............................................................................................
51
3.1.3
Register Configuration.....................................................................................
54
3.1.4
Caution ...........................................................................................................
54
3.2
Register Descriptions ...................................................................................................
55
3.3
Address Space..............................................................................................................
58
3.3.1
Physical Address Space ...................................................................................
58
3.3.2
External Memory Space...................................................................................
61
3.3.3
Virtual Address Space .....................................................................................
62
3.3.4
On-Chip RAM Space.......................................................................................
63
3.3.5
Address Translation.........................................................................................
63
3.3.6
Single Virtual Memory Mode and Multiple Virtual Memory Mode ..................
64
3.3.7
Address Space Identifier (ASID)......................................................................
64
3.4
TLB Functions.............................................................................................................
65
3.4.1
Unified TLB (UTLB) Configuration ................................................................
65
Rev. 3.0, 04/02, page vi of xxxviii
3.4.2
Instruction TLB (ITLB) Configuration.............................................................
69
3.4.3
Address Translation Method ............................................................................
69
3.5
MMU Functions ..........................................................................................................
72
3.5.1
MMU Hardware Management .........................................................................
72
3.5.2
MMU Software Management...........................................................................
72
3.5.3
MMU Instruction (LDTLB) .............................................................................
72
3.5.4
Hardware ITLB Miss Handling........................................................................
73
3.5.5
Avoiding Synonym Problems ..........................................................................
74
3.6
MMU Exceptions.........................................................................................................
75
3.6.1
Instruction TLB Multiple Hit Exception...........................................................
75
3.6.2
Instruction TLB Miss Exception ......................................................................
75
3.6.3
Instruction TLB Protection Violation Exception...............................................
76
3.6.4
Data TLB Multiple Hit Exception ....................................................................
77
3.6.5
Data TLB Miss Exception ...............................................................................
78
3.6.6
Data TLB Protection Violation Exception ........................................................
79
3.6.7
Initial Page Write Exception ............................................................................
79
3.7
Memory-Mapped TLB Configuration...........................................................................
80
3.7.1
ITLB Address Array........................................................................................
81
3.7.2
ITLB Data Array 1 ..........................................................................................
82
3.7.3
ITLB Data Array 2 ..........................................................................................
83
3.7.4
UTLB Address Array ......................................................................................
83
3.7.5
UTLB Data Array 1.........................................................................................
85
3.7.6
UTLB Data Array 2.........................................................................................
86
Section 4
Caches
..........................................................................................................
87
4.1
Overview.....................................................................................................................
87
4.1.1
Features...........................................................................................................
87
4.1.2
Register Configuration.....................................................................................
88
4.2
Register Descriptions ...................................................................................................
89
4.3
Operand Cache (OC)....................................................................................................
91
4.3.1
Configuration ..................................................................................................
91
4.3.2
Read Operation ...............................................................................................
94
4.3.3
Write Operation...............................................................................................
95
4.3.4
Write-Back Buffer ...........................................................................................
97
4.3.5
Write-Through Buffer......................................................................................
97
4.3.6
RAM Mode .....................................................................................................
97
4.3.7
OC Index Mode...............................................................................................
99
4.3.8
Coherency between Cache and External Memory.............................................
99
4.3.9
Prefetch Operation...........................................................................................
99
4.4
Instruction Cache (IC)..................................................................................................
99
4.4.1
Configuration ..................................................................................................
99
4.4.2
Read Operation ............................................................................................... 102
4.4.3
IC Index Mode ................................................................................................ 102
Rev. 3.0, 04/02, page vii of xxxviii
4.5
Memory-Mapped Cache Configuration (SH7751)......................................................... 103
4.5.1
IC Address Array............................................................................................. 103
4.5.2
IC Data Array.................................................................................................. 104
4.5.3
OC Address Array ........................................................................................... 105
4.5.4
OC Data Array ................................................................................................ 106
4.6
Memory-Mapped Cache Configuration (SH7751R) ...................................................... 107
4.6.1
IC Address Array............................................................................................. 108
4.6.2
IC Data Array.................................................................................................. 109
4.6.3
OC Address Array ........................................................................................... 110
4.6.4
OC Data Array ................................................................................................ 111
4.6.5
Summary of Memory-Mapped OC Addresses .................................................. 112
4.7
Store Queues................................................................................................................ 113
4.7.1
SQ Configuration ............................................................................................ 113
4.7.2
SQ Writes........................................................................................................ 113
4.7.3
Transfer to External Memory ........................................................................... 113
4.7.4
Determination of SQ Access Exception............................................................ 115
4.7.5
SQ Read (SH7751R only)................................................................................ 115
4.7.6
SQ Usage Notes .............................................................................................. 116
Section 5
Exceptions
................................................................................................... 119
5.1
Overview ..................................................................................................................... 119
5.1.1
Features........................................................................................................... 119
5.1.2
Register Configuration..................................................................................... 119
5.2
Register Descriptions ................................................................................................... 120
5.3
Exception Handling Functions...................................................................................... 121
5.3.1
Exception Handling Flow ................................................................................ 121
5.3.2
Exception Handling Vector Addresses ............................................................. 121
5.4
Exception Types and Priorities ..................................................................................... 122
5.5
Exception Flow............................................................................................................ 125
5.5.1
Exception Flow ............................................................................................... 125
5.5.2
Exception Source Acceptance .......................................................................... 126
5.5.3
Exception Requests and BL Bit........................................................................ 128
5.5.4
Return from Exception Handling ..................................................................... 128
5.6
Description of Exceptions ............................................................................................ 128
5.6.1
Resets.............................................................................................................. 129
5.6.2
General Exceptions.......................................................................................... 134
5.6.3
Interrupts......................................................................................................... 148
5.6.4
Priority Order with Multiple Exceptions........................................................... 151
5.7
Usage Notes................................................................................................................. 152
5.8
Restrictions.................................................................................................................. 153
Section 6
Floating-Point Unit
.................................................................................... 155
6.1
Overview ..................................................................................................................... 155
Rev. 3.0, 04/02, page viii of xxxviii
6.2
Data Formats ............................................................................................................... 155
6.2.1
Floating-Point Format...................................................................................... 155
6.2.2
Non-Numbers (NaN) ....................................................................................... 157
6.2.3
Denormalized Numbers ................................................................................... 158
6.3
Registers...................................................................................................................... 159
6.3.1
Floating-Point Registers .................................................................................. 159
6.3.2
Floating-Point Status/Control Register (FPSCR) .............................................. 161
6.3.3
Floating-Point Communication Register (FPUL).............................................. 162
6.4
Rounding ..................................................................................................................... 162
6.5
Floating-Point Exceptions ............................................................................................ 163
6.6
Graphics Support Functions ......................................................................................... 164
6.6.1
Geometric Operation Instructions .................................................................... 164
6.6.2
Pair Single-Precision Data Transfer ................................................................. 166
Section 7
Instruction Set
............................................................................................. 167
7.1
Execution Environment................................................................................................ 167
7.2
Addressing Modes ....................................................................................................... 169
7.3
Instruction Set.............................................................................................................. 173
Section 8
Pipelining
..................................................................................................... 187
8.1
Pipelines...................................................................................................................... 187
8.2
Parallel-Executability................................................................................................... 194
8.3
Execution Cycles and Pipeline Stalling......................................................................... 198
Section 9
Power-Down Modes
.................................................................................. 215
9.1
Overview..................................................................................................................... 215
9.1.1
Types of Power-Down Modes.......................................................................... 215
9.1.2
Register Configuration..................................................................................... 217
9.1.3
Pin Configuration ............................................................................................ 217
9.2
Register Descriptions ................................................................................................... 218
9.2.1
Standby Control Register (STBCR) ................................................................. 218
9.2.2
Peripheral Module Pin High Impedance Control .............................................. 220
9.2.3
Peripheral Module Pin Pull-Up Control............................................................ 220
9.2.4
Standby Control Register 2 (STBCR2)............................................................. 221
9.2.5
Clock Stop Register 00 (CLKSTP00)............................................................... 222
9.2.6
Clock Stop Clear Register 00 (CLKSTPCLR00) .............................................. 223
9.3
Sleep Mode.................................................................................................................. 224
9.3.1
Transition to Sleep Mode................................................................................. 224
9.3.2
Exit from Sleep Mode...................................................................................... 224
9.4
Deep Sleep Mode......................................................................................................... 224
9.4.1
Transition to Deep Sleep Mode........................................................................ 224
9.4.2
Exit from Deep Sleep Mode............................................................................. 225
9.5
Pin Sleep Mode............................................................................................................ 225
Rev. 3.0, 04/02, page ix of xxxviii
9.5.1
Transition to Pin Sleep Mode........................................................................... 225
9.5.2
Exit from Pin Sleep Mode................................................................................ 225
9.6
Standby Mode.............................................................................................................. 225
9.6.1
Transition to Standby Mode............................................................................. 225
9.6.2
Exit from Standby Mode.................................................................................. 226
9.6.3
Clock Pause Function ...................................................................................... 227
9.7
Module Standby Function ............................................................................................ 227
9.7.1
Transition to Module Standby Function ........................................................... 227
9.7.2
Exit from Module Standby Function ................................................................ 228
9.8
Hardware Standby Mode.............................................................................................. 229
9.8.1
Transition to Hardware Standby Mode ............................................................. 229
9.8.2
Exit from Hardware Standby Mode.................................................................. 229
9.8.3
Usage Notes .................................................................................................... 230
9.9
STATUS Pin Change Timing ....................................................................................... 230
9.9.1
In Reset ........................................................................................................... 230
9.9.2
In Exit from Standby Mode.............................................................................. 231
9.9.3
In Exit from Sleep Mode.................................................................................. 233
9.9.4
In Exit from Deep Sleep Mode......................................................................... 236
9.9.5
Hardware Standby Mode Timing ..................................................................... 238
Section 10 Clock Oscillation Circuits
........................................................................ 241
10.1
Overview ..................................................................................................................... 241
10.1.1 Features........................................................................................................... 241
10.2
Overview of CPG......................................................................................................... 243
10.2.1 Block Diagram of CPG.................................................................................... 243
10.2.2 CPG Pin Configuration .................................................................................... 246
10.2.3 CPG Register Configuration ............................................................................ 246
10.3
Clock Operating Modes................................................................................................ 247
10.4
CPG Register Description ............................................................................................ 249
10.4.1 Frequency Control Register (FRQCR) ............................................................. 249
10.5
Changing the Frequency............................................................................................... 251
10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off) ........... 251
10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On)............ 251
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On) ..................... 252
10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off)..................... 252
10.5.5 Changing CPU or Peripheral Module Clock Division Ratio .............................. 252
10.6
Output Clock Control ................................................................................................... 253
10.7
Overview of Watchdog Timer ...................................................................................... 253
10.7.1 Block Diagram ................................................................................................ 253
10.7.2 Register Configuration..................................................................................... 254
10.8
WDT Register Descriptions.......................................................................................... 254
10.8.1 Watchdog Timer Counter (WTCNT)................................................................ 254
10.8.2 Watchdog Timer Control/Status Register (WTCSR)......................................... 255
Rev. 3.0, 04/02, page x of xxxviii
10.8.3 Notes on Register Access................................................................................. 257
10.9
Using the WDT............................................................................................................ 258
10.9.1 Standby Clearing Procedure............................................................................. 258
10.9.2 Frequency Changing Procedure ....................................................................... 258
10.9.3 Using Watchdog Timer Mode.......................................................................... 259
10.9.4 Using Interval Timer Mode.............................................................................. 259
10.10 Notes on Board Design ................................................................................................ 260
Section 11 Realtime Clock (RTC)
.............................................................................. 263
11.1
Overview..................................................................................................................... 263
11.1.1 Features........................................................................................................... 263
11.1.2 Block Diagram ................................................................................................ 264
11.1.3 Pin Configuration ............................................................................................ 265
11.1.4 Register Configuration..................................................................................... 265
11.2
Register Descriptions ................................................................................................... 267
11.2.1 64 Hz Counter (R64CNT)................................................................................ 267
11.2.2 Second Counter (RSECCNT)........................................................................... 267
11.2.3 Minute Counter (RMINCNT) .......................................................................... 268
11.2.4 Hour Counter (RHRCNT)................................................................................ 268
11.2.5 Day-of-Week Counter (RWKCNT).................................................................. 269
11.2.6 Day Counter (RDAYCNT) .............................................................................. 270
11.2.7 Month Counter (RMONCNT).......................................................................... 270
11.2.8 Year Counter (RYRCNT) ................................................................................ 271
11.2.9 Second Alarm Register (RSECAR).................................................................. 272
11.2.10 Minute Alarm Register (RMINAR).................................................................. 272
11.2.11 Hour Alarm Register (RHRAR) ....................................................................... 273
11.2.12 Day-of-Week Alarm Register (RWKAR)......................................................... 273
11.2.13 Day Alarm Register (RDAYAR) ..................................................................... 274
11.2.14 Month Alarm Register (RMONAR) ................................................................. 275
11.2.15 RTC Control Register 1 (RCR1) ...................................................................... 275
11.2.16 RTC Control Register 2 (RCR2) ...................................................................... 277
11.2.17 RTC Control Register (RCR3) and Year-Alarm Register (RYRAR)
(SH7751R Only) ............................................................................................. 280
11.3
Operation..................................................................................................................... 281
11.3.1 Time Setting Procedures.................................................................................. 281
11.3.2 Time Reading Procedures ................................................................................ 282
11.3.3 Alarm Function ............................................................................................... 284
11.4
Interrupts ..................................................................................................................... 285
11.5
Usage Notes................................................................................................................. 285
11.5.1 Register Initialization ...................................................................................... 285
11.5.2 Carry Flag and Interrupt Flag in Standby Mode................................................ 285
11.5.3 Crystal Oscillator Circuit ................................................................................. 285
Rev. 3.0, 04/02, page xi of xxxviii
Section 12 Timer Unit (TMU)
..................................................................................... 287
12.1
Overview ..................................................................................................................... 287
12.1.1 Features........................................................................................................... 287
12.1.2 Block Diagram ................................................................................................ 288
12.1.3 Pin Configuration ............................................................................................ 288
12.1.4 Register Configuration..................................................................................... 289
12.2
Register Descriptions ................................................................................................... 290
12.2.1 Timer Output Control Register (TOCR) ........................................................... 290
12.2.2 Timer Start Register (TSTR)............................................................................ 291
12.2.3 Timer Start Register 2 (TSTR2) ....................................................................... 292
12.2.4 Timer Constant Registers (TCOR) ................................................................... 293
12.2.5 Timer Counters (TCNT) .................................................................................. 293
12.2.6 Timer Control Registers (TCR)........................................................................ 294
12.2.7 Input Capture Register (TCPR2) ...................................................................... 297
12.3 Operation..................................................................................................................... 298
12.3.1 Counter Operation ........................................................................................... 298
12.3.2 Input Capture Function .................................................................................... 301
12.4
Interrupts ..................................................................................................................... 302
12.5
Usage Notes................................................................................................................. 303
12.5.1 Register Writes................................................................................................ 303
12.5.2 TCNT Register Reads...................................................................................... 303
12.5.3 Resetting the RTC Frequency Divider.............................................................. 303
12.5.4 External Clock Frequency................................................................................ 303
Section 13 Bus State Controller (BSC)
...................................................................... 305
13.1
Overview ..................................................................................................................... 305
13.1.1 Features........................................................................................................... 305
13.1.2 Block Diagram ................................................................................................ 307
13.1.3 Pin Configuration ............................................................................................ 308
13.1.4 Register Configuration..................................................................................... 310
13.1.5 Overview of Areas........................................................................................... 311
13.1.6 PCMCIA Support ............................................................................................ 314
13.2
Register Descriptions ................................................................................................... 318
13.2.1 Bus Control Register 1 (BCR1)........................................................................ 318
13.2.2 Bus Control Register 2 (BCR2)........................................................................ 326
13.2.3 Bus Control Register 3 (BCR3) (SH7751R Only)............................................. 327
13.2.4 Bus Control Register 4 (BCR4) (SH7751R Only)............................................. 329
13.2.5 Wait Control Register 1 (WCR1) ..................................................................... 331
13.2.6 Wait Control Register 2 (WCR2) ..................................................................... 334
13.2.7 Wait Control Register 3 (WCR3) ..................................................................... 342
13.2.8 Memory Control Register (MCR) .................................................................... 344
13.2.9 PCMCIA Control Register (PCR) .................................................................... 350
13.2.10 Synchronous DRAM Mode Register (SDMR).................................................. 352
Rev. 3.0, 04/02, page xii of xxxviii
13.2.11 Refresh Timer Control/Status Register (RTCSR).............................................. 354
13.2.12 Refresh Timer Counter (RTCNT) .................................................................... 356
13.2.13 Refresh Time Constant Register (RTCOR)....................................................... 357
13.2.14 Refresh Count Register (RFCR)....................................................................... 358
13.2.15 Notes on Accessing Refresh Control Registers ................................................. 358
13.3
Operation..................................................................................................................... 359
13.3.1 Endian/Access Size and Data Alignment.......................................................... 359
13.3.2 Areas............................................................................................................... 366
13.3.3 SRAM Interface .............................................................................................. 370
13.3.4 DRAM Interface.............................................................................................. 378
13.3.5 Synchronous DRAM Interface ......................................................................... 393
13.3.6 Burst ROM Interface ....................................................................................... 419
13.3.7 PCMCIA Interface .......................................................................................... 422
13.3.8 MPX Interface................................................................................................. 433
13.3.9 Byte Control SRAM Interface.......................................................................... 451
13.3.10 Waits between Access Cycles .......................................................................... 455
13.3.11 Bus Arbitration................................................................................................ 457
13.3.12 Master Mode ................................................................................................... 460
13.3.13 Slave Mode ..................................................................................................... 461
13.3.14 Cooperation between Master and Slave............................................................ 461
13.3.15 Notes on Usage ............................................................................................... 462
Section 14 Direct Memory Access Controller (DMAC)
........................................ 463
14.1
Overview..................................................................................................................... 463
14.1.1 Features........................................................................................................... 463
14.1.2 Block Diagram (SH7751) ................................................................................ 466
14.1.3 Pin Configuration (SH7751) ............................................................................ 467
14.1.4 Register Configuration (SH7751)..................................................................... 468
14.2
Register Descriptions ................................................................................................... 470
14.2.1 DMA Source Address Registers 03 (SAR0SAR3) ........................................ 470
14.2.2 DMA Destination Address Registers 03 (DAR0DAR3) ................................ 471
14.2.3 DMA Transfer Count Registers 03 (DMATCR0DMATCR3) ....................... 472
14.2.4 DMA Channel Control Registers 03 (CHCR0CHCR3) ................................. 473
14.2.5 DMA Operation Register (DMAOR) ............................................................... 481
14.3
Operation..................................................................................................................... 483
14.3.1 DMA Transfer Procedure ................................................................................ 483
14.3.2 DMA Transfer Requests .................................................................................. 486
14.3.3 Channel Priorities............................................................................................ 490
14.3.4 Types of DMA Transfer .................................................................................. 493
14.3.5 Number of Bus Cycle States and
'5(4 Pin Sampling Timing......................... 502
14.3.6 Ending DMA Transfer ..................................................................................... 516
14.4
Examples of Use .......................................................................................................... 519
Rev. 3.0, 04/02, page xiii of xxxviii
14.4.1 Examples of Transfer between External Memory and an External Device
with DACK ..................................................................................................... 519
14.5
On-Demand Data Transfer Mode (DDT Mode)............................................................. 520
14.5.1 Operation ........................................................................................................ 520
14.5.2 Pins in DDT Mode........................................................................................... 522
14.5.3 Transfer Request Acceptance on Each Channel ................................................ 525
14.5.4 Notes on Use of DDT Module ......................................................................... 547
14.6
Configuration of the DMAC (SH7751R) ...................................................................... 550
14.6.1 Block Diagram of the DMAC .......................................................................... 550
14.6.2 Pin Configuration (SH7751R).......................................................................... 551
14.6.3 Register Configuration (SH7751R) .................................................................. 552
14.7
Register Descriptions (SH7751R)................................................................................. 555
14.7.1 DMA Source Address Registers 07 (SAR0SAR7) ........................................ 555
14.7.2 DMA Destination Address Registers 07 (DAR0DAR7) ................................ 555
14.7.3 DMA Transfer Count Registers 07 (DMATCR0DMATCR7) ....................... 556
14.7.4 DMA Channel Control Registers 07 (CHCR0CHCR7) ................................. 556
14.7.5 DMA Operation Register (DMAOR) ............................................................... 559
14.8
Operation (SH7751R) .................................................................................................. 562
14.8.1 Channel Specification for a Normal DMA Transfer.......................................... 562
14.8.2 Channel Specification for DDT-Mode DMA Transfer ...................................... 562
14.8.3 Transfer Channel Notification in DDT Mode ................................................... 562
14.8.4 Clearing Request Queues by DTR Format........................................................ 563
14.8.5 Interrupt-Request Codes .................................................................................. 564
14.9
Usage Notes................................................................................................................. 567
Section 15 Serial Communication Interface (SCI)
.................................................. 569
15.1
Overview ..................................................................................................................... 569
15.1.1 Features........................................................................................................... 569
15.1.2 Block Diagram ................................................................................................ 571
15.1.3 Pin Configuration ............................................................................................ 572
15.1.4 Register Configuration..................................................................................... 572
15.2
Register Descriptions ................................................................................................... 573
15.2.1 Receive Shift Register (SCRSR1) .................................................................... 573
15.2.2 Receive Data Register (SCRDR1).................................................................... 573
15.2.3 Transmit Shift Register (SCTSR1) ................................................................... 574
15.2.4 Transmit Data Register (SCTDR1)................................................................... 574
15.2.5 Serial Mode Register (SCSMR1) ..................................................................... 575
15.2.6 Serial Control Register (SCSCR1) ................................................................... 577
15.2.7 Serial Status Register (SCSSR1) ...................................................................... 581
15.2.8 Serial Port Register (SCSPTR1)....................................................................... 585
15.2.9 Bit Rate Register (SCBRR1)............................................................................ 589
15.3
Operation..................................................................................................................... 597
15.3.1 Overview......................................................................................................... 597
Rev. 3.0, 04/02, page xiv of xxxviii
15.3.2 Operation in Asynchronous Mode.................................................................... 599
15.3.3 Multiprocessor Communication Function......................................................... 609
15.3.4 Operation in Synchronous Mode...................................................................... 618
15.4
SCI Interrupt Sources and DMAC ................................................................................ 627
15.5
Usage Notes................................................................................................................. 628
Section 16 Serial Communication Interface with FIFO (SCIF)
........................... 633
16.1
Overview..................................................................................................................... 633
16.1.1 Features........................................................................................................... 633
16.1.2 Block Diagram ................................................................................................ 635
16.1.3 Pin Configuration ............................................................................................ 636
16.1.4 Register Configuration..................................................................................... 636
16.2
Register Descriptions ................................................................................................... 637
16.2.1 Receive Shift Register (SCRSR2) .................................................................... 637
16.2.2 Receive FIFO Data Register (SCFRDR2) ........................................................ 637
16.2.3 Transmit Shift Register (SCTSR2) ................................................................... 638
16.2.4 Transmit FIFO Data Register (SCFTDR2) ....................................................... 638
16.2.5 Serial Mode Register (SCSMR2) ..................................................................... 639
16.2.6 Serial Control Register (SCSCR2) ................................................................... 641
16.2.7 Serial Status Register (SCFSR2) ...................................................................... 644
16.2.8 Bit Rate Register (SCBRR2)............................................................................ 650
16.2.9 FIFO Control Register (SCFCR2) .................................................................... 651
16.2.10 FIFO Data Count Register (SCFDR2) .............................................................. 654
16.2.11 Serial Port Register (SCSPTR2)....................................................................... 655
16.2.12 Line Status Register (SCLSR2)........................................................................ 662
16.3
Operation..................................................................................................................... 663
16.3.1 Overview ........................................................................................................ 663
16.3.2 Serial Operation .............................................................................................. 664
16.4
SCIF Interrupt Sources and the DMAC ........................................................................ 675
16.5
Usage Notes................................................................................................................. 676
Section 17 Smart Card Interface
................................................................................. 679
17.1
Overview..................................................................................................................... 679
17.1.1 Features........................................................................................................... 679
17.1.2 Block Diagram ................................................................................................ 680
17.1.3 Pin Configuration ............................................................................................ 681
17.1.4 Register Configuration..................................................................................... 681
17.2
Register Descriptions ................................................................................................... 682
17.2.1 Smart Card Mode Register (SCSCMR1) .......................................................... 682
17.2.2 Serial Mode Register (SCSMR1) ..................................................................... 683
17.2.3 Serial Control Register (SCSCR1) ................................................................... 684
17.2.4 Serial Status Register (SCSSR1) ...................................................................... 685
17.3
Operation..................................................................................................................... 686
Rev. 3.0, 04/02, page xv of xxxviii
17.3.1 Overview......................................................................................................... 686
17.3.2 Pin Connections............................................................................................... 687
17.3.3 Data Format .................................................................................................... 688
17.3.4 Register Settings.............................................................................................. 689
17.3.5 Clock .............................................................................................................. 691
17.3.6 Data Transfer Operations ................................................................................. 694
17.4
Usage Notes................................................................................................................. 701
Section 18 I/O Ports
....................................................................................................... 707
18.1
Overview ..................................................................................................................... 707
18.1.1 Features........................................................................................................... 707
18.1.2 Block Diagrams............................................................................................... 708
18.1.3 Pin Configuration ............................................................................................ 715
18.1.4 Register Configuration..................................................................................... 718
18.2
Register Descriptions ................................................................................................... 719
18.2.1 Port Control Register A (PCTRA).................................................................... 719
18.2.2 Port Data Register A (PDTRA) ........................................................................ 720
18.2.3 Port Control Register B (PCTRB) .................................................................... 720
18.2.4 Port Data Register B (PDTRB) ........................................................................ 722
18.2.5 GPIO Interrupt Control Register (GPIOIC) ...................................................... 722
18.2.6 Serial Port Register (SCSPTR1)....................................................................... 723
18.2.7 Serial Port Register (SCSPTR2)....................................................................... 725
Section 19 Interrupt Controller (INTC)
..................................................................... 729
19.1
Overview ..................................................................................................................... 729
19.1.1 Features........................................................................................................... 729
19.1.2 Block Diagram ................................................................................................ 729
19.1.3 Pin Configuration ............................................................................................ 731
19.1.4 Register Configuration..................................................................................... 731
19.2
Interrupt Sources.......................................................................................................... 732
19.2.1 NMI Interrupt .................................................................................................. 732
19.2.2 IRL Interrupts.................................................................................................. 733
19.2.3 On-Chip Peripheral Module Interrupts ............................................................. 735
19.2.4 Interrupt Exception Handling and Priority ........................................................ 736
19.3
Register Descriptions ................................................................................................... 739
19.3.1 Interrupt Priority Registers A to D (IPRAIPRD)............................................. 739
19.3.2 Interrupt Control Register (ICR) ...................................................................... 740
19.3.3 Interrupt Priority Level Settting Register 00 (INTPRI00).................................. 742
19.3.4 Interrupt Factor Register 00 (INTREQ00) ........................................................ 743
19.3.5 Interrupt Mask Register 00 (INTMSK00)......................................................... 744
19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) ........................................ 745
19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 bit allocation........................... 746
19.4
INTC Operation ........................................................................................................... 747
Rev. 3.0, 04/02, page xvi of xxxviii
19.4.1 Interrupt Operation Sequence........................................................................... 747
19.4.2 Multiple Interrupts........................................................................................... 749
19.4.3 Interrupt Masking with MAI Bit ...................................................................... 749
19.5
Interrupt Response Time .............................................................................................. 750
Section 20 User Break Controller (UBC)
.................................................................. 751
20.1
Overview..................................................................................................................... 751
20.1.1 Features........................................................................................................... 751
20.1.2 Block Diagram ................................................................................................ 752
20.2
Register Descriptions ................................................................................................... 754
20.2.1 Access to UBC Registers ................................................................................. 754
20.2.2 Break Address Register A (BARA).................................................................. 755
20.2.3 Break ASID Register A (BASRA) ................................................................... 756
20.2.4 Break Address Mask Register A (BAMRA) ..................................................... 756
20.2.5 Break Bus Cycle Register A (BBRA)............................................................... 757
20.2.6 Break Address Register B (BARB) .................................................................. 759
20.2.7 Break ASID Register B (BASRB).................................................................... 759
20.2.8 Break Address Mask Register B (BAMRB) ..................................................... 759
20.2.9 Break Data Register B (BDRB) ....................................................................... 759
20.2.10 Break Data Mask Register B (BDMRB)........................................................... 760
20.2.11 Break Bus Cycle Register B (BBRB) ............................................................... 761
20.2.12 Break Control Register (BRCR)....................................................................... 761
20.3
Operation..................................................................................................................... 763
20.3.1 Explanation of Terms Relating to Accesses...................................................... 763
20.3.2 Explanation of Terms Relating to Instruction Intervals ..................................... 764
20.3.3 User Break Operation Sequence....................................................................... 765
20.3.4 Instruction Access Cycle Break........................................................................ 766
20.3.5 Operand Access Cycle Break ........................................................................... 767
20.3.6 Condition Match Flag Setting .......................................................................... 768
20.3.7 Program Counter (PC) Value Saved ................................................................. 768
20.3.8 Contiguous A and B Settings for Sequential Conditions ................................... 769
20.3.9 Usage Notes .................................................................................................... 770
20.4
User Break Debug Support Function ............................................................................ 771
20.5
Examples of Use .......................................................................................................... 773
20.6
User Break Controller Stop Function............................................................................ 775
20.6.1 Transition to User Break Controller Stopped State ........................................... 775
20.6.2 Cancelling the User Break Controller Stopped State ......................................... 775
20.6.3 Examples of Stopping and Restarting the User Break Controller....................... 776
Section 21 Hitachi User Debug Interface (H-UDI)
................................................. 777
21.1
Overview..................................................................................................................... 777
21.1.1 Features........................................................................................................... 777
21.1.2 Block Diagram ................................................................................................ 777
Rev. 3.0, 04/02, page xvii of xxxviii
21.1.3 Pin Configuration ............................................................................................ 779
21.1.4 Register Configuration..................................................................................... 780
21.2
Register Descriptions ................................................................................................... 781
21.2.1 Instruction Register (SDIR) ............................................................................. 781
21.2.2 Data Register (SDDR) ..................................................................................... 782
21.2.3 Bypass Register (SDBPR) ............................................................................... 782
21.2.4 Interrupt Factor Register (SDINT) ................................................................... 783
21.2.5 Boundary Scan Register (SDBSR) ................................................................... 783
21.3
Operation..................................................................................................................... 798
21.3.1 TAP Control.................................................................................................... 798
21.3.2 H-UDI Reset ................................................................................................... 799
21.3.3 H-UDI Interrupt............................................................................................... 799
21.3.4 Boundary Scan (EXTEST, SAMPLE/PRELOAD, BYPASS) ........................... 800
21.4
Usage Notes................................................................................................................. 800
Section 22 PCI Controller (PCIC)
.............................................................................. 801
22.1
Overview ..................................................................................................................... 801
22.1.1 Features........................................................................................................... 801
22.1.2 Block Diagram ................................................................................................ 803
22.1.3 Pin Configuration ............................................................................................ 804
22.1.4 Register Configuration..................................................................................... 805
22.2
PCIC Register Descriptions.......................................................................................... 811
22.2.1 PCI Configuration Register 0 (PCICONF0)...................................................... 811
22.2.2 PCI Configuration Register 1 (PCICONF1)...................................................... 812
22.2.3 PCI Configuration Register 2 (PCICONF2)...................................................... 817
22.2.4 PCI Configuration Register 3 (PCICONF3)...................................................... 819
22.2.5 PCI Configuration Register 4 (PCICONF4)...................................................... 821
22.2.6 PCI Configuration Register 5 (PCICONF5)...................................................... 823
22.2.7 PCI Configuration Register 6 (PCICONF6)...................................................... 825
22.2.8 PCI Configuration Register 7 (PCICONF7) to PCI Configuration Register 10
(PCICONF10) ................................................................................................. 827
22.2.9 PCI Configuration Register 11 (PCICONF11).................................................. 828
22.2.10 PCI Configuration Register 12 (PCICONF12).................................................. 829
22.2.11 PCI Configuration Register 13 (PCICONF13).................................................. 830
22.2.12 PCI Configuration Register 14 (PCICONF14).................................................. 831
22.2.13 PCI Configuration Register 15 (PCICONF15).................................................. 832
22.2.14 PCI Configuration Register 16 (PCICONF16).................................................. 834
22.2.15 PCI Configuration Register 17 (PCICONF17).................................................. 836
22.2.16 Reserved Area ................................................................................................. 838
22.2.17 PCI Control Register (PCICR) ......................................................................... 839
22.2.18 PCI Local Space Register [1:0] (PCILSR [1:0])................................................ 842
22.2.19 PCI Local Address Register [1:0] (PCILAR [1:0])............................................ 844
22.2.20 PCI Interrupt Register (PCIINT) ...................................................................... 846
Rev. 3.0, 04/02, page xviii of xxxviii
22.2.21 PCI Interrupt Mask Register (PCIINTM) ......................................................... 848
22.2.22 PCI Address Data Register at Error (PCIALR) ................................................. 850
22.2.23 PCI Command Data Register at Error (PCICLR).............................................. 851
22.2.24 PCI Arbiter Interrupt Register (PCIAINT) ....................................................... 853
22.2.25 PCI Arbiter Interrupt Mask Register (PCIAINTM)........................................... 855
22.2.26 PCI Error Bus Master Data Register (PCIBMLR) ............................................ 856
22.2.27 PCI DMA Transfer Arbitration Register (PCIDMABT).................................... 857
22.2.28 PCI DMA Transfer PCI Address Register [3:0] (PCIDPA [3:0])....................... 858
22.2.29 PCI DMA Transfer Local Bus Start Address Register [3:0] (PCIDLA [3:0])..... 859
22.2.30 PCI DMA Transfer Counter Register [3:0] (PCIDTC [3:0]).............................. 860
22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0])............................................ 862
22.2.32 PIO Address Register (PCIPAR)...................................................................... 865
22.2.33 Memory Space Base Register (PCIMBR)......................................................... 867
22.2.34 I/O Space Base Register (PCIIOBR) ................................................................ 868
22.2.35 PCI Power Management Interrupt Register (PCIPINT)..................................... 870
22.2.36 PCI Power Management Interrupt Mask Register (PCIPINTM)........................ 871
22.2.37 PCI Clock Control Register (PCICLKR) .......................................................... 872
22.2.38 PCIC-BSC Registers........................................................................................ 873
22.2.39 Port Control Register (PCIPCTR) .................................................................... 874
22.2.40 Port Data Register (PCIPDTR) ........................................................................ 877
22.2.41 PIO Data Register (PCIPDR) ........................................................................... 878
22.3
Description of Operation .............................................................................................. 879
22.3.1 Operating Modes ............................................................................................. 879
22.3.2 PCI Commands ............................................................................................... 880
22.3.3 PCIC Initialization........................................................................................... 881
22.3.4 Local Register Access...................................................................................... 882
22.3.5 Host Functions ................................................................................................ 882
22.3.6 PCI Bus Arbitration in Non-host Mode ............................................................ 885
22.3.7 PIO Transfers .................................................................................................. 885
22.3.8 Target Transfers .............................................................................................. 888
22.3.9 DMA Transfers ............................................................................................... 891
22.3.10 Transfer Contention within PCIC..................................................................... 897
22.3.11 PCI Bus Basic Interface ................................................................................... 898
22.4
Endians........................................................................................................................ 910
22.4.1 Internal Bus (Peripheral Bus) Interface for Peripheral Modules ........................ 910
22.4.2 Endian Control for Local Bus .......................................................................... 912
22.4.3 Endian Control in DMA Transfers ................................................................... 912
22.4.4 Endian Control in Target Transfers (Memory Read/Memory Write) ................. 914
22.4.5 Endian Control in Target Transfers (I/O Read/I/O Write) ................................. 917
22.4.6 Endian Control in Target Transfers (Configuration Read/Configuration Write). 917
22.5
Resetting...................................................................................................................... 919
22.6
Interrupts ..................................................................................................................... 920
22.6.1 Interrupts from PCIC to CPU........................................................................... 920
Rev. 3.0, 04/02, page xix of xxxviii
22.6.2 Interrupts from External PCI Devices............................................................... 921
22.6.3
,17$ .............................................................................................................. 921
22.7
Error Detection ............................................................................................................ 922
22.8
PCIC Clock ................................................................................................................. 922
22.9
Power Management...................................................................................................... 923
22.9.1 Power Management Overview ......................................................................... 923
22.9.2 Stopping the Clock .......................................................................................... 924
22.9.3 Compatibility with Standby and Sleep.............................................................. 927
22.10 Port Functions.............................................................................................................. 927
22.11 Version Management ................................................................................................... 928
Section 23 Electrical Characteristics
.......................................................................... 929
23.1
Absolute Maximum Ratings ......................................................................................... 929
23.2
DC Characteristics ....................................................................................................... 930
23.3
AC Characteristics ....................................................................................................... 948
23.3.1 Clock and Control Signal Timing..................................................................... 950
23.3.2 Control Signal Timing ..................................................................................... 961
23.3.3 Bus Timing ..................................................................................................... 964
23.3.4 Peripheral Module Signal Timing .................................................................. 1015
23.3.5 AC Characteristic Test Conditions ................................................................. 1027
23.3.6 Change in Delay Time Based on Load Capacitance ........................................ 1028
Appendix A
Address List
.......................................................................................... 1031
Appendix B
Package Dimensions
........................................................................... 1039
Appendix C
Mode Pin Settings
............................................................................... 1041
Appendix D
Pin Functions
........................................................................................ 1044
D.1
Pin States................................................................................................................... 1044
D.2
Handling of Unused Pins............................................................................................ 1048
Appendix E
Synchronous DRAM Address Multiplexing Tables
................... 1050
Appendix F
Instruction Prefetching and Its Side Effects
................................... 1061
Appendix G
Power-On and Power-Off Procedures
............................................. 1062
Appendix H
List of Models
...................................................................................... 1063
Rev. 3.0, 04/02, page xx of xxxviii
Figures
Figure 1.1
Block Diagram of SH7751 Series Functions .................................................
10
Figure 1.2
Pin Arrangement (256-Pin QFP)...................................................................
11
Figure 1.3
Pin Arrangement (256-Pin BGA)..................................................................
12
Figure 2.1
Data Formats................................................................................................
35
Figure 2.2
CPU Register Configuration in Each Processor Mode ...................................
38
Figure 2.3
General Registers .........................................................................................
40
Figure 2.4
Floating-Point Registers ...............................................................................
42
Figure 2.5
Data Formats In Memory .............................................................................
47
Figure 2.6
Processor State Transitions...........................................................................
49
Figure 3.1
Role of the MMU.........................................................................................
53
Figure 3.2
MMU-Related Registers...............................................................................
55
Figure 3.3
Physical Address Space (MMUCR.AT = 0) ..................................................
59
Figure 3.4
P4 Area........................................................................................................
60
Figure 3.5
External Memory Space ...............................................................................
61
Figure 3.6
Virtual Address Space (MMUCR.AT = 1) ....................................................
62
Figure 3.7
UTLB Configuration ....................................................................................
65
Figure 3.8
Relationship between Page Size and Address Format ....................................
66
Figure 3.9
ITLB Configuration .....................................................................................
69
Figure 3.10
Flowchart of Memory Access Using UTLB ..................................................
70
Figure 3.11
Flowchart of Memory Access Using ITLB....................................................
71
Figure 3.12
Operation of LDTLB Instruction ..................................................................
73
Figure 3.13
Memory-Mapped ITLB Address Array .........................................................
81
Figure 3.14
Memory-Mapped ITLB Data Array 1 ...........................................................
82
Figure 3.15
Memory-Mapped ITLB Data Array 2 ...........................................................
83
Figure 3.16
Memory-Mapped UTLB Address Array .......................................................
84
Figure 3.17
Memory-Mapped UTLB Data Array 1..........................................................
85
Figure 3.18
Memory-Mapped UTLB Data Array 2..........................................................
86
Figure 4.1
Cache and Store Queue Control Registers (CCR)..........................................
89
Figure 4.2
Configuration of Operand Cache (SH7751) ..................................................
92
Figure 4.3
Configuration of Operand Cache (SH7751R) ................................................
93
Figure 4.4
Configuration of Write-Back Buffer .............................................................
97
Figure 4.5
Configuration of Write-Through Buffer ........................................................
97
Figure 4.6
Configuration of Instruction Cache (SH7751) ............................................... 100
Figure 4.7
Configuration of Instruction Cache (SH7751R)............................................. 101
Figure 4.8
Memory-Mapped IC Address Array.............................................................. 104
Figure 4.9
Memory-Mapped IC Data Array................................................................... 105
Figure 4.10
Memory-Mapped OC Address Array ............................................................ 106
Figure 4.11
Memory-Mapped OC Data Array ................................................................. 107
Figure 4.12
Memory-Mapped IC Address Array.............................................................. 109
Figure 4.13
Memory-Mapped IC Data Array................................................................... 110
Figure 4.14
Memory-Mapped OC Address Array ............................................................ 111
Figure 4.15
Memory-Mapped OC Data Array ................................................................. 112
Rev. 3.0, 04/02, page xxi of xxxviii
Figure 4.16
Store Queue Configuration ........................................................................... 113
Figure 5.1
Register Bit Configurations .......................................................................... 120
Figure 5.2
Instruction Execution and Exception Handling.............................................. 125
Figure 5.3
Example of General Exception Acceptance Order ......................................... 127
Figure 6.1
Format of Single-Precision Floating-Point Number ....................................... 155
Figure 6.2
Format of Double-Precision Floating-Point Number ..................................... 156
Figure 6.3
Single-Precision NaN Bit Pattern.................................................................. 158
Figure 6.4
Floating-Point Registers ............................................................................... 160
Figure 8.1
Basic Pipelines............................................................................................. 188
Figure 8.2
Instruction Execution Patterns ...................................................................... 189
Figure 8.3
Examples of Pipelined Execution.................................................................. 201
Figure 9.1
STATUS Output in Power-On Reset............................................................. 230
Figure 9.2
STATUS Output in Manual Reset................................................................. 231
Figure 9.3
STATUS Output in Standby
Interrupt Sequence....................................... 231
Figure 9.4
STATUS Output in Standby
Power-On Reset Sequence ........................... 232
Figure 9.5
STATUS Output in Standby
Manual Reset Sequence ............................... 233
Figure 9.6
STATUS Output in Sleep
Interrupt Sequence........................................... 233
Figure 9.7
STATUS Output in Sleep
Power-On Reset Sequence ............................... 234
Figure 9.8
STATUS Output in Sleep
Manual Reset Sequence ................................... 235
Figure 9.9
STATUS Output in Deep Sleep
Interrupt Sequence .................................. 236
Figure 9.10
STATUS Output in Deep Sleep
Power-On Reset Sequence ...................... 236
Figure 9.11
STATUS Output in Deep Sleep
Manual Reset Sequence .......................... 237
Figure 9.12
Hardware Standby Mode Timing (When CA = Low in Normal Operation).... 238
Figure 9.13
Hardware Standby Mode Timing (When CA = Low in WDT Operation)....... 239
Figure 9.14
Timing When Power Other than VDD-RTC is Off........................................ 239
Figure 9.15
Timing When VDD-RTC Power is Off
On............................................... 240
Figure 10.1(1) Block Diagram of CPG (SH7751)................................................................. 243
Figure 10.1(2) Block Diagram of CPG (SH7751R) .............................................................. 244
Figure 10.2
Block Diagram of WDT ............................................................................... 253
Figure 10.3
Writing to WTCNT and WTCSR.................................................................. 257
Figure 10.4
Points for Attention when Using Crystal Resonator....................................... 260
Figure 10.5
Points for Attention when Using PLL Oscillator Circuit ................................ 261
Figure 11.1
Block Diagram of RTC................................................................................. 264
Figure 11.2
Examples of Time Setting Procedures........................................................... 281
Figure 11.3
Examples of Time Reading Procedures......................................................... 283
Figure 11.4
Example of Use of Alarm Function............................................................... 284
Figure 11.5
Example of Crystal Oscillator Circuit Connection ......................................... 286
Figure 12.1
Block Diagram of TMU ............................................................................... 288
Figure 12.2
Example of Count Operation Setting Procedure ............................................ 299
Figure 12.3
TCNT Auto-Reload Operation...................................................................... 299
Figure 12.4
Count Timing when Operating on Internal Clock .......................................... 300
Figure 12.5
Count Timing when Operating on External Clock ......................................... 300
Figure 12.6
Count Timing when Operating on On-Chip RTC Output Clock ..................... 301
Rev. 3.0, 04/02, page xxii of xxxviii
Figure 12.7
Operation Timing when Using Input Capture Function ................................. 302
Figure 13.1
Block Diagram of BSC................................................................................. 307
Figure 13.2
Correspondence between Virtual Address Space and External Memory Space 311
Figure 13.3
External Memory Space Allocation .............................................................. 313
Figure 13.4
Example of
5'< Sampling Timing at which BCR4 is Set
(Two Wait Cycles are Inserted by WCR2) .................................................... 330
Figure 13.5
Writing to RTCSR, RTCNT, RTCOR, and RFCR......................................... 359
Figure 13.6
Basic Timing of SRAM Interface ................................................................. 371
Figure 13.7
Example of 32-Bit Data Width SRAM Connection ....................................... 372
Figure 13.8
Example of 16-Bit Data Width SRAM Connection ....................................... 373
Figure 13.9
Example of 8-Bit Data Width SRAM Connection ......................................... 374
Figure 13.10
SRAM Interface Wait Timing (Software Wait Only)..................................... 375
Figure 13.11
SRAM Interface Wait State Timing (Wait State Insertion by
5'< Signal).... 376
Figure 13.12
SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting) .... 377
Figure 13.13
Example of DRAM Connection (32-Bit Data Width, Area 3) ........................ 378
Figure 13.14
Basic DRAM Access Timing........................................................................ 380
Figure 13.15
DRAM Wait State Timing............................................................................ 381
Figure 13.16
DRAM Burst Access Timing........................................................................ 382
Figure 13.17
DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)..................... 383
Figure 13.18
Burst Access Timing in DRAM EDO Mode ................................................. 384
Figure 13.19(1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, Anw = 0) .......................................................... 385
Figure 13.19(2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(Fast Page Mode, RCD = 0, Anw = 0) .......................................................... 386
Figure 13.19(3) DRAM Burst Bus Cycle, RAS Down Mode Start
(EDO Mode, RCD = 0, Anw = 0) ................................................................. 387
Figure 13.19(4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, Anw = 0) ................................................................. 388
Figure 13.20
CAS-Before-RAS Refresh Operation............................................................ 389
Figure 13.21
DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1) ....... 390
Figure 13.22
DRAM Self-Refresh Cycle Timing............................................................... 392
Figure 13.23
Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .... 394
Figure 13.24
Basic Timing for Synchronous DRAM Burst Read ....................................... 396
Figure 13.25
Basic Timing for Synchronous DRAM Single Read...................................... 398
Figure 13.26
Basic Timing for Synchronous DRAM Burst Write ...................................... 399
Figure 13.27
Basic Timing for Synchronous DRAM Single Write ..................................... 401
Figure 13.28
Burst Read Timing ....................................................................................... 403
Figure 13.29
Burst Read Timing (RAS Down, Same Row Address) .................................. 404
Figure 13.30
Burst Read Timing (RAS Down, Different Row Addresses).......................... 405
Figure 13.31
Burst Write Timing ...................................................................................... 406
Figure 13.32
Burst Write Timing (Same Row Address) ..................................................... 407
Figure 13.33
Burst Write Timing (Different Row Addresses) ............................................ 408
Rev. 3.0, 04/02, page xxiii of xxxviii
Figure 13.34
Burst Read Cycle for Different Bank and Row Address Following Preceding
Burst Read Cycle ......................................................................................... 410
Figure 13.35
Auto-Refresh Operation ............................................................................... 411
Figure 13.36
Synchronous DRAM Auto-Refresh Timing .................................................. 412
Figure 13.37
Synchronous DRAM Self-Refresh Timing .................................................... 413
Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL)........................................ 415
Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting) ............... 416
Figure 13.39
Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)
417
Figure 13.40
Basic Timing of a Burst Write to Synchronous DRAM ................................. 418
Figure 13.41
Burst ROM Basic Access Timing ................................................................. 420
Figure 13.42
Burst ROM Wait Access Timing .................................................................. 421
Figure 13.43
Burst ROM Wait Access Timing .................................................................. 421
Figure 13.44
Example of PCMCIA Interface..................................................................... 426
Figure 13.45
Basic Timing for PCMCIA Memory Card Interface ...................................... 427
Figure 13.46
Wait Timing for PCMCIA Memory Card Interface ....................................... 428
Figure 13.47
PCMCIA Space Allocation........................................................................... 429
Figure 13.48
Basic Timing for PCMCIA I/O Card Interface .............................................. 430
Figure 13.49
Wait Timing for PCMCIA I/O Card Interface ............................................... 431
Figure 13.50
Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ....................... 432
Figure 13.51
Example of 32-Bit Data Width MPX Connection .......................................... 434
Figure 13.52
MPX Interface Timing 1
(Single Read Cycle, AnW = 0, No External Wait)......................................... 435
Figure 13.53
MPX Interface Timing 2
(Single Read, AnW = 0, One External Wait Inserted).................................... 436
Figure 13.54
MPX Interface Timing 3
(Single Write Cycle, AnW = 0, No External Wait) ........................................ 437
Figure 13.55
MPX Interface Timing 4
(Single Write, AnW = 1, One External Wait Inserted) ................................... 438
Figure 13.56
MPX Interface Timing 5
(Burst Read Cycle, AnW = 0, No External Wait) .......................................... 439
Figure 13.57
MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control) ................................... 440
Figure 13.58
MPX Interface Timing 7
(Burst Write Cycle, AnW = 0, No External Wait) ......................................... 441
Figure 13.59
MPX Interface Timing 8
(Burst Write Cycle, AnW = 1, External Wait Control)................................... 442
Figure 13.60
MPX Interface Timing 1
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits).......................................................................... 443
Figure 13.61
MPX Interface Timing 2
(Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits).......................................................................... 444
Rev. 3.0, 04/02, page xxiv of xxxviii
Figure 13.62
MPX Interface Timing 3
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits).......................................................................... 445
Figure 13.63
MPX Interface Timing 4
(Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits).......................................................................... 446
Figure 13.64
MPX Interface Timing 5
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) ....................................................................... 447
Figure 13.65
MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) ....................................................................... 448
Figure 13.66
MPX Interface Timing 7
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) ....................................................................... 449
Figure 13.67
MPX Interface Timing 8
(Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) ....................................................................... 450
Figure 13.68
Example of 52-Bit Data Width Byte Control SRAM ..................................... 451
Figure 13.69
Byte Control SRAM Basic Read Cycle (No Wait) ........................................ 452
Figure 13.70
Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle) ................ 453
Figure 13.71
Byte Control SRAM Basic Read Cycle (One Internal Wait + One External
Wait) ........................................................................................................... 454
Figure 13.72
Waits between Access Cycles....................................................................... 456
Figure 13.73
Arbitration Sequence.................................................................................... 459
Figure 14.1
Block Diagram of DMAC ............................................................................ 466
Figure 14.2
DMAC Transfer Flowchart........................................................................... 485
Figure 14.3
Round Robin Mode ...................................................................................... 491
Figure 14.4
Example of Changes in Priority Order in Round Robin Mode ....................... 492
Figure 14.5
Data Flow in Single Address Mode............................................................... 494
Figure 14.6
DMA Transfer Timing in Single Address Mode............................................ 495
Figure 14.7
Operation in Dual Address Mode.................................................................. 496
Figure 14.8
Example of Transfer Timing in Dual Address Mode ..................................... 497
Figure 14.9
Example of DMA Transfer in Cycle Steal Mode ........................................... 498
Figure 14.10
Example of DMA Transfer in Burst Mode .................................................... 498
Figure 14.11
Bus Handling with Two DMAC Channels Operating .................................... 502
Figure 14.12
Dual Address Mode/Cycle Steal Mode External Bus
External Bus/
'5(4 (Level Detection), DACK (Read Cycle) ............................................ 505
Figure 14.13
Dual Address Mode/Cycle Steal Mode External Bus
External Bus/
'5(4 (Edge Detection), DACK (Read Cycle) ............................................. 506
Figure 14.14
Dual Address Mode/Burst Mode External Bus
External Bus/
'5(4 (Level Detection), DACK (Read Cycle) ............................................ 507
Rev. 3.0, 04/02, page xxv of xxxviii
Figure 14.15
Dual Address Mode/Burst Mode External Bus
External Bus/
'5(4 (Edge Detection), DACK (Read Cycle) ............................................. 508
Figure 14.16
Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection)
External Bus................................................................................................. 509
Figure 14.17
Dual Address Mode/Cycle Steal Mode External Bus
On-Chip SCI
(Level Detection) ......................................................................................... 510
Figure 14.18
Single Address Mode/Cycle Steal Mode External Bus
External Bus/
'5(4
(Level Detection) ......................................................................................... 511
Figure 14.19
Single Address Mode/Cycle Steal Mode External Bus
External Bus/
'5(4
(Edge Detection) .......................................................................................... 512
Figure 14.20
Single Address Mode/Burst Mode External Bus
External Bus/
'5(4
(Level Detection) ......................................................................................... 513
Figure 14.21
Single Address Mode/Burst Mode External Bus
External Bus/
'5(4
(Edge Detection) .......................................................................................... 514
Figure 14.22
Single Address Mode/Burst Mode External Bus
External Bus/
'5(4
(Level Detection)/32-Byte Block Transfer (Bus Width: 32 Bits, SDRAM:
Row Hit Write) ............................................................................................ 515
Figure 14.23
On-Demand Transfer Mode Block Diagram.................................................. 520
Figure 14.24
System Configuration in On-Demand Data Transfer Mode............................ 522
Figure 14.25
Data Transfer Request Format ...................................................................... 523
Figure 14.26
Single Address Mode/Synchronous DRAM
External Device Longword
Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD=1, CAS
latency=3, TPC=3) ....................................................................................... 526
Figure 14.27
Single Address Mode/External Device
Synchronous DRAM Longword
Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD=1,
TRWL=2, TPC=1) ....................................................................................... 527
Figure 14.28
Dual Address Mode/Synchronous DRAM
SRAM Longword Transfer....... 528
Figure 14.29
Single Address Mode/Burst Mode/External Bus
External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ................................... 529
Figure 14.30
Single Address Mode/Burst Mode/External Device
External Bus 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ................................... 529
Figure 14.31
Single Address Mode/Burst Mode/External Bus
External Device 32-Bit
Transfer/Channel 0 On-Demand Data Transfer ............................................. 530
Figure 14.32
Single Address Mode/Burst Mode/External Device
External Bus 32-Bit
Transfer/Channel 0 On-Demand Data Transfer ............................................. 531
Figure 14.33
Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) 532
Figure 14.34
Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data
Transfer) ...................................................................................................... 533
Figure 14.35
Read from Synchronous DRAM Precharge Bank .......................................... 534
Figure 14.36
Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ............... 534
Figure 14.37
Read from Synchronous DRAM (Row Hit)................................................... 535
Figure 14.38
Write to Synchronous DRAM Precharge Bank.............................................. 535
Figure 14.39
Write to Synchronous DRAM Non-Precharge Bank (Row Miss) ................... 536
Rev. 3.0, 04/02, page xxvi of xxxviii
Figure 14.40
Write to Synchronous DRAM (Row Hit) ...................................................... 536
Figure 14.41
Single Address Mode/Burst Mode/External Bus
External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ................................... 537
Figure 14.42
DDT Mode Setting....................................................................................... 538
Figure 14.43
Single Address Mode/Burst Mode/Edge Detection/ External Device
External Bus Data Transfer........................................................................... 538
Figure 14.44
Single Address Mode/Burst Mode/Level Detection/ External Bus
External
Device Data Transfer ................................................................................... 539
Figure 14.45
Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Bus
External Device Data Transfer ........................... 539
Figure 14.46
Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device
External Bus Data Transfer ........................... 540
Figure 14.47
Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Request to Channels 13 Using Data Bus ..................................................... 541
Figure 14.48
Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus
External Device Data Transfer/ Direct Data Transfer Request to Channel 2
without Using Data Bus................................................................................ 542
Figure 14.49
Single Address Mode/Burst Mode/External Bus
External Device Data
Transfer/Direct Data Transfer Request to Channel 2 ..................................... 543
Figure 14.50
Single Address Mode/Burst Mode/External Device
External Bus Data
Transfer/Direct Data Transfer Request to Channel 2 ..................................... 544
Figure 14.51
Single Address Mode/Burst Mode/External Bus
External Device Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 545
Figure 14.52
Single Address Mode/Burst Mode/External Device
External Bus Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 546
Figure 14.53
Block Diagram of the DMAC....................................................................... 550
Figure 14.54
DTR Format (Transfer Request Format) (SH7751R) ..................................... 560
Figure 14.55
Single Address Mode/Burst Mode/External Bus
External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ................................... 565
Figure 14.56
Single Address Mode/Cycle Steal Mode/External Bus
External Device/
32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 ................. 566
Figure 15.1
Block Diagram of SCI .................................................................................. 571
Figure 15.2
SCK Pin....................................................................................................... 587
Figure 15.3
TxD Pin ....................................................................................................... 588
Figure 15.4
RxD Pin ....................................................................................................... 588
Figure 15.5
Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits) .................................................................................. 599
Figure 15.6
Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode) .................................................................................. 601
Figure 15.7
Sample SCI Initialization Flowchart ............................................................. 602
Figure 15.8
Sample Serial Transmission Flowchart ......................................................... 603
Figure 15.9
Example of Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ........................................... 605
Rev. 3.0, 04/02, page xxvii of xxxviii
Figure 15.10
Sample Serial Reception Flowchart (1) ......................................................... 606
Figure 15.11
Example of SCI Receive Operation (Example with 8-Bit Data, Parity,
One Stop Bit) ............................................................................................... 609
Figure 15.12
Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A).................................... 610
Figure 15.13
Sample Multiprocessor Serial Transmission Flowchart ................................. 612
Figure 15.14
Example of SCI Transmit Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)................................................................. 614
Figure 15.15
Sample Multiprocessor Serial Reception Flowchart (1) ................................. 615
Figure 15.16
Example of SCI Receive Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)................................................................. 617
Figure 15.17
Data Format in Synchronous Communication ............................................... 618
Figure 15.18
Sample SCI Initialization Flowchart ............................................................. 620
Figure 15.19
Sample Serial Transmission Flowchart ......................................................... 621
Figure 15.20
Example of SCI Transmit Operation ............................................................. 622
Figure 15.21
Sample Serial Reception Flowchart (1) ......................................................... 623
Figure 15.22
Example of SCI Receive Operation............................................................... 625
Figure 15.23
Sample Flowchart for Serial Data Transmission and Reception ..................... 626
Figure 15.24
Receive Data Sampling Timing in Asynchronous Mode................................ 630
Figure 15.25
Example of Synchronous Transmission by DMAC ....................................... 631
Figure 16.1
Block Diagram of SCIF................................................................................ 635
Figure 16.2
MD8/RTS2 Pin ............................................................................................ 658
Figure 16.3
MD7/CTS2 Pin ............................................................................................ 659
Figure 16.4
MD1/TxD2 Pin ............................................................................................ 660
Figure 16.5
MD2/RxD2 Pin ............................................................................................ 660
Figure 16.6
MD0/SCK2 Pin ............................................................................................ 661
Figure 16.7
Sample SCIF Initialization Flowchart ........................................................... 667
Figure 16.8
Sample Serial Transmission Flowchart ......................................................... 668
Figure 16.9
Example of Transmit Operation (Example with 8-Bit Data, Parity,
One Stop Bit) ............................................................................................... 670
Figure 16.10
Example of Operation Using Modem Control (CTS2) ................................... 670
Figure 16.11
Sample Serial Reception Flowchart (1) ......................................................... 671
Figure 16.11
Sample Serial Reception Flowchart (2) ......................................................... 672
Figure 16.12
Example of SCIF Receive Operation (Example with 8-Bit Data, Parity,
One Stop Bit) ............................................................................................... 674
Figure 16.13
Example of Operation Using Modem Control (RTS2) ................................... 674
Figure 16.14
Receive Data Sampling Timing in Asynchronous Mode................................ 677
Figure 17.1
Block Diagram of Smart Card Interface ........................................................ 680
Figure 17.2
Schematic Diagram of Smart Card Interface Pin Connections........................ 687
Figure 17.3
Smart Card Interface Data Format ................................................................ 688
Figure 17.4
TEND Generation Timing ............................................................................ 690
Figure 17.5
Sample Start Character Waveforms .............................................................. 691
Figure 17.6
Difference in Clock Output According to GM Bit Setting.............................. 693
Rev. 3.0, 04/02, page xxviii of xxxviii
Figure 17.7
Sample Initialization Flowchart .................................................................... 695
Figure 17.8
Sample Transmission Processing Flowchart.................................................. 697
Figure 17.9
Sample Reception Processing Flowchart....................................................... 699
Figure 17.10
Receive Data Sampling Timing in Smart Card Mode .................................... 701
Figure 17.11
Retransfer Operation in SCI Receive Mode................................................... 702
Figure 17.12
Retransfer Operation in SCI Transmit Mode ................................................. 703
Figure 17.13
Procedure for Stopping and Restarting the Clock .......................................... 704
Figure 18.1
16-Bit Port A ............................................................................................... 708
Figure 18.2
16-Bit Port B................................................................................................ 709
Figure 18.3
SCK Pin....................................................................................................... 710
Figure 18.4
TxD Pin ....................................................................................................... 711
Figure 18.5
RxD Pin ....................................................................................................... 711
Figure 18.6
MD1/TxD2 Pin ............................................................................................ 712
Figure 18.7
MD2/RxD2 Pin ............................................................................................ 712
Figure 18.8
MD0/SCK2 Pin............................................................................................ 713
Figure 18.9
MD7/CTS2 Pin ............................................................................................ 714
Figure 18.10
MD8/RTS2 Pin ............................................................................................ 715
Figure 19.1
Block Diagram of INTC ............................................................................... 730
Figure 19.2
Example of IRL Interrupt Connection ........................................................... 733
Figure 19.3
Interrupt Operation Flowchart ...................................................................... 748
Figure 20.1
Block Diagram of User Break Controller ...................................................... 752
Figure 20.2
User Break Debug Support Function Flowchart ............................................ 772
Figure 21.1
Block Diagram of H-UDI Circuit.................................................................. 778
Figure 21.2
TAP Control State Transition Diagram ......................................................... 798
Figure 21.3
H-UDI Reset ................................................................................................ 799
Figure 22.1
PCIC Block Diagram ................................................................................... 803
Figure 22.2
PIO Memory Space Access .......................................................................... 887
Figure 22.3
PIO I/O Space Access .................................................................................. 888
Figure 22.4
Local Address Space Accessing Method ....................................................... 889
Figure 22.5
Example of DMA Transfer Control Register Settings.................................... 893
Figure 22.6
Example of DMA Transfer Flowchart........................................................... 895
Figure 22.7
Master Write Cycle in Host Mode (Single) ................................................... 899
Figure 22.8
Master Read Cycle in Host Mode (Single) .................................................... 900
Figure 22.9
Master Memory Write Cycle in Non-Host Mode (Burst) ............................... 901
Figure 22.10
Master Memory Read Cycle in Non-Host Mode (Burst)................................ 902
Figure 22.11
Target Read Cycle in Non-Host Mode (Single) ............................................. 904
Figure 22.12
Target Write Cycle in Non-Host Mode (Single) ............................................ 905
Figure 22.13
Target Memory Read Cycle in Host Mode (Burst) ........................................ 906
Figure 22.14
Target Memory Write Cycle in Host Mode (Burst) ....................................... 907
Figure 22.15
Master Memory Write Cycle in Host Mode (Burst, With Stepping) ............... 908
Figure 22.16
Target Memory Read Cycle in Host Mode (Burst, With Stepping) ................ 909
Figure 22.17
Endian Conversion Modes for Peripheral Bus ............................................... 910
Figure 22.18
Peripheral Bus
PCI Bus Data Alignment .................................................. 911
Rev. 3.0, 04/02, page xxix of xxxviii
Figure 22.19
Endian Control for Local Bus ....................................................................... 912
Figure 22.20
Data Alignment at DMA Transfer................................................................. 913
Figure 22.21(1) Data Alignment at Target Memory Transfer (Big-Endian Local Bus) ............ 915
Figure 22.21(2) Data Alignment at Target Memory Transfer (Little-Endian Local Bus).......... 916
Figure 22.22
Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian) . 917
Figure 22.23
Data Alignment at Target Configuration Transfer
(Both Big Endian and Little Endian) ............................................................. 918
Figure 23.1
EXTAL Clock Input Timing......................................................................... 956
Figure 23.2(1) CKIO Clock Output Timing ......................................................................... 956
Figure 23.2(2) CKIO Clock Output Timing ......................................................................... 956
Figure 23.3
Power-On Oscillation Settling Time ............................................................. 957
Figure 23.4
Standby Return Oscillation Settling Time (Return by
5(6(7 or 05(6(7) .. 957
Figure 23.5
Power-On Oscillation Settling Time ............................................................. 958
Figure 23.6
Standby Return Oscillation Settling Time (Return by
5(6(7 or 05(6(7) .. 958
Figure 23.7
Standby Return Oscillation Settling Time (Return by NMI) .......................... 959
Figure 23.8
Standby Return Oscillation Settling Time (Return by
,5/,5/)................ 959
Figure 23.9
PLL Synchronization Settling Time in Case of
5(6(7 05(6(7 or
NMI Interrupt............................................................................................... 960
Figure 23.10
PLL Synchronization Settling Time in Case of IRL Interrupt ........................ 960
Figure 23.11
Control Signal Timing .................................................................................. 963
Figure 23.12
Pin Drive Timing for Standby Mode ............................................................. 963
Figure 23.13
SRAM Bus Cycle: Basic Bus Cycle (No Wait) ............................................. 968
Figure 23.14
SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ............................... 969
Figure 23.15
SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait) 970
Figure 23.16
SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time
Insertion, AnS = 1, AnH = 1)........................................................................ 971
Figure 23.17
Burst ROM Bus Cycle (No Wait) ................................................................. 972
Figure 23.18
Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;
2nd/3rd/4th Data: One Internal Wait)............................................................ 973
Figure 23.19
Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion,
AnS = 1, AnH = 1) ....................................................................................... 974
Figure 23.20
Burst ROM Bus Cycle (One Internal Wait + One External Wait)................... 975
Figure 23.21
Synchronous DRAM Auto-Precharge Read Bus Cycle:
Single (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) ........................ 976
Figure 23.22
Synchronous DRAM Auto-Precharge Read Bus Cycle:
Burst (RCD [1:0] = 01, CAS Latency = 3, TPC [2:0] = 011) ......................... 977
Figure 23.23
Synchronous DRAM Normal Read Bus Cycle: ACT + READ Commands,
Burst (RCD [1:0] = 01, CAS Latency = 3) .................................................... 978
Figure 23.24
Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3) ...... 979
Figure 23.25
Synchronous DRAM Normal Read Bus Cycle: READ Command,
Burst (CAS Latency = 3) .............................................................................. 980
Rev. 3.0, 04/02, page xxx of xxxviii
Figure 23.26
Synchronous DRAM Auto-Precharge Write Bus Cycle:
Single (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010)...................... 981
Figure 23.27
Synchronous DRAM Auto-Precharge Write Bus Cycle:
Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010) ....................... 982
Figure 23.28
Synchronous DRAM Normal Write Bus Cycle: ACT + WRITE Commands,
Burst (RCD [1:0] = 01, TRWL [2:0] = 010).................................................. 983
Figure 23.29
Synchronous DRAM Normal Write Bus Cycle: PRE + ACT + WRITE
Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, TRWL [2:0] = 010).... 984
Figure 23.30
Synchronous DRAM Normal Write Bus Cycle: WRITE Command,
Burst (TRWL [2:0] = 010)............................................................................ 985
Figure 23.31
Synchronous DRAM Bus Cycle: Precharge Command (TPC [2:0] = 001) ..... 986
Figure 23.32
Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS = 1, TRC [2:0] = 001) 987
Figure 23.33
Synchronous DRAM Bus Cycle: Self-Refresh (TRC [2:0] = 001) ................. 988
Figure 23.34(a) Synchronous DRAM Bus Cycle: Mode Register Setting (PALL) .................. 989
Figure 23.34(b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET) ..................... 990
Figure 23.35
DRAM Bus Cycles
(1) RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001
(2) RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 010................................ 991
Figure 23.36
DRAM Bus Cycle
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) ............... 992
Figure 23.37
DRAM Bus Cycle
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) ............... 993
Figure 23.38
DRAM Burst Bus Cycle
(EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) ............... 994
Figure 23.39
DRAM Burst Bus Cycle (EDO Mode, RCD [1:0] = 01, AnW [2:0] = 001,
TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) .................................... 995
Figure 23.40
DRAM Burst Bus Cycle: RAS Down Mode State
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) .......................................... 996
Figure 23.41
DRAM Burst Bus Cycle: RAS Down Mode Continuation
(EDO Mode, RCD [1:0] = 00, AnW [2:0] = 000) .......................................... 997
Figure 23.42
DRAM Burst Bus Cycle
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000, TPC [2:0] = 001) ........ 998
Figure 23.43
DRAM Burst Bus Cycle
(Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001, TPC [2:0] = 001) ........ 999
Figure 23.44
DRAM Burst Bus Cycle (Fast Page Mode, RCD [1:0] = 01, AnW [2:0] = 001,
TPC [2:0] = 001, 2-Cycle CAS Negate Pulse Width) .................................... 1000
Figure 23.45
DRAM Burst Bus Cycle: RAS Down Mode State
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) ................................... 1001
Figure 23.46
DRAM Burst Bus Cycle: RAS Down Mode Continuation
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000) ................................... 1002
Figure 23.47
DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS [2:0] = 000, TRC [2:0] = 001)........................................................... 1003
Rev. 3.0, 04/02, page xxxi of xxxviii
Figure 23.48
DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS [2:0] = 001, TRC [2:0] = 001)........................................................... 1004
Figure 23.49
DRAM Bus Cycle: DRAM Self-Refresh (TRC [2:0] = 001) .......................... 1005
Figure 23.50
PCMCIA Memory Bus Cycle
(1) TED [2:0] = 000, TEH [2:0] = 000, No Wait
(2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External
Wait............................................................................................................. 1006
Figure 23.51
PCMCIA I/O Bus Cycle
(1) TED [2:0] = 000, TEH [2:0] = 000, No Wait
(2) TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait + One External
Wait............................................................................................................. 1007
Figure 23.52
PCMCIA I/O Bus Cycle
(TED [2:0] = 001, TEH [2:0] = 001, One Internal Wait, Bus Sizing) ............. 1008
Figure 23.53
MPX Basic Bus Cycle: Read
(1) 1st Data (One Internal Wait)
(2) 1st Data (One Internal Wait + One External Wait) ................................... 1009
Figure 23.54
MPX Basic Bus Cycle: Write
(1) 1st Data (No Wait)
(2) 1st Data (One Internal Wait)
(3) 1st Data (One Internal Wait + One External Wait) ................................... 1010
Figure 23.55
MPX Bus Cycle: Burst Read
(1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait)
(2) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait + One
External Wait).............................................................................................. 1011
Figure 23.56
MPX Bus Cycle: Burst Write
(1) No Internal Wait
(2) 1st Data (One Internal Wait), 2nd to 8th Data (No Internal Wait + External
Wait Control) ............................................................................................... 1012
Figure 23.57
Memory Byte Control SRAM Bus Cycles
(1) Basic Read Cycle (No Wait)
(2) Basic Read Cycle (One Internal Wait)
(3) Basic Read Cycle (One Internal Wait + One External Wait)..................... 1013
Figure 23.58
Memory Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait,
Address Setup/Hold Time Insertion, AnS [0] = 1, AnH [1:0] = 01)................ 1014
Figure 23.59
TCLK Input Timing ..................................................................................... 1019
Figure 23.60
RTC Oscillation Settling Time at Power-On ................................................. 1019
Figure 23.61
SCK Input Clock Timing.............................................................................. 1019
Figure 23.62
SCI I/O Synchronous Mode Clock Timing.................................................... 1019
Figure 23.63
I/O Port Input/Output Timing ....................................................................... 1020
Figure 23.64(a)
'5(4/DRAK Timing.................................................................................. 1020
Figure 23.64(b)
'%5(4/75 Input Timing and %$9/ Output Timing ................................... 1020
Figure 23.65
TCK Input Timing........................................................................................ 1021
Figure 23.66
5(6(7 Hold Timing.................................................................................... 1021
Rev. 3.0, 04/02, page xxxii of xxxviii
Figure 23.67
H-UDI Data Transfer Timing ....................................................................... 1021
Figure 23.68
Pin Break Timing ......................................................................................... 1021
Figure 23.69
NMI Input Timing........................................................................................ 1022
Figure 23.70
PCI Clock Input Timing ............................................................................... 1025
Figure 23.71
Output Signal Timing................................................................................... 1025
Figure 23.72
Output Signal Timing................................................................................... 1026
Figure 23.73
I/O Port Input/Output Timing ....................................................................... 1027
Figure 23.74
Output Load Circuit ..................................................................................... 1028
Figure 23.75
Load Capacitance
-
Delay Time..................................................................... 1029
Figure B.1
Package Dimensions (256-pin QFP) ............................................................. 1039
Figure B.2
Package Dimensions (256-pin BGA) ............................................................ 1040
Figure F.1
Instruction Prefetch ...................................................................................... 1061
Figure G.1
Power-On and Power-Off Procedures ........................................................... 1062
Rev. 3.0, 04/02, page xxxiii of xxxviii
Tables
Table 1.1
SH7751 Series Features ..................................................................................
2
Table 1.2
Pin Functions..................................................................................................
13
Table 1.3
Pin Functions..................................................................................................
24
Table 2.1
Initial Register Values ....................................................................................
37
Table 3.1
MMU Registers ..............................................................................................
54
Table 4.1
Cache Features (SH7751) ...............................................................................
87
Table 4.2
Cache Features (SH7751R).............................................................................
88
Table 4.3
Store Queue Features......................................................................................
88
Table 4.4
Cache Control Registers .................................................................................
88
Table 5.1
Exception-Related Registers ........................................................................... 119
Table 5.2
Exceptions...................................................................................................... 122
Table 5.3
Types of Reset................................................................................................ 130
Table 6.1
Floating-Point Number Formats and Parameters.............................................. 156
Table 6.2
Floating-Point Ranges .................................................................................... 157
Table 7.1
Addressing Modes and Effective Addresses .................................................... 169
Table 7.2
Notation Used in Instruction List .................................................................... 173
Table 7.3
Fixed-Point Transfer Instructions .................................................................... 174
Table 7.4
Arithmetic Operation Instructions ................................................................... 176
Table 7.5
Logic Operation Instructions........................................................................... 178
Table 7.6
Shift Instructions ............................................................................................ 179
Table 7.7
Branch Instructions......................................................................................... 180
Table 7.8
System Control Instructions ............................................................................ 181
Table 7.9
Floating-Point Single-Precision Instructions.................................................... 183
Table 7.10
Floating-Point Double-Precision Instructions .................................................. 184
Table 7.11
Floating-Point Control Instructions ................................................................. 184
Table 7.12
Floating-Point Graphics Acceleration Instructions........................................... 185
Table 8.1
Instruction Groups .......................................................................................... 194
Table 8.2
Parallel-Executability ..................................................................................... 198
Table 8.3
Execution Cycles............................................................................................ 205
Table 9.1
Status of CPU and Peripheral Modules in Power-Down Modes ....................... 216
Table 9.2
Power-Down Mode Registers ......................................................................... 217
Table 9.3
Power-Down Mode Pins ................................................................................. 217
Table 9.4
State of Registers in Standby Mode................................................................. 226
Table 10.1
CPG Pins........................................................................................................ 246
Table 10.2
CPG Register.................................................................................................. 246
Table 10.3(1) Clock Operating Modes (SH7751) .................................................................. 247
Table 10.3(2) Clock Operating Modes (SH7751R)................................................................ 247
Table 10.4
FRQCR Settings and Internal Clock Frequencies............................................. 248
Table 10.5
WDT Registers............................................................................................... 254
Table 11.1
RTC Pins........................................................................................................ 265
Table 11.2
RTC Registers ................................................................................................ 265
Rev. 3.0, 04/02, page xxxiv of xxxviii
Table 11.3
Crystal Oscillator Circuit Constants (Recommended Values)........................... 285
Table 12.1
TMU Pins ...................................................................................................... 288
Table 12.2
TMU Registers............................................................................................... 289
Table 12.3
TMU Interrupt Sources................................................................................... 303
Table 13.1
BSC Pins........................................................................................................ 308
Table 13.2
BSC Registers ................................................................................................ 310
Table 13.3
External Memory Space Map.......................................................................... 312
Table 13.4
PCMCIA Interface Features............................................................................ 314
Table 13.5
PCMCIA Support Interfaces ........................................................................... 315
Table 13.6
Idle Insertion between Accesses...................................................................... 333
Table 13.7
When MPX Interface is Set (Areas 0 to 6)....................................................... 341
Table 13.8
32-Bit External Device/Big-Endian Access and Data Alignment ..................... 360
Table 13.9
16-Bit External Device/Big-Endian Access and Data Alignment ..................... 361
Table 13.10
8-Bit External Device/Big-Endian Access and Data Alignment ....................... 362
Table 13.11
32-Bit External Device/Little-Endian Access and Data Alignment................... 363
Table 13.12
16-Bit External Device/Little-Endian Access and Data Alignment................... 364
Table 13.13
8-Bit External Device/Little-Endian Access and Data Alignment..................... 365
Table 13.14
Relationship between AMXEXT and AMX20 Bits and Address Multiplexing 379
Table 13.15
Example of Correspondence between SH7751 Series and Synchronous DRAM
Address Pins (32-Bit Bus Width, AMX2AMX0 = 000, AMXEXT = 0) ......... 395
Table 13.16
Cycles in Which Pipelined Access Can Be Used ............................................. 409
Table 13.17
Relationship between Address and CE When Using PCMCIA Interface .......... 424
Table 14.1
DMAC Pins.................................................................................................... 467
Table 14.2
DMAC Pins in DDT Mode ............................................................................. 468
Table 14.3
DMAC Registers ............................................................................................ 468
Table 14.4
Selecting External Request Mode with RS Bits ............................................... 487
Table 14.5
Selecting On-Chip Peripheral Module Request Mode with RS Bits.................. 489
Table 14.6
Supported DMA Transfers.............................................................................. 493
Table 14.7
Relationship between DMA Transfer Type, Request Mode, and Bus Mode...... 499
Table 14.8
External Request Transfer Sources and Destinations in Normal Mode ............. 500
Table 14.9
External Request Transfer Sources and Destinations in DDT Mode ................. 501
Table 14.10
Conditions for Transfer between External Memory and an External Device
with DACK, and Corresponding Register Settings .......................................... 519
Table 14.11
Usable SZ, ID, and MD Combination in DDT Mode ....................................... 524
Table 14.12
DMAC Pins.................................................................................................... 551
Table 14.13
DMAC Pins in DDT Mode ............................................................................. 552
Table 14.14
Register Configuration.................................................................................... 553
Table 14.15
Channel Selection by DTR Format (DMAOR.DBL = 1).................................. 560
Table 14.16
Notification of Transfer Channel in Eight-Channel DDT Mode ....................... 563
Table 14.17
Function of
%$9/.......................................................................................... 563
Table 14.18
DTR Format for Clearing Request Queues ...................................................... 564
Table 14.19
DMAC Interrupt-Request Codes..................................................................... 565
Table 15.1
SCI Pins ......................................................................................................... 572
Rev. 3.0, 04/02, page xxxv of xxxviii
Table 15.2
SCI Registers.................................................................................................. 572
Table 15.3
Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ............. 591
Table 15.4
Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode ............... 594
Table 15.5
Maximum Bit Rate for Various Frequencies with Baud Rate Generator
(Asynchronous Mode) .................................................................................... 595
Table 15.6
Maximum Bit Rate with External Clock Input (Asynchronous Mode).............. 596
Table 15.7
Maximum Bit Rate with External Clock Input (Synchronous Mode)................ 596
Table 15.8
SCSMR1 Settings for Serial Transfer Format Selection ................................... 598
Table 15.9
SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection ..................... 598
Table 15.10
Serial Transfer Formats (Asynchronous Mode) ............................................... 600
Table 15.11
Receive Error Conditions................................................................................ 608
Table 15.12
SCI Interrupt Sources ..................................................................................... 627
Table 15.13
SCSSR1 Status Flags and Transfer of Receive Data ........................................ 628
Table 16.1
SCIF Pins ....................................................................................................... 636
Table 16.2
SCIF Registers ............................................................................................... 636
Table 16.3
SCSMR2 Settings for Serial Transfer Format Selection ................................... 663
Table 16.4
SCSCR2 Settings for SCIF Clock Source Selection......................................... 664
Table 16.5
Serial Transfer Formats................................................................................... 665
Table 16.6
SCIF Interrupt Sources ................................................................................... 675
Table 17.1
Smart Card Interface Pins ............................................................................... 681
Table 17.2
Smart Card Interface Registers........................................................................ 681
Table 17.3
Smart Card Interface Register Settings ............................................................ 689
Table 17.4
Values of n and Corresponding CKS1 and CKS0 Settings ............................... 691
Table 17.5
Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0) ... 692
Table 17.6
Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) ................ 692
Table 17.7
Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ........ 692
Table 17.8
Register Settings and SCK Pin State ............................................................... 693
Table 17.9
Smart Card Mode Operating States and Interrupt Sources................................ 700
Table 18.1
32-Bit General-Purpose I/O Port Pins.............................................................. 715
Table 18.2
SCI I/O Port Pins............................................................................................ 717
Table 18.3
SCIF I/O Port Pins.......................................................................................... 717
Table 18.4
I/O Port Registers ........................................................................................... 718
Table 19.1
INTC Pins ...................................................................................................... 731
Table 19.2
INTC Registers............................................................................................... 731
Table 19.3
,5/,5/ Pins and Interrupt Levels ............................................................. 734
Table 19.4
Interrupt Exception Handling Sources and Priority Order ................................ 737
Table 19.5
Interrupt Request Sources and IPRAIPRD Registers...................................... 740
Table 19.6
Interrupt Request Sources and INTPRI00 Register .......................................... 743
Table 19.7
Bit Allocation ................................................................................................. 746
Table 19.8
Interrupt Response Time................................................................................. 750
Table 20.1
UBC Registers................................................................................................ 753
Table 21.1
H-UDI Pins .................................................................................................... 779
Table 21.2
H-UDI Registers............................................................................................. 780
Rev. 3.0, 04/02, page xxxvi of xxxviii
Table 21.3
Structure of Boundary Scan Register............................................................... 784
Table 22.1
Pin Configuration ........................................................................................... 804
Table 22.2
List of PCI Configuration Registers ................................................................ 806
Table 22.3
PCI Configuration Register Configuration....................................................... 807
Table 22.4
List of PCIC Local Registers .......................................................................... 808
Table 22.5
List of CLASS23 to 16 Base Class Codes (CLASS23 to 16)............................ 818
Table 22.6
Memory Space Base Address Register (BASE0) ............................................. 824
Table 22.7
Memory Space Base Address Register (BASE1) ............................................. 826
Table 22.8
Operating Modes ............................................................................................ 879
Table 22.9
PCI Command Support................................................................................... 880
Table 22.10
Access Size .................................................................................................... 911
Table 22.11
DMA Transfer Access Size and Endian Conversion Mode .............................. 913
Table 22.12
Target Transfer Access Size and Endian Conversion Mode ............................. 914
Table 22.13
Interrupts........................................................................................................ 920
Table 22.14
Method of Stopping Clock per Operating Mode .............................................. 925
Table 23.1
Absolute Maximum Ratings ........................................................................... 929
Table 23.2
DC Characteristics (HD6417751RBP240)....................................................... 930
Table 23.3
DC Characteristics (HD6417751RF240) ......................................................... 932
Table 23.4
DC Characteristics (HD6417751RBP200)....................................................... 934
Table 23.5
DC Characteristics (HD6417751RF200) ......................................................... 936
Table 23.6
DC Characteristics (HD6417751BP167) ......................................................... 938
Table 23.7
DC Characteristics (HD6417751BP167I) ........................................................ 940
Table 23.8
DC Characteristics (HD6417751F167)............................................................ 942
Table 23.9
DC Characteristics (HD6417751F167I) .......................................................... 944
Table 23.10
DC Characteristics (HD6417751VF133) ......................................................... 946
Table 23.11
Permissible Output Currents ........................................................................... 948
Table 23.12
Clock Timing (HD6417751RBP240) .............................................................. 948
Table 23.13
Clock Timing (HD6417751RF240)................................................................. 948
Table 23.14
Clock Timing (HD6417751RBP200) .............................................................. 949
Table 23.15
Clock Timing (HD6417751RF200)................................................................. 949
Table 23.16
Clock Timing (HD6417751BP167(I), HD6417751F167(I))............................. 949
Table 23.17
Clock Timing (HD6417751VF133)................................................................. 949
Table 23.18
Clock and Control Signal Timing (HD6417751RBP240)................................. 950
Table 23.19
Clock and Control Signal Timing (HD6417751RF240) ................................... 951
Table 23.20
Clock and Control Signal Timing (HD6417751RBP200)................................. 952
Table 23.21
Clock and Control Signal Timing (HD6417751RF200) ................................... 953
Table 23.22
Clock and Control Signal Timing (HD6417751BP167, HD6417751F167,
HD6417751BP167I, HD6417751F167I) ......................................................... 954
Table 23.23
Clock and Control Signal Timing (HD6417751VF133) ................................... 955
Table 23.24
Control Signal Timing (1)............................................................................... 961
Table 23.25
Control Signal Timing (2)............................................................................... 962
Table 23.26
Bus Timing (1) ............................................................................................... 964
Table 23.27
Bus Timing (2) ............................................................................................... 966
Rev. 3.0, 04/02, page xxxvii of xxxviii
Table 23.28
Peripheral Module Signal Timing (1) .............................................................. 1015
Table 23.29
Peripheral Module Signal Timing (2) .............................................................. 1017
Table 23.30
PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (1)...................... 1023
Table 23.31
PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2)...................... 1024
Table 23.32
PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings
in Non-Host Mode) (1) ................................................................................... 1026
Table 23.33
PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings
in Non-Host Mode) (2) ................................................................................... 1026
Table 23.34
PCIC Signal Timing (With PCIREQ/PCIGNT Port Settings
in Non-Host Mode) ........................................................................................ 1027
Table A.1
Address List ................................................................................................... 1031
Table C.1
Clock Operating Modes (SH7751) .................................................................. 1041
Table C.2
Clock Operating Modes (SH7751R)................................................................ 1041
Table C.3
Area 0 Memory Map and Bus Width............................................................... 1042
Table C.4
Endian............................................................................................................ 1042
Table C.5
Master/Slave .................................................................................................. 1042
Table C.6
Clock Input .................................................................................................... 1042
Table C.7
PCI Mode....................................................................................................... 1043
Table D.1
Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable,
Disable Common)........................................................................................... 1044
Table D.2
Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable) . 1046
Table D.3
Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable) 1047
Table D.4
Handling of Pins When PCI is Not Used ......................................................... 1049
Table H.1
SH7751 Series Models.................................................................................... 1063
Rev. 3.0, 04/02, page xxxviii of xxxviii
Rev. 3.0, 04/02, page 1 of 1064
Section 1 Overview
1.1
SH7751 Series Features
The SH7751 Series microprocessor, featuring a built-in PCI bus controller compatible with PCs
and multimedia devices. The SuperH
TM
* RISC engine is a Hitachi-original 32-bit RISC (Reduced
Instruction Set Computer) microcomputer. The SuperH
TM
RISC engine employs a fixed-length 16-
bit instruction set, allowing an approximately 50% reduction in program size over a 32-bit
instruction set.
The SH7751 Series feature the SH-4 CPU, which at the object code level is upwardly compatible
with the SH-1, SH-2, and SH-3 microcomputers. The SH7751 Series have an instruction cache, an
operand cache that can be switched between copy-back and write-through modes, a 4-entry full-
associative instruction TLB (table look aside buffer), and MMU (memory management unit) with
64-entry full-associative shared TLB.
The SH7751 Series also feature a bus state controller (BSC) that can be directly coupled to
DRAM (page/EDO) and synchronous DRAM without external circuitry. Also, because of its built-
in functions, such as PCI bus controller, timers, and serial communications functions, required for
multimedia and OA equipment, use of the SH7751 Series enable a dramatic reduction in system
costs.
The features of the SH7751 Series are summarized in table 1.1.
Note: * SuperH is a trademark of Hitachi, Ltd.
Rev. 3.0, 04/02, page 2 of 1064
Table 1.1
SH7751 Series Features
Item
Features
LSI
Operating frequency: 240 MHz*
1
/200 MHz*
1
/167 MHz*
2
/133 MHz*
2
Performance:
430 MIPS (240 MHz), 360 MIPS (200 MHz)
300 MIPS (167 MHz), 240 MIPS (133 MHz)
1.2 GFLOPS (167 MHz), 0.93 GFLOPS (133 MHz)
1.7 GFLOPS (240 MHz), 1.4 GFLOPS (200 MHz)
Superscalar architecture: Parallel execution of two instructions
Packages: 256-pin QFP, 256-pin BGA
External buses (SH buses)
Separate 26-bit address and 32-bit data buses
External bus frequency of 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times internal
bus frequency
External bus (PCI bus):
32-bit address/data multiplexing
Selection of internal clock or external PCI-dedicated clock
Rev. 3.0, 04/02, page 3 of 1064
Table 1.1
SH7751 Series Features (cont)
Item
Features
CPU
Original Hitachi SuperH architecture
32-bit internal data bus
General register file:
Sixteen 32-bit general registers (and eight 32-bit shadow registers)
Seven 32-bit control registers
Four 32-bit system registers
RISC-type instruction set (upward-compatible with SuperH Series)
Fixed 16-bit instruction length for improved code efficiency
Load-store architecture
Delayed branch instructions
Conditional execution
C-based instruction set
Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
Instruction execution time: Maximum 2 instructions/cycle
Virtual address space: 4 Gbytes (448-Mbyte external memory space)
Space identifier ASIDs: 8 bits, 256 virtual address spaces
On-chip multiplier
Five-stage pipeline
Rev. 3.0, 04/02, page 4 of 1064
Table 1.1
SH7751 Series Features (cont)
Item
Features
FPU
On-chip floating-point coprocessor
Supports single-precision (32 bits) and double-precision (64 bits)
Supports IEEE754-compliant data types and exceptions
Two rounding modes: Round to Nearest and Round to Zero
Handling of denormalized numbers: Truncation to zero or interrupt
generation for compliance with IEEE754
Floating-point registers: 32 bits
16 words
2 banks
(single-precision
16 words or double-precision
8 words)
2 banks
32-bit CPU-FPU floating-point communication register (FPUL)
Supports FMAC (multiply-and-accumulate) instruction
Supports FDIV (divide) and FSQRT (square root) instructions
Supports FLDI0/FLDI1 (load constant 0/1) instructions
Instruction execution times
Latency (FMAC/FADD/FSUB/FMUL): 3 cycles (single-precision), 8
cycles (double-precision)
Pitch (FMAC/FADD/FSUB/FMUL): 1 cycle (single-precision), 6 cycles
(double-precision)
Note: FMAC is supported for single-precision only.
3-D graphics instructions (single-precision only):
4-dimensional vector conversion and matrix operations (FTRV): 4
cycles (pitch), 7 cycles (latency)
4-dimensional vector inner product (FIPR): 1 cycle (pitch), 4 cycles
(latency)
Five-stage pipeline
Rev. 3.0, 04/02, page 5 of 1064
Table 1.1
SH7751 Series Features (cont)
Item
Features
Clock pulse
generator (CPG)
Choice of main clock
SH7751: 1/2, 1, 3, or 6 times EXTAL
SH7751R: 1, 6, or 12 times EXTAL
Clock modes: (Maximum frequency: Varies with models)
CPU frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
Bus frequency: 1, 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
Peripheral frequency: 1/2, 1/3, 1/4, 1/6, or 1/8 times main clock
Power-down modes
Sleep mode
Deep sleep mode
Pin sleep mode
Standby mode
Hardware standby mode
Module standby function
Single-channel watchdog timer
Memory
management
unit (MMU)
4-Gbyte address space, 256 address space identifiers (8-bit ASIDs)
Single virtual mode and multiple virtual memory mode
Supports multiple page sizes: 1 kbyte, 4 kbytes, 64 kbytes, 1 Mbyte
4-entry fully-associative TLB for instructions
64-entry fully-associative TLB for instructions and operands
Supports software-controlled replacement and random-counter
replacement algorithm
TLB contents can be accessed directly by address mapping
Rev. 3.0, 04/02, page 6 of 1064
Table 1.1
SH7751 Series Features (cont)
Item
Features
Cache memory
[SH7751]
Instruction cache (IC)
8 kbytes, direct mapping
256 entries, 32-byte block length
Normal mode (8-kbyte cache)
Index mode
Operand cache (OC)
16 kbytes, direct mapping
512 entries, 32-byte block length
Normal mode (16-kbyte cache)
Index mode
RAM mode (8-kbyte cache + 8-kbyte RAM)
Choice of write method (copy-back or write-through)
Single-stage copy-back buffer, single-stage write-through buffer
Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
Store queue (32 bytes
2 entries)
Cache memory
[SH7751R]
Instruction cache (IC)
16 kbytes, 2-way set associative
256 entries/way, 32-byte block length
Cache-double-mode (16-kbyte cache)
Index mode
SH7751-compatible mode (8 kbytes, direct mapping)
Operand cache (OC)
32 kbytes, 2-way set associative
512 entries/way, 32-byte block length
Cache-double-mode (32-kbyte cache)
Index mode
RAM mode (16-kbyte cache + 16-kbyte RAM)
Choice of write method (copy-back or write-through)
SH7751-compatible mode (16 kbytes, direct mapping)
Single-stage copy-back buffer, single-stage write-through buffer
Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
Store queue (32 bytes
2 entries)
Rev. 3.0, 04/02, page 7 of 1064
Table 1.1
SH7751 Series Features (cont)
Item
Features
Interrupt controller
(INTC)
Five independent external interrupts (NMI, IRL3 to IRL0)
15-level signed external interrupts: IRL3 to IRL0
On-chip peripheral module interrupts: Priority level can be set for each
module
User break
controller (UBC)
Supports debugging by means of user break interrupts
Two break channels
Address, data value, access type, and data size can all be set as break
conditions
Supports sequential break function
Bus state
controller (BSC)
Supports external memory access
32/16/8-bit external data bus
External memory space divided into seven areas, each of up to 64
Mbytes, with the following parameters settable for each area:
Bus size (8, 16, or 32 bits)
Number of wait cycles (hardware wait function also supported)
Direct connection of DRAM, synchronous DRAM, and burst ROM
possible by setting space type
Supports fast page mode and DRAM EDO
Supports PCMCIA interface
Chip select signals (
$
to
$
) output for relevant areas
DRAM/synchronous DRAM refresh functions
Programmable refresh interval
Supports CAS-before-RAS refresh mode and self-refresh mode
DRAM/synchronous DRAM burst access function
Big endian or little endian mode can be set
Rev. 3.0, 04/02, page 8 of 1064
Table 1.1
SH7751 Series Features (cont)
Item
Features
Direct memory
access controller
(DMAC)
Physical address DMA controller
SH7751: 4-channel
SH7751R: 8-channel
Transfer data size: 8, 16, 32, or 64 bits, or 32 bytes
Address modes:
1-bus-cycle single address mode
2-bus-cycle dual address mode
Transfer requests: External, on-chip peripheral module, or auto-requests
Bus modes: Cycle-steal or burst mode
Supports on-demand data transfer mode (external bus 32 bit)
Timer unit (TMU)
5-channel auto-reload 32-bit timer
Input-capture function on one channel
Selection from 7 counter input clocks in 3 of 5 channels and from 5
counter input clocks on remaining 2 of 5 channels
Realtime clock
(RTC)
On-chip clock and calendar functions
Built-in 32 kHz crystal oscillator with maximum 1/256 second resolution
(cycle interrupts)
Serial
communication
interface
(SCI, SCIF)
Two full-duplex communication channels (SCI, SCIF)
Channel 1 (SCI):
Choice of asynchronous mode or synchronous mode
Supports smart card interface
Channel 2 (SCIF):
Supports asynchronous mode
Separate 16-byte FIFOs provided for transmitter and receiver
Rev. 3.0, 04/02, page 9 of 1064
Table 1.1
SH7751 Series Features (cont)
Item
Features
PCI bus controller
(PCIC)
PCI bus controller (Rev.2.1-compatible)*
3
32-bit bus
33 MHz/66 MHz support
PCI master/slave support
PCI host function support
Built-in bus arbiter
4 built-in PCI-dedicated DMAC (direct memory access controller)
channels
Each channel equipped with 64-byte FIFO
Selection of built-in clock or external PCI-dedicated clock
Interrupt requests can be sent to CPU
Product lineup
Abbreviation
Voltage
Operating
Frequency
Model No.
Package
SH7751
1.8 V
167 MHz
HD6417751BP167
256-pin BGA
HD6417751F167
256-pin QFP
1.5 V
133 MHz
HD6417751VF133
SH7751R
1.5 V
240 MHz
HD6417751RBP240
256-pin BGA
HD6417751RF240
256-pin QFP
200 MHz
HD6417751RBP200
256-pin BGA
HD6417751RF200
256-pin QFP
Note:
*1 SH7751R only
*2 SH7751 only
*3 Some items are not compatible with PCI 2.1.
For more information, see section 22.1.1, Features.
Rev. 3.0, 04/02, page 10 of 1064
1.2
Block Diagram
Figure 1.1 shows an internal block diagram of the SH7751 Series.
Lower 32-bit data
64-bit data (store)
CPG
INTC
SCI
(SCIF)
RTC
TMU
External (SH) bus
interface
DMAC
32-bit data
29-bit address
32-bit data
Address
32-bit data
32-bit data
Upper 32-bit data
32-bit address (instructions)
32-bit data (instructions)
32-bit address (data)
Peripheral address bus
26-bit
SH bus
address
32-bit
PCI
address/
data
32-bit
SH bus
data
Peripheral data bus
UBC
32-bit data (store)
32-bit data (load)
CPU
I cache
O cache
ITLB
UTLB
Cache and
TLB
controller
FPU
BSC:
Bus state controller
CPG:
Clock pulse generator
DMAC: Direct memory access controller
FPU:
Floating-point unit
INTC:
Interrupt controller
ITLB:
Instruction TLB (translation lookaside buffer)
UTLB:
Unified TLB (translation lookaside buffer)
RTC:
Realtime clock
SCI:
Serial communication interface
SCIF:
Serial communication interface with FIFO
TMU:
Timer unit
UBC:
User break controller
PCIC:
PCI bus controller
32-bit data
PCIC
BSC
Address
(PCI)DMAC
Figure 1.1 Block Diagram of SH7751 Series Functions
Rev. 3.0, 04/02, page 11 of 1064
1.3
Pin Arrangement
,
,
,,
,,
,
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
XTAL2
EXTAL2
VDD-RTC
VSS-RTC
CA
NMI
/
/
MD6/
TXD
MD2/RXD2
RXD
TCLK
MD8/
SCK
MD1/TXD2
MD0/SCK2
MD7/
AUDSYNC
AUDCK
AUDATA0
AUDATA1
AUDATA2
AUDATA3
Reserved
MD3/
MD4/
MD5
DACK0
DACK1
DRAK0
DRAK1
STATUS0
STATUS1
/BRKACK
TDO
VDD-PLL2
VSS-PLL2
VDD-PLL1
VSS-PLL1
VDD-CPG
VSS-CPG
XTAL
EXTAL
,
,,
,
,
,
,
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
/
/
PCICLK
IDSEL
/MD9
/MD10
/
/
A25
A24
A23
A22
A21
A20
A19
A18
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
/DQM3
/DQM2
A17
A16
A15
A14
A13
A12
,
,
,
,
,
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TMS
TCK
TDI
/
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
/DQM0
/DQM1
RD/
CKIO
Reserved
Reserved
/
/
CKE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
,
,
,
,
,
,
,
,
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
C/
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
C/
PAR
C/
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
C/
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
QFP256
(Top view)
,
VDD (internal)
VSS (internal)
VDDQ (IO)
VSSQ (IO)
Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1,
VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL
circuits, crystal resonator, and RTC are used.
Figure 1.2 Pin Arrangement (256-Pin QFP)
Rev. 3.0, 04/02, page 12 of 1064
,,
,,
,
,
,,
,,
,
,,
,,
,,
,,
,,
,
,,
,,
,,
,,
,,
,,
,
,
,,
,
,
,,
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
19
20
18
J
K
L
M
N
P
R
T
U
V
W
Y
BGA256
(Top view)
,
,
VDDQ(IO)
VSSQ(IO)
VDD (internal)
VSS (internal)
NC
VSS-PLL1/2
VDD-PLL1/2
VDD-CPG/RTC
VSS-CPG/RTC
*
Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2,
VSS-PLL1, VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of
whether or not the PLL circuits, crystal resonator, and RTC are used.
*
May be connected to V
SS
Q.
Figure 1.3 Pin Arrangement (256-Pin BGA)
Rev. 3.0, 04/02, page 13 of 1064
1.4
Pin Functions
1.4.1
Pin Functions (256-Pin QFP)
Table 1.2
Pin Functions
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
1
TMS
I
Mode
(H-UDI)
2
TCK
I
Clock
(H-UDI)
3
VDDQ
Power
IO VDD
4
VSSQ
Power
IO GND
5
TDI
I
Data in
(H-UDI)
6
&6
O
Chip select 0
&6
&6
7
&6
O
Chip select 1
&6
&6
8
&6
O
Chip select 4
&6
&6
9
&6
O
Chip select 5
&6
&($
&6
10
&6
O
Chip select 6
&6
&(%
&6
11
%6
O
Bus start
(
%6
)
(
%6
)
(
%6
)
(
%6
)
(
%6
)
12
:(
/
5(*
O
D7D0
select signal
:(
5(*
13
:(
O
D15-D8
select signal
:(
:(
14
D0
I/O
Data
A0
15
VDDQ
Power
IO VDD
16
VSSQ
Power
IO GND
17
VDD
Power
Internal VDD
18
VSS
Power
Internal GND
19
D1
I/O
Data
A1
20
D2
I/O
Data
A2
21
D3
I/O
Data
A3
22
D4
I/O
Data
A4
23
D5
I/O
Data
A5
24
D6
I/O
Data
A6
25
D7
I/O
Data
A7
Rev. 3.0, 04/02, page 14 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
26
D8
I/O
Data
A8
27
D9
I/O
Data
A9
28
D10
I/O
Data
A10
29
VDDQ
Power
IO VDD
30
VSSQ
Power
IO GND
31
D11
I/O
Data
A11
32
D12
I/O
Data
A12
33
D13
I/O
Data
A13
34
D14
I/O
Data
A14
35
D15
I/O
Data
A15
36
&$6
/
DQM0
O
D7D0
select signal
&$6
DQM0
37
&$6
/
DQM1
O
D15D8
select signal
&$6
DQM1
38
RD/
:5
O
Read/write
RD/
:5
RD/
:5
RD/
:5
39
CKIO
O
Clock output
CKIO
40
Reserved
Do not connect
41
VDDQ
Power
IO VDD
42
VSSQ
Power
IO GND
43
Reserved
Do not connect
44
5'
/
&$66
/
)5$0(
O
Read/
&$6
/
)5$0(
2(
&$6
2(
)5$0(
45
CKE
O
Clock output
enable
CKE
46
5$6
O
5$6
5$6
5$6
47
VDD
Power
Internal VDD
48
VSS
Power
Internal GND
49
&6
O
Chip select 2
&6
(
&6
)
&6
&6
50
&6
O
Chip select 3
&6
(
&6
)
&6
&6
51
A0
O
Address
52
A1
O
Address
53
A2
O
Address
54
A3
O
Address
55
VDDQ
Power
IO VDD
Rev. 3.0, 04/02, page 15 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
56
VSSQ
Power
IO GND
57
A4
O
Address
58
A5
O
Address
59
A6
O
Address
60
A7
O
Address
61
A8
O
Address
62
A9
O
Address
63
A10
O
Address
64
A11
O
Address
65
A12
O
Address
66
A13
O
Address
67
VDDQ
Power
IO VDD
68
VSSQ
Power
IO GND
69
A14
O
Address
70
A15
O
Address
71
A16
O
Address
72
A17
O
Address
73
&$6
/
DQM2
O
D23D16
select signal
&$6
DQM2
74
&$6
/
DQM3
O
D31D24
select signal
&$6
DQM3
75
D16
I/O
Data
A16
76
D17
I/O
Data
A17
77
D18
I/O
Data
A18
78
D19
I/O
Data
A19
79
VDDQ
Power
IO VDD
80
VSSQ
Power
IO GND
81
VDD
Power
Internal VDD
82
VSS
Power
Internal GND
83
D20
I/O
Data
A20
84
D21
I/O
Data
A21
85
D22
I/O
Data
A22
86
D23
I/O
Data
A23
Rev. 3.0, 04/02, page 16 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
87
D24
I/O
Data
A24
88
D25
I/O
Data
A25
89
D26
I/O
Data
90
D27
I/O
Data
91
D28
I/O
Data
92
D29
I/O
Data
ACCSIZE0
93
VDDQ
Power
IO VDD
94
VSSQ
Power
IO GND
95
D30
I/O
Data
ACCSIZE1
96
D31
I/O
Data
ACCSIZE2
97
VDD
Power
Internal VDD
98
VSS
Power
Internal GND
99
A18
O
Address
100
A19
O
Address
101
A20
O
Address
102
A21
O
Address
103
A22
O
Address
104
A23
O
Address
105
VDDQ
Power
IO VDD
106
VSSQ
Power
IO GND
107
A24
O
Address
108
A25
O
Address
109
:(
/
,&,25'
O
D23D16
select signal
:(
,&,25'
110
:(
/
,&,2:5
O
D31D24
select signal
:(
,&,2:5
111
VDD
Power
Internal VDD
112
VSS
Power
Internal GND
113
6/((3
I
Sleep
114
3&,*17
O
Bus grant
(host function)
115
3&,*17
O
Bus grant
(host function)
Rev. 3.0, 04/02, page 17 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
116
3&,*17
O
Bus grant
(host function)
117
3&,5(4
I
*
Bus request
(host function)
118
3&,5(4
/
MD10
I
*
Bus request
(host
function)/
mode
MD10
119
VDDQ
Power
IO VDD
120
VSSQ
Power
IO GND
121
3&,5(4
/
MD9
I
*
Bus request
(host
function)/
mode
MD9
122
IDSEL
I
Configuration
device select
123
,17$
O
Interrupt
(async)
124
3&,567
O
Reset output
125
PCICLK
I
PCI input
clock
126
3&,*17
/
5(4287
O
Bus grant (host
function)/
bus request
127
3&,5(4
/
*17,1
I
Bus request
(host function)
/bus grant
128
6(55
I/O
System error
129
AD31
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
130
AD30
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
131
VDDQ
Power
IO VDD
132
VSSQ
Power
IO GND
133
AD29
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
Rev. 3.0, 04/02, page 18 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
134
AD28
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
135
AD27
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
136
AD26
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
137
AD25
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
138
AD24
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
139
C/
%(
I/O
Command/byte
enable
140
AD23
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
141
AD22
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
142
AD21
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
143
VDDQ
Power
IO VDD
144
VSSQ
Power
IO GND
145
VDD
Power
Internal VDD
146
VSS
Power
Internal GND
147
AD20
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
148
AD19
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
149
AD18
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
150
AD17
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
151
AD16
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
152
C/
%(
I/O
Command/
byte enable
153
3&,)5$0(
I/O
Bus cycle
154
,5'<
I/O
Initiator ready
155
75'<
I/O
Target read
Rev. 3.0, 04/02, page 19 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
156
'(96(/
I/O
Device select
157
VDDQ
Power
IO VDD
158
VSSQ
Power
IO GND
159
3&,6723
I/O
Transaction
stop
160
3&,/2&.
I/O
Exclusive
access
161
3(55
I/O
Parity error
162
PAR
I/O
Parity
163
C/
%(
I/O
Command/
byte enable
164
AD15
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
165
AD14
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
166
AD13
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
167
AD12
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
168
AD11
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
169
VDDQ
Power
IO VDD
170
VSSQ
Power
IO GND
171
AD10
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
172
AD9
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
173
AD8
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
174
C/
%(
I/O
Command/
byte enable
175
VDD
Power
Internal VDD
176
VSS
Power
Internal GND
177
AD7
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
178
AD6
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
Rev. 3.0, 04/02, page 20 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
179
AD5
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
180
AD4
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
181
AD3
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
182
AD2
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
183
VDDQ
Power
I/O VDD
184
VSSQ
Power
I/O GND
185
AD1
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
186
AD0
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
187
,5/
I
Interrupt 0
188
,5/
I
Interrupt 1
189
,5/
I
Interrupt 2
190
,5/
I
Interrupt 3
191
VSSQ
Power
I/O GND
192
VDDQ
Power
I/O VDD
193
XTAL2
O
RTC crystal
resonator pin
194
EXTAL2
I
RTC crystal
resonator pin
195
VDD-RTC
Power
RTC VDD
196
VSS-RTC
Power
RTC GND
197
CA
I
Hardware
standby
198
5(6(7
I
Reset
5(6(7
199
7567
I
Reset
(H-UDI)
200
05(6(7
I
Manual reset
201
NMI
I
Nonmaskable
interrupt
Rev. 3.0, 04/02, page 21 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
202
%$&.
/
%65(4
O
Bus
acknowledge/
bus request
203
%5(4
/
%6$&.
I
Bus
request/bus
acknowledge
204
MD6/
,2,6
I
Mode/
,2,6
(PCMCIA)
MD6
,2,6
205
5'<
I
Bus ready
5'<
5'<
5'<
206
TXD
O
SCI data
output
207
VDDQ
Power
IO VDD
208
VSSQ
Power
IO GND
209
VDD
Power
Internal VDD
210
VSS
Power
Internal GND
211
MD2/RXD2 I
Mode/SCIF
data input
MD2
RXD2
RXD2
RXD2
RXD2
RXD2
212
RXD
I
SCI data input
213
TCLK
I/O
RTC/TMU
clock
214
MD8/
576
I/O
Mode/SCIF
data control
(RTS)
MD8
576
576
576
576
576
215
SCK
I/O
SCIF clock
216
MD1/TXD2
I/O
Mode/SCIF
data output
MD1
TXD2
TXD2
TXD2
TXD2
TXD2
217
MD0/SCK2 I/O
Mode/SCIF
clock
MD0
SCK2
SCK2
SCK2
SCK2
SCK2
218
MD7/
&76
I/O
Mode/SCIF
data control
(CTS)
MD7
&76
&76
&76
&76
&76
219
AUDSYNC
AUD sync
220
AUDCK
AUD clock
221
VDDQ
Power
IO VDD
222
VSSQ
Power
IO GND
223
AUDATA0
AUD data
224
AUDATA1
AUD data
Rev. 3.0, 04/02, page 22 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
225
VDD
Power
Internal VDD
226
VSS
Power
Internal GND
227
AUDATA2
AUD data
228
AUDATA3
AUD data
229
Reserved
Do not connect
230
MD3/
&($
I/O
Mode/
PCMCIA-CE
MD3
&($
231
MD4/
&(%
I/O
Mode/
PCMCIA-CE
MD4
&(%
232
MD5
I
Mode
MD5
233
VDDQ
Power
IO VDD
234
VSSQ
Power
IO GND
235
DACK0
O
DMAC0 bus
acknowledge
236
DACK1
O
DMAC1 bus
acknowledge
237
DRAK0
O
DMAC0
request
acknowledge
238
DRAK1
O
DMAC1
request
acknowledge
239
VDD
Power
Internal VDD
240
VSS
Power
Internal GND
241
STATUS0
O
Status
242
STATUS1
O
Status
243
'5(4
I
Request from
DMAC0
244
'5(4
I
Request from
DMAC1
245
$6(%5.
/
BRKACK
I/O
Pin break/
acknowledge
(H-UDI)
246
TDO
O
Data out
(H-UDI)
Rev. 3.0, 04/02, page 23 of 1064
Table 1.2
Pin Functions (cont)
Memory Interface
No.
Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
247
VDDQ
Power
IO VDD
248
VSSQ
Power
IO GND
249
VDD-PLL2
Power
PLL2 VDD
250
VSS-PLL2
Power
PLL2 GND
251
VDD-PLL1
Power
PLL1 VDD
252
VSS-PLL1
Power
PLL1 GND
253
VDD-CPG
Power
CPG VDD
254
VSS-CPG
Power
CPG GND
255
XTAL
O
Crystal
resonator
256
EXTAL
I
External input
clock/crystal
resonator
I:
Input
O:
Output
I/O:
Input/output
Power: Power supply
Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby
mode, supply power to RTC as a minimum.
2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not
the on-chip PLL circuits are used.
3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the
on-chip crystal resonator is used.
4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the
on-chip RTC is used.
5. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix
D.
*
I/O attribute is I/O when used as a port.
Rev. 3.0, 04/02, page 24 of 1064
1.4.2
Pin Functions (256-Pin BGA)
Table 1.3
Pin Functions
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
1
B3
TMS
I
Mode
(H-UDI)
2
C4
TCK
I
Clock
(H-UDI)
3
G3
VDDQ
Power
IO VDD
4
F2
VSSQ
Power
IO GND
5
D4
TDI
I
Data in
(H-UDI)
6
B1
&6
O
Chip select 0
&6
&6
7
C2
&6
O
Chip select 1
&6
&6
8
C1
&6
O
Chip select 4
&6
&6
9
D3
&6
O
Chip select 5
&6
&($
&6
10
D2
&6
O
Chip select 6
&6
&(%
&6
11
D1
%6
O
Bus start
(
%6
)
(
%6
)
(
%6
)
(
%6
)
(
%6
)
12
E4
:(
/
5(*
O
D7D0
select signal
:(
5(*
13
E3
:(
O
D15D8
select signal
:(
:(
14
E2
D0
I/O
Data
A0
15
G2
VDDQ
Power
IO VDD
16
L4
VSSQ
Power
IO GND
17
G4
VDD
Power
Internal VDD
18
F4
VSS
Power
Internal GND
19
E1
D1
I/O
Data
A1
20
F3
D2
I/O
Data
A2
21
F1
D3
I/O
Data
A3
22
G1
D4
I/O
Data
A4
23
H4
D5
I/O
Data
A5
24
H3
D6
I/O
Data
A6
25
H2
D7
I/O
Data
A7
26
H1
D8
I/O
Data
A8
27
J4
D9
I/O
Data
A9
Rev. 3.0, 04/02, page 25 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
28
J3
D10
I/O
Data
A10
29
K3
VDDQ
Power
IO VDD
30
L3
VSSQ
Power
IO GND
31
J2
D11
I/O
Data
A11
32
J1
D12
I/O
Data
A12
33
K4
D13
I/O
Data
A13
34
K2
D14
I/O
Data
A14
35
K1
D15
I/O
Data
A15
36
L2
&$6
/
DQM0
O
D7D0
select signal
&$6
DQM0
37
M4
&$6
/
DQM1
O
D15D8
select signal
&$6
DQM1
38
M3
RD/
:5
O
Read/write
RD/
:5
RD/
:5
RD/
:5
39
M1
CKIO
O
Clock output
CKIO
40
M2
NC
Do not connect
41
P3
VDDQ
Power
IO VDD
42
L1
VSSQ
Power
IO GND
43
N3
NC
Do not connect
44
P1
5'
/
&$66
/
)5$0(
O
Read/
&$6
/
)5$0(
2(
&$6
2(
)5$0(
45
N2
CKE
O
Clock output
enable
CKE
46
N1
5$6
O
5$6
5$6
5$6
47
P4
VDD
Power
Internal VDD
48
R4
VSS
Power
Internal GND
49
N4
&6
O
Chip select 2
&6
(
&6
)
&6
&6
50
R3
&6
O
Chip select 3
&6
(
&6
)
&6
&6
51
R1
A0
O
Address
52
T4
A1
O
Address
53
T3
A2
O
Address
54
T2
A3
O
Address
55
P2
VDDQ
Power
IO VDD
Rev. 3.0, 04/02, page 26 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
56
R2
VSSQ
Power
IO GND
57
T1
A4
O
Address
58
U4
A5
O
Address
59
U3
A6
O
Address
60
U2
A7
O
Address
61
U1
A8
O
Address
62
V2
A9
O
Address
63
V1
A10
O
Address
64
W1
A11
O
Address
65
Y1
A12
O
Address
66
Y2
A13
O
Address
67
V7
VDDQ
Power
IO VDD
68
V3
VSSQ
Power
IO GND
69
W3
A14
O
Address
70
Y3
A15
O
Address
71
V4
A16
O
Address
72
W4
A17
O
Address
73
Y4
&$6
/
DQM2
O
D23D16 select
signal
&$6
DQM2
74
U5
&$6
/
DQM3
O
D31D24 select
signal
&$6
DQM3
75
V5
D16
I/O
Data
A16
76
W5
D17
I/O
Data
A17
77
Y5
D18
I/O
Data
A18
78
V6
D19
I/O
Data
A19
79
W7
VDDQ
Power
IO VDD
80
W2
VSSQ
Power
IO GND
81
U7
VDD
Power
Internal VDD
82
U6
VSS
Power
Internal GND
83
Y6
D20
I/O
Data
A20
84
Y7
D21
I/O
Data
A21
85
U8
D22
I/O
Data
A22
86
V8
D23
I/O
Data
A23
Rev. 3.0, 04/02, page 27 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
87
W8
D24
I/O
Data
A24
88
Y8
D25
I/O
Data
A25
89
U9
D26
I/O
Data
90
V9
D27
I/O
Data
91
W9
D28
I/O
Data
92
Y9
D29
I/O
Data
ACCSIZE0
93
V10
VDDQ
Power
IO VDD
94
W6
VSSQ
Power
IO GND
95
W10
D30
I/O
Data
ACCSIZE1
96
Y10
D31
I/O
Data
ACCSIZE2
97
U10
VDD
Power
Internal VDD
98
U11
VSS
Power
Internal GND
99
V11
A18
O
Address
100
Y11
A19
O
Address
101
U12
A20
O
Address
102
V12
A21
O
Address
103
W12
A22
O
Address
104
Y12
A23
O
Address
105
V14
VDDQ
Power
IO VDD
106
W11
VSSQ
Power
IO GND
107
U13
A24
O
Address
108
V13
A25
O
Address
109
W13
:(
/
,&,25'
O
D23D16 select
signal
:(
,&,25'
110
Y13
:(
/
,&,2:5
O
D31D24 select
signal
:(
,&,2:5
111
U14
VDD
Power
Internal VDD
112
U15
VSS
Power
Internal GND
113
Y14
6/((3
I
Sleep
114
V15
3&,*17
O
Bus grant (host
function)
115
Y15
3&,*17
O
Bus grant (host
function)
Rev. 3.0, 04/02, page 28 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
116
U16
3&,*17
O
Bus grant
(host function)
117
V16
3&,5(4
I
*
1
Bus request
(host function)
118
W16
3&,5(4
/
MD10
I
*
1
Bus request
(host function)/
mode
MD10
119
W14
VDDQ
Power
IO VDD
120
W15
VSSQ
Power
IO GND
121
Y16
3&,5(4
/
MD9
I
*
1
Bus request
(host function)/
mode
MD9
122
U17
IDSEL
I
Configuration
device select
123
V17
,17$
O
Interrupt (async)
124
W17
3&,567
O
Reset output
125
Y17
PCICLK
I
PCI input
clock
126
W18
3&,*17
/
5(4287
O
Bus grant (host
function)/
bus request
127
Y18
3&,5(4
/
*17,1
I
Bus request
(host function)/
bus grant
128
Y19
6(55
I/O
System error
129
Y20
AD31
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
130
W20
AD30
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
131
P18
VDDQ
Power
IO VDD
132
V18
VSSQ
Power
IO GND
133
V19
AD29
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
134
V20
AD28
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
135
U18
AD27
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
Rev. 3.0, 04/02, page 29 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
136
U20
AD26
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
137
T17
AD25
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
138
T18
AD24
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
139
U19
C/
%(
I/O
PCI address/
data/port
140
T20
AD23
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
141
R18
AD22
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
142
T19
AD21
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
143
N19
VDDQ
Power
IO VDD
144
W19
VSSQ
Power
IO GND
145
P17
VDD
Power
Internal VDD
146
R17
VSS
Power
Internal GND
147
R20
AD20
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
148
P20
AD19
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
149
P19
AD18
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
150
N20
AD17
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
151
N17
AD16
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
152
N18
C/
%(
I/O
Command/
byte enable
153
M20
3&,)5$0(
I/O
Bus cycle
154
M19
,5'<
I/O
Initiator ready
155
M18
75'<
I/O
Target read
156
M17
'(96(/
I/O
Device select
157
L18
VDDQ
Power
IO VDD
Rev. 3.0, 04/02, page 30 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
158
R19
VSSQ
Power
IO GND
159
L20
3&,6723
I/O
Transaction stop
160
L19
3&,/2&.
I/O
Exclusive access
161
L17
3(55
I/O
Parity error
162
K20
PAR
I/O
Parity
163
K18
C/
%(
I/O
Command/
byte enable
164
J20
AD15
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
165
J19
AD14
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
166
J18
AD13
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
167
J17
AD12
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
168
H20
AD11
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
169
G18
VDDQ
Power
IO VDD
170
K17
VSSQ
Power
IO GND
171
H19
AD10
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
172
G20
AD9
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
173
H18
AD8
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
174
H17
C/
%(
I/O
Command/
byte enable
175
G17
VDD
Power
Internal VDD
176
F17
VSS
Power
Internal GND
177
F18
AD7
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
178
F20
AD6
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
179
E20
AD5
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
Rev. 3.0, 04/02, page 31 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
180
E19
AD4
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
181
E18
AD3
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
182
D20
AD2
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
183
G19
VDDQ
Power
I/O VDD
184
K19
VSSQ
Power
I/O GND
185
D19
AD1
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
186
D18
AD0
I/O
PCI address/
data/port
(Port)
(Port)
(Port)
(Port)
(Port)
187
E17
,5/
I
Interrupt 0
188
C20
,5/
I
Interrupt 1
189
C19
,5/
I
Interrupt 2
190
B20
,5/
I
Interrupt 3
191
B18
NC
Do not connect
*
2
192
D17
VDDQ
Power
I/O VDD
193
A20
XTAL2
O
RTC crystal
resonator pin
194
A19
EXTAL2
I
RTC crystal
resonator pin
195
A18
VDD-RTC
Power
RTC VDD
196
B19
VSS-RTC
Power
RTC GND
197
B17
CA
I
Hardware standby
198
A17
5(6(7
I
Reset
5(6(7
199
C16
7567
I
Reset (H-UDI)
200
B16
05(6(7
I
Manual reset
201
D16
NMI
I
Nonmaskable
interrupt
202
A16
%$&.
/
%65(4
O
Bus acknowledge/
bus request
Rev. 3.0, 04/02, page 32 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
203
B15
%5(4
/
%6$&.
I
Bus
request/bus
acknowledge
204
C15
MD6/
,2,6
I
Mode/
,2,6
(PCMCIA)
MD6
,2,6
205
A15
5'<
I
Bus ready
5'<
5'<
5'<
206
A14
TXD
O
SCI data output
207
B14
VDDQ
Power
IO VDD
208
F19
VSSQ
Power
IO GND
209
D14
VDD
Power
Internal VDD
210
D15
VSS
Power
Internal GND
211
D13
MD2/
RXD2
I
Mode/SCIF
data input
MD2
RXD2
RXD2
RXD2
RXD2
RXD2
212
C13
RXD
I
SCI data input
213
B13
TCLK
I/O
RTC/TMU clock
214
A13
MD8/
576
I/O
Mode/SCIF
data control
(RTS)
MD8
576
576
576
576
576
215
D12
SCK
I/O
SCIF clock
216
B11
MD1/
TXD2
I/O
Mode/SCIF
data output
MD1
TXD2
TXD2
TXD2
TXD2
TXD2
217
C12
MD0/
SCK2
I/O
Mode/SCIF
clock
MD0
SCK2
SCK2
SCK2
SCK2
SCK2
218
A12
MD7/
&76
I/O
Mode/SCIF
data control
(CTS)
MD7
&76
&76
&76
&76
&76
219
B12
AUDSYNC
AUD sync
220
A11
AUDCK
AUD clock
221
C14
VDDQ
Power
IO VDD
222
C18
VSSQ
Power
IO GND
223
C10
AUDATA0
AUD data
224
A10
AUDATA1
AUD data
225
D11
VDD
Power
Internal VDD
226
D10
VSS
Power
Internal GND
Rev. 3.0, 04/02, page 33 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
227
B9
AUDATA2
AUD data
228
D9
AUDATA3
AUD data
229
C9
NC
Do not connect
230
A9
MD3/
&($
I/O
Mode/
PCMCIA-CE
MD3
&($
231
D8
MD4/
&(%
I/O
Mode/
PCMCIA-CE
MD4
&(%
232
C8
MD5
I
Mode
MD5
233
C11
VDDQ
Power
IO VDD
234
C17
VSSQ
Power
IO GND
235
B8
DACK0
O
DMAC0 bus
acknowledge
236
A8
DACK1
O
DMAC1 bus
acknowledge
237
B7
DRAK0
O
DMAC0 request
acknowledge
238
A7
DRAK1
O
DMAC1 request
acknowledge
239
D7
VDD
Power
Internal VDD
240
D6
VSS
Power
Internal GND
241
C6
STATUS0
O
Status
242
B6
STATUS1
O
Status
243
A6
'5(4
I
Request from
DMAC0
244
C5
'5(4
I
Request from
DMAC1
245
D5
$6(%5.
/
BRKACK
I/O
Pin break/
acknowledge
(H-UDI)
246
B4
TDO
O
Data out
(H-UDI)
247
C7
VDDQ
Power
IO VDD
248
B10
VSSQ
Power
IO GND
249
A5
VDD-PLL2
Power
PLL2 VDD
Rev. 3.0, 04/02, page 34 of 1064
Table 1.3
Pin Functions (cont)
Memory Interface
No.
Pin
Number Pin Name
I/O
Function
Reset
SRAM
DRAM
SDRAM
PCMCIA
MPX
250
B5
VSS-PLL2
Power
PLL2 GND
251
A4
VDD-PLL1
Power
PLL1 VDD
252
C3
VSS-PLL1
Power
PLL1 GND
253
A3
VDD-CPG
Power
CPG VDD
254
B2
VSS-CPG
Power
CPG GND
255
A2
XTAL
O
Crystal resonator
256
A1
EXTAL
I
External input
clock/crystal
resonator
I:
Input
O:
Output
I/O:
Input/output
Power: Power supply
Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby
mode, supply power to RTC as a minimum.
2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not
the on-chip PLL circuits are used.
3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the
on-chip crystal resonator is used.
4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the
on-chip RTC is used.
5. For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix
D.
*
1 I/O attribute is I/O when used as a port.
*
2 May be connected to V
SS
Q.
Rev. 3.0, 04/02, page 35 of 1064
Section 2 Programming Model
2.1
Data Formats
The data formats handled by the SH7751 Series are shown in figure 2.1.
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
Single-precision floating-point (32 bits)
Double-precision floating-point (64 bits)
0
7
0
15
0
31
0
31 30
22
fraction
exp
s
0
63 62
51
exp
s
fraction
Figure 2.1 Data Formats
Rev. 3.0, 04/02, page 36 of 1064
2.2
Register Configuration
2.2.1
Privileged Mode and Banks
Processor Modes: The SH7751 Series has two processor modes, user mode and privileged mode.
The SH7751 Series normally operates in user mode, and switches to privileged mode when an
exception occurs or an interrupt is accepted. There are four kinds of registers--general registers,
system registers, control registers, and floating-point registers--and the registers that can be
accessed differ in the two processor modes.
General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to
R7 are banked registers which are switched by a processor mode change.
In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked
register set is accessed as general registers, and which set is accessed only through the load control
register (LDC) and store control register (STC) instructions.
When the RB bit is 1 (that is, when bank 1 is selected), the 16 registers comprising bank 1 general
registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 can be accessed
as general registers R0 to R15. In this case, the eight registers comprising bank 0 general registers
R0_BANK0 to R7_BANK0 are accessed by the LDC/STC instructions. When the RB bit is 0 (that
is, when bank 0 is selected), the 16 registers comprising bank 0 general registers R0_BANK0 to
R7_BANK0 and non-banked general registers R8 to R15 can be accessed as general registers R0
to R15. In this case, the eight registers comprising bank 1 general registers R0_BANK1 to
R7_BANK1 are accessed by the LDC/STC instructions.
In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and
non-banked general registers R8 to R15 can be accessed as general registers R0 to R15. The eight
registers comprising bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed.
Control Registers: Control registers comprise the global base register (GBR) and status register
(SR), which can be accessed in both processor modes, and the saved status register (SSR), saved
program counter (SPC), vector base register (VBR), saved general register 15 (SGR), and debug
base register (DBR), which can only be accessed in privileged mode. Some bits of the status
register (such as the RB bit) can only be accessed in privileged mode.
System Registers: System registers comprise the multiply-and-accumulate registers
(MACH/MACL), the procedure register (PR), the program counter (PC), the floating-point
status/control register (FPSCR), and the floating-point communication register (FPUL). Access to
these registers does not depend on the processor mode.
Rev. 3.0, 04/02, page 37 of 1064
Floating-Point Registers: There are thirty-two floating-point registers, FR0FR15 and XF0
XF15. FR0FR15 and XF0XF15 can be assigned to either of two banks (FPR0_BANK0
FPR15_BANK0 or FPR0_BANK1FPR15_BANK1).
FR0FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating-
point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0
XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix
XMTRX.
Register values after a reset are shown in table 2.1.
Table 2.1
Initial Register Values
Type
Registers
Initial Value*
General registers
R0_BANK0R7_BANK0,
R0_BANK1R7_BANK1,
R8R15
Undefined
SR
MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,
I3I0 = 1111 (H'F), reserved bits = 0, others
undefined
GBR, SSR, SPC, SGR,
DBR
Undefined
Control registers
VBR
H'00000000
MACH, MACL, PR, FPUL
Undefined
PC
H'A0000000
System registers
FPSCR
H'00040001
Floating-point
registers
FR0FR15, XF0XF15
Undefined
Note: * Initialized by a power-on reset and manual reset.
The register configuration in each processor mode is shown in figure 2.2.
Switching between user mode and privileged mode is controlled by the processor mode bit (MD)
in the status register.
Rev. 3.0, 04/02, page 38 of 1064
31
0
R0_BANK0*
1,
*
2
R1_BANK0*
2
R2_BANK0*
2
R3_BANK0*
2
R4_BANK0*
2
R5_BANK0*
2
R6_BANK0*
2
R7_BANK0*
2
R8
R9
R10
R11
R12
R13
R14
R15
SR
GBR
MACH
MACL
PR
PC
(a) Register configuration
in user mode
31
0
R0_BANK1*
1,
*
3
R1_BANK1*
3
R2_BANK1*
3
R3_BANK1*
3
R4_BANK1*
3
R5_BANK1*
3
R6_BANK1*
3
R7_BANK1*
3
R8
R9
R10
R11
R12
R13
R14
R15
R0_BANK0*
1,
*
4
R1_BANK0*
4
R2_BANK0*
4
R3_BANK0*
4
R4_BANK0*
4
R5_BANK0*
4
R6_BANK0*
4
R7_BANK0*
4
(b) Register configuration in
privileged mode (RB = 1)
GBR
MACH
MACL
VBR
PR
SR
SSR
PC
SPC
31
0
R0_BANK1*
1,
*
3
R1_BANK1*
3
R2_BANK1*
3
R3_BANK1*
3
R4_BANK1*
3
R5_BANK1*
3
R6_BANK1*
3
R7_BANK1*
3
R8
R9
R10
R11
R12
R13
R14
R15
R0_BANK0*
1,
*
4
R1_BANK0*
4
R2_BANK0*
4
R3_BANK0*
4
R4_BANK0*
4
R5_BANK0*
4
R6_BANK0*
4
R7_BANK0*
4
(c) Register configuration in
privileged mode (RB = 0)
GBR
MACH
MACL
VBR
PR
SR
SSR
PC
SPC
SGR
DBR
SGR
DBR
Notes: *1 The R0 register is used as the index register in indexed register-indirect addressing mode and
indexed GBR indirect addressing mode.
*2 Banked
registers
*3 Banked
registers
Accessed as general registers when the RB bit is set to 1 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
*4 Banked registers
Accessed as general registers when the RB bit is cleared to 0 in the SR register. Accessed only by
LDC/STC instructions when the RB bit is set to 1.
Figure 2.2 CPU Register Configuration in Each Processor Mode
Rev. 3.0, 04/02, page 39 of 1064
2.2.2
General Registers
Figure 2.3 shows the relationship between the processor modes and general registers. The SH7751
Series has twenty-four 32-bit general registers (R0_BANK0R7_BANK0, R0_BANK1
R7_BANK1, and R8R15). However, only 16 of these can be accessed as general registers R0
R15 in one processor mode. The SH7751 Series has two processor modes, user mode and
privileged mode, in which R0R7 are assigned as shown below.
R0_BANK0R7_BANK0
In user mode (SR.MD = 0), R0R7 are always assigned to R0_BANK0R7_BANK0.
In privileged mode (SR.MD = 1), R0R7 are assigned to R0_BANK0R7_BANK0 only when
SR.RB = 0.
R0_BANK1R7_BANK1
In user mode, R0_BANK1R7_BANK1 cannot be accessed.
In privileged mode, R0R7 are assigned to R0_BANK1R7_BANK1 only when SR.RB = 1.
Rev. 3.0, 04/02, page 40 of 1064
SR.MD = 0 or
(SR.MD = 1, SR.RB = 0)
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R0_BANK0
R1_BANK0
R2_BANK0
R3_BANK0
R4_BANK0
R5_BANK0
R6_BANK0
R7_BANK0
R0_BANK1
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
R0_BANK1
R1_BANK1
R2_BANK1
R3_BANK1
R4_BANK1
R5_BANK1
R6_BANK1
R7_BANK1
R0
R1
R2
R3
R4
R5
R6
R7
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R8
R9
R10
R11
R12
R13
R14
R15
R8
R9
R10
R11
R12
R13
R14
R15
(SR.MD = 1, SR.RB = 1)
Figure 2.3 General Registers
Programming Note: As the user's R0R7 are assigned to R0_BANK0R7_BANK0, and after an
exception or interrupt R0R7 are assigned to R0_BANK1R7_BANK1, it is not necessary for the
interrupt handler to save and restore the user's R0R7 (R0_BANK0R7_BANK0).
After a reset, the values of R0_BANK0R7_BANK0, R0_BANK1R7_BANK1, and R8R15 are
undefined.
Rev. 3.0, 04/02, page 41 of 1064
2.2.3
Floating-Point Registers
Figure 2.4 shows the floating-point registers. There are thirty-two 32-bit floating-point registers,
divided into two banks (FPR0_BANK0FPR15_BANK0 and FPR0_BANK1FPR15_BANK1).
These 32 registers are referenced as FR0FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0XF15,
XD0/2/4/6/8/10/12/14, or XMTRX. The correspondence between FPRn_BANKi and the reference
name is determined by the FR bit in FPSCR (see figure 2.4).
Floating-point registers, FPRn_BANKi (32 registers)
FPR0_BANK0, FPR1_BANK0, FPR2_BANK0, FPR3_BANK0, FPR4_BANK0,
FPR5_BANK0, FPR6_BANK0, FPR7_BANK0, FPR8_BANK0, FPR9_BANK0,
FPR10_BANK0, FPR11_BANK0, FPR12_BANK0, FPR13_BANK0, FPR14_BANK0,
FPR15_BANK0
FPR0_BANK1, FPR1_BANK1, FPR2_BANK1, FPR3_BANK1, FPR4_BANK1,
FPR5_BANK1, FPR6_BANK1, FPR7_BANK1, FPR8_BANK1, FPR9_BANK1,
FPR10_BANK1, FPR11_BANK1, FPR12_BANK1, FPR13_BANK1, FPR14_BANK1,
FPR15_BANK1
Single-precision floating-point registers, FRi (16 registers)
When FPSCR.FR = 0, FR0FR15 are assigned to FPR0_BANK0FPR15_BANK0.
When FPSCR.FR = 1, FR0FR15 are assigned to FPR0_BANK1FPR15_BANK1.
Double-precision floating-point registers or single-precision floating-point register pairs, DRi
(8 registers): A DR register comprises two FR registers.
DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7},
DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15}
Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises
four FR registers
FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7},
FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15}
Single-precision floating-point extended registers, XFi (16 registers)
When FPSCR.FR = 0, XF0XF15 are assigned to FPR0_BANK1FPR15_BANK1.
When FPSCR.FR = 1, XF0XF15 are assigned to FPR0_BANK0FPR15_BANK0.
Single-precision floating-point extended register pairs, XDi (8 registers): An XD register
comprises two XF registers
XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7},
XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15}
Rev. 3.0, 04/02, page 42 of 1064
Single-precision floating-point extended register matrix, XMTRX: XMTRX comprises all 16
XF registers
XMTRX =
XF0
XF4
XF8
XF12
XF1
XF5
XF9
XF13
XF2
XF6
XF10
XF14
XF3
XF7
XF11
XF15
FPR0_BANK0
FPR1_BANK0
FPR2_BANK0
FPR3_BANK0
FPR4_BANK0
FPR5_BANK0
FPR6_BANK0
FPR7_BANK0
FPR8_BANK0
FPR9_BANK0
FPR10_BANK0
FPR11_BANK0
FPR12_BANK0
FPR13_BANK0
FPR14_BANK0
FPR15_BANK0
XF0
XF1
XF2
XF3
XF4
XF5
XF6
XF7
XF8
XF9
XF10
XF11
XF12
XF13
XF14
XF15
FR0
FR1
FR2
FR3
FR4
FR5
FR6
FR7
FR8
FR9
FR10
FR11
FR12
FR13
FR14
FR15
DR0
DR2
DR4
DR6
DR8
DR10
DR12
DR14
FV0
FV4
FV8
FV12
XD0
XMTRX
XD2
XD4
XD6
XD8
XD10
XD12
XD14
FPR0_BANK1
FPR1_BANK1
FPR2_BANK1
FPR3_BANK1
FPR4_BANK1
FPR5_BANK1
FPR6_BANK1
FPR7_BANK1
FPR8_BANK1
FPR9_BANK1
FPR10_BANK1
FPR11_BANK1
FPR12_BANK1
FPR13_BANK1
FPR14_BANK1
FPR15_BANK1
XF0
XF1
XF2
XF3
XF4
XF5
XF6
XF7
XF8
XF9
XF10
XF11
XF12
XF13
XF14
XF15
FR0
FR1
FR2
FR3
FR4
FR5
FR6
FR7
FR8
FR9
FR10
FR11
FR12
FR13
FR14
FR15
DR0
DR2
DR4
DR6
DR8
DR10
DR12
DR14
FV0
FV4
FV8
FV12
XD0
XMTRX
XD2
XD4
XD6
XD8
XD10
XD12
XD14
FPSCR.FR = 0
FPSCR.FR = 1
Figure 2.4 Floating-Point Registers
Rev. 3.0, 04/02, page 43 of 1064
Programming Note: After a reset, the values of FPR0_BANK0FPR15_BANK0 and
FPR0_BANK1FPR15_BANK1 are undefined.
2.2.4
Control Registers
Status register, SR (32 bits, privilege protection, initial value = 0111 0000 0000 0000 0000
00XX 1111 00XX (X = undefined))
31 30
29 28 27
16
15 14
10
9
8
7
4
3
2
1
0
-- MD RB BL
--
FD
--
M
Q
IMASK
--
S
T
Note:
--: Reserved. These bits are always read as 0, and should only be written with 0.
MD: Processor mode
MD = 0: User mode (some instructions cannot be executed, and some resources cannot be
accessed)
MD = 1: Privileged mode
RB: General register specification bit in privileged mode (set to 1 by a reset, exception, or
interrupt)
RB = 0: R0_BANK0R7_BANK0 are accessed as general registers R0R7. (R0_BANK1
R7_BANK1 can be accessed using LDC/STC instructions.)
RB = 1: R0_BANK1R7_BANK1 are accessed as general registers R0R7. (R0_BANK0
R7_BANK0 can be accessed using LDC/STC instructions.)
BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt)
BL = 1: Interrupt requests are masked. If a general exception other than a user break occurs
while BL = 1, the processor switches to the reset state.
FD: FPU disable bit (cleared to 0 by a reset)
FD = 1: An FPU instruction causes a general FPU disable exception, and if the FPU instruction
is in a delay slot, a slot FPU disable exception is generated. (FPU instructions: H'F***
instructions, LDC(.L)/STS(.L) instructions for FPUL/FPSCR)
M, Q: Used by the DIV0S, DIV0U, and DIV1 instructions.
IMASK: Interrupt mask level
Interrupts of a lower level than IMASK are masked. IMASK does not change when an
interrupt is generated.
S: Specifies a saturation operation for a MAC instruction.
T: True/false condition or carry/borrow bit
Rev. 3.0, 04/02, page 44 of 1064
Saved status register, SSR (32 bits, privilege protection, initial value undefined): The current
contents of SR are saved to SSR in the event of an exception or interrupt.
Saved program counter, SPC (32 bits, privilege protection, initial value undefined): The
address of an instruction at which an interrupt or exception occurs is saved to SPC.
Global base register, GBR (32 bits, initial value undefined): GBR is referenced as the base
address in a GBR-referencing MOV instruction.
Vector base register, VBR (32 bits, privilege protection, initial value = H'0000 0000): VBR is
referenced as the branch destination base address in the event of an exception or interrupt. For
details, see section 5, Exceptions.
Saved general register 15, SGR (32 bits, privilege protection, initial value undefined): The
contents of R15 are saved to SGR in the event of an exception or interrupt.
Debug base register, DBR (32 bits, privilege protection, initial value undefined): When the
user break debug function is enabled (BRCR.UBDE = 1), DBR is referenced as the user break
handler branch destination address instead of VBR.
2.2.5
System Registers
Multiply-and-accumulate register high, MACH (32 bits, initial value undefined)
Multiply-and-accumulate register low, MACL (32 bits, initial value undefined)
MACH/MACL is used for the added value in a MAC instruction, and to store a MAC instruction
or MUL instruction operation result.
Procedure register, PR (32 bits, initial value undefined): The return address is stored in PR in a
subroutine call using a BSR, BSRF, or JSR instruction, and PR is referenced by the subroutine
return instruction (RTS).
Program counter, PC (32 bits, initial value = H'A000 0000): PC indicates the executing
instruction address.
Rev. 3.0, 04/02, page 45 of 1064
Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)
31
22
21 20 19
18 17
12
11
7
6
2
1
0
--
FR SZ PR DN
Cause
Enable
Flag
RM
Note:
--: Reserved. These bits are always read as 0, and should only be written with 0.
FR: Floating-point register bank
FR = 0: FPR0_BANK0FPR15_BANK0 are assigned to FR0FR15; FPR0_BANK1
FPR15_BANK1 are assigned to XF0XF15.
FR = 1: FPR0_BANK0FPR15_BANK0 are assigned to XF0XF15; FPR0_BANK1
FPR15_BANK1 are assigned to FR0FR15.
SZ: Transfer size mode
SZ = 0: The data size of the FMOV instruction is 32 bits.
SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).
PR: Precision mode
PR = 0: Floating-point instructions are executed as single-precision operations.
PR = 1: Floating-point instructions are executed as double-precision operations (the result of
instructions for which double-precision is not supported is undefined).
Do not set SZ and PR to 1 simultaneously; this setting is reserved.
[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)
DN: Denormalization mode
DN = 0: A denormalized number is treated as such.
DN = 1: A denormalized number is treated as zero.
Cause: FPU exception cause field
Enable: FPU exception enable field
Flag: FPU exception flag field
FPU
Error (E)
Invalid
Operation (V)
Division
by Zero (Z)
Overflow
(O)
Underflow
(U)
Inexact
(I)
Cause
FPU exception
cause field
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Enable
FPU exception
enable field
None
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Flag
FPU exception
flag field
None
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Rev. 3.0, 04/02, page 46 of 1064
When an FPU operation instruction is executed, the FPU exception cause field is cleared to
zero first. When the next FPU exception is occured, the corresponding bits in the FPU
exception cause field and FPU exception flag field are set to 1. The FPU exception flag field
holds the status of the exception generated after the field was last cleared.
RM: Rounding mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
Bits 22 to 31: Reserved
Floating-point communication register, FPUL (32 bits, initial value undefined): Data transfer
between FPU registers and CPU registers is carried out via the FPUL register.
Programming Note: When SZ = 1 and big endian mode is selected, FMOV can be used for
double-precision floating-point data load or store operations. In little endian mode, two 32-bit data
size moves must be executed, with SZ = 0, to load or store a double-precision floating-point data.
2.3
Memory-Mapped Registers
Appendix A shows the control registers mapped to memory. The control registers are double-
mapped to the following two memory areas. All registers have two addresses.
H'1C00 0000H'1FFF FFFF
H'FC00 0000H'FFFF FFFF
These two areas are used as follows.
H'1C00 0000H'1FFF FFFF
This area must be accessed using the address translation function of the MMU. Setting the
page number of this area to the corresponding filed of the TLB enables access to a memory-
mapped register. Accessing this area without using the address translation function of the
MMU is not guaranteed.
H'FC00 0000H'FFFF FFFF
Access to area H'FC00 0000H'FFFF FFFF in user mode will cause an address error. Memory-
mapped registers can be referenced in user mode by means of access that involves address
translation.
Note:
Do not access undefined locations in either area The operation of an access to an
undefined location is undefined. Also, memory-mapped registers must be accessed using a
fixed data size. The operation of an access using an invalid data size is undefined.
Rev. 3.0, 04/02, page 47 of 1064
2.4
Data Format in Registers
Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits)
or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31
0
Longword
2.5
Data Formats in Memory
Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in
8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is
sign-extended before being loaded into a register.
A word operand must be accessed starting from a word boundary (even address of a 2-byte unit:
address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte
unit: address 4n). An address error will result if this rule is not observed. A byte operand can be
accessed from any address.
Big endian or little endian byte order can be selected for the data format. The endian should be set
with the MD5 external pin in a power-on reset. Big endian is selected when the MD5 pin is low,
and little endian when high. The endian cannot be changed dynamically. Bit positions are
numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the
leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant
bit.
The data format in memory is shown in figure 2.5.
Address A
A
7
0 7
0 7
0 7
0
31
15
0 15
0
31
0
15
0
31
0
23
15
7
0
A + 1
A + 2
A + 3
Byte 0
Word 0
Longword
Word 1
Byte 1 Byte 2 Byte 3
A + 11
7
0 7
0 7
0 7
0
31
15
0
23
15
7
0
A + 10 A + 9
A + 8
Byte 3
Word 1
Longword
Word 0
Byte 2 Byte 1 Byte 0
Address A + 4
Address A + 8
Address A + 8
Address A + 4
Address A
Big endian
Little endian
Figure 2.5 Data Formats In Memory
Rev. 3.0, 04/02, page 48 of 1064
Note:
The SH7751 Series does not support endian conversion for the 64-bit data format.
Therefore, if double-precision floating-point format (64-bit) access is performed in little
endian mode, the upper and lower 32 bits will be reversed.
2.6
Processor States
The SH7751 Series has five processor states: the reset state, exception-handling state, bus-released
state, program execution state, and power-down state.
Reset State: In this state the CPU is reset. The power-on reset state is entered when the
#$%
pin goes low. The CPU enters the manual reset state if the
#$% pin is high and the #$%
pin is low. For more information on resets, see section 5, Exceptions.
In the power-on reset state, the internal state of the CPU and the on-chip peripheral module
registers are initialized. In the manual reset state, the internal state of the CPU and registers of on-
chip peripheral modules other than the bus state controller (BSC) are initialized. Since the bus
state controller (BSC) is not initialized in the manual reset state, refreshing operations continue.
Refer to the register configurations in the relevant sections for further details.
Exception-Handling State: This is a transient state during which the CPU's processor state flow
is altered by a reset, general exception, or interrupt exception source.
In the case of a reset, the CPU branches to address H'A000 0000 and starts executing the user-
coded exception handling program.
In the case of a general exception or interrupt, the program counter (PC) contents are saved in the
saved program counter (SPC), the status register (SR) contents are saved in the saved status
register (SSR), and the R15 contents are saved in saved general register 15 (SGR). The CPU
branches to the start address of the user-coded exception service routine found from the sum of the
contents of the vector base address and the vector offset. See section 5, Exceptions, for more
information on resets, general exceptions, and interrupts.
Program Execution State: In this state the CPU executes program instructions in sequence.
Power-Down State: In the power-down state, CPU operation halts and power consumption is
reduced. The power-down state is entered by executing a SLEEP instruction. There are three
modes in the power-down state: sleep mode, deep sleep mode, and standby mode. For details, see
section 9, Power-Down Modes.
Bus-Released State: In this state the CPU has released the bus to a device that requested it.
Transitions between the states are shown in figure 2.6.
Rev. 3.0, 04/02, page 49 of 1064
RESET = 0
RESET = 1,
MRESET = 1
RESET = 1
Power-on reset state
Manual reset state
Program execution state
Bus-released state
Exception-handling state
Interrupt
Interrupt
End of exception
transition
processing
Bus request
clearance
Exception
interrupt
Bus request
clearance
Bus
request
Bus request
clearance
SLEEP instruction
with STBY bit
cleared
SLEEP instruction
with STBY bit set
From any state when
RESET = 0
From any state when
RESET = 1 and MRESET = 0
Reset state
Power-down state
Bus request
Bus request
Standby mode
Sleep mode
Figure 2.6 Processor State Transitions
2.7
Processor Modes
There are two processor modes: user mode and privileged mode. The processor mode is
determined by the processor mode bit (MD) in the status register (SR). User mode is selected
when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset
state or exception state is entered, the MD bit is set to 1. There are certain registers and bits which
can only be accessed in privileged mode.
Rev. 3.0, 04/02, page 50 of 1064
Rev. 3.0, 04/02, page 51 of 1064
Section 3 Memory Management Unit (MMU)
3.1
Overview
3.1.1
Features
The SH7751 Series can handle 29-bit external memory space from an 8-bit address space
identifier and 32-bit logical (virtual) address space. Address translation from virtual address to
physical address is performed using the memory management unit (MMU) built into the SH7751
Series. The MMU performs high-speed address translation by caching user-created address
translation table information in an address translation buffer (translation lookaside buffer: TLB).
The SH7751 Series has four instruction TLB (ITLB) entries and 64 unified TLB (UTLB) entries.
UTLB copies are stored in the ITLB by hardware. A paging system is used for address translation,
with support for four page sizes (1, 4, and 64 kbytes, and 1 Mbyte). It is possible to set the virtual
address space access right and implement storage protection independently for privileged mode
and user mode.
3.1.2
Role of the MMU
The MMU was conceived as a means of making efficient use of physical memory. As shown in
figure 3.1, when a process is smaller in size than the physical memory, the entire process can be
mapped onto physical memory, but if the process increases in size to the point where it does not fit
into physical memory, it becomes necessary to divide the process into smaller parts, and map the
parts requiring execution onto physical memory on an ad hoc basis ((1)). Having this mapping
onto physical memory executed consciously by the process itself imposes a heavy burden on the
process. The virtual memory system was devised as a means of handling all physical memory
mapping to reduce this burden ((2)). With a virtual memory system, the size of the available
virtual memory is much larger than the actual physical memory, and processes are mapped onto
this virtual memory. Thus processes only have to consider their operation in virtual memory, and
mapping from virtual memory to physical memory is handled by the MMU. The MMU is
normally managed by the OS, and physical memory switching is carried out so as to enable the
virtual memory required by a task to be mapped smoothly onto physical memory. Physical
memory switching is performed via secondary storage, etc.
The virtual memory system that came into being in this way works to best effect in a time sharing
system (TSS) that allows a number of processes to run simultaneously ((3)). Running a number of
processes in a TSS did not increase efficiency since each process had to take account of physical
memory mapping. Efficiency is improved and the load on each process reduced by the use of a
virtual memory system ((4)). In this system, virtual memory is allocated to each process. The task
of the MMU is to map a number of virtual memory areas onto physical memory in an efficient
manner. It is also provided with memory protection functions to prevent a process from
inadvertently accessing another process's physical memory.
Rev. 3.0, 04/02, page 52 of 1064
When address translation from virtual memory to physical memory is performed using the MMU,
it may happen that the translation information has not been recorded in the MMU, or the virtual
memory of a different process is accessed by mistake. In such cases, the MMU will generate an
exception, change the physical memory mapping, and record the new address translation
information.
Although the functions of the MMU could be implemented by software alone, having address
translation performed by software each time a process accessed physical memory would be very
inefficient. For this reason, a buffer for address translation (the translation lookaside buffer: TLB)
is provided in hardware, and frequently used address translation information is placed here. The
TLB can be described as a cache for address translation information. However, unlike a cache, if
address translation fails--that is, if an exception occurs--switching of the address translation
information is normally performed by software. Thus memory management can be performed in a
flexible manner by software.
There are two methods by which the MMU can perform mapping from virtual memory to physical
memory: the paging method, using fixed-length address translation, and the segment method,
using variable-length address translation. With the paging method, the unit of translation is a
fixed-size address space called a page (usually from 1 to 64 kbytes in size).
In the following descriptions, the address space in virtual memory in the SH7751 Series is referred
to as virtual address space, and the address space in physical memory as physical address space.
Rev. 3.0, 04/02, page 53 of 1064
,,
,
,,,,
(2)
Process 1
Process 1
Physical
memory
Process 1
Process 2
Process 3
Virtual
memory
Process 1
Process 1
Process 2
Process 3
MMU
MMU
(4)
(3)
(1)
Physical
memory
Physical
memory
Physical
memory
Physical
memory
Virtual
memory
,,
,,,
,,,,
,,,
,
,
,,,
,,
,
,,,
,,,
,
,,,
,,,,
,
,,,
,,,,
,,
,,,
,,,,
,,
,,
,,,,
,,
,
,,,,
,,
,
,,,
,,
,
,,
,,
,
,
,,
,,,
,,
,,
,,,
,,
,
,
,,
,,
,
,,
,,,
,
,,
,,,,
,
,,
,,,,
,,
,,
,,,,
,,
,,
,,,,
,,
,
,,,,
,,
,
,,,
,,
,
,,
,,
,
,
,,
,,,
,,
,
,,
,,,
,,
,
,
,,
,,
,
,,
,,,
,
,,
,,,,
,
,,
,,,,
,,
,,
,,,,
,,
,,
,,,,
,,
,
,,,,
,,
,
,,,
,,
,
,,
,,
,
,
,,
,,,
,,
,
,
,,
,,,
,,
,
,
,,
,,
,
,,
,,,
,
,,
,,,,
,
,,
,,,,
,,
,,
,,,,
,,
,,
,,,,
,,
,
,,,,
,,
,
,,,
,,
,
,,
,,
,
,
,,
,,,
,,
,
Figure 3.1 Role of the MMU
Rev. 3.0, 04/02, page 54 of 1064
3.1.3
Register Configuration
The MMU registers are shown in table 3.1.
Table 3.1
MMU Registers
Name
Abbrevia-
tion
R/W
Initial
Value*
1
P4
Address*
2
Area 7
Address*
2
Access
Size
Page table entry high
register
PTEH
R/W
Undefined
H'FF00 0000 H'1F00 0000
32
Page table entry low
register
PTEL
R/W
Undefined
H'FF00 0004 H'1F00 0004
32
Page table entry
assistance register
PTEA
R/W
Undefined
H'FF00 0034 H'1F00 0034
32
Translation table base
register
TTB
R/W
Undefined
H'FF00 0008 H'1F00 0008
32
TLB exception address
register
TEA
R/W
Undefined
H'FF00 000C H'1F00 000C 32
MMU control register
MMUCR
R/W
H'0000 0000 H'FF00 0010 H'1F00 0010
32
Notes: *1 The initial value is the value after a power-on reset or manual reset.
*2 P4 address is the address when using the virtual/physical address space P4 area. The
area 7 address is the address used when making an access from physical address
space area 7 using the TLB.
3.1.4
Caution
Operation is not guaranteed if an area designated as a reserved area in this manual is accessed.
Rev. 3.0, 04/02, page 55 of 1064
3.2
Register Descriptions
There are six MMU-related registers.
31
10 9
8
7
0
VPN
PPN
-- --
ASID
1. PTEH
31 30 29 28
10 9
8
7
6
5
4
3
2
1
0
-- -- --
-- V SZ
PR
SZ C D SH WT
2. PTEL
31
4
3
2
0
TC
SA
3. PTEA
31
0
0
TTB
4. TTB
31
Virtual address at which MMU exception or address error occurred
5. TEA
31
26
24 23
18 17 16 15
10 9
8
7
6
5
4
3
2
1
0
LRUI
-- --
-- --
URC
SQMD
SV -- -- -- -- -- TI -- AT
6. MMUCR
-- indicates a reserved bit: the write value must be 0, and a read will return 0.
URB
25
Figure 3.2 MMU-Related Registers
Rev. 3.0, 04/02, page 56 of 1064
1. Page table entry high register (PTEH): Longword access to PTEH can be performed from
H'FF00 0000 in the P4 area and H'1F00 0000 in area 7. PTEH consists of the virtual page number
(VPN) and address space identifier (ASID). When an MMU exception or address error exception
occurs, the VPN of the virtual address at which the exception occurred is set in the VPN field by
hardware. VPN varies according to the page size, but the VPN set by hardware when an exception
occurs consists of the upper 22 bits of the virtual address which caused the exception. VPN setting
can also be carried out by software. The number of the currently executing process is set in the
ASID field by software. ASID is not updated by hardware. VPN and ASID are recorded in the
UTLB by means of the LDLTB instruction. A branch to the P0, P3, or V0 area which uses the
updated ASID after the ASID field in PTEH is rewritten should be made at least 6 instructions
after the PTEH update instruction.
2. Page table entry low register (PTEL): Longword access to PTEL can be performed from
H'FF00 0004 in the P4 area and H'1F00 0004 in area 7. PTEL is used to hold the physical page
number and page management information to be recorded in the UTLB by means of the LDTLB
instruction. The contents of this register are not changed unless a software directive is issued.
3. Page table entry assistance register (PTEA): Longword access to PTEA can be performed
from H'FF00 0034 in the P4 area and H'1F00 0034 in area 7. PTEA is used to store assistance bits
for PCMCIA access to the UTLB by means of the LDTLB instruction. When performing
PCMCIA access with the MMU off, access is always performed using the values of the SA and
TC bits in this register. Access to a PCMCIA interface area by the DMAC is always performed
using the DMAC's CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. The
contents of this register are not changed unless a software directive is issued.
4. Translation table base register (TTB): Longword access to TTB can be performed from
H'FF00 0008 in the P4 area and H'1F00 0008 in area 7. TTB is used, for example, to hold the base
address of the currently used page table. The contents of TTB are not changed unless a software
directive is issued. This register can be freely used by software.
5. TLB exception address register (TEA): Longword access to TEA can be performed from
H'FF00 000C in the P4 area and H'1F00 000C in area 7. After an MMU exception or address error
exception occurs, the virtual address at which the exception occurred is set in TEA by hardware.
The contents of this register can be changed by software.
6. MMU control register (MMUCR): MMUCR contains the following bits:
LRUI:
Least recently used ITLB
URB:
UTLB replace boundary
URC:
UTLB replace counter
SQMD: Store queue mode bit
SV:
Single virtual mode bit
TI:
TLB invalidate
AT:
Address translation bit
Rev. 3.0, 04/02, page 57 of 1064
Longword access to MMUCR can be performed from H'FF00 0010 in the P4 area and H'1F00
0010 in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR
rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an
instruction that performs data access to the P0, P3, U0, or store queue area should be located at
least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0,
P3, or U0 area should be located at least eight instructions after the MMUCR update instruction.
MMUCR contents can be changed by software. The LRUI bits and URC bits may also be updated
by hardware.
LRUI: LRU bits that indicate the ITLB entry for which replacement is to be performed. The
LRU (least recently used) method is used to decide the ITLB entry to be replaced in the event
of an ITLB miss. The entry to be purged from the ITLB can be confirmed using the LRUI bits.
LRUI is updated by means of the algorithm shown below. A dash in this table means that
updating is not performed.
LRUI
[5]
[4]
[3]
[2]
[1]
[0]
When ITLB entry 0 is used
0
0
0
--
--
--
When ITLB entry 1 is used
1
--
--
0
0
--
When ITLB entry 2 is used
--
1
--
1
--
0
When ITLB entry 3 is used
--
--
1
--
1
1
Other than the above
--
--
--
--
--
--
When the LRUI bit settings are as shown below, the corresponding ITLB entry is updated by
an ITLB miss. An asterisk in this table means "Don't care".
LRUI
[5]
[4]
[3]
[2]
[1]
[0]
ITLB entry 0 is updated
1
1
1
*
*
*
ITLB entry 1 is updated
0
*
*
1
1
*
ITLB entry 2 is updated
*
0
*
0
*
1
ITLB entry 3 is updated
*
*
0
*
0
0
Other than the above
Setting prohibited
Ensure that values for which "Setting prohibited" is indicated in the above table are not set at
the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0,
and therefore a prohibited setting is never made by a hardware update.
URB: Bits that indicate the UTLB entry boundary at which replacement is to be performed.
Valid only when URB > 0.
Rev. 3.0, 04/02, page 58 of 1064
URC: Random counter for indicating the UTLB entry for which replacement is to be
performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed.
When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a
value is written to URC by software which results in the condition URC > URB, incrementing
is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB
instruction.
SQMD: Store queue mode bit. Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception in case of user access)
SV: Bit that switches between single virtual memory mode and multiple virtual memory mode.
0: Multiple virtual memory mode
1: Single virtual memory mode
When this bit is changed, ensure that 1 is also written to the TI bit.
TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB
bits. This bit always returns 0 when read.
AT: Address translation enable bit. Specifies MMU enabling or disabling.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is 0. In the case of software that does not
use the MMU, therefore, the AT bit should be cleared to 0.
3.3
Address Space
3.3.1
Physical Address Space
The SH7751 Series supports a 32-bit physical address space, and can access a 4-Gbyte address
space. When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is
this physical address space. The physical address space is divided into a number of areas, as
shown in figure 3.3. The physical address space is permanently mapped onto 29-bit external
memory space; this correspondence can be implemented by ignoring the upper 3 bits of the
physical address space addresses. In privileged mode, the 4-Gbyte space from the P0 area to the
P4 area can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing
the P1 to P4 areas (except the store queue area) in user mode will cause an address error.
Rev. 3.0, 04/02, page 59 of 1064
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
memory space
Address error
Address error
Store queue area
User mode
Privileged mode
P1 area
Cacheable
P0 area
Cacheable
P2 area
Non-cacheable
P3 area
Cacheable
P4 area
Non-cacheable
U0 area
Cacheable
H'0000 0000
H'8000 0000
H'E000 0000
H'E400 0000
H'FFFF FFFF
H'0000 0000
H'8000 0000
H'FFFF FFFF
H'A000 0000
H'C000 0000
H'E000 0000
Figure 3.3 Physical Address Space (MMUCR.AT = 0)
When performing access from the CPU to a PCMCIA interface area in the SH7751 Series, access
is always performed using the values of the SA and TC bits set in the PTEA register. Access to a
PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn,
CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. For details, see section 14, Direct
Memory Access Controller.
P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or
not the cache is used is determined by the cache control register (CCR). When the cache is used,
with the exception of the P1 area, switching between the copy-back method and the write-through
method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified
by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding
external memory space address. However, since area 7 in the external memory space is a reserved
area, a reserved area also appears in these areas.
P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3
bits of an address gives the corresponding external memory space address. However, since area 7
in the external memory space is a reserved area, a reserved area also appears in this area.
P4 Area: The P4 area is mapped onto SH7751 Series on-chip I/O channels. This area cannot be
accessed using the cache. The P4 area is shown in detail in figure 3.4.
Rev. 3.0, 04/02, page 60 of 1064
H'E000 0000
H'E400 0000
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'F500 0000
H'F600 0000
H'F700 0000
H'F800 0000
H'FC00 0000
H'FFFF FFFF
Store queue
Reserved area
Instruction cache address array
Instruction cache data array
Instruction TLB address array
Instruction TLB data arrays 1 and 2
Operand cache address array
Operand cache data array
Unified TLB address array
Unified TLB data arrays 1 and 2
Reserved area
Control register area
Figure 3.4 P4 Area
The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues
(SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the
MMUCR.SQMD bit. For details, see section 4.7, Store Queues.
The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache
address array. For details, see section 4.5.1, IC Address Array.
The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data
array. For details, see section 4.5.2, IC Data Array.
The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB
address array. For details, see section 3.7.1, ITLB Address Array.
The area from H'F300 0000 to H'F3FF FFFF is used for direct access to instruction TLB data
arrays 1 and 2. For details, see sections 3.7.2, ITLB Data Array 1, and 3.7.3, ITLB Data Array 2.
Rev. 3.0, 04/02, page 61 of 1064
The area from H'F400 0000 to H'F4FF FFFF is used for direct access to the operand cache address
array. For details, see section 4.5.3, OC Address Array.
The area from H'F500 0000 to H'F5FF FFFF is used for direct access to the operand cache data
array. For details, see section 4.5.4, OC Data Array.
The area from H'F600 0000 to H'F6FF FFFF is used for direct access to the unified TLB address
array. For details, see section 3.7.4, UTLB Address Array.
The area from H'F700 0000 to H'F7FF FFFF is used for direct access to unified TLB data arrays 1
and 2. For details, see sections 3.7.5, UTLB Data Array 1, and 3.7.6, UTLB Data Array 2.
The area from H'FC00 0000 to H'FFFF FFFF is the on-chip peripheral module control register
area. For details, see appendix A, Address List.
3.3.2
External Memory Space
The SH7751 Series supports a 29-bit external memory space. The external memory space is
divided into eight areas as shown in figure 3.5. Areas 0 to 6 relate to memory, such as SRAM,
synchronous DRAM, DRAM, and PCMCIA. Area 7 is a reserved area. For details, see section 13,
Bus State Controller (BSC).
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1C00 0000
H'1FFF FFFF
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7 (reserved area)
Figure 3.5 External Memory Space
Rev. 3.0, 04/02, page 62 of 1064
3.3.3
Virtual Address Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical address space in
the SH7751 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-
Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue
areas can be increased to a maximum of 256. This is called the virtual address space. Mapping
from virtual address space to 29-bit external memory space is carried out using the TLB. Only
when area 7 in external memory space is accessed using virtual address space, addresses H'1C00
0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4
area control register area in the physical address space. Virtual address space is illustrated in
figure 3.6.
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
memory space
256
256
U0 area
Cacheable
Address translation possible
Address error
Address error
Store queue area
P0 area
Cacheable
Address translation possible
User mode
Privileged mode
P1 area
Cacheable
Address translation not possible
P2 area
Non-cacheable
Address translation not possible
P3 area
Cacheable
Address translation possible
P4 area
Non-cacheable
Address translation not possible
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto the area of the
PCMCIA interface by means of the TLB, it is necessary either to specify 1 for the WT bit or to
specify 0 for the C bit on that page. At that time, the regions are accessed by the values of SA and
TC set in page units of the TLB.
Rev. 3.0, 04/02, page 63 of 1064
Here, access to an area of the PCMCIA interface by accessing an area of P1, P2, or P4 from the
CPU is disabled. In addition, the PCMCIA interface is always accessed by the DMAC with the
values of CHCRn, SSAn, CHCRn.DsAn, CHCRn.STC and CHCRn.DTC in the DMAC. For
details, see Section 14, Direct Memory Access Controller (DMAC).
P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and
U0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF) allow access using the cache and
address translation using the TLB. These areas can be mapped onto any external memory space in
1-, 4-, or 64-kbyte, or 1-Mbyte, page units. When CCR is in the cache-enabled state and the
cacheability bit (C bit) in the TLB is 1, accesses can be performed using the cache. In write
accesses to the cache, switching between the copy-back method and the write-through method is
indicated by the TLB write-through bit (WT bit), and is specified in page units.
Only when the P0, P3, and U0 areas are mapped onto external memory space by means of the
TLB, addresses H'1C00 0000 to H'1FFF FFFF of area 7 in external memory space are allocated to
the control register area. This enables control registers to be accessed from the U0 area in user
mode. In this case, the C bit for the corresponding page must be cleared to 0.
P1, P2, P4 Areas: Address translation using the TLB cannot be performed for the P1, P2, or P4
area (except for the store queue area). Accesses to these areas are the same as for physical address
space. The store queue area can be mapped onto any external memory space by the MMU.
However, operation in the case of an exception differs from that for normal P0, U0, and P3 spaces.
For details, see section 4.7, Store Queues.
3.3.4
On-Chip RAM Space
In the SH7751 Series, half of the operand cache can be used as on-chip RAM. This can be done by
changing the CCR settings.
When the operand cache is used as on-chip RAM (CCR.ORA = 1), P0, U0 area addresses H'7C00
0000 to H'7FFF FFFF are an on-chip RAM area. Data accesses (byte/word/longword/quadword)
can be used in this area. This area can only be used in RAM mode.
3.3.5
Address Translation
When the MMU is used, the virtual address space is divided into units called pages, and
translation to physical addresses is carried out in these page units. The address translation table in
external memory contains the physical addresses corresponding to virtual addresses and additional
information such as memory protection codes. Fast address translation is achieved by caching the
contents of the address translation table located in external memory into the TLB. In the SH7751
Series, basically, the ITLB is used for instruction accesses and the UTLB for data accesses. In the
event of an access to an area other than the P4 area, the accessed virtual address is translated to a
physical address. If the virtual address belongs to the P1 or P2 area, the physical address is
Rev. 3.0, 04/02, page 64 of 1064
uniquely determined without accessing the TLB. If the virtual address belongs to the P0, U0, or P3
area, the TLB is searched using the virtual address, and if the virtual address is recorded in the
TLB, a TLB hit is made and the corresponding physical address is read from the TLB. If the
accessed virtual address is not recorded in the TLB, a TLB miss exception is generated and
processing switches to the TLB miss exception handling routine. In the TLB miss exception
handling routine, the address translation table in external memory is searched, and the
corresponding physical address and page management information are recorded in the TLB. After
the return from the exception handling routine, the instruction which caused the TLB miss
exception is re-executed.
3.3.6
Single Virtual Memory Mode and Multiple Virtual Memory Mode
There are two virtual memory systems, single virtual memory and multiple virtual memory, either
of which can be selected with the MMUCR.SV bit. In the single virtual memory system, a number
of processes run simultaneously, using virtual address space on an exclusive basis, and the
physical address corresponding to a particular virtual address is uniquely determined. In the
multiple virtual memory system, a number of processes run while sharing the virtual address
space, and a particular virtual address may be translated into different physical addresses
depending on the process. The only difference between the single virtual memory and multiple
virtual memory systems in terms of operation is in the TLB address comparison method (see
section 3.4.3, Address Translation Method).
3.3.7
Address Space Identifier (ASID)
In multiple virtual memory mode, the 8-bit address space identifier (ASID) is used to distinguish
between processes running simultaneously while sharing the virtual address space. Software can
set the ASID of the currently executing process in PTEH in the MMU. The TLB does not have to
be purged when processes are switched by means of ASID.
In single virtual memory mode, ASID is used to provide memory protection for processes running
simultaneously while using the virtual memory space on an exclusive basis.
Notes: (1) In single virtual memory mode of the SH7751 Series, entries with the same virtual
page number (VPN) but different ASIDs cannot be set in the TLB simultaneously.
(2) In single virtual memory mode of the SH7751, if the UTLB contains address
translation information including an ITLB miss address with a different ASID and
unshared state (SH bit is 0), SH7751 may hang up or an instruction TLB multiple hit
exception may occur during hardware ITLB miss handling (see section 3.5.4,
Hardware ITLB Miss Handling). To avoid this, when switching the ASID values
(PTEH and ASID) of the current processing, purge the UTLB, or manage the changes
of the program instruction addresses in user mode so that no instruction is executed in
an address area (including overrun prefetch of instruction) that is registered in the
Rev. 3.0, 04/02, page 65 of 1064
UTLB with a different ASID and unshared address translation information. Note that
this restriction does not apply to the SH7751R.
3.4
TLB Functions
3.4.1
Unified TLB (UTLB) Configuration
The unified TLB (UTLB) is so called because of its use for the following two purposes:
1. To translate a virtual address to a physical address in a data access
2. As a table of address translation information to be recorded in the instruction TLB in the event
of an ITLB miss
Information in the address translation table located in external memory is cached into the UTLB.
The address translation table contains virtual page numbers and address space identifiers, and
corresponding physical page numbers and page management information. Figure 3.7 shows the
overall configuration of the UTLB. The UTLB consists of 64 fully-associative type entries. Figure
3.8 shows the relationship between the address format and page size.
PPN [28:10]
PPN [28:10]
PPN [28:10]
SZ [1:0]
SZ [1:0]
SZ [1:0]
SH
SH
SH
C
C
C
PR [1:0]
PR [1:0]
PR [1:0]
ASID [7:0]
ASID [7:0]
ASID [7:0]
VPN [31:10]
VPN [31:10]
VPN [31:10]
V
V
V
Entry 0
Entry 1
Entry 2
D
D
D
WT
WT
WT
PPN [28:10] SZ [1:0] SH C PR [1:0]
SA [2:0]
SA [2:0]
SA [2:0]
TC
TC
TC
SA [2:0] TC
ASID [7:0] VPN [31:10] V
Entry 63
D WT
Figure 3.7 UTLB Configuration
Rev. 3.0, 04/02, page 66 of 1064
31
1-kbyte page
10 9
0
Virtual address
31
4-kbyte page
12 11
0
Virtual address
31
64-kbyte page
16 15
0
Virtual address
31
1-Mbyte page
20 19
0
Virtual address
VPN
Offset
VPN
Offset
VPN
Offset
VPN
Offset
28
10 9
0
Physical address
28
12 11
0
Physical address
28
16 15
0
Physical address
28
20 19
0
Physical address
PPN
Offset
PPN
Offset
PPN
Offset
PPN
Offset
Figure 3.8 Relationship between Page Size and Address Format
VPN: Virtual page number
For 1-kbyte page: upper 22 bits of virtual address
For 4-kbyte page: upper 20 bits of virtual address
For 64-kbyte page: upper 16 bits of virtual address
For 1-Mbyte page: upper 12 bits of virtual address
ASID: Address space identifier
Indicates the process that can access a virtual page.
In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH
bit is 0, this identifier is compared with the ASID in PTEH when address comparison is
performed.
SH: Share status bit
When 0, pages are not shared by processes.
When 1, pages are shared by processes.
Rev. 3.0, 04/02, page 67 of 1064
SZ: Page size bits
Specify the page size.
00: 1-kbyte page
01: 4-kbyte page
10: 64-kbyte page
11: 1-Mbyte page
V: Validity bit
Indicates whether the entry is valid.
0: Invalid
1: Valid
Cleared to 0 by a power-on reset.
Not affected by a manual reset.
PPN: Physical page number
Upper 22 bits of the physical address.
With a 1-kbyte page, PPN bits [28:10] are valid.
With a 4-kbyte page, PPN bits [28:12] are valid.
With a 64-kbyte page, PPN bits [28:16] are valid.
With a 1-Mbyte page, PPN bits [28:20] are valid.
The synonym problem must be taken into account when setting the PPN (see section 3.5.5,
Avoiding Synonym Problems).
PR: Protection key data
2-bit data expressing the page access right as a code.
00: Can be read only, in privileged mode
01: Can be read and written in privileged mode
10: Can be read only, in privileged or user mode
11: Can be read and written in privileged mode or user mode
C: Cacheability bit
Indicates whether a page is cacheable.
0: Not cacheable
1: Cacheable
When control register space is mapped, this bit must be cleared to 0.
When performing PCMCIA space mapping in the cache enabled state, either clear this bit to 0
or set the WT bit to 1.
Rev. 3.0, 04/02, page 68 of 1064
D: Dirty bit
Indicates whether a write has been performed to a page.
0: Write has not been performed
1: Write has been performed
WT: Write-through bit
Specifies the cache write mode.
0: Copy-back mode
1: Write-through mode
When performing PCMCIA space mapping in the cache enabled state, either set this bit to 1 or
clear the C bit to 0.
SA: Space attribute bits
Valid only when the page is mapped onto PCMCIA connected to area 5 or 6.
000: Undefined
001: Variable-size I/O space (base size according to
,2,6 signal)
010: 8-bit I/O space
011: 16-bit I/O space
100: 8-bit common memory space
101: 16-bit common memory space
110: 8-bit attribute memory space
111: 16-bit attribute memory space
TC: Timing control bit
Used to select wait control register bits in the bus control unit for areas 5 and 6.
0: WCR2 (A5W2A5W0) and PCR (A5PCW1A5PCW0, A5TED2A5TED0, A5TEH2
A5TEH0) are used
1: WCR2 (A6W2A6W0) and PCR (A6PCW1A6PCW0, A6TED2A6TED0, A6TEH2
A6TEH0) are used
Rev. 3.0, 04/02, page 69 of 1064
3.4.2
Instruction TLB (ITLB) Configuration
The ITLB is used to translate a virtual address to a physical address in an instruction access.
Information in the address translation table located in the UTLB is cached into the ITLB. Figure
3.9 shows the overall configuration of the ITLB. The ITLB consists of 4 fully-associative type
entries. The address translation information is almost the same as that in the UTLB, but with the
following differences:
1. D and WT bits are not supported.
2. There is only one PR bit, corresponding to the upper of the PR bits in the UTLB.
PPN [28:10]
PPN [28:10]
PPN [28:10]
PPN [28:10]
SZ [1:0]
SZ [1:0]
SZ [1:0]
SZ [1:0]
SH
SH
SH
SH
C
C
C
C
PR
PR
PR
PR
ASID [7:0]
ASID [7:0]
ASID [7:0]
ASID [7:0]
VPN [31:10]
VPN [31:10]
VPN [31:10]
VPN [31:10]
V
V
V
V
Entry 0
Entry 1
Entry 2
Entry 3
SA [2:0]
SA [2:0]
SA [2:0]
SA [2:0]
TC
TC
TC
TC
Figure 3.9 ITLB Configuration
3.4.3
Address Translation Method
Figures 3.10 and 3.11 show flowcharts of memory accesses using the UTLB and ITLB.
Rev. 3.0, 04/02, page 70 of 1064
MMUCR.AT = 1
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs match
and ASIDs match and
V = 1
Only one
entry matches
SR.MD?
CCR.OCE?
CCR.CB?
CCR.WT?
VPNs match
and V = 1
Cache access
in write-through mode
Memory access
PR?
Data TLB multiple
hit exception
Data TLB protection
violation exception
Data TLB miss
exception
Initial page write
exception
Data TLB protection
violation exception
Cache access
in copy-back mode
Data access to virtual address (VA)
On-chip I/O access
R/W?
R/W?
VA is
in P4 area
VA is
in P2 area
VA is
in P1 area
VA is in P0, U0,
or P3 area
Yes
No
1
0
Yes
Yes
No
No
Yes
Yes
Yes
No
No
1 (Privileged)
1
0
0
PR?
0 (User)
D?
R/W?
W
W
W
R
R
R
R
W
R/W?
(Non-cacheable)
WT?
C = 1
and CCR.OCE = 1
No
1
1
0
0
00 or
01
10
11
01 or 11
00 or 10
Figure 3.10 Flowchart of Memory Access Using UTLB
Rev. 3.0, 04/02, page 71 of 1064
MMUCR.AT = 1
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs match
and ASIDs match and
V = 1
Only one
entry matches
SR.MD?
CCR.ICE?
VPNs match
and V = 1
Memory access
Instruction TLB
multiple hit exception
Instruction TLB
miss exception
Instruction access to virtual address (VA)
VA is
in P4 area
VA is
in P2 area
VA is
in P1 area
VA is in P0, U0,
or P3 area
Yes
No
1
0
Yes
Yes
No
No
Yes
Yes
No
(Non-cacheable)
C = 1
and CCR.ICE = 1
No
PR?
Instruction TLB protection
violation exception
Match?
Record in ITLB
Access prohibited
0
1
No
Yes
Yes
No
Hardware ITLB
miss handling
0 (User)
1 (Privileged)
Search UTLB
Cache access
Figure 3.11 Flowchart of Memory Access Using ITLB
Rev. 3.0, 04/02, page 72 of 1064
3.5
MMU Functions
3.5.1
MMU Hardware Management
The SH7751 Series supports the following MMU functions.
1. The MMU decodes the virtual address to be accessed by software, and performs address
translation by controlling the UTLB/ITLB in accordance with the MMUCR settings.
2. The MMU determines the cache access status on the basis of the page management
information read during address translation (C, WT, SA, and TC bits).
3. If address translation cannot be performed normally in a data access or instruction access, the
MMU notifies software by means of an MMU exception.
4. If address translation information is not recorded in the ITLB in an instruction access, the
MMU searches the UTLB, and if the necessary address translation information is recorded in
the UTLB, the MMU copies this information into the ITLB in accordance with
MMUCR.LRUI.
3.5.2
MMU Software Management
Software processing for the MMU consists of the following:
1. Setting of MMU-related registers. Some registers are also partially updated by hardware
automatically.
2. Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB
entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB.
ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. For
deleting or reading UTLB/ITLB entries, it is possible to access the memory-mapped
UTLB/ITLB.
3. MMU exception handling. When an MMU exception occurs, processing is performed based on
information set by hardware.
3.5.3
MMU Instruction (LDTLB)
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB
instruction is issued, the SH7751 Series copies the contents of PTEH, PTEL, and PTEA to the
UTLB entry indicated by MMUCR.URC. ITLB entries are not updated by the LDTLB instruction,
and therefore address translation information purged from the UTLB entry may still remain in the
ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is
issued by a program in the P1 or P2 area. The operation of the LDTLB instruction is shown in
figure 3.12.
Rev. 3.0, 04/02, page 73 of 1064
PPN [28:10]
PPN [28:10]
PPN [28:10]
SZ [1:0]
SZ [1:0]
SZ [1:0]
SH
SH
SH
C
C
C
PR [1:0]
PR [1:0]
PR [1:0]
ASID [7:0]
ASID [7:0]
ASID [7:0]
VPN [31:10]
VPN [31:10]
VPN [31:10]
V
V
V
Entry 0
Entry 1
Entry 2
D
D
D
WT
WT
WT
PPN [28:10] SZ [1:0]
SH C PR [1:0]
SA [2:0]
SA [2:0]
SA [2:0]
TC
TC
TC
SA [2:0] TC
ASID [7:0]
VPN [31:10]
V
Entry 63
D WT
31
29 28
9 8 7 6 5 4 3 2 1 0
--
-- V SZ PR SZ C D SHWT
PTEL
Write
UTLB
31
10 9 8 7
0
--
ASID
PTEH
31
26 25 24 23
18 17 16 15
10 9 8 7
3 2 1 0
LRUI
--
URB
--
URC
SV
SQMD
--
TI -- AT
MMUCR
VPN
10
PPN
31
4 3 2
0
--
SA
TC
PTEA
Entry specification
Figure 3.12 Operation of LDTLB Instruction
3.5.4
Hardware ITLB Miss Handling
In an instruction access, the SH7751 Series searches the ITLB. If it cannot find the necessary
address translation information (i.e. in the event of an ITLB miss), the UTLB is searched by
hardware, and if the necessary address translation information is present, it is recorded in the
ITLB. This procedure is known as hardware ITLB miss handling. If the necessary address
translation information is not found in the UTLB search, an instruction TLB miss exception is
generated and processing passes to software.
Rev. 3.0, 04/02, page 74 of 1064
3.5.5
Avoiding Synonym Problems
When 1- or 4-kbyte pages are recorded in TLB entries, a synonym problem may arise. The
problem is that, when a number of virtual addresses are mapped onto a single physical address, the
same physical address data is recorded in a number of cache entries, and it becomes impossible to
guarantee data integrity. This problem does not occur with the instruction TLB or instruction
cache. In the SH7751 Series, entry specification is performed using bits [13:5] of the virtual
address in order to achieve fast operand cache operation. However, bits [13:10] of the virtual
address in the case of a 1-kbyte page, and bits [13:12] of the virtual address in the case of a 4-
kbyte page, are subject to address translation. As a result, bits [13:10] of the physical address after
translation may differ from bits [13:10] of the virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in UTLB entries.
1. When address translation information whereby a number of 1-kbyte page UTLB entries are
translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:10]
values are the same.
2. When address translation information whereby a number of 4-kbyte page UTLB entries are
translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:12]
values are the same.
3. Do not use 1-kbyte page UTLB entry physical addresses with UTLB entries of a different page
size.
4. Do not use 4-kbyte page UTLB entry physical addresses with UTLB entries of a different page
size.
The above restrictions apply only when performing accesses using the cache. When cache index
mode is used, VPN [25] is used for the entry address instead of VPN [13], and therefore the above
restrictions apply to VPN [25].
Note:
When multiple items of address translation information use the same physical memory to
provide for future SH Series expansion, ensure that the VPN [20:10] values are the same.
Also, do not use the same physical address for address translation information of different
page sizes.
Rev. 3.0, 04/02, page 75 of 1064
3.6
MMU Exceptions
There are seven MMU exceptions: the instruction TLB multiple hit exception, instruction TLB
miss exception, instruction TLB protection violation exception, data TLB multiple hit exception,
data TLB miss exception, data TLB protection violation exception, and initial page write
exception. Refer to figures 3.10 and 3.11 for the conditions under which each of these exceptions
occurs.
3.6.1
Instruction TLB Multiple Hit Exception
An instruction TLB multiple hit exception occurs when more than one ITLB entry matches the
virtual address to which an instruction access has been made. If multiple hits occur when the
UTLB is searched by hardware in hardware ITLB miss handling, a data TLB multiple hit
exception will result.
When an instruction TLB multiple hit exception occurs a reset is executed, and cache coherency is
not guaranteed.
Hardware Processing: In the event of an instruction TLB multiple hit exception, hardware
carries out the following processing:
1. Sets the virtual address at which the exception occurred in TEA.
2. Sets exception code H'140 in EXPEVT.
3. Branches to the reset handling routine (H'A000 0000).
Software Processing (Reset Routine): The ITLB entries which caused the multiple hit exception
are checked in the reset handling routine. This exception is intended for use in program
debugging, and should not normally be generated.
3.6.2
Instruction TLB Miss Exception
An instruction TLB miss exception occurs when address translation information for the virtual
address to which an instruction access is made is not found in the UTLB entries by the hardware
ITLB miss handling procedure. The instruction TLB miss exception processing carried out by
hardware and software is shown below. This is the same as the processing for a data TLB miss
exception.
Rev. 3.0, 04/02, page 76 of 1064
Hardware Processing: In the event of an instruction TLB miss exception, hardware carries out
the following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'040 in EXPEVT.
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are
saved in SGR.
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and
starts the instruction TLB miss exception handling routine.
Software Processing (Instruction TLB Miss Exception Handling Routine): Software is
responsible for searching the external memory page table and assigning the necessary page table
entry. Software should carry out the following processing in order to find and assign the necessary
page table entry.
1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table
entry recorded in the external memory address translation table. If necessary, the values of the
SA and TC bits should be written to PTEA.
2. When the entry to be replaced in entry replacement is specified by software, write that value to
URC in the MMUCR register. If URC is greater than URB at this time, the value should be
changed to an appropriate value after issuing an LDTLB instruction.
3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the TLB.
4. Finally, execute the exception handling return instruction (RTE), terminate the exception
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
3.6.3
Instruction TLB Protection Violation Exception
An instruction TLB protection violation exception occurs when, even though an ITLB entry
contains address translation information matching the virtual address to which an instruction
access is made, the actual access type is not permitted by the access right specified by the PR bit.
The instruction TLB protection violation exception processing carried out by hardware and
software is shown below.
Rev. 3.0, 04/02, page 77 of 1064
Hardware Processing: In the event of an instruction TLB protection violation exception,
hardware carries out the following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'0A0 in EXPEVT.
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
5. Sets the SR contents at the time of the exception in SSR. Set the current R15 value in SGR.
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and
starts the instruction TLB protection violation exception handling routine.
Software Processing (Instruction TLB Protection Violation Exception Handling Routine):
Resolve the instruction TLB protection violation, execute the exception handling return instruction
(RTE), terminate the exception handling routine, and return control to the normal flow. The RTE
instruction should be issued at least one instruction after the LDTLB instruction.
3.6.4
Data TLB Multiple Hit Exception
A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual
address to which a data access has been made. A data TLB multiple hit exception is also generated
if multiple hits occur when the UTLB is searched in hardware ITLB miss handling.
When a data TLB multiple hit exception occurs a reset is executed, and cache coherency is not
guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted.
Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the
following processing:
1. Sets the virtual address at which the exception occurred in TEA.
2. Sets exception code H'140 in EXPEVT.
3. Branches to the reset handling routine (H'A000 0000).
Software Processing (Reset Routine): The UTLB entries which caused the multiple hit
exception are checked in the reset handling routine. This exception is intended for use in program
debugging, and should not normally be generated.
Rev. 3.0, 04/02, page 78 of 1064
3.6.5
Data TLB Miss Exception
A data TLB miss exception occurs when address translation information for the virtual address to
which a data access is made is not found in the UTLB entries. The data TLB miss exception
processing carried out by hardware and software is shown below.
Hardware Processing: In the event of a data TLB miss exception, hardware carries out the
following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write, in EXPEVT
(OCBP, OCBWB: read; OCBI, MOVCA.L: write).
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
5. Sets the SR contents at the time of the exception in SSR, and sets the R15 contents at the time
in SGR.
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0400 to the contents of VBR, and
starts the data TLB miss exception handling routine.
Software Processing (Data TLB Miss Exception Handling Routine): Software is responsible
for searching the external memory page table and assigning the necessary page table entry.
Software should carry out the following processing in order to find and assign the necessary page
table entry.
1. Write to PTEL the values of the PPN, PR, SZ, C, D, SH, V, and WT bits in the page table
entry recorded in the external memory address translation table. If necessary, the values of the
SA and TC bits should be written to PTEA.
2. When the entry to be replaced in entry replacement is specified by software, write that value to
URC in the MMUCR register. If URC is greater than URB at this time, the value should be
changed to an appropriate value after issuing an LDTLB instruction.
3. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the
UTLB.
4. Finally, execute the exception handling return instruction (RTE), terminate the exception
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
Rev. 3.0, 04/02, page 79 of 1064
3.6.6
Data TLB Protection Violation Exception
A data TLB protection violation exception occurs when, even though a UTLB entry contains
address translation information matching the virtual address to which a data access is made, the
actual access type is not permitted by the access right specified by the PR bit. The data TLB
protection violation exception processing carried out by hardware and software is shown below.
Hardware Processing: In the event of a data TLB protection violation exception, hardware
carries out the following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'0A0 in the case of a read, or H'0C0 in the case of a write, in EXPEVT
(OCBP, OCBWB: read; OCBI, MOVCA.L: write).
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are
saved in SGR.
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and
starts the data TLB protection violation exception handling routine.
Software Processing (Data TLB Protection Violation Exception Handling Routine): Resolve
the data TLB protection violation, execute the exception handling return instruction (RTE),
terminate the exception handling routine, and return control to the normal flow. The RTE
instruction should be issued at least one instruction after the LDTLB instruction.
3.6.7
Initial Page Write Exception
An initial page write exception occurs when the D bit is 0 even though a UTLB entry contains
address translation information matching the virtual address to which a data access (write) is
made, and the access is permitted. The initial page write exception processing carried out by
hardware and software is shown below.
Hardware Processing: In the event of an initial page write exception, hardware carries out the
following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
Rev. 3.0, 04/02, page 80 of 1064
3. Sets exception code H'080 in EXPEVT.
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are
saved in SGR.
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and
starts the initial page write exception handling routine.
Software Processing (Initial Page Write Exception Handling Routine): The following
processing should be carried out as the responsibility of software:
1. Retrieve the necessary page table entry from external memory.
2. Write 1 to the D bit in the external memory page table entry.
3. Write to PTEL the values of the PPN, PR, SZ, C, D, WT, SH, and V bits in the page table
entry recorded in external memory. If necessary, the values of the SA and TC bits should be
written to PTEA.
4. When the entry to be replaced in entry replacement is specified by software, write that value to
URC in the MMUCR register. If URC is greater than URB at this time, the value should be
changed to an appropriate value after issuing an LDTLB instruction.
5. Execute the LDTLB instruction and write the contents of PTEH, PTEL, and PTEA to the
UTLB.
6. Finally, execute the exception handling return instruction (RTE), terminate the exception
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
3.7
Memory-Mapped TLB Configuration
To enable the ITLB and UTLB to be managed by software, their contents can be read and written
by a P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if
access is made from a program in the other area. A branch to an area other than the P2 area should
be made at least 8 instructions after this MOV instruction. The ITLB and UTLB are allocated to
the P4 area in physical address space. VPN, V, and ASID in the ITLB can be accessed as an
address array, PPN, V, SZ, PR, C, and SH as data array 1, and SA and TC as data array 2. VPN,
D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and
SH as data array 1, and SA and TC as data array 2. V and D can be accessed from both the address
array side and the data array side. Only longword access is possible. Instruction fetches cannot be
Rev. 3.0, 04/02, page 81 of 1064
performed in these areas. For reserved bits, a write value of 0 should be specified; their read value
is undefined.
3.7.1
ITLB Address Array
The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array, and the
entry is selected by bits [9:8]. As longword access is used, 0 should be specified for address field
bits [1:0].
In the data field, VPN is indicated by bits [31:10], V by bit [8], and ASID by bits [7:0].
The following two kinds of operation can be used on the ITLB address array:
1. ITLB address array read
VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry
set in the address field.
2. ITLB address array write
VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to
the entry set in the address field.
Address field
31
23
0
1 1 1 1 0 0 1 0
E
Data field
31
10 9
0
V
VPN
VPN:
V:
E:
24
Virtual page number
Validity bit
Entry
10 9 8 7
9 8 7
ASID
ASID:
:
Address space identifier
Reserved bits (0 write value, undefined
read value)
Figure 3.13 Memory-Mapped ITLB Address Array
Rev. 3.0, 04/02, page 82 of 1064
3.7.2
ITLB Data Array 1
ITLB data array 1 is allocated to addresses H'F300 0000 to H'F37F FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, and SH to be written to the data array are
specified in the data field.
In the address field, bits [31:23] have the value H'F30 indicating ITLB data array 1, and the entry
is selected by bits [9:8].
In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bit
[6], C by bit [3], and SH by bit [1].
The following two kinds of operation can be used on ITLB data array 1:
1. ITLB data array 1 read
PPN, V, SZ, PR, C, and SH are read into the data field from the ITLB entry corresponding to
the entry set in the address field.
2. ITLB data array 1 write
PPN, V, SZ, PR, C, and SH specified in the data field are written to the ITLB entry
corresponding to the entry set in the address field.
Address field
31
23
0
1 1 1 1 0 0
0
1 1
E
Data field
PPN:
V:
E:
SZ:
24
Physical page number
Validity bit
Entry
Page size bits
10 9 8 7
PR:
C:
SH:
:
Protection key data
Cacheability bit
Share status bit
Reserved bits (0 write value, undefined
read value)
31
2 1 0
V
10 9 8 7
30 29 28
4 3
6 5
SZ
SH
PR
C
PPN
Figure 3.14 Memory-Mapped ITLB Data Array 1
Rev. 3.0, 04/02, page 83 of 1064
3.7.3
ITLB Data Array 2
ITLB data array 2 is allocated to addresses H'F380 0000 to H'F3FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F38 indicating ITLB data array 2, and the entry
is selected by bits [9:8].
In the data field, SA is indicated by bits [2:0], and TC by bit [3].
The following two kinds of operation can be used on ITLB data array 2:
1. ITLB data array 2 read
SA and TC are read into the data field from the ITLB entry corresponding to the entry set in
the address field.
2. ITLB data array 2 write
SA and TC specified in the data field are written to the ITLB entry corresponding to the entry
set in the address field.
Address field
31
23
0
1 1 1 1 0 0 1 1 1
E
Data field
31
4
0
TC:
E:
24
Timing control bit
Entry
8
9
7
3 2
SA:
:
Space attribute bits
Reserved bits (0 write value, undefined read
value)
10
SA
TC
Figure 3.15 Memory-Mapped ITLB Data Array 2
3.7.4
UTLB Address Array
The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, D, V, and ASID to be written to the address array are
specified in the data field.
Rev. 3.0, 04/02, page 84 of 1064
In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array, and the
entry is selected by bits [13:8]. The address array bit [7] association bit (A bit) specifies whether
or not address comparison is performed when writing to the UTLB address array.
In the data field, VPN is indicated by bits [31:10], D by bit [9], V by bit [8], and ASID by bits
[7:0].
The following three kinds of operation can be used on the UTLB address array:
1. UTLB address array read
VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
2. UTLB address array write (non-associative)
VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding
to the entry set in the address field. The A bit in the address field should be cleared to 0.
3. UTLB address array write (associative)
When a write is performed with the A bit in the address field set to 1, comparison of all the
UTLB entries is carried out using the VPN specified in the data field and PTEH.ASID. The
usual address comparison rules are followed, but if a UTLB miss occurs, the result is no
operation, and an exception is not generated. If the comparison identifies a UTLB entry
corresponding to the VPN specified in the data field, D and V specified in the data field are
written to that entry. If there is more than one matching entry, a data TLB multiple hit
exception results. This associative operation is simultaneously carried out on the ITLB, and if
a matching entry is found in the ITLB, V is written to that entry. Even if the UTLB
comparison results in no operation, a write to the ITLB side only is performed as long as there
is an ITLB match. If there is a match in both the UTLB and ITLB, the UTLB information is
also written to the ITLB.
Address field
Data field
VPN:
V:
E:
D:
Virtual page number
Validity bit
Entry
Dirty bit
ASID:
A:
:
Address space identifier
Association bit
Reserved bits (0 write value, undefined
read value)
31
0
V
D
10 9 8 7
30 29 28
A
8 7
ASID
VPN
31
23
2 1 0
1 1 1 1 0 1 1 0
E
24
14 13
Figure 3.16 Memory-Mapped UTLB Address Array
Rev. 3.0, 04/02, page 85 of 1064
3.7.5
UTLB Data Array 1
UTLB data array 1 is allocated to addresses H'F700 0000 to H'F77F FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and PPN, V, SZ, PR, C, D, SH, and WT to be written to the data
array are specified in the data field.
In the address field, bits [31:23] have the value H'F70 indicating UTLB data array 1, and the entry
is selected by bits [13:8].
In the data field, PPN is indicated by bits [28:10], V by bit [8], SZ by bits [7] and [4], PR by bits
[6:5], C by bit [3], D by bit [2], SH by bit [1], and WT by bit [0].
The following two kinds of operation can be used on UTLB data array 1:
1. UTLB data array 1 read
PPN, V, SZ, PR, C, D, SH, and WT are read into the data field from the UTLB entry
corresponding to the entry set in the address field.
2. UTLB data array 1 write
PPN, V, SZ, PR, C, D, SH, and WT specified in the data field are written to the UTLB entry
corresponding to the entry set in the address field.
Address field
Data field
PPN:
V:
E:
SZ:
D:
Physical page number
Validity bit
Entry
Page size bits
Dirty bit
PR:
C:
SH:
WT:
:
Protection key data
Cacheability bit
Share status bit
Write-through bit
Reserved bits (0 write value, undefined
read value)
31
2 1 0
V
10 9 8 7
30 29 28
4 3
6 5
PR
C
PPN
31
23
0
1 1 1 1 0 1 1 1 0
E
24
8 7
14 13
D
SZ
SH WT
Figure 3.17 Memory-Mapped UTLB Data Array 1
Rev. 3.0, 04/02, page 86 of 1064
3.7.6
UTLB Data Array 2
UTLB data array 2 is allocated to addresses H'F780 0000 to H'F7FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and SA and TC to be written to data array 2 are specified in the data
field.
In the address field, bits [31:23] have the value H'F78 indicating UTLB data array 2, and the entry
is selected by bits [13:8].
In the data field, TC is indicated by bit [3], and SA by bits [2:0].
The following two kinds of operation can be used on UTLB data array 2:
1. UTLB data array 2 read
SA and TC are read into the data field from the UTLB entry corresponding to the entry set in
the address field.
2. UTLB data array 2 write
SA and TC specified in the data field are written to the UTLB entry corresponding to the entry
set in the address field.
Address field
31
23
0
1 1 1 1 0 1 1 1 1
E
Data field
31
4
0
TC
24
8
13
7
3 2
14
SA
TC:
E:
Timing control bit
Entry
SA:
:
Space attribute bits
Reserved bits (0 write value, undefined read
value)
Figure 3.18 Memory-Mapped UTLB Data Array 2
Rev. 3.0, 04/02, page 87 of 1064
Section 4 Caches
4.1
Overview
4.1.1
Features
The SH7751 Series has an on-chip 8-kbyte instruction cache (IC) for instructions and 16-kbyte
operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) can also be used
as on-chip RAM. The features of these caches are summarized in table 4.1.
The SH7751R incorporates a 16-kbyte instruction cache (IC) for instructions and a 32-kbyte
operand cache (OC) for data. Half of the operand cache memory (16 kbytes) can also be used as
on-chip RAM. When the EMODE bit in the CCR register is cleared to 0 in the SH7751R, both the
IC and OC are set to SH7751 compatible mode. Operation is as shown in table 4.1. When the
EMODE bit in the CCR register is set to 1, the cache characteristics are as shown in table 4.2.
After a power-on reset or manual reset, the initial value of the EMODE bit is 0.
The SH7751 Series supports two 32-byte store queues (SQs) for performing high-speed writes to
external memory. SQ features are shown in table 4.3.
Table 4.1
Cache Features (SH7751)
Item
Instruction Cache
Operand Cache
Capacity
8-kbyte cache
16-kbyte cache or 8-kbyte cache +
8-kbyte RAM
Type
Direct mapping
Direct mapping
Line size
32 bytes
32 bytes
Entries
256 entry
512 entry
Write method
Copy-back/write-through selectable
Rev. 3.0, 04/02, page 88 of 1064
Table 4.2
Cache Features (SH7751R)
Item
Instruction Cache
Operand Cache
Capacity
16-kbyte cache
32-kbyte cache or 16-kbyte cache +
16-kbyte RAM
Type
2-way set-associative
2-way set-associative
Line size
32 bytes
32 bytes
Entries
256 entry/way
512 entry/way
Write method
Copy-back/write-through selectable
Replace method
LRU (Least Recently Used)
algorithm
LRU (Least Recently Used)
algorithm
Table 4.3
Store Queue Features
Item
Store Queues
Capacity
2
32 bytes
Addresses
H'E000 0000 to H'E3FF FFFF
Write
Store instruction (1-cycle write)
Write-back
Prefetch instruction (PREF instruction)
Access right
MMU off: according to MMUCR.SQMD
MMU on: according to individual page PR
4.1.2
Register Configuration
Table 4.4 shows the cache control registers.
Table 4.4
Cache Control Registers
Name
Abbreviation R/W
Initial
Value*
1
P4
Address*
2
Area 7
Address*
2
Access
Size
Cache control
register
CCR
R/W
H'0000 0000
H'FF00 001C
H'1F00 001C
32
Queue address
control register 0
QACR0
R/W
Undefined
H'FF00 0038
H'1F00 0038
32
Queue address
control register 1
QACR1
R/W
Undefined
H'FF00 003C
H'1F00 003C
32
Notes: *1 The initial value is the value after a power-on or manual reset.
*2 P4 address is the address when using the virtual/physical address space P4 area. The
area 7 address is the address used when making an access from physical address
space area 7 using the TLB.
Rev. 3.0, 04/02, page 89 of 1064
4.2
Register Descriptions
There are three cache and store queue related control registers, as shown in figure 4.1.
CCR
31
14
16
30
15
12 11 10 9 8 7 6 5 4 3 2
CB
1 0
ICI ICE
ORA
OIX
OCI
AREA
indicates reserved bits: 0 must be specified in a write; the read value is 0.
Notes: * SH7751R only
WT OCE
IIX
EMODE*
QACR0
31
5 4
2 1 0
AREA
QACR1
31
5 4
2 1 0
Figure 4.1 Cache and Store Queue Control Registers (CCR)
(1) Cache Control Register (CCR): CCR contains the following bits:
EMODE: Cache-double-mode (SH7751R only. Reserved bit in SH7751.)
IIX:
IC index enable
ICI:
IC invalidation
ICE:
IC enable
OIX:
OC index enable
ORA:
OC RAM enable
OCI:
OC invalidation
CB:
Copy-back enable
WT:
Write-through enable
OCE:
OC enable
CCR can be accessed by longword-size access from H'FF00001C in the P4 area and H'1F00001C
in area 7. The CCR bits are used for the cache settings described below. Consequently, CCR
modifications must only be made by a program in the non-cached P2 area. After CCR is updated,
an instruction that performs data access to the P0, P1, P3, or U0 area should be located at least
four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or
U0 area should be located at least eight instructions after the CCR update instruction.
Rev. 3.0, 04/02, page 90 of 1064
EMODE: Cache-double-mode bit
Indicates whether or not cache-double-mode is used in the SH7751R. This bit is reserved in
the SH7751. The EMODE bit cannot be modified while the cache is in use.
0: SH7751-compatible-mode
*1
(Initial value)
1: Cache-double-mode
Note: *1 Address allocation in OC index mode and RAM mode is not compatible with that in
RAM mode.
IIX: IC index enable bit
0: Effective address bits [12:5] used for IC entry selection
1: Effective address bits [25] and [11:5] used for IC entry selection
ICI: IC invalidation bit
When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns
0 when read.
ICE: IC enable bit
Indicates whether or not the IC is to be used. When address translation is performed, the IC
cannot be used unless the C bit in the page management information is also 1.
0: IC not used
1: IC used
OIX: OC index enable bit
*2
0: Effective address bits [13:5] used for OC entry selection
1: Effective address bits [25] and [12:5] used for OC entry selection
Note: *2 In the SH7751R, clear the OIX bit to 0 when the ORA bit is 1.
ORA: OC RAM enable bit
*3
When the OC is enabled (OCE = 1), the ORA bit specifies whether the 8 kbytes from entry
128 to entry 255 and from entry 384 to entry 511 of the OC are to be used as RAM. When the
OC is not enabled (OCE = 0), the ORA bit should be cleared to 0.
0: 16 kbytes used as cache
1: 8 kbytes used as cache, and 8 kbytes as RAM
Note: *3 In the SH7751R, clear the ORA bit to 0 when the OIX bit is 1.
OCI: OC invalidation bit
When 1 is written to this bit, the V and U bits of all OC entries are cleared to 0. This bit always
returns 0 when read.
Rev. 3.0, 04/02, page 91 of 1064
CB: Copy-back bit
Indicates the P1 area cache write mode.
0: Write-through mode
1: Copy-back mode
WT: Write-through bit
Indicates the P0, U0, and P3 area cache write mode. When address translation is performed,
the value of the WT bit in the page management information has priority.
0: Copy-back mode
1: Write-through mode
OCE: OC enable bit
Indicates whether or not the OC is to be used. When address translation is performed, the OC
cannot be used unless the C bit in the page management information is also 1.
0: OC not used
1: OC used
(2) Queue Address Control Register 0 (QACR0): QACR0 can be accessed by longword-size
access from H'FF000038 in the P4 area and H'1F000038 in area 7. QACR0 specifies the area onto
which store queue 0 (SQ0) is mapped when the MMU is off.
(3) Queue Address Control Register 1 (QACR1): QACR1 can be accessed by longword-size
access from H'FF00003C in the P4 area and H'1F00003C in area 7. QACR1 specifies the area
onto which store queue 1 (SQ1) is mapped when the MMU is off.
4.3
Operand Cache (OC)
4.3.1
Configuration
The operand cache in the SH7751 adopts the direct-mapping method, and consists of 512 cache
lines. Each cache line is composed of a 19-bit tag, V bit, U bit, and 32-byte data. The operand
cache in the SH7751R adopts the 2-way set-associative method, and each way consists of 512
cache lines.
Figure 4.2 shows the configuration of the operand cache in the SH7751.
Figure 4.3 shows the configuration of the operand cache in the SH7751R.
Rev. 3.0, 04/02, page 92 of 1064
31
26 25
5 4 3 2 1
LW0
32 bits
LW1
32 bits
LW2
32 bits
LW3
32 bits
LW4
32 bits
LW5
32 bits
LW6
32 bits
LW7
32 bits
MMU
RAM area
determination
ORA
OIX
[13]
[12]
[11:5]
511
19 bits
1 bit 1 bit
Tag
U
V
Address array
Data array
Entry selection
Longword (LW) selection
Effective address
3
9
22
19
0
Write data
Read data
Hit signal
Compare
13 12 11 10 9
0
Figure 4.2 Configuration of Operand Cache (SH7751)
Rev. 3.0, 04/02, page 93 of 1064
31
26 25
5 4
2
LW0
32 bits
LW1
32 bits
LW2
32 bits
LW3
32 bits
LW4
32 bits
LW5
32 bits
LW6
32 bits
LW7
32 bits
1 bit
MMU
RAM area
determination
OIX
ORA
[13]
[12:5]
511
19 bits
1 bit 1 bit
Tag
U
V
Address array
(way 0, way 1)
Data array (way 0, way 1)
LRU
Entry
selection
Longword (LW)
selection
Effective address
3
9
22
19
0
Write data
Read data
Hit signal
Compare
way-0
Compare
way-1
13 12
10
0
Figure 4.3 Configuration of Operand Cache (SH7751R)
Tag
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Rev. 3.0, 04/02, page 94 of 1064
U bit (dirty bit)
The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 4.5,
Memory-Mapped Cache Configuration (SH7751) and 4.6, Memory-Mapped Cache
Configuration (SH7751R)). The U bit is initialized to 0 by a power-on reset, but retains its
value in a manual reset.
Data field
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
LRU (SH7751R only)
In a 2-way set-associative system, up to two entry addresses (among addresses 13 to 15) can
register the same data in cache. The LRU bit indicates to which way the entry is to be
registered among the two ways. There is one LRU bit in each entry, and it is controlled by
hardware. The LRU (Last Recently Used) algorithm that selects the most recently accessed
way is used for way selection. The LRU bit is initialized to 0 by a power-on reset, but is not
initialized by a manual reset. The LRU bit cannot be read from or written to by software.
4.3.2
Read Operation
When the OC is enabled (CCR.OCE = 1) and data is read by means of an effective address from a
cacheable area, the cache operates as follows:
1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
If the tag matches and the V bit is 1
(3a)
If the tag matches and the V bit is 0
(3b)
If the tag does not match and the V bit is 0
(3b)
If the tag does not match, the V bit is 1, and the U bit is 0
(3b)
If the tag does not match, the V bit is 1, and the U bit is 1
(3c)
3a. Cache hit
The data indexed by effective address bits [4:0] is read from the data field of the cache line
indexed by effective address bits [13:5] in accordance with the access size
(quadword/longword/word/byte).
Rev. 3.0, 04/02, page 95 of 1064
3b. Cache miss (no write-back)
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU. While the remaining one cache line of data is being
read, the CPU can execute the next processing. When reading of one line of data is completed,
the tag corresponding to the effective address is recorded in the cache, and 1 is written to the V
bit.
3c. Cache miss (with write-back)
The tag and data field of the cache line indexed by effective address bits [13:5] are saved in the
write-back buffer. Then data is read into the cache line from the external memory space
corresponding to the effective address. Data reading is performed, using the wraparound
method, in order from the longword data corresponding to the effective address, and when the
corresponding data arrives in the cache, the read data is returned to the CPU. While the
remaining one cache line of data is being read, the CPU can execute the next processing. When
reading of one line of data is completed, the tag corresponding to the effective address is
recorded in the cache, 1 is written to the V bit, and 0 to the U bit. The data in the write-back
buffer is then written back to external memory.
4.3.3
Write Operation
When the OC is enabled (CCR.OCE = 1) and data is written by means of an effective address to a
cacheable area, the cache operates as follows:
1. The tag, V bit, and U bit are read from the cache line indexed by effective address bits [13:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
Copy-back
Write-through
If the tag matches and the V bit is 1
(3a)
(3b)
If the tag matches and the V bit is 0
(3c)
(3d)
If the tag does not match and the V bit is 0
(3c)
(3d)
If the tag does not match, the V bit is 1, and the U bit is 0
(3c)
(3d)
If the tag does not match, the V bit is 1, and the U bit is 1
(3e)
(3d)
3a. Cache hit (copy-back)
A data write in accordance with the access size (quadword/longword/word/byte) is performed
for the data indexed by bits [4:0] of the effective address and the data field of the cache line
indexed by effective address bits [13:5]. Then 1 is set in the U bit.
Rev. 3.0, 04/02, page 96 of 1064
3b. Cache hit (write-through)
A data write in accordance with the access size (quadword/longword/word/byte) is performed
for the data field of the cache line indexed by effective address bits [13:5] and for the data
indexed by effective address bits [4:0]. A write is also performed to the corresponding external
memory using the specified access size.
3c. Cache miss (copy-back/no write-back)
A data write in accordance with the access size (quadword/longword/word/byte) is performed
for the data field indexed by effective address bits [13:5] and for the data indexed by effective
address bits [4:0]. Then, data is read into the cache line from the external memory space
corresponding to the effective address. Data reading is performed, using the wraparound
method, in order from the longword data corresponding to the effective address, and one cache
line of data is read excluding the written data. During this time, the CPU can execute the next
processing. When reading of one line of data is completed, the tag corresponding to the
effective address is recorded in the cache, and 1 is written to the V bit and U bit.
3d. Cache miss (write-through)
A write of the specified access size is performed to the external memory corresponding to the
effective address. In this case, a write to cache is not performed.
3e. Cache miss (copy-back/with write-back)
The tag and data field of the cache line indexed by effective address bits [13:5] are first saved
in the write-back buffer, and then a data write in accordance with the access size
(quadword/longword/word/byte) is performed for the data indexed by bits [4:0] of the effective
address of the data field of the cache line indexed by effective address bits [13:5]. Then, data is
read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and one cache line of data is read excluding the
written data. During this time, the CPU can execute the next processing. When reading of one
line of data is completed, the tag corresponding to the effective address is recorded in the
cache, and 1 is written to the V bit and U bit. The data in the write-back buffer is then written
back to external memory.
Rev. 3.0, 04/02, page 97 of 1064
4.3.4
Write-Back Buffer
In order to give priority to data reads to the cache and improve performance, the SH7751 Series
has a write-back buffer which holds the relevant cache entry when it becomes necessary to purge a
dirty cache entry into external memory as the result of a cache miss. The write-back buffer
contains one cache line of data and the physical address of the purge destination.
LW7
Physical address bits [28:5]
LW6
LW5
LW4
LW3
LW2
LW1
LW0
Figure 4.4 Configuration of Write-Back Buffer
4.3.5
Write-Through Buffer
The SH7751 Series has a 64-bit buffer for holding write data when writing data in write-through
mode or writing to a non-cacheable area. This allows the CPU to proceed to the next operation as
soon as the write to the write-through buffer is completed, without waiting for completion of the
write to external memory.
Physical address bits [28:0]
LW1
LW0
Figure 4.5 Configuration of Write-Through Buffer
4.3.6
RAM Mode
Setting CCR.ORA to 1 enables 8 kbytes of the operand cache to be used as RAM. The operand
cache entries used as RAM are the 8 kbytes of entries 128 to 255 and 384 to 511. In SH7751-
compatible-mode in the SH7751R, the 8 kbytes of operand cache entries 256 to 511 are used as
RAM. In cache-double-mode in the SH7751R, the total 16 kbytes of entries 256 to 511 in each
way of the operand cache are used as RAM. Other entries can still be used as cache. RAM can be
accessed using addresses H'7C00 0000 to H'7FFF FFFF. Byte-, word-, longword-, and quadword-
size data reads and writes can be performed in the operand cache RAM area. Instruction fetches
cannot be performed in this area.
Note that in the SH7751R, OC index mode cannot be used when RAM mode is used.
An example of RAM use is shown below. Here, the 4 kbytes comprising OC entries 128 to 256
are designated as RAM area 1, and the 4 kbytes comprising OC entries 384 to 511 as RAM area 2.
When OC index mode is off (CCR.OIX = 0)
H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1
H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1
Rev. 3.0, 04/02, page 98 of 1064
H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 2
H'7C00 3000 to H'7C00 3FFF (4 kB): Corresponds to RAM area 2
H'7C00 4000 to H'7C00 4FFF (4 kB): Corresponds to RAM area 1
:
:
:
RAM areas 1 and 2 then repeat every 8 kbytes up to H'7FFF FFFF.
Thus, to secure a continuous 8-kbyte RAM area, the area from H'7C00 1000 to H'7C00 2FFF
can be used, for example.
When OC index mode is on (CCR.OIX = 1)
H'7C00 0000 to H'7C00 0FFF (4 kB): Corresponds to RAM area 1
H'7C00 1000 to H'7C00 1FFF (4 kB): Corresponds to RAM area 1
H'7C00 2000 to H'7C00 2FFF (4 kB): Corresponds to RAM area 1
:
:
:
H'7DFF F000 to H'7DFF FFFF (4 kB): Corresponds to RAM area 1
H'7E00 0000 to H'7E00 0FFF (4 kB): Corresponds to RAM area 2
H'7E00 1000 to H'7E00 1FFF (4 kB): Corresponds to RAM area 2
:
:
:
H'7FFF F000 to H'7FFF FFFF (4 kB): Corresponds to RAM area 2
As the distinction between RAM areas 1 and 2 is indicated by address bit [25], the area from
H'7DFF F000 to H'7E00 0FFF should be used to secure a continuous 8-kbyte RAM area.
An example of RAM use in the SH7751R is shown below.
SH7751-compatible-mode (CCR.EMODE = 0)
H'7C00 0000 to H'7C00 1FFF (8 kB): Corresponds to RAM area (entries 256 to 511)
H'7C00 2000 to H'7C00 3FFF (8 kB): Corresponds to RAM area (entries 256 to 511)
:
:
:
A shadow of the RAM area occurs every 8 kbytes up to H'7FFF FFFF.
Cache-double-mode (CCR.EMODE = 1)
The 8 kbytes of entries 256 to 511 in OC way 0 are used as RAM area 1, and the 8 kbytes of
entries 256 to 511 in OC way 1 are used as RAM area 2.
H'7C00 0000 to H'7C00 1FFF (8 kB): Corresponds to RAM area 1
H'7C00 2000 to H'7C00 3FFF (8 kB): Corresponds to RAM area 2
H'7C00 4000 to H'7C00 5FFF (8 kB): Corresponds to RAM area 1
H'7C00 6000 to H'7C00 7FFF (8 kB): Corresponds to RAM area 2
:
:
:
A shadow of the RAM area occurs every 16 kbytes up to H'7FFF FFFF.
Rev. 3.0, 04/02, page 99 of 1064
4.3.7
OC Index Mode
Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective
address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing
is performed using bits [13:5] of the effective address. Using index mode allows the OC to be
handled as two areas by means of effective address bit [25], providing efficient use of the cache.
Note that in the SH7751R, RAM mode cannot be used when OC index mode is used.
4.3.8
Coherency between Cache and External Memory
Coherency between cache and external memory should be assured by software. In the SH7751
Series, the following four new instructions are supported for cache operations. Details of these
instructions are given in the Programming Manual.
Invalidate instruction:
OCBI @Rn
Cache invalidation (no write-back)
Purge instruction:
OCBP @Rn
Cache invalidation (with write-back)
Write-back instruction:
OCBWB @Rn
Cache write-back
Allocate instruction:
MOVCA.L R0,@Rn
Cache allocation
4.3.9
Prefetch Operation
The SH7751 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the
result of a cache miss. If it is known that a cache miss will result from a read or write operation, it
is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a
cache miss due to the read or write operation, and so improve software performance. If a prefetch
instruction is executed for data already held in the cache, or if the prefetch address results in a
UTLB miss or a protection violation, the result is no operation, and an exception is not generated.
Details of the prefetch instruction are given in the Programming Manual.
Prefetch instruction:
PREF @Rn
4.4
Instruction Cache (IC)
4.4.1
Configuration
The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32-
byte data (16 instructions). The instruction cache in the SH7751R adopts the 2-way set-associative
method, and each way consists of 256 cache lines.
Rev. 3.0, 04/02, page 100 of 1064
Figure 4.6 shows the configuration of the instruction cache in the SH7751.
Figure 4.7 shows the configuration of the instruction cache in the SH7751R.
LW0
32 bits
LW1
32 bits
LW2
32 bits
LW3
32 bits
LW4
32 bits
LW5
32 bits
LW6
32 bits
LW7
32 bits
255
19 bits
1 bit
Tag
V
Address array
Longword (LW) selection
Data array
0
Read data
Hit signal
Compare
31
26 25
5 4 3 2 1
MMU
IIX
[12]
[11:5]
Entry selection
Effective address
8
3
22
19
13 12 11 10 9
0
Figure 4.6 Configuration of Instruction Cache (SH7751)
Rev. 3.0, 04/02, page 101 of 1064
31
25
5 4
2
LW0
32 bits
LW1
32 bits
LW2
32 bits
LW3
32 bits
LW4
32 bits
LW5
32 bits
LW6
32 bits
LW7
32 bits
1 bit
MMU
IIX
[12]
[11:5]
255
19 bits
1 bit
Tag
V
Address array
(way 0, way 1)
Data array (way 0, way 1)
LRU
Entry
selection
Longword (LW)
selection
Effective address
3
8
22
19
0
Read data
Hit signal
Compare
way-0
Compare
way-1
13 12 11 10
0
Figure 4.7 Configuration of Instruction Cache (SH7751R)
Tag
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
Rev. 3.0, 04/02, page 102 of 1064
LRU (SH7751R only)
In a 2-way set-associative system, up to two entry addresses (among addresses 12 to 15) can
register the same data in cache. The LRU bit indicates to which way the entry is to be
registered among the two ways. There is one LRU bit in each entry, and it is controlled by
hardware. The LRU (Last Recently Used) algorithm that selects the most recently accessed
way is used for way selection. The LRU bit is initialized to 0 by a power-on reset, but is not
initialized by a manual reset. The LRU bit cannot be read from or written to by software.
4.4.2
Read Operation
When the IC is enabled (CCR.ICE = 1) and instruction fetches are performed by means of an
effective address from a cacheable area, the instruction cache operates as follows:
1. The tag and V bit are read from the cache line indexed by effective address bits [12:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
If the tag matches and the V bit is 1
(3a)
If the tag matches and the V bit is 0
(3b)
If the tag does not match and the V bit is 0
(3b)
If the tag does not match and the V bit is 1
(3b)
3a. Cache hit
The data indexed by effective address bits [4:2] is read as an instruction from the data field of
the cache line indexed by effective address bits [12:5].
3b. Cache miss
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU as an instruction. When reading of one line of data
is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is
written to the V bit.
4.4.3
IC Index Mode
Setting CCR.IIX to 1 enables IC indexing to be performed using bit [25] of the effective address.
This is called IC index mode. In normal mode, with CCR.IIX cleared to 0, IC indexing is
performed using bits [12:5] of the effective address. Using index mode allows the IC to be handled
as two areas by means of effective address bit [25], providing efficient use of the cache.
Rev. 3.0, 04/02, page 103 of 1064
4.5
Memory-Mapped Cache Configuration (SH7751)
To enable the IC and OC to be managed by software, the IC contents can be read and written by a
P2 area program with a MOV instruction in privileged mode. Operation is not guaranteed if access
is made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should
be made at least 8 instructions after this MOV instruction. The OC contents can be read and
written by a P1 or P2 area program with a MOV instruction in privileged mode. Operation is not
guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0,
or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are
allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC
address array and data array and the OC address array and data array, and the access size is always
longword. Instruction fetches cannot be performed in these areas. For reserved bits, a write value
of 0 should be specified, and read values are undefined.
4.5.1
IC Address Array
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The entry to be accessed is specified in the address field, and the
write tag and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry
is specified by bits [12:5]. CCR.IIX has no effect on this entry specification. The address array bit
[3] association bit (A bit) specifies whether or not association is performed when writing to the IC
address array. As only longword access is used, 0 should be specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address
array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which
association is not performed. Data field bits [31:29] are used for the virtual address specification
only in the case of a write in which association is performed.
The following three kinds of operation can be used on the IC address array:
1. IC address array read
The tag and V bit are read into the data field from the IC entry corresponding to the entry set in
the address field. In a read, associative operation is not performed regardless of whether the
association bit specified in the address field is 1 or 0.
2. IC address array write (non-associative)
The tag and V bit specified in the data field are written to the IC entry corresponding to the
entry set in the address field. The A bit in the address field should be cleared to 0.
3. IC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tag stored in the
entry specified in the address field is compared with the tag specified in the data field. If the
Rev. 3.0, 04/02, page 104 of 1064
MMU is enabled at this time, comparison is performed after the virtual address specified by
data field bits [31:10] has been translated to a physical address using the ITLB. If the addresses
match and the V bit is 1, the V bit specified in the data field is written into the IC entry. In
other cases, no operation is performed. This operation is used to invalidate a specific IC entry.
If an ITLB miss occurs during address translation, or the comparison shows a mismatch, an
interrupt is not generated, no operation is performed, and the write is not executed. If an
instruction TLB multiple hit exception occurs during address translation, processing switches
to the instruction TLB multiple hit exception handling routine.
Address field
31
23
12
5 4 3 2 1 0
1 1 1 1 0 0 0 0
Entry
A
Data field
31
10 9
1 0
V
Tag
V
A
24
13
: Validity bit
: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.8 Memory-Mapped IC Address Array
4.5.2
IC Data Array
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F1 indicating the IC data array, and the entry is
specified by bits [12:5]. CCR.IIX has no effect on this entry specification. Address field bits [4:2]
are used for the longword data specification in the entry. As only longword access is used, 0
should be specified for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the IC data array:
1. IC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the IC entry corresponding to the entry set in the address field.
Rev. 3.0, 04/02, page 105 of 1064
2. IC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the IC entry corresponding to the entry set in the
address field.
Address field
31
23
12
5 4
2 1 0
1 1 1 1 0 0 0 1
Entry
L
Data field
31
0
Longword data
L
24
13
: Longword specification bits
: Reserved bits (0 write value, undefined read value)
Figure 4.9 Memory-Mapped IC Data Array
4.5.3
OC Address Array
The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The entry to be accessed is specified in the address field, and the
write tag, U bit, and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F4 indicating the OC address array, and the
entry is specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry
specification. The address array bit [3] association bit (A bit) specifies whether or not association
is performed when writing to the OC address array. As only longword access is used, 0 should be
specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0].
As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a
write in which association is not performed. Data field bits [31:29] are used for the virtual address
specification only in the case of a write in which association is performed.
The following three kinds of operation can be used on the OC address array:
1. OC address array read
The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
2. OC address array write (non-associative)
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
Rev. 3.0, 04/02, page 106 of 1064
the entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
3. OC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tag stored in the
entry specified in the address field is compared with the tag specified in the data field. If the
MMU is enabled at this time, comparison is performed after the virtual address specified by
data field bits [31:10] has been translated to a physical address using the UTLB. If the
addresses match and the V bit is 1, the U bit and V bit specified in the data field are written
into the OC entry. This operation is used to invalidate a specific OC entry. In other cases, no
operation is performed. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit,
write-back is performed. If a UTLB miss occurs during address translation, or the comparison
shows a mismatch, an exception is not generated, no operation is performed, and the write is
not executed. If a data TLB multiple hit exception occurs during address translation,
processing switches to the data TLB multiple hit exception handling routine.
Address field
31
23
5 4 3 2 1 0
1 1 1 1 0 1 0 0
Entry
A
Data field
31
10 9
1 0
V
Tag
24
13
14
2
U
V
U
A
: Validity bit
: Dirty bit
: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.10 Memory-Mapped OC Address Array
4.5.4
OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The entry to be accessed is specified in the address field, and the longword
data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, and the entry is
specified by bits [13:5]. CCR.OIX and CCR.ORA have no effect on this entry specification.
Address field bits [4:2] are used for the longword data specification in the entry. As only longword
access is used, 0 should be specified for address field bits [1:0].
The data field is used for the longword data specification.
Rev. 3.0, 04/02, page 107 of 1064
The following two kinds of operation can be used on the OC data array:
1. OC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the entry set in the address field.
2. OC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding the entry set in the address
field. This write does not set the U bit to 1 on the address array side.
Address field
31
23
5 4
2 1 0
1 1 1 1 0 1 0 1
Entry
L
Data field
31
0
Longword data
24
13
14
L : Longword specification bits
: Reserved bits (0 write value, undefined read value)
Figure 4.11 Memory-Mapped OC Data Array
4.6
Memory-Mapped Cache Configuration (SH7751R)
To enable the IC and OC to be managed by software, IC contents can be read and written by a P2
area program with a MOV instruction in privileged mode. Operation is not guaranteed if access is
made from a program in another area. In this case, a branch to the P0, U0, P1, or P3 area should be
made at least 8 instructions after this MOV instruction. The OC contents can be read and written
by a P1 or P2 area program with a MOV instruction in privileged mode. Operation is not
guaranteed if access is made from a program in another area. In this case, a branch to the P0, U0,
or P3 area should be made at least 8 instructions after this MOV instruction. The IC and OC are
allocated to the P4 area in physical memory space. Only data accesses can be used on both the IC
address array and data array and the OC address array and data array, and the access size is always
longword. Instruction fetches cannot be performed in these areas. For reserved bits, a write value
of 0 should be specified, and read values are undefined. Note that the memory-mapped cache
configuration in SH7751-compatible-mode of the SH7751R is the same as that in the SH7751.
Rev. 3.0, 04/02, page 108 of 1064
4.6.1
IC Address Array
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed are specified in the address field,
and the write tag and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is
specified by bit [13], and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry
specification. Address field bit [3], that is the association bit (A bit), specifies whether or not
association is performed when writing to the IC address array. As only longword access is used, 0
should be specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address
array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which
association is not performed. Data field bits [31:29] are used for the virtual address specification
only in the case of a write in which association is performed.
The following three kinds of operation can be used on the IC address array:
1. IC address array read
The tag and V bit are read into the data field from the IC entry corresponding to the way and
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
2. IC address array write (non-associative)
The tag and V bit specified in the data field are written to the IC entry corresponding to the
way and entry set in the address field. The A bit in the address field should be cleared to 0.
3. IC address array write (associative)
When a write is performed with the A bit in the address field set to 1, each way's tag stored in
the entry specified in the address field is compared with the tag specified in the data field. The
way number set in bit [13] is ignored. If the MMU is enabled at this time, comparison is
performed after the virtual address specified by data field bits [31:10] has been translated to a
physical address using the ITLB. If the addresses match and the V bit in that way is 1, the V
bit specified in the data field is written into the IC entry. In other cases, no operation is
performed. This operation is used to invalidate a specific IC entry. If an ITLB miss occurs
during address translation, or the comparison shows a mismatch, an interrupt is not generated,
no operation is performed, and the write is not executed. If an instruction TLB multiple hit
exception occurs during address translation, processing switches to the instruction TLB
multiple hit exception handling routine.
Rev. 3.0, 04/02, page 109 of 1064
Address field
31
23
12
5 4 3 2 1 0
1 1 1 1 0 0 0 0
Entry
A
Data field
31
10 9
1 0
V
Tag
Way
V
A
24
13
: Validity bit
: Association bit
: Reserved bits (0 write value, undefined read value)
Figure 4.12 Memory-Mapped IC Address Array
4.6.2
IC Data Array
The IC data array is allocated to addresses H'F100 0000 to H'F1FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The way and entry to be accessed are specified in the address field, and
the longword data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F1 indicating the IC data array, the way is
specified by bit [13], and the entry is specified by bits [12:5]. CCR.IIX has no effect on this entry
specification. Address field bits [4:2] are used for the longword data specification in the entry. As
only longword access is used, 0 should be specified for address field bits [1:0].
The data field is used for the longword data specification.
The following two kinds of operation can be used on the IC data array:
1. IC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the IC entry corresponding to the way and entry set in the address
field.
2. IC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the IC entry corresponding to the way and entry set in
the address field.
Rev. 3.0, 04/02, page 110 of 1064
Address field
31
23
12
5 4
2 1 0
1 1 1 1 0 0 0 1
Entry
L
Data field
31
0
Longword data
L
24
13
: Longword specification bits
: Reserved bits (0 write value, undefined read value)
Way
Figure 4.13 Memory-Mapped IC Data Array
4.6.3
OC Address Array
The OC address array is allocated to addresses H'F400 0000 to H'F4FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed are specified in the address field,
and the write tag, U bit, and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F4 indicating the OC address array, the way is
specified by bit [14], and the entry is specified by bits [13:5]. CCR.OIX has no effect on this entry
specification. The OC address array access in RAM mode (CCR.ORA = 1) is performed only to
cache, and bit [13] specifies the way. For details on address allocation, see section 4.6.5, Summary
of Memory-Mapped OC Addresses. Address field bit [3], that is the association bit (A bit),
specifies whether or not association is performed when writing to the OC address array. As only
longword access is used, 0 should be specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], the U bit by bit [1], and the V bit by bit [0].
As the OC address array tag is 19 bits in length, data field bits [31:29] are not used in the case of a
write in which association is not performed. Data field bits [31:29] are used for the virtual address
specification only in the case of a write in which association is performed.
The following three kinds of operation can be used on the OC address array:
1. OC address array read
The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the
way and entry set in the address field. In a read, associative operation is not performed
regardless of whether the association bit specified in the address field is 1 or 0.
2. OC address array write (non-associative)
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
the way and entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
Rev. 3.0, 04/02, page 111 of 1064
3. OC address array write (associative)
When a write is performed with the A bit in the address field set to 1, each way's tag stored in
the entry specified in the address field is compared with the tag specified in the data field. The
way number set in bit [14] is ignored. If the MMU is enabled at this time, comparison is
performed after the virtual address specified by data field bits [31:10] has been translated to a
physical address using the UTLB. If the addresses match and the V bit in that way is 1, the U
bit and V bit specified in the data field are written into the OC entry. This operation is used to
invalidate a specific OC entry. In other cases, no operation is performed. If the OC entry U bit
is 1, and 0 is written to the V bit or to the U bit, write-back is performed. If a UTLB miss
occurs during address translation, or the comparison shows a mismatch, an exception is not
generated, no operation is performed, and the write is not executed. If a data TLB multiple hit
exception occurs during address translation, processing switches to the data TLB multiple hit
exception handling routine.
Address field
31
23
5 4 3 2 1 0
1 1 1 1 0 1 0 0
Entry
A
Data field
31
10 9
1 0
V
Tag
24
13
14
15
2
U
V
U
A
: Validity bit
: Dirty bit
: Association bit
: Reserved bits (0 write value, undefined read value)
Way
Figure 4.14 Memory-Mapped OC Address Array
4.6.4
OC Data Array
The OC data array is allocated to addresses H'F500 0000 to H'F5FF FFFF in the P4 area. A data
array access requires a 32-bit address field specification (when reading or writing) and a 32-bit
data field specification. The way and entry to be accessed are specified in the address field, and
the longword data to be written is specified in the data field.
In the address field, bits [31:24] have the value H'F5 indicating the OC data array, the way is
specified by bit [14], and the entry is specified by bits [13:5]. CCR.OIX has no effect on this entry
specification. The OC address array access in RAM mode (CCR.ORA = 1) is performed only to
cache, and bit [13] specifies the way. For details on address allocation, see section 4.6.5, Summary
of Memory-Mapped OC Addresses. Address field bits [4:2] are used for the longword data
specification in the entry. As only longword access is used, 0 should be specified for address field
bits [1:0].
The data field is used for the longword data specification.
Rev. 3.0, 04/02, page 112 of 1064
The following two kinds of operation can be used on the OC data array:
1. OC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the way and entry set in the address
field.
2. OC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding to the way and entry set in
the address field. This write does not set the U bit to 1 on the address array side.
Address field
31
23
5 4
2 1 0
1 1 1 1 0 1 0 1
Entry
L
Data field
31
0
Longword data
24
13
14
L : Longword specification bits
: Reserved bits (0 write value, undefined read value)
15
Way
Figure 4.15 Memory-Mapped OC Data Array
4.6.5
Summary of Memory-Mapped OC Addresses
The memory-mapped OC addresses in cache-double-mode in the SH7751R are summarized below
using data area access as an example.
Normal mode (CCR.ORA = 0)
H'F500 0000 to H'F500 3FFF (16 kB): Way 0 (entries 0 to 511)
H'F500 4000 to H'F500 7FFF (16 kB): Way 1 (entries 0 to 511)
:
:
:
A shadow of the cache area occurs every 32 kbytes up to H'F5FF FFFF.
RAM mode (CCR.ORA = 1)
H'F500 0000 to H'F500 1FFF (8 kB): Way 0 (entries 0 to 255)
H'F500 2000 to H'F500 3FFF (8 kB): Way 1 (entries 0 to 255)
:
:
:
A shadow of the cache area occurs every 16 kbytes up to H'F5FF FFFF.
Rev. 3.0, 04/02, page 113 of 1064
4.7
Store Queues
Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory.
When not using the SQs, the low power dissipation power-down modes, in which SQ functions
are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be
accessed while SQ functions are stopped. See section 9, Power-Down Modes, for the procedure
for stopping SQ functions.
4.7.1
SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store
queues can be set independently.
SQ0
SQ0[0]
SQ0[1]
SQ0[2]
SQ0[3]
SQ0[4]
SQ0[5]
SQ0[6]
SQ0[7]
SQ1
SQ1[0]
SQ1[1]
SQ1[2]
SQ1[3]
SQ1[4]
SQ1[5]
SQ1[6]
SQ1[7]
4B
4B
4B
4B
4B
4B
4B
4B
Figure 4.16 Store Queue Configuration
4.7.2
SQ Writes
A write to the SQs can be performed using a store instruction on P4 area H'E000 0000 to H'E3FF
FFFC. A longword or quadword access size can be used. The meaning of the address bits is as
follows:
[31:26]:
111000
Store queue specification
[25:6]:
Don't care
Used for external memory transfer/access right
[5]:
0/1
0: SQ0 specification 1: SQ1 specification
[4:2]:
LW specification
Specifies longword position in SQ0/SQ1
[1:0]
00
Fixed at 0
4.7.3
Transfer to External Memory
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).
Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from
the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is
always at a 32-byte boundary. While the contents of one SQ are being transferred to external
memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in
the transfer to external memory is deferred until the transfer is completed.
Rev. 3.0, 04/02, page 114 of 1064
The SQ transfer destination external address bit [28:0] specification is as shown below, according
to whether the MMU is on or off.
When MMU is on
The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer
destination external address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same
meaning as for normal address translation, but the C and WT bits have no meaning with regard
to this page. Since burst transfer is prohibited for PCMCIA areas, the SA and TC bits also have
no meaning.
When a prefetch instruction is issued for the SQ area, address translation is performed and
external address bits [28:10] are generated in accordance with the SZ bit specification. For
external address bits [9:5], the address prior to address translation is generated in the same way
as when the MMU is off. External address bits [4:0] are fixed at 0. Transfer from the SQs to
external is performed to this address.
When MMU is off
The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a PREF
instruction is issued. The meaning of address bits [31:0] is as follows:
[31:26]:
111000
Store queue specification
[25:6]:
Address
External address bits [25:6]
[5]:
0/1
0: SQ0 specification
1: SQ1 specification and external address bit [5]
[4:2]:
Don't care
No meaning in a prefetch
[1:0]
00
Fixed at 0
External address bits [28:26], which cannot be generated from the above address, are generated
from the QACR0/1 registers.
QACR0 [4:2]:
External address bits [28:26] corresponding to SQ0
QACR1 [4:2]:
External address bits [28:26] corresponding to SQ1
External address bits [4:0] are always fixed at 0 since burst transfer starts at a 32-byte
boundary.
In the SH7751 Series, data transfer to a PCMCIA interface area is always performed using the
SA and TC bits in the PTEA register.
Rev. 3.0, 04/02, page 115 of 1064
4.7.4
Determination of SQ Access Exception
Determination of an exception in a write to an SQ or transfer to external memory (PREF
instruction) is performed as follows. If an exception occurs in an SQ write, the SQ contents may
be corrupted in the SH7751 (see section 4.7.6, SQ Usage Notes), but the previous values of the SQ
contents are guaranteed in the SH7751R. If an exception occurs in transfer from an SQ to external
memory, the transfer to external memory will be aborted.
When MMU is on
Operation is in accordance with the address translation information recorded in the UTLB, and
MMUCR.SQMD. Write type exception judgment is performed for writes to the SQs, and read
type for transfer from the SQs to external memory (PREF instruction), and a TLB miss
exception, protection violation exception, or initial page write exception is generated.
However, if SQ access is enabled, in privileged mode only, by MMUCR.SQMD, an address
error will be flagged in user mode even if address translation is successful.
When MMU is off
Operation is in accordance with MMUCR.SQMD.
0: Privileged/user access possible
1: Privileged access possible
If the SQ area is accessed in user mode when MMUCR.SQMD is set to 1, an address error will
be flagged.
4.7.5
SQ Read (SH7751R only)
In the SH7751R, the SQ contents can be read by a load instruction for addresses H'FF001000 to
H'FF00103C in the P4 area in privileged mode. The access size is always longword.
[31:6]: H'FF001000 (store queue specification)
[5]:
0/1 (0: SQ0 specification, 1: SQ1 specification)
[4:2]:
LW specification (specification of longword position in SQ0 or SQ1)
[1:0]:
00 (fixed to 0)
Rev. 3.0, 04/02, page 116 of 1064
4.7.6
SQ Usage Notes
If an exception occurs within the three instructions preceding an instruction that writes to an SQ in
the SH7751, a branch may be made to the exception handling routine after execution of the SQ
write that should be suppressed when an exception occurs.
This may be due to the bug described in (1) or (2) below.
(1) When SQ data is transferred to external memory within a normal program
If a PREF instruction for transfer from an SQ to external memory is included in the three
instructions preceding an SQ store instruction, the SQ is updated because the SQ write that
should be suppressed when a branch is made to the exception handling routine is executed, and
after returning from the exception handling routine the execution order of the PREF instruction
and SQ store instruction is reversed, so that erroneous data may be transferred to external
memory.
(2) When SQ data is transferred to external memory in an exception handling routine
If store queue contents are transferred to external memory within an exception handling
routine, erroneous data may be transferred to external memory.
Example 1: When an SQ store instruction is executed after a PREF instruction for transfer from that same SQ
to external memory
PREF instruction
; PREF instruction for transfer from SQ to external memory
; Address of this instruction is saved to SPC when exception occurs.
; Instruction 1, instruction 2, or instruction 3 may be executed on return from exception handling routine.
Instruction 1 ; May be executed if an SQ store instruction.
Instruction 2 ; May be executed if an SQ store instruction.
Instruction 3 ; May be executed if an SQ store instruction.
Instruction 4 ; Not executed even if an SQ store instruction.
Example 2: When an instruction at which an exception occurs is a branch instruction and a branch is made
Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Instruction 2
; May be executed if an instruction 1 delay slot instruction and an SQ store instruction.
Instruction 3
Instruction 4
Instruction 5
Instruction 6
Instruction 7 (instruction 1 branch destination)
; May be executed if an SQ store instruction.
Instruction 8
; May be executed if an SQ store instruction.
Rev. 3.0, 04/02, page 117 of 1064
Example 3: When an instruction at which an exception occurs is a branch instruction but a branch is not made
Instruction 1 (branch instruction) ; Address of this instruction is saved to SPC when exception occurs.
Instruction 2
; May be executed if an SQ store instruction.
Instruction 3
; May be executed if an SQ store instruction.
Instruction 4
; May be executed if an SQ store instruction.
Instruction 5
Both A and B below must be satisfied in order to prevent this bug.
A: When a store queue store instruction is executed after a PREF instruction for transfer from that
same store queue (SQ0, SQ1) to external memory, (1) and (2) below must be satisfied.
(1) Insert three NOP instructions*
1
between the two instructions.
(2) Do not place a PREF instruction for transfer from a store queue to external memory in the
delay slot of a branch instruction.
B: Do not execute a PREF instruction for transfer from a store queue to external memory within
an exception handling routine.
If the above is executed and there is a store queue store instruction among the four
instructions*
2
including the instruction at the address indicated by the SPC, the state of the
contents transferred to external memory by the PREF instruction may be that when execution
of this store instruction is completed.
Notes: *1 If there are other instructions between the two instructions, this bug can be prevented if
the total number of other instructions plus NOP instructions is at least three.
*2 If the instruction at the address indicated by the SPC is a branch instruction, this also
applies to two instructions at the branch destination.
Rev. 3.0, 04/02, page 118 of 1064
Rev. 3.0, 04/02, page 119 of 1064
Section 5 Exceptions
5.1
Overview
5.1.1
Features
Exception handling is processing handled by a special routine, separate from normal program
processing, that is executed by the CPU in case of abnormal events. For example, if the executing
instruction ends abnormally, appropriate action must be taken in order to return to the original
program sequence, or report the abnormality before terminating the processing. The process of
generating an exception handling request in response to abnormal termination, and passing control
flow to an exception handling routine, etc., is given the generic name of exception handling.
SH7751 Series exception handling is of three kinds: for resets, general exceptions, and interrupts.
5.1.2
Register Configuration
The registers used in exception handling are shown in table 5.1.
Table 5.1
Exception-Related Registers
Name
Abbrevia-
tion
R/W
Initial Value
P4
Address*
2
Area 7
Address*
2
Access
Size
TRAPA exception
register
TRA
R/W
Undefined
H'FF00 0020 H'1F00 0020
32
Exception event
register
EXPEVT
R/W
H'0000 0000/
H'0000 0020*
1
H'FF00 0024 H'1F00 0024
32
Interrupt event
register
INTEVT
R/W
Undefined
H'FF00 0028 H'1F00 0028
32
Notes: *1 H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset.
*2 P4 address is the address when using the virtual/physical address space P4 area.
When making an access from area 7 in the physical address space using the TLB, the
three high most bits of the address are ignored.
Rev. 3.0, 04/02, page 120 of 1064
5.2
Register Descriptions
There are three registers related to exception handling. Addresses are allocated for these, and can
be accessed by specifying the P4 address or area 7 address.
1. The exception event register (EXPEVT) resides at P4 address H'FF00 0024, and contains a 12-
bit exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception is accepted.
EXPEVT can also be modified by software.
2. The interrupt event register (INTEVT) resides at P4 address H'FF00 0028, and contains a 14-
bit exception code. The exception code set in INTEVT is that for an interrupt request. The
exception code is set automatically by hardware when an exception is accepted. INTEVT can
also be modified by software.
3. The TRAPA exception register (TRA) resides at P4 address H'FF00 0020, and contains 8-bit
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
The bit configurations of EXPEVT, INTEVT, and TRA are shown in figure 5.1.
31
0
0
0
0
0
0 0
0
31
10 9
1 0
0:
imm:
Reserved bits. These bits are always read as 0, and should only be written
with 0.
8-bit immediate data of the TRAPA instruction
12 11
2
EXPEVT
TRA
imm
0
14 13
0
31
INTEVT
Exception code
Exception code
Figure 5.1 Register Bit Configurations
Rev. 3.0, 04/02, page 121 of 1064
5.3
Exception Handling Functions
5.3.1
Exception Handling Flow
In exception handling, the contents of the program counter (PC), status register (SR) and R15 are
saved in the saved program counter (SPC), saved status register (SSR), and saved general register
15 (SGR), and the CPU starts execution of the appropriate exception handling routine according to
the vector address. An exception handling routine is a program written by the user to handle a
specific exception. The exception handling routine is terminated and control returned to the
original program by executing a return-from-exception instruction (RTE). This instruction restores
the PC and SR contents and returns control to the normal processing routine at the point at which
the exception occurred. The SGR contents are not written back to R15 by an RTE instruction.
The basic processing flow is as follows. See section 2, Data Formats and Registers, for the
meaning of the individual SR bits.
1. The PC, SR, and R15 contents are saved in SPC, SSR, and SGR.
2. The block bit (BL) in SR is set to 1.
3. The mode bit (MD) in SR is set to 1.
4. The register bank bit (RB) in SR is set to 1.
5. In a reset, the FPU disable bit (FD) in SR is cleared to 0.
6. The exception code is written to bits 110 of the exception event register (EXPEVT) or to bits
130 of the interrupt event register (INTEVT).
7. The CPU branches to the determined exception handling vector address, and the exception
handling routine begins.
5.3.2
Exception Handling Vector Addresses
The reset vector address is fixed at H'A000 0000. Exception and interrupt vector addresses are
determined by adding the offset for the specific event to the vector base address, which is set by
software in the vector base register (VBR). In the case of the TLB miss exception, for example,
the offset is H'0000 0400, so if H'9C08 0000 is set in VBR, the exception handling vector address
will be H'9C08 0400. If a further exception occurs at the exception handling vector address, a
duplicate exception will result, and recovery will be difficult; therefore, fixed physical addresses
(P1, P2) should be specified for vector addresses.
Rev. 3.0, 04/02, page 122 of 1064
5.4
Exception Types and Priorities
Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.2
Exceptions
Exception
Category
Execution
Mode
Exception
Priority
Level
Priority
Order
Vector
Address
Offset
Exception
Code
Power-on reset
1
1
H'A000 0000 --
H'000
Manual reset
1
2
H'A000 0000 --
H'020
H-UDI reset
1
1
H'A000 0000 --
H'000
Instruction TLB multiple-hit
exception
1
3
H'A000 0000 --
H'140
Reset
Abort type
Data TLB multiple-hit exception 1
4
H'A000 0000 --
H'140
User break before instruction
execution*
1
2
0
(VBR/DBR)
H'100/-- H'1E0
Instruction address error
2
1
(VBR)
H'100
H'0E0
Instruction TLB miss exception
2
2
(VBR)
H'400
H'040
Instruction TLB protection
violation exception
2
3
(VBR)
H'100
H'0A0
General illegal instruction
exception
2
4
(VBR)
H'100
H'180
Slot illegal instruction exception 2
4
(VBR)
H'100
H'1A0
General FPU disable exception
2
4
(VBR)
H'100
H'800
Slot FPU disable exception
2
4
(VBR)
H'100
H'820
Data address error (read)
2
5
(VBR)
H'100
H'0E0
Data address error (write)
2
5
(VBR)
H'100
H'100
Data TLB miss exception (read) 2
6
(VBR)
H'400
H'040
Data TLB miss exception (write) 2
6
(VBR)
H'400
H'060
Data TLB protection
violation exception (read)
2
7
(VBR)
H'100
H'0A0
Data TLB protection
violation exception (write)
2
7
(VBR)
H'100
H'0C0
FPU exception
2
8
(VBR)
H'100
H'120
Re-
execution
type
Initial page write exception
2
9
(VBR)
H'100
H'080
Unconditional trap (TRAPA)
2
4
(VBR)
H'100
H'160
General
exception
Completion
type
User break after instruction
execution*
1
2
10
(VBR/DBR)
H'100/-- H'1E0
Rev. 3.0, 04/02, page 123 of 1064
Table 5.2
Exceptions (cont)
Exception
Category
Execution
Mode
Exception
Priority
Level
Priority
Order
Vector
Address
Offset
Exception
Code
Nonmaskable interrupt
3
--
(VBR)
H'600
H'1C0
0
H'200
1
H'220
2
H'240
3
H'260
4
H'280
5
H'2A0
6
H'2C0
7
H'2E0
8
H'300
9
H'320
A
H'340
B
H'360
C
H'380
D
H'3A0
External
interrupts
IRL3IRL0
E
4
*2
(VBR)
H'600
H'3C0
TMU0
TUNI0
H'400
TMU1
TUNI1
H'420
TUNI2
H'440
TMU2
TICPI2
H'460
TMU3
TUNI3
H'B00
TMU4
TUNI4
H'B80
ATI
H'480
PRI
H'4A0
RTC
CUI
H'4C0
SCI
ERI
H'4E0
RXI
H'500
TXI
H'520
TEI
H'540
WDT
ITI
H'560
RCMI
H'580
Interrupt
Completion
type
Peripheral
module
interrupt
(module/
source)
REF
ROVI
4
*2
(VBR)
H'600
H'5A0
Rev. 3.0, 04/02, page 124 of 1064
Table 5.2
Exceptions (cont)
Exception
Category
Execution
Mode
Exception
Priority
Level
Priority
Order
Vector
Address
Offset
Exception
Code
H-UDI
H-UDI
H'600
GPIO
GPIOI
H'620
DMTE0
H'640
DMTE1
H'660
DMTE2
H'680
DMTE3
H'6A0
DMTE4*
3
H'780
DMTE5*
3
H'7A0
DMTE6*
3
H'7C0
DMTE7*
3
H'7E0
DMAC
DMAE
H'6C0
ERI
H'700
RXI
H'720
BRI
H'740
SCIF
TXI
H'760
PCIC(0) PCISERR
H'A00
PCIERR
H'AE0
PCIPWDWN
H'AC0
PCIPWON
H'AA0
PCIDMA0
H'A80
PCIDMA1
H'A60
PCIDMA2
H'A40
Interrupt
Completion
type
Peripheral
module
interrupt
(module/
source)
PCIC(1)
PCIDMA3
4
*2
(VBR)
H'600
H'A20
Priority: Priority is first assigned by priority level, then by priority order within each level (the lowest
number represents the highest priority).
Exception transition destination: Control passes to H'A000 0000 in a reset, and to [VBR + offset] in
other cases.
Exception code: Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
IRL: Interrupt request level (pins IRL3IRL0).
Module/source: See the sections on the relevant peripheral modules.
Notes: *1 When BRCR.UBDE = 1, PC = DBR. In other cases, PC = VBR + H'100.
*2 The priority order of external interrupts and peripheral module interrupts can be set by
software.
*3 SH7751R only
Rev. 3.0, 04/02, page 125 of 1064
5.5
Exception Flow
5.5.1
Exception Flow
Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and
exception handling. For the sake of clarity, the following description assumes that instructions are
executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different
kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an
exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers
may be set automatically by hardware, depending on the exception. For details, see section 5.6,
Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for
exception handling during execution of a delayed branch instruction and a delay slot instruction,
and in the case of instructions in which two data accesses are performed.
Execute next instruction
Is highest-
priority exception
re-exception
type?
Cancel instruction execution
result
Yes
Yes
Yes
No
No
No
No
Yes
SSR
SR
SPC
PC
SGR
R15
EXPEVT/INTEVT
exception code
SR.{MD,RB,BL}
111
PC
(BRCR.UBDE=1 && User_Break?
DBR: (VBR + Offset))
EXPEVT
exception code
SR. {MD, RB, BL, FD, IMASK}
11101111
PC
H'A000 0000
Interrupt
requested?
General
exception requested?
Reset
requested?
Figure 5.2 Instruction Execution and Exception Handling
Rev. 3.0, 04/02, page 126 of 1064
5.5.2
Exception Source Acceptance
A priority ranking is provided for all exceptions for use in determining which of two or more
simultaneously generated exceptions should be accepted. Five of the general exceptions--the
general illegal instruction exception, slot illegal instruction exception, general FPU disable
exception, slot FPU disable exception, and unconditional trap exception--are detected in the
process of instruction decoding, and do not occur simultaneously in the instruction pipeline. These
exceptions therefore all have the same priority. General exceptions are detected in the order of
instruction execution. However, exception handling is performed in the order of instruction flow
(program order). Thus, an exception for an earlier instruction is accepted before that for a later
instruction. An example of the order of acceptance for general exceptions is shown in figure 5.3.
Rev. 3.0, 04/02, page 127 of 1064
IF
IF
ID
ID
EX
EX
MA
MA
WB
WB
TLB miss (data access)
Pipeline flow:
Order of detection:
Instruction n
Instruction n+1
General illegal instruction exception (instruction n+1) and
TLB miss (instruction n+2) are detected simultaneously
Order of exception handling:
TLB miss (instruction n)
Program order
1
Instruction n+2
General illegal instruction exception
IF
ID
EX
MA
WB
IF
ID
EX
MA
WB
TLB miss (instruction access)
2
3
4
IF: Instruction
fetch
ID: Instruction
decode
EX: Instruction execution
MA: Memory access
WB: Write-back
Instruction n+3
TLB miss (instruction n)
Re-execution of instruction n
General illegal instruction exception
(instruction n+1)
Re-execution of instruction n+1
TLB miss (instruction n+2)
Re-execution of instruction n+2
Execution of instruction n+3
Figure 5.3 Example of General Exception Acceptance Order
Rev. 3.0, 04/02, page 128 of 1064
5.5.3
Exception Requests and BL Bit
When the BL bit in SR is 0, exceptions and interrupts are accepted.
When the BL bit in SR is 1 and an exception other than a user break is generated, the CPU's
internal registers and the registers of the other modules are set to their post-reset state, and the
CPU branches to the same address as in a reset (H'A000 0000). For the operation in the event of a
user break, see section 20, User Break Controller. If an ordinary interrupt occurs, the interrupt
request is held pending and is accepted after the BL bit has been cleared to 0 by software. If a
nonmaskable interrupt (NMI) occurs, it can be held pending or accepted according to the setting
made by software.
Thus, normally, SPC and SSR are saved and then the BL bit in SR is cleared to 0, to enable
multiple exception state acceptance.
5.5.4
Return from Exception Handling
The RTE instruction is used to return from exception handling. When the RTE instruction is
executed, the SPC contents are restored to PC and the SSR contents to SR, and the CPU returns
from the exception handling routine by branching to the SPC address. If SPC and SSR were saved
to external memory, set the BL bit in SR to 1 before restoring the SPC and SSR contents and
issuing the RTE instruction.
5.6
Description of Exceptions
The various exception handling operations are described here, covering exception sources,
transition addresses, and processor operation when a transition is made.
Rev. 3.0, 04/02, page 129 of 1064
5.6.1
Resets
(1) Power-On Reset
Sources:
5(6(7 pin low level
When the watchdog timer overflows while the WT/
,7 bit is set to 1 and the RSTS bit is
cleared to 0 in WTCSR. For details, see section 10, Clock Oscillation Circuits.
Transition address: H'A000 0000
Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3I0) are
set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections. For some CPU functions, the
7567 pin and 5(6(7 pin
must be driven low. It is therefore essential to execute a power-on reset and drive the
7567
pin low when powering on.
If the
5(6(7 pin is driven high before the 05(6(7 pin while both these pins are low, a
manual reset may occur after the power-on reset operation. The
5(6(7 pin must be driven
high at the same time as, or after, the
05(6(7 pin.
Power_on_reset()
{
EXPEVT = H'00000000;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD=0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A0000000;
}
Rev. 3.0, 04/02, page 130 of 1064
(2) Manual Reset
Sources:
05(6(7 pin low level and 5(6(7 pin high level
When a general exception other than a user break occurs while the BL bit is set to 1 in SR
When the watchdog timer overflows while the RSTS bit is set to 1 in WTCSR. For details,
see section 10, Clock Oscillation Circuits.
Transition address: H'A000 0000
Transition operations:
Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3I0) are
set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections.
Manual_reset()
{
EXPEVT = H'00000020;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A0000000;
}
Table 5.3
Types of Reset
Reset State Transition
Conditions
Internal States
Type
#$%
#$%
#$%
#$%
CPU
On-Chip Peripheral
Modules
Power-on reset
--
Low
Initialized
Manual reset
Low
High
Initialized
See Register
Configuration in
each section
Rev. 3.0, 04/02, page 131 of 1064
(3) H-UDI Reset
Source: SDIR.TI3TI0 = B'0110 (negation) or B'0111 (assertion)
Transition address: H'A000 0000
Transition operations:
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3I0) are
set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections.
H-UDI_reset()
{
EXPEVT = H'00000000;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A0000000;
}
Rev. 3.0, 04/02, page 132 of 1064
(4) Instruction TLB Multiple-Hit Exception
Source: Multiple ITLB address matches
Transition address: H'A000 0000
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3I0) are
set to B'1111.
CPU and on-chip peripheral module initialization is performed in the same way as in a manual
reset. For details, see the register descriptions in the relevant sections.
TLB_multi_hit()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
EXPEVT = H'00000140;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A0000000;
}
Rev. 3.0, 04/02, page 133 of 1064
(5) Data TLB Multiple-Hit Exception
Source: Multiple UTLB address matches
Transition address: H'A000 0000
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3I0) are
set to B'1111.
CPU and on-chip peripheral module initialization is performed in the same way as in a manual
reset. For details, see the register descriptions in the relevant sections.
TLB_multi_hit()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
EXPEVT = H'00000140;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A0000000;
}
Rev. 3.0, 04/02, page 134 of 1064
5.6.2
General Exceptions
(1) Data TLB Miss Exception
Source: Address mismatch in UTLB address comparison
Transition address: VBR + H'0000 0400
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'040 (for a read access) or H'060 (for a write access) is set in EXPEVT. The
BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0400.
To speed up TLB miss processing, the offset is separate from that of other exceptions.
Data_TLB_miss_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = read_access ? H'00000040 : H'00000060;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000400;
}
Rev. 3.0, 04/02, page 135 of 1064
(2) Instruction TLB Miss Exception
Source: Address mismatch in ITLB address comparison
Transition address: VBR + H'0000 0400
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0400.
To speed up TLB miss processing, the offset is separate from that of other exceptions.
ITLB_miss_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'00000040;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000400;
}
Rev. 3.0, 04/02, page 136 of 1064
(3) Initial Page Write Exception
Source: TLB is hit in a store access, but dirty bit D = 0
Transition address: VBR + H'0000 0100
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'080 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
Initial_write_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'00000080;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 137 of 1064
(4) Data TLB Protection Violation Exception
Source: The access does not accord with the UTLB protection information (PR bits) shown
below.
PR
Privileged Mode
User Mode
00
Only read access possible
Access not possible
01
Read/write access possible
Access not possible
10
Only read access possible
Only read access possible
11
Read/write access possible
Read/write access possible
Transition address: VBR + H'0000 0100
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'0A0 (for a read access) or H'0C0 (for a write access) is set in EXPEVT. The
BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100.
Data_TLB_protection_violation_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = read_access ? H'000000A0 : H'000000C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 138 of 1064
(5) Instruction TLB Protection Violation Exception
Source: The access does not accord with the ITLB protection information (PR bits) shown
below.
PR
Privileged Mode
User Mode
0
Access possible
Access not possible
1
Access possible
Access possible
Transition address: VBR + H'0000 0100
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'0A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
ITLB_protection_violation_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'000000A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 139 of 1064
(6) Data Address Error
Sources:
Word data access from other than a word boundary (2n +1)
Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)
Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n
+ 4, 8n + 5, 8n + 6, or 8n + 7)
Access to area H'8000 0000H'FFFF FFFF in user mode
Transition address: VBR + H'0000 0100
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'0E0 (for a read access) or H'100 (for a write access) is set in EXPEVT. The
BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. For
details, see section 3, Memory Management Unit (MMU).
Data_address_error()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = read_access? H'000000E0: H'00000100;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 140 of 1064
(7) Instruction Address Error
Sources:
Instruction fetch from other than a word boundary (2n +1)
Instruction fetch from area H'8000 0000H'FFFF FFFF in user mode
Transition address: VBR + H'0000 0100
Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in the
SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code H'0E0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. For details, see section 3, Memory Management Unit
(MMU).
Instruction_address_error()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'000000E0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 141 of 1064
(8) Unconditional Trap
Source: Execution of TRAPA instruction
Transition address: VBR + H'0000 0100
Transition operations:
As this is a processing-completion-type exception, the PC contents for the instruction
following the TRAPA instruction are saved in SPC. The value of SR and R15 when the
TRAPA instruction is executed are saved in SSR and SGR. The 8-bit immediate value in the
TRAPA instruction is multiplied by 4, and the result is set in TRA [9:0]. Exception code H'160
is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC =
VBR + H'0100.
TRAPA_exception()
{
SPC = PC + 2;
SSR = SR;
SGR = R15;
TRA = imm << 2;
EXPEVT = H'00000160;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 142 of 1064
(9) General Illegal Instruction Exception
Sources:
Decoding of an undefined instruction not in a delay slot
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'FFFD
Decoding in user mode of a privileged instruction not in a delay slot
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC
instructions that access GBR
Transition address: VBR + H'0000 0100
Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'180 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other
than H'FFFD is decoded.
General_illegal_instruction_exception()
{
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'00000180;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 143 of 1064
(10) Slot Illegal Instruction Exception
Sources:
Decoding of an undefined instruction in a delay slot
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'FFFD
Decoding of an instruction that modifies PC in a delay slot
Instructions that modify PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm,SR, LDC.L @Rm+,SR
Decoding in user mode of a privileged instruction in a delay slot
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC
instructions that access GBR
Decoding of a PC-relative MOV instruction or MOVA instruction in a delay slot
Transition address: VBR + H'0000 0100
Transition operations:
The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and
R15 contents when this exception occurred are saved in SSR and SGR.
Exception code H'1A0 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other
than H'FFFD is decoded.
Slot_illegal_instruction_exception()
{
SPC = PC - 2;
SSR = SR;
SGR = R15;
EXPEVT = H'000001A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 144 of 1064
(11) General FPU Disable Exception
Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1
Transition address: VBR + H'0000 0100
Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are F (but
excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L
instructions corresponding to FPUL and FPSCR.
General_fpu_disable_exception()
{
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'00000800;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 145 of 1064
(12) Slot FPU Disable Exception
Source: Decoding of an FPU instruction in a delay slot with SR.FD =1
Transition address: VBR + H'0000 0100
Transition operations:
The PC contents for the preceding delayed branch instruction are saved in SPC. The SR and
R15 contents when this exception occurred are saved in SSR and SGR.
Exception code H'820 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
Slot_fpu_disable_exception()
{
SPC = PC - 2;
SSR = SR;
SGR = R15;
EXPEVT = H'00000820;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 146 of 1064
(13) User Breakpoint Trap
Source: Fulfilling of a break condition set in the user break controller
Transition address: VBR + H'0000 0100, or DBR
Transition operations:
In the case of a post-execution break, the PC contents for the instruction following the
instruction at which the breakpoint is set are set in SPC. In the case of a pre-execution break,
the PC contents for the instruction at which the breakpoint is set are set in SPC.
The SR and R15 contents when the break occurred are saved in SSR and SGR. Exception code
H'1E0 is set in EXPEVT.
The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR + H'0100. It is
also possible to branch to PC = DBR.
For details of PC, etc., when a data break is set, see section 20, User Break Controller.
User_break_exception()
{
SPC = (pre_execution break? PC : PC + 2);
SSR = SR;
SGR = R15;
EXPEVT = H'000001E0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = (BRCR.UBDE==1 ? DBR : VBR + H'00000100);
}
Rev. 3.0, 04/02, page 147 of 1064
(14) FPU Exception
Source: Exception due to execution of a floating-point operation
Transition address: VBR + H'0000 0100
Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR . The R15 contents at this time are saved in SGR. Exception code H'120 is set in
EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to PC = VBR +
H'0100.
FPU_exception()
{
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'00000120;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 3.0, 04/02, page 148 of 1064
5.6.3
Interrupts
(1) NMI
Source: NMI pin edge detection
Transition address: VBR + H'0000 0600
Transition operations:
The PC and SR contents for the instruction at which this exception is accepted are saved in
SPC and SSR. The R15 contents at this time are saved in SGR.
Exception code H'1C0 is set in INTEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0600. When the BL bit in SR is 0, this interrupt is not
masked by the interrupt mask bits in SR, and is accepted at the highest priority level. When the
BL bit in SR is 1, a software setting can specify whether this interrupt is to be masked or
accepted. For details, see section 19, Interrupt Controller (INTC).
NMI()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'000001C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000600;
}
Rev. 3.0, 04/02, page 149 of 1064
(2) IRL Interrupts
Source: The interrupt mask bit setting in SR is smaller than the IRL (30) level, and the BL bit
in SR is 0 (accepted at instruction boundary).
Transition address: VBR + H'0000 0600
Transition operations:
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
The code corresponding to the IRL (30) level is set in INTEVT. See table 19.4, for the
corresponding codes. The BL, MD, and RB bits are set to 1 in SR, and a branch is made to
VBR + H'0600. The acceptance level is not set in the interrupt mask bits in SR. When the BL
bit in SR is 1, the interrupt is masked. For details, see section 19, Interrupt Controller (INTC).
IRL()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'00000200 ~ H'000003C0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000600;
}
Rev. 3.0, 04/02, page 150 of 1064
(3) Peripheral Module Interrupts
Source: The interrupt mask bit setting in SR is smaller than the peripheral module (H-UDI,
GPIO, DMAC, PCIC, TMU, RTC, SCI, SCIF, WDT, or REF) interrupt level, and the BL bit in
SR is 0 (accepted at instruction boundary).
Transition address: VBR + H'0000 0600
Transition operations:
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
The code corresponding to the interrupt source is set in INTEVT. The BL, MD, and RB bits
are set to 1 in SR, and a branch is made to VBR + H'0600. The module interrupt levels should
be set as values between B'0000 and B'1111 in the interrupt priority registers (IPRAIPRC) in
the interrupt controller. For details, see section 19, Interrupt Controller (INTC).
Module_interruption()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'00000400 ~ H'00000B40;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000600;
}
Rev. 3.0, 04/02, page 151 of 1064
5.6.4
Priority Order with Multiple Exceptions
With some instructions, such as instructions that make two accesses to memory, and the
indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple
exceptions occur. Care is required in these cases, as the exception priority order differs from the
normal order.
1. Instructions that make two accesses to memory
With MAC instructions, memory-to-memory arithmetic/logic instructions, and TAS
instructions, two data transfers are performed by a single instruction, and an exception will be
detected for each of these data transfers. In these cases, therefore, the following order is used
to determine priority.
a. Data address error in first data transfer
b. TLB miss in first data transfer
c. TLB protection violation in first data transfer
d. Initial page write exception in first data transfer
e. Data address error in second data transfer
f. TLB miss in second data transfer
g. TLB protection violation in second data transfer
h. Initial page write exception in second data transfer
2. Indivisible delayed branch instruction and delay slot instruction
As a delayed branch instruction and its associated delay slot instruction are indivisible, they
are treated as a single instruction. Consequently, the priority order for exceptions that occur in
these instructions differs from the usual priority order. The priority order shown below is for
the case where the delay slot instruction has only one data transfer.
a. A check is performed for the abort type and reexecution type exceptions of priority levels 1
and 2 in the delayed branch instruction.
b. A check is performed for the abort type and reexecution type exceptions of priority levels 1
and 2 in the delay slot instruction.
c. A check is performed for the completion type exception of priority level 2 in the delayed
branch instruction.
d. A check is performed for the completion type exception of priority level 2 in the delay slot
instruction.
e. A check is performed for priority level 3 in the delayed branch instruction and priority
level 3 in the delay slot instruction. (There is no priority ranking between these two.)
f. A check is performed for priority level 4 in the delayed branch instruction and priority
level 4 in the delay slot instruction. (There is no priority ranking between these two.)
If the delay slot instruction has a second data transfer, two checks are performed in step b, as in
1 above.
Rev. 3.0, 04/02, page 152 of 1064
If the accepted exception (the highest-priority exception) is a delay slot instruction re-
execution type exception, the branch instruction PR register write operation (PC
PR
operation performed in BSR, BSRF, JSR) is not inhibited.
5.7
Usage Notes
1. Return from exception handling
a. Check the BL bit in SR with software. If SPC and SSR have been saved to external
memory, set the BL bit in SR to 1 before restoring them.
b. Issue an RTE instruction. When RTE is executed, the SPC contents are set in PC, the SSR
contents are set in SR, and branch is made to the SPC address to return from the exception
handling routine.
2. If an exception or interrupt occurs when SR.BL = 1
a. Exception
When an exception other than a user break occurs, manual reset occurs. The value in
EXPEVT at this time is H'0000 0020; the value of the SPC and SSR registers is undefined.
b. Interrupt
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after
the BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI)
occurs, it can be held pending or accepted according to the setting made by software. In the
sleep or standby state, however, an interrupt is accepted even if the BL bit in SR is set to 1.
3. SPC when an exception occurs
a. Re-execution type exception
The PC value for the instruction in which the exception occurred is set in SPC, and the
instruction is re-executed after returning from exception handling. If an exception occurs in
a delay slot instruction, however, the PC value for the delay slot instruction is saved in SPC
regardless of whether or not the preceding delay slot instruction condition is satisfied.
b. Completion type exception or interrupt
The PC value for the instruction following that in which the exception occurred is set in
SPC. If an exception occurs in a branch instruction with delay slot, however, the PC value
for the branch destination is saved in SPC.
4.
An exception must not be generated in an RTE instruction delay slot, as the operation will be
undefined in this case.
Rev. 3.0, 04/02, page 153 of 1064
5.8
Restrictions
1. Restrictions on first instruction of exception handling routine
Do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at address VBR + H'100, VBR
+ H'400, or VBR + H'600.
When the UBDE bit in the BRCR register is set to 1 and the user break debug support
function* is used, do not locate a BT, BF, BT/S, BF/S, BRA, or BSR instruction at the address
indicated by the DBR register.
Note: * See section 20.4, User Break Debug Support Function.
Rev. 3.0, 04/02, page 154 of 1064
Rev. 3.0, 04/02, page 155 of 1064
Section 6 Floating-Point Unit
6.1
Overview
The floating-point unit (FPU) has the following features:
Conforms to IEEE754 standard
32 single-precision floating-point registers (can also be referenced as 16 double-precision
registers)
Two rounding modes: Round to Nearest and Round to Zero
Two denormalization modes: Flush to Zero and Treat Denormalized Number
Six exception sources: FPU Error, Invalid Operation, Divide By Zero, Overflow, Underflow,
and Inexact
Comprehensive instructions: Single-precision, double-precision, graphics support, system
control
When the FD bit in SR is set to 1, the FPU cannot be used, and an attempt to execute an FPU
instruction will cause an FPU disable exception.
6.2
Data Formats
6.2.1
Floating-Point Format
A floating-point number consists of the following three fields:
Sign (s)
Exponent (e)
Fraction (f)
The SH7751 Series can handle single-precision and double-precision floating-point numbers,
using the formats shown in figures 6.1 and 6.2.
31
s
e
f
30
23 22
0
Figure 6.1 Format of Single-Precision Floating-Point Number
Rev. 3.0, 04/02, page 156 of 1064
63
s
e
f
62
52 51
0
Figure 6.2 Format of Double-Precision Floating-Point Number
The exponent is expressed in biased form, as follows:
e = E + bias
The range of unbiased exponent E is E
min
1 to E
max
+ 1. The two values E
min
1 and E
max
+ 1 are
distinguished as follows. E
min
1 indicates zero (both positive and negative sign) and a
denormalized number, and E
max
+ 1 indicates positive or negative infinity or a non-number (NaN).
Table 6.1 shows bias, E
min
, and E
max
values.
Table 6.1
Floating-Point Number Formats and Parameters
Parameter
Single-Precision
Double-Precision
Total bit width
32 bits
64 bits
Sign bit
1 bit
1 bit
Exponent field
8 bits
11 bits
Fraction field
23 bits
52 bits
Precision
24 bits
53 bits
Bias
+127
+1023
E
max
+127
+1023
E
min
126
1022
Floating-point number value v is determined as follows:
If E = E
max
+ 1 and f
0, v is a non-number (NaN) irrespective of sign s
If E = E
max
+ 1 and f = 0, v = (1)
s
(infinity) [positive or negative infinity]
If E
min
E
E
max
, v = (1)
s
2
E
(1.f) [normalized number]
If E = E
min
1 and f
0, v = (1)
s
2
Emin
(0.f) [denormalized number]
If E = E
min
1 and f = 0, v = (1)
s
0 [positive or negative zero]
Table 6.2 shows the ranges of the various numbers in hexadecimal notation.
Rev. 3.0, 04/02, page 157 of 1064
Table 6.2
Floating-Point Ranges
Type
Single-Precision
Double-Precision
Signaling non-number
H'7FFFFFFF to H'7FC00000
H'7FFFFFFF FFFFFFFF to
H'7FF80000 00000000
Quiet non-number
H'7FBFFFFF to H'7F800001
H'7FF7FFFF FFFFFFFF to
H'7FF00000 00000001
Positive infinity
H'7F800000
H'7FF00000 00000000
Positive normalized
number
H'7F7FFFFF to H'00800000
H'7FEFFFFF FFFFFFFF to
H'00100000 00000000
Positive denormalized
number
H'007FFFFF to H'00000001
H'000FFFFF FFFFFFFF to
H'00000000 00000001
Positive zero
H'00000000
H'00000000 00000000
Negative zero
H'80000000
H'80000000 00000000
Negative denormalized
number
H'80000001 to H'807FFFFF
H'80000000 00000001 to
H'800FFFFF FFFFFFFF
Negative normalized
number
H'80800000 to H'FF7FFFFF
H'80100000 00000000 to
H'FFEFFFFF FFFFFFFF
Negative infinity
H'FF800000
H'FFF00000 00000000
Quiet non-number
H'FF800001 to H'FFBFFFFF
H'FFF00000 00000001 to
H'FFF7FFFF FFFFFFFF
Signaling non-number
H'FFC00000 to H'FFFFFFFF
H'FFF80000 00000000 to
H'FFFFFFFF FFFFFFFF
6.2.2
Non-Numbers (NaN)
Figure 6.3 shows the bit pattern of a non-number (NaN). A value is NaN in the following case:
Sign bit: Don't care
Exponent field: All bits are 1
Fraction field: At least one bit is 1
The NaN is a signaling NaN (sNaN) if the MSB of the fraction field is 1, and a quiet NaN (qNaN)
if the MSB is 0.
Rev. 3.0, 04/02, page 158 of 1064
31
x
11111111
Nxxxxxxxxxxxxxxxxxxxxxx
30
23 22
0
N = 1: sNaN
N = 0: qNaN
Figure 6.3 Single-Precision NaN Bit Pattern
An sNAN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point
value.
When the EN.V bit in the FPSCR register is 0, the operation result (output) is a qNaN.
When the EN.V bit in the FPSCR register is 1, an invalid operation exception will be
generated. In this case, the contents of the operation destination register are unchanged.
If a qNaN is input in an operation that generates a floating-point value, and an sNaN has not been
input in that operation, the output will always be a qNaN irrespective of the setting of the EN.V bit
in the FPSCR register. An exception will not be generated in this case.
The qNAN values generated by the SH7751 Series as operation results are as follows:
Single-precision qNaN: H'7FBFFFFF
Double-precision qNaN: H'7FF7FFFF FFFFFFFF
See the individual instruction descriptions for details of floating-point operations when a non-
number (NaN) is input.
6.2.3
Denormalized Numbers
For a denormalized number floating-point value, the exponent field is expressed as 0, and the
fraction field as a non-zero value.
When the DN bit in the FPU's status register FPSCR is 1, a denormalized number (source operand
or operation result) is always flushed to 0 in a floating-point operation that generates a value (an
operation other than copy, FNEG, or FABS).
When the DN bit in FPSCR is 0, a denormalized number (source operand or operation result) is
processed as it is. See the individual instruction descriptions for details of floating-point
operations when a denormalized number is input.
Rev. 3.0, 04/02, page 159 of 1064
6.3
Registers
6.3.1
Floating-Point Registers
Figure 6.4 shows the floating-point register configuration. There are thirty-two 32-bit floating-
point registers, referenced by specifying FR0FR15, DR0/2/4/6/8/10/12/14, FV0/4/8/12, XF0
XF15, XD0/2/4/6/8/10/12/14, or XMTRX.
1. Floating-point registers, FPRi_BANKj (32 registers)
FPR0_BANK0FPR15_BANK0
FPR0_BANK1FPR15_BANK1
2. Single-precision floating-point registers, FRi (16 registers)
When FPSCR.FR = 0, FR0FR15 indicate FPR0_BANK0FPR15_BANK0;
when FPSCR.FR = 1, FR0FR15 indicate FPR0_BANK1FPR15_BANK1.
3. Double-precision floating-point registers, DRi (8 registers): A DR register comprises two FR
registers
DR0 = {FR0, FR1}, DR2 = {FR2, FR3}, DR4 = {FR4, FR5}, DR6 = {FR6, FR7},
DR8 = {FR8, FR9}, DR10 = {FR10, FR11}, DR12 = {FR12, FR13}, DR14 = {FR14, FR15}
4. Single-precision floating-point vector registers, FVi (4 registers): An FV register comprises
four FR registers
FV0 = {FR0, FR1, FR2, FR3}, FV4 = {FR4, FR5, FR6, FR7},
FV8 = {FR8, FR9, FR10, FR11}, FV12 = {FR12, FR13, FR14, FR15}
5. Single-precision floating-point extended registers, XFi (16 registers)
When FPSCR.FR = 0, XF0XF15 indicate FPR0_BANK1FPR15_BANK1;
when FPSCR.FR = 1, XF0XF15 indicate FPR0_BANK0FPR15_BANK0.
6. Double-precision floating-point extended registers, XDi (8 registers): An XD register
comprises two XF registers
XD0 = {XF0, XF1}, XD2 = {XF2, XF3}, XD4 = {XF4, XF5}, XD6 = {XF6, XF7},
XD8 = {XF8, XF9}, XD10 = {XF10, XF11}, XD12 = {XF12, XF13}, XD14 = {XF14, XF15}
7. Single-precision floating-point extended register matrix: XMTRX
XMTRX comprises all 16 XF registers
XMTRX =
XF0
XF4
XF8
XF12
XF1
XF5
XF9
XF13
XF2
XF6
XF10
XF14
XF3
XF7
XF11
XF15
Rev. 3.0, 04/02, page 160 of 1064
FPR0_BANK0
FPR1_BANK0
FPR2_BANK0
FPR3_BANK0
FPR4_BANK0
FPR5_BANK0
FPR6_BANK0
FPR7_BANK0
FPR8_BANK0
FPR9_BANK0
FPR10_BANK0
FPR11_BANK0
FPR12_BANK0
FPR13_BANK0
FPR14_BANK0
FPR15_BANK0
XF0
XF1
XF2
XF3
XF4
XF5
XF6
XF7
XF8
XF9
XF10
XF11
XF12
XF13
XF14
XF15
FR0
FR1
FR2
FR3
FR4
FR5
FR6
FR7
FR8
FR9
FR10
FR11
FR12
FR13
FR14
FR15
DR0
DR2
DR4
DR6
DR8
DR10
DR12
DR14
FV0
FV4
FV8
FV12
XD0
XMTRX
XD2
XD4
XD6
XD8
XD10
XD12
XD14
FPR0_BANK1
FPR1_BANK1
FPR2_BANK1
FPR3_BANK1
FPR4_BANK1
FPR5_BANK1
FPR6_BANK1
FPR7_BANK1
FPR8_BANK1
FPR9_BANK1
FPR10_BANK1
FPR11_BANK1
FPR12_BANK1
FPR13_BANK1
FPR14_BANK1
FPR15_BANK1
XF0
XF1
XF2
XF3
XF4
XF5
XF6
XF7
XF8
XF9
XF10
XF11
XF12
XF13
XF14
XF15
FR0
FR1
FR2
FR3
FR4
FR5
FR6
FR7
FR8
FR9
FR10
FR11
FR12
FR13
FR14
FR15
DR0
DR2
DR4
DR6
DR8
DR10
DR12
DR14
FV0
FV4
FV8
FV12
XD0
XMTRX
XD2
XD4
XD6
XD8
XD10
XD12
XD14
FPSCR.FR = 0
FPSCR.FR = 1
Figure 6.4 Floating-Point Registers
Rev. 3.0, 04/02, page 161 of 1064
6.3.2
Floating-Point Status/Control Register (FPSCR)
Floating-point status/control register, FPSCR (32 bits, initial value = H'0004 0001)
31
22
21 20 19
18 17
12
11
7
6
2
1
0
--
FR SZ PR DN
Cause
Enable
Flag
RM
Note:
--: Reserved. These bits are always read as 0, and should only be written with 0.
FR: Floating-point register bank
FR = 0: FPR0_BANK0FPR15_BANK0 are assigned to FR0FR15; FPR0_BANK1
FPR15_BANK1 are assigned to XF0XF15.
FR = 1: FPR0_BANK0FPR15_BANK0 are assigned to XF0XF15; FPR0_BANK1
FPR15_BANK1 are assigned to FR0FR15.
SZ: Transfer size mode
SZ = 0: The data size of the FMOV instruction is 32 bits.
SZ = 1: The data size of the FMOV instruction is a 32-bit register pair (64 bits).
PR: Precision mode
PR = 0: Floating-point instructions are executed as single-precision operations.
PR = 1: Floating-point instructions are executed as double-precision operations (graphics
support instructions are undefined).
Do not set SZ and PR to 1 simultaneously; this setting is reserved.
[SZ, PR = 11]: Reserved (FPU operation instruction is undefined.)
DN: Denormalization mode
DN = 0: A denormalized number is treated as such.
DN = 1: A denormalized number is treated as zero.
Cause: FPU exception cause field
Enable: FPU exception enable field
Flag: FPU exception flag field
FPU
Error (E)
Invalid
Operation (V)
Division
by Zero (Z)
Overflow
(O)
Underflow
(U)
Inexact
(I)
Cause
FPU exception
cause field
Bit 17
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Enable
FPU exception
enable field
None
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Flag
FPU exception
flag field
None
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Rev. 3.0, 04/02, page 162 of 1064
When an FPU operation instruction is executed, the FPU exception cause field is cleared to
zero first. When the next FPU exception is occurred, the corresponding bits in the FPU
exception cause field and FPU exception flag field are set to 1. The FPU exception flag field
holds the status of the exception generated after the field was last cleared.
RM: Rounding mode
RM = 00: Round to Nearest
RM = 01: Round to Zero
RM = 10: Reserved
RM = 11: Reserved
Bits 22 to 31: Reserved
These bits are always read as 0, and should only be written with 0.
6.3.3
Floating-Point Communication Register (FPUL)
Information is transferred between the FPU and CPU via the FPUL register. The 32-bit FPUL
register is a system register, and is accessed from the CPU side by means of LDS and STS
instructions. For example, to convert the integer stored in general register R1 to a single-precision
floating-point number, the processing flow is as follows:
R1
(LDS instruction)
FPUL
(single-precision FLOAT instruction)
FR1
6.4
Rounding
In a floating-point instruction, rounding is performed when generating the final operation result
from the intermediate result. Therefore, the result of combination instructions such as FMAC,
FTRV, and FIPR will differ from the result when using a basic instruction such as FADD, FSUB,
or FMUL. Rounding is performed once in FMAC, but twice in FADD, FSUB, and FMUL.
There are two rounding methods, the method to be used being determined by the RM field in
FPSCR.
RM = 00: Round to Nearest
RM = 01: Round to Zero
Round to Nearest: The operation result is rounded to the nearest expressible value. If there are
two nearest expressible values, the one with an LSB of 0 is selected.
If the unrounded value is 2
Emax
(2 2
P
) or more, the result will be infinity with the same sign as the
unrounded value. The values of Emax and P, respectively, are 127 and 24 for single-precision, and
1023 and 53 for double-precision.
Rev. 3.0, 04/02, page 163 of 1064
Round to Zero: The digits below the round bit of the unrounded value are discarded.
If the unrounded value is larger than the maximum expressible absolute value, the value will be
the maximum expressible absolute value.
6.5
Floating-Point Exceptions
FPU-related exceptions are as follows:
General illegal instruction/slot illegal instruction exception
The exception occurs if an FPU instruction is executed when SR.FD = 1.
FPU exceptions
The exception sources are as follows:
FPU error (E): When FPSCR.DN = 0 and a denormalized number is input
Invalid operation (V): In case of an invalid operation, such as NaN input
Division by zero (Z): Division with a zero divisor
Overflow (O): When the operation result overflows
Underflow (U): When the operation result underflows
Inexact exception (I): When overflow, underflow, or rounding occurs
The FPSCR FPU exception cause field contains bits corresponding to all of above E, V, Z, O,
U, and I, and the FPSCR flag and enable fields contain bits corresponding to V, Z, O, U, and I,
but not E. Thus, FPU errors cannot be disabled.
When an FPU exception occurs, the corresponding bit in the FPU exception cause field is set
to 1, and 1 is added to the corresponding bit in the FPU exception flag field. When an FPU
exception does not occur, the corresponding bit in the FPU exception cause field is cleared to
0, but the corresponding bit in the FPU exception flag field remains unchanged.
Enable/disable exception handling
The SH7751 Series supports enable exception handling and disable exception handling.
Enable exception handling is initiated in the following cases:
FPU error (E): FPSCR.DN = 0 and a denormalized number is input
Invalid operation (V): FPSCR.EN.V = 1 and (instruction = FTRV or invalid operation)
Division by zero (Z): FPSCR.EN.Z = 1 and division with a zero divisor
Overflow (O): FPSCR.EN.O = 1 and instruction with possibility of operation result
overflow
Underflow (U): FPSCR.EN.U = 1 and instruction with possibility of operation result
underflow
Inexact exception (I): FPSCR.EN.I = 1 and instruction with possibility of inexact operation
result
Rev. 3.0, 04/02, page 164 of 1064
These possibilities are shown in the individual instruction descriptions. All exception events
that originate in the FPU are assigned as the same exception event. The meaning of an
exception is determined by software by reading system register FPSCR and interpreting the
information it contains. If no bits are set in the FPU exception cause field of FPSCR when one
or more of bits O, U, I, and V (in case of FTRV only) are set in the FPU exception enable
field, this indicates that an actual FPU exception is not generated. Also, the destination register
is not changed by any FPU exception handling operation.
Except for the above, the bit corresponding to V, Z, O, U, or I is set to 1 in all processing, and
the default value is generated as the result of the operation.
Invalid operation (V): qNAN is generated as the result.
Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
Overflow (O):
In round to zero mode, the maximum normalized number, with the same sign as the
unrounded value, is generated.
In round to nearest mode, infinity with the same sign as the unrounded value is generated.
Underflow (U):
When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value,
or zero with the same sign as the unrounded value, is generated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.
Inexact exception (I): An inexact result is generated.
6.6
Graphics Support Functions
The SH7751 Series supports two kinds of graphics functions: new instructions for geometric
operations, and pair single-precision transfer instructions that enable high-speed data transfer.
6.6.1
Geometric Operation Instructions
Geometric operation instructions perform approximate-value computations. To enable high-speed
computation with a minimum of hardware, the SH7751 Series ignores comparatively small values
in the partial computation results of four multiplications. Consequently, the error shown below is
produced in the result of the computation:
Maximum error = MAX (individual multiplication result
2
MIN (number of multiplier significant digits1, number of multiplicand significant digits1)
) + MAX (result value
2
23
, 2
149
)
The number of significant digits is 24 for a normalized number and 23 for a denormalized number
(number of leading zeros in the fractional part).
In future version of SuperH series, the above error is guaranteed, but the same result as SH7751
Series is not guaranteed.
Rev. 3.0, 04/02, page 165 of 1064
FIPR FVm, FVn (m, n: 0, 4, 8, 12): Examples of the use of this instruction are given below.
Inner product (m
n):
This operation is generally used for surface/rear surface determination for polygon surfaces.
Sum of square of elements (m = n):
This operation is generally used to find the length of a vector.
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in the FPU exception cause field and FPU exception flag field is always
set to 1 when an FIPR instruction is executed. Therefore, if the corresponding bit is set in the FPU
exception enable field, FPU exception handling will be executed.
FTRV XMTRX, FVn (n: 0, 4, 8, 12): Examples of the use of this instruction are given below.
Matrix (4
4)
vector (4):
This operation is generally used for viewpoint changes, angle changes, or movements called
vector transformations (4-dimensional). Since affine transformation processing for angle +
parallel movement basically requires a 4
4 matrix, the SH7751 Series supports 4-dimensional
operations.
Matrix (4
4)
matrix (4
4):
This operation requires the execution of four FTRV instructions.
Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in the FPU exception cause field and FPU exception flag field is always
set to 1 when an FTRV instruction is executed. Therefore, if the corresponding bit is set in the
FPU exception enable field, FPU exception handling will be executed. For the same reason, it is
not possible to check all data types in the registers beforehand when executing an FTRV
instruction. If the V bit is set in the FPU exception enable field, FPU exception handling will be
executed.
FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is
executed, matrix elements must be set in an array in the background bank. However, to create the
actual elements of a translation matrix, it is easier to use registers in the foreground bank. When
the LDC instruction is used on FPSCR, this instruction expends 4 to 5 cycles in order to maintain
the FPU state. With the FRCHG instruction, an FPSCR.FR bit modification can be performed in
one cycle.
Rev. 3.0, 04/02, page 166 of 1064
6.6.2
Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, the SH7751 Series also supports
high-speed data transfer instructions.
When FPSCR.SZ = 1, the SH7751 Series can perform data transfer by means of pair single-
precision data transfer instructions.
FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2
32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
FSCHG
This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between
use and non-use of pair single-precision data transfer.
Programming Note:
When FPSCR.SZ = 1 and big-endian mode is used, FMOV can be used for a double-precision
floating-point load or store. In little-endian mode, a double-precision floating-point load or store
requires execution of two 32-bit data size operations with FPSCR.SZ = 0.
Rev. 3.0, 04/02, page 167 of 1064
Section 7 Instruction Set
7.1
Execution Environment
PC: PC indicates the address of the instruction itself.
Data sizes and data types: The SH7751 Series instruction set is implemented with 16-bit fixed-
length instructions. The SH7751 Series can use byte (8-bit), word (16-bit), longword (32-bit), and
quadword (64-bit) data sizes for memory access. Single-precision floating-point data (32 bits) can
be moved to and from memory using longword or quadword size. Double-precision floating-point
data (64 bits) can be moved to and from memory using longword size. When a double-precision
floating-point operation is specified (FPSCR.PR = 1), the result of an operation using quadword
access will be undefined. When the SH7751 Series moves byte-size or word-size data from
memory to a register, the data is sign-extended.
Load-Store Architecture: The SH7751 Series features a load-store architecture in which
operations are basically executed using registers. Except for bit-manipulation operations such as
logical AND that are executed directly in memory, operands in an operation that requires memory
access are loaded into registers and the operation is executed between the registers.
Delayed Branches: Except for the two branch instructions BF and BT, the SH7751 Series branch
instructions and RTE are delayed branches. In a delayed branch, the instruction following the
branch is executed before the branch destination instruction. This execution slot following a
delayed branch is called a delay slot. For example, the BRA execution sequence is as follows:
Static Sequence
Dynamic Sequence
BRA
TARGET
BRA
TARGET
ADD
R1, R0
next_2
ADD
R1, R0
target_instr
ADD in delay slot is executed before
branching to TARGET
Delay Slot: A slot illegal instruction exception may occur when a specific instruction is executed
in a delay slot. See section 5, Exceptions. The instruction following BF/S or BT/S for which the
branch is not taken is also a delay slot instruction.
T Bit: The T bit in the status register (SR) is used to show the result of a compare operation, and
is referenced by a conditional branch instruction. An example of the use of a conditional branch
instruction is shown below.
ADD #1, R0
; T bit is not changed by ADD operation
CMP/EQ R1, R0 ; If R0 = R1, T bit is set to 1
BT TARGET
; Branches to TARGET if T bit = 1 (R0 = R1)
Rev. 3.0, 04/02, page 168 of 1064
In an RTE delay slot, status register (SR) bits are referenced as follows. In instruction access, the
MD bit is used before modification, and in data access, the MD bit is accessed after modification.
The other bits--S, T, M, Q, FD, BL, and RB--after modification are used for delay slot
instruction execution. The STC and STC.L SR instructions access all SR bits after modification.
Constant Values: An 8-bit constant value can be specified by the instruction code and an
immediate value. 16-bit and 32-bit constant values can be defined as literal constant values in
memory, and can be referenced by a PC-relative load instruction.
MOV.W
@(disp, PC), Rn
MOV.L
@(disp, PC), Rn
There are no PC-relative load instructions for floating-point operations. However, it is possible to
set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point
register.
Rev. 3.0, 04/02, page 169 of 1064
7.2
Addressing Modes
Addressing modes and effective address calculation methods are shown in table 7.1. When a
location in virtual memory space is accessed (MMUCR.AT = 1), the effective address is translated
into a physical address. If multiple virtual memory space systems are selected (MMUCR.SV = 0),
the least significant bit of PTEH is also referenced as the access ASID. See section 3, Memory
Management Unit (MMU).
Table 7.1
Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation
Formula
Register
direct
Rn
Effective address is register Rn.
(Operand is register Rn contents.)
--
Register
indirect
@Rn
Effective address is register Rn contents.
Rn
Rn
Rn
EA
(EA: effective
address)
Register
indirect
with post-
increment
@Rn+
Effective address is register Rn contents.
A constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand, 8 for a
quadword operand.
Rn
Rn
1/2/4/8
+
Rn + 1/2/4/8
Rn
EA
After
instruction
execution
Byte:
Rn + 1
Rn
Word:
Rn + 2
Rn
Longword:
Rn + 4
Rn
Quadword:
Rn + 8
Rn
Register
indirect
with pre-
decrement
@Rn
Effective address is register Rn contents,
decremented by a constant beforehand:
1 for a byte operand, 2 for a word operand,
4 for a longword operand, 8 for a quadword
operand.
Rn
1/2/4/8
Rn 1/2/4/8
Rn 1/2/4/8
Byte:
Rn 1
Rn
Word:
Rn 2
Rn
Longword:
Rn 4
Rn
Quadword:
Rn 8
Rn
Rn
EA
(Instruction
executed
with Rn after
calculation)
Rev. 3.0, 04/02, page 170 of 1064
Table 7.1
Addressing Modes and Effective Addresses (cont)
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation
Formula
Register
indirect with
displacement
@(disp:4, Rn) Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
Rn
Rn + disp
1/2/4
+
1/2/4
disp
(zero-extended)
Byte: Rn +
disp
EA
Word: Rn +
disp
2
EA
Longword:
Rn + disp
4
EA
Indexed
register
indirect
@(R0, Rn)
Effective address is sum of register Rn and R0
contents.
Rn
R0
Rn + R0
+
Rn + R0
EA
GBR indirect
with
displacement
@(disp:8,
GBR)
Effective address is register GBR contents with
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2 (word),
or 4 (longword), according to the operand size.
GBR
1/2/4
GBR
+ disp
1/2/4
+
disp
(zero-extended)
Byte: GBR +
disp
EA
Word: GBR +
disp
2
EA
Longword:
GBR + disp
4
EA
Indexed
GBR indirect
@(R0, GBR)
Effective address is sum of register GBR and R0
contents.
GBR
R0
GBR + R0
+
GBR + R0
EA
Rev. 3.0, 04/02, page 171 of 1064
Table 7.1
Addressing Modes and Effective Addresses (cont)
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation
Formula
PC-relative
with
displacement
@(disp:8, PC) Effective address is PC+4 with 8-bit displacement
disp added. After disp is zero-extended, it is
multiplied by 2 (word), or 4 (longword), according
to the operand size. With a longword operand,
the lower 2 bits of PC are masked.
PC
H'FFFFFFFC
PC + 4 + disp
2
or PC &
H'FFFFFFFC
+ 4 + disp
4
+
4
2/4
+
& *
disp
(zero-extended)
* With longword operand
Word: PC + 4
+ disp
2
EA
Longword:
PC &
H'FFFFFFFC
+ 4 + disp
4
EA
PC-relative
disp:8
Effective address is PC+4 with 8-bit displacement
disp added after being sign-extended and
multiplied by 2.
2
+
disp
(sign-extended)
4
+
PC
PC + 4 + disp
2
PC + 4 + disp
2
Branch-
Target
Rev. 3.0, 04/02, page 172 of 1064
Table 7.1
Addressing Modes and Effective Addresses (cont)
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation
Formula
PC-relative
disp:12
Effective address is PC+4 with 12-bit displacement
disp added after being sign-extended and
multiplied by 2.
2
+
disp
(sign-extended)
4
+
PC
PC + 4 + disp
2
PC + 4 + disp
2
Branch-
Target
Rn
Effective address is sum of PC+4 and Rn.
PC
4
Rn
+
+
PC + 4 + Rn
PC + 4 + Rn
Branch-
Target
Immediate
#imm:8
8-bit immediate data imm of TST, AND, OR, or
XOR instruction is zero-extended.
--
#imm:8
8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.
--
#imm:8
8-bit immediate data imm of TRAPA instruction is
zero-extended and multiplied by 4.
--
Note: For the addressing modes below that use a displacement (disp), the assembler descriptions
in this manual show the value before scaling (
1,
2, or
4) is performed according to the
operand size. This is done to clarify the operation of the chip. Refer to the relevant
assembler notation rules for the actual assembler descriptions.
@ (disp:4, Rn)
; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC)
; PC-relative with displacement
disp:8, disp:12
; PC-relative
Rev. 3.0, 04/02, page 173 of 1064
7.3
Instruction Set
Table 7.2 shows the notation used in the following SH instruction list.
Table 7.2
Notation Used in Instruction List
Item
Format
Description
Instruction
mnemonic
OP.Sz SRC, DEST
OP:
Operation code
Sz: Size
SRC:
Source
DEST:
Source and/or destination operand
Summary of
operation
,
:
Transfer direction
(xx):
Memory operand
M/Q/T:
SR flag bits
&:
Logical AND of individual bits
|:
Logical OR of individual bits
:
Logical exclusive-OR of individual bits
~:
Logical NOT of individual bits
<<n, >>n: n-bit shift
Instruction code
MSB
LSB
mmmm: Register number (Rm, FRm)
nnnn:
Register number (Rn, FRn)
0000:
R0, FR0
0001:
R1, FR1
:
1111:
R15, FR15
mmm:
Register number (DRm, XDm, Rm_BANK)
nnn:
Register number (DRm, XDm, Rn_BANK)
000:
DR0, XD0, R0_BANK
001:
DR2, XD2, R1_BANK
:
111:
DR14, XD14, R7_BANK
mm:
Register number (FVm)
nn:
Register number (FVn)
00:
FV0
01:
FV4
10:
FV8
11:
FV12
iiii:
Immediate data
dddd:
Displacement
Privileged mode
"Privileged" means the instruction can only be executed
in privileged mode.
T bit
Value of T bit after
instruction execution
--: No change
Note: Scaling (
1,
2,
4, or
8) is executed according to the size of the instruction operand(s).
Rev. 3.0, 04/02, page 174 of 1064
Table 7.3
Fixed-Point Transfer Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
MOV
#imm,Rn
imm
sign extension
Rn
1110nnnniiiiiiii
--
--
MOV.W
@(disp,PC),Rn
(disp
2 + PC + 4)
sign
extension
Rn
1001nnnndddddddd
--
--
MOV.L
@(disp,PC),Rn
(disp
4 + PC & H'FFFFFFFC
+ 4)
Rn
1101nnnndddddddd
--
--
MOV
Rm,Rn
Rm
Rn
0110nnnnmmmm0011
--
--
MOV.B
Rm,@Rn
Rm
(Rn)
0010nnnnmmmm0000
--
--
MOV.W
Rm,@Rn
Rm
(Rn)
0010nnnnmmmm0001
--
--
MOV.L
Rm,@Rn
Rm
(Rn)
0010nnnnmmmm0010
--
--
MOV.B
@Rm,Rn
(Rm)
sign extension
Rn
0110nnnnmmmm0000
--
--
MOV.W
@Rm,Rn
(Rm)
sign extension
Rn
0110nnnnmmmm0001
--
--
MOV.L
@Rm,Rn
(Rm)
Rn
0110nnnnmmmm0010
--
--
MOV.B
Rm,@-Rn
Rn-1
Rn, Rm
(Rn)
0010nnnnmmmm0100
--
--
MOV.W
Rm,@-Rn
Rn-2
Rn, Rm
(Rn)
0010nnnnmmmm0101
--
--
MOV.L
Rm,@-Rn
Rn-4
Rn, Rm
(Rn)
0010nnnnmmmm0110
--
--
MOV.B
@Rm+,Rn
(Rm)
sign extension
Rn,
Rm + 1
Rm
0110nnnnmmmm0100
--
--
MOV.W
@Rm+,Rn
(Rm)
sign extension
Rn,
Rm + 2
Rm
0110nnnnmmmm0101
--
--
MOV.L
@Rm+,Rn
(Rm)
Rn, Rm + 4
Rm
0110nnnnmmmm0110
--
--
MOV.B
R0,@(disp,Rn)
R0
(disp + Rn)
10000000nnnndddd
--
--
MOV.W
R0,@(disp,Rn)
R0
(disp
2 + Rn)
10000001nnnndddd
--
--
MOV.L
Rm,@(disp,Rn)
Rm
(disp
4 + Rn)
0001nnnnmmmmdddd
--
--
MOV.B
@(disp,Rm),R0
(disp + Rm)
sign extension
R0
10000100mmmmdddd
--
--
MOV.W
@(disp,Rm),R0
(disp
2 + Rm)
sign
extension
R0
10000101mmmmdddd
--
--
MOV.L
@(disp,Rm),Rn
(disp
4 + Rm)
Rn
0101nnnnmmmmdddd
--
--
MOV.B
Rm,@(R0,Rn)
Rm
(R0 + Rn)
0000nnnnmmmm0100
--
--
MOV.W
Rm,@(R0,Rn)
Rm
(R0 + Rn)
0000nnnnmmmm0101
--
--
MOV.L
Rm,@(R0,Rn)
Rm
(R0 + Rn)
0000nnnnmmmm0110
--
--
MOV.B
@(R0,Rm),Rn
(R0 + Rm)
sign extension
Rn
0000nnnnmmmm1100
--
--
MOV.W
@(R0,Rm),Rn
(R0 + Rm)
sign extension
Rn
0000nnnnmmmm1101
--
--
MOV.L
@(R0,Rm),Rn
(R0 + Rm)
Rn
0000nnnnmmmm1110
--
--
Rev. 3.0, 04/02, page 175 of 1064
Table 7.3
Fixed-Point Transfer Instructions (cont)
Instruction
Operation
Instruction Code
Privileged
T Bit
MOV.B
R0,@(disp,GBR)
R0
(disp + GBR)
11000000dddddddd
--
--
MOV.W
R0,@(disp,GBR)
R0
(disp
2 + GBR)
11000001dddddddd
--
--
MOV.L
R0,@(disp,GBR)
R0
(disp
4 + GBR)
11000010dddddddd
--
--
MOV.B
@(disp,GBR),R0
(disp + GBR)
sign extension
R0
11000100dddddddd
--
--
MOV.W
@(disp,GBR),R0
(disp
2 + GBR)
sign extension
R0
11000101dddddddd
--
--
MOV.L
@(disp,GBR),R0
(disp
4 + GBR)
R0
11000110dddddddd
--
--
MOVA
@(disp,PC),R0
disp
4 + PC & H'FFFFFFFC
+ 4
R0
11000111dddddddd
--
--
MOVT
Rn
T
Rn
0000nnnn00101001
--
--
SWAP.B
Rm,Rn
Rm
swap lower 2 bytes
Rn
0110nnnnmmmm1000
--
--
SWAP.W
Rm,Rn
Rm
swap upper/lower
words
Rn
0110nnnnmmmm1001
--
--
XTRCT
Rm,Rn
Rm:Rn middle 32 bits
Rn
0010nnnnmmmm1101
--
--
Rev. 3.0, 04/02, page 176 of 1064
Table 7.4
Arithmetic Operation Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
ADD
Rm,Rn
Rn + Rm
Rn
0011nnnnmmmm1100
--
--
ADD
#imm,Rn
Rn + imm
Rn
0111nnnniiiiiiii
--
--
ADDC
Rm,Rn
Rn + Rm + T
Rn, carry
T
0011nnnnmmmm1110
--
Carry
ADDV
Rm,Rn
Rn + Rm
Rn, overflow
T
0011nnnnmmmm1111
--
Overflow
CMP/EQ
#imm,R0
When R0 = imm, 1
T
Otherwise, 0
T
10001000iiiiiiii
--
Comparison
result
CMP/EQ
Rm,Rn
When Rn = Rm, 1
T
Otherwise, 0
T
0011nnnnmmmm0000
--
Comparison
result
CMP/HS
Rm,Rn
When Rn
Rm (unsigned),
1
T
Otherwise, 0
T
0011nnnnmmmm0010
--
Comparison
result
CMP/GE
Rm,Rn
When Rn
Rm (signed), 1
T
Otherwise, 0
T
0011nnnnmmmm0011
--
Comparison
result
CMP/HI
Rm,Rn
When Rn > Rm (unsigned),
1
T
Otherwise, 0
T
0011nnnnmmmm0110
--
Comparison
result
CMP/GT
Rm,Rn
When Rn > Rm (signed), 1
T
Otherwise, 0
T
0011nnnnmmmm0111
--
Comparison
result
CMP/PZ
Rn
When Rn
0, 1
T
Otherwise, 0
T
0100nnnn00010001
--
Comparison
result
CMP/PL
Rn
When Rn > 0, 1
T
Otherwise, 0
T
0100nnnn00010101
--
Comparison
result
CMP/STR Rm,Rn
When any bytes are equal,
1
T
Otherwise, 0
T
0010nnnnmmmm1100
--
Comparison
result
DIV1
Rm,Rn
1-step division (Rn
Rm)
0011nnnnmmmm0100
--
Calculation
result
DIV0S
Rm,Rn
MSB of Rn
Q,
MSB of Rm
M, M^Q
T
0010nnnnmmmm0111
--
Calculation
result
DIV0U
0
M/Q/T
0000000000011001
--
0
DMULS.L
Rm,Rn
Signed, Rn
Rm
MAC,
32
32
64 bits
0011nnnnmmmm1101
--
--
DMULU.L
Rm,Rn
Unsigned, Rn
Rm
MAC,
32
32
64 bits
0011nnnnmmmm0101
--
--
DT
Rn
Rn 1
Rn; when Rn = 0,
1
T
When Rn
0, 0
T
0100nnnn00010000
--
Comparison
result
EXTS.B
Rm,Rn
Rm sign-extended from
byte
Rn
0110nnnnmmmm1110
--
--
Rev. 3.0, 04/02, page 177 of 1064
Table 7.4
Arithmetic Operation Instructions (cont)
Instruction
Operation
Instruction Code
Privileged
T Bit
EXTS.W
Rm,Rn
Rm sign-extended from
word
Rn
0110nnnnmmmm1111
--
--
EXTU.B
Rm,Rn
Rm zero-extended from
byte
Rn
0110nnnnmmmm1100
--
--
EXTU.W
Rm,Rn
Rm zero-extended from
word
Rn
0110nnnnmmmm1101
--
--
MAC.L
@Rm+,@Rn+ Signed, (Rn)
(Rm) + MAC
MAC
Rn + 4
Rn, Rm + 4
Rm
32
32 + 64
64 bits
0000nnnnmmmm1111
--
--
MAC.W
@Rm+,@Rn+ Signed, (Rn)
(Rm) + MAC
MAC
Rn + 2
Rn, Rm + 2
Rm
16
16 + 64
64 bits
0100nnnnmmmm1111
--
--
MUL.L
Rm,Rn
Rn
Rm
MACL
32
32
32 bits
0000nnnnmmmm0111
--
--
MULS.W
Rm,Rn
Signed, Rn
Rm
MACL
16
16
32 bits
0010nnnnmmmm1111
--
--
MULU.W
Rm,Rn
Unsigned, Rn
Rm
MACL
16
16
32 bits
0010nnnnmmmm1110
--
--
NEG
Rm,Rn
0 Rm
Rn
0110nnnnmmmm1011
--
--
NEGC
Rm,Rn
0 Rm T
Rn, borrow
T
0110nnnnmmmm1010
--
Borrow
SUB
Rm,Rn
Rn Rm
Rn
0011nnnnmmmm1000
--
--
SUBC
Rm,Rn
Rn Rm T
Rn, borrow
T
0011nnnnmmmm1010
--
Borrow
SUBV
Rm,Rn
Rn Rm
Rn, underflow
T
0011nnnnmmmm1011
--
Underflow
Rev. 3.0, 04/02, page 178 of 1064
Table 7.5
Logic Operation Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
AND
Rm,Rn
Rn & Rm
Rn
0010nnnnmmmm1001
--
--
AND
#imm,R0
R0 & imm
R0
11001001iiiiiiii
--
--
AND.B
#imm,@(R0,GBR)
(R0 + GBR) & imm
(R0 +
GBR)
11001101iiiiiiii
--
--
NOT
Rm,Rn
~Rm
Rn
0110nnnnmmmm0111
--
--
OR
Rm,Rn
Rn | Rm
Rn
0010nnnnmmmm1011
--
--
OR
#imm,R0
R0 | imm
R0
11001011iiiiiiii
--
--
OR.B
#imm,@(R0,GBR)
(R0 + GBR) | imm
(R0 +
GBR)
11001111iiiiiiii
--
TAS.B
@Rn
When (Rn) = 0, 1
T
Otherwise, 0
T
In both cases, 1
MSB of (Rn)
0100nnnn00011011
--
Test result
TST
Rm,Rn
Rn & Rm; when result = 0,
1
T
Otherwise, 0
T
0010nnnnmmmm1000
--
Test result
TST
#imm,R0
R0 & imm; when result = 0,
1
T
Otherwise, 0
T
11001000iiiiiiii
--
Test result
TST.B
#imm,@(R0,GBR)
(R0 + GBR) & imm; when result
= 0, 1
T
Otherwise, 0
T
11001100iiiiiiii
--
Test result
XOR
Rm,Rn
Rn
Rm
Rn
0010nnnnmmmm1010
--
--
XOR
#imm,R0
R0
imm
R0
11001010iiiiiiii
--
--
XOR.B #imm,@(R0,GBR)
(R0 + GBR)
imm
(R0 +
GBR)
11001110iiiiiiii
--
--
Rev. 3.0, 04/02, page 179 of 1064
Table 7.6
Shift Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
ROTL
Rn
T
Rn
MSB
0100nnnn00000100
--
MSB
ROTR
Rn
LSB
Rn
T
0100nnnn00000101
--
LSB
ROTCL
Rn
T
Rn
T
0100nnnn00100100
--
MSB
ROTCR
Rn
T
Rn
T
0100nnnn00100101
--
LSB
SHAD
Rm,Rn
When Rn
0, Rn << Rm
Rn
When Rn < 0, Rn >> Rm
[MSB
Rn]
0100nnnnmmmm1100
--
--
SHAL
Rn
T
Rn
0
0100nnnn00100000
--
MSB
SHAR
Rn
MSB
Rn
T
0100nnnn00100001
--
LSB
SHLD
Rm,Rn
When Rn
0, Rn << Rm
Rn
When Rn < 0, Rn >> Rm
[0
Rn]
0100nnnnmmmm1101
--
--
SHLL
Rn
T
Rn
0
0100nnnn00000000
--
MSB
SHLR
Rn
0
Rn
T
0100nnnn00000001
--
LSB
SHLL2
Rn
Rn << 2
Rn
0100nnnn00001000
--
--
SHLR2
Rn
Rn >> 2
Rn
0100nnnn00001001
--
--
SHLL8
Rn
Rn << 8
Rn
0100nnnn00011000
--
--
SHLR8
Rn
Rn >> 8
Rn
0100nnnn00011001
--
--
SHLL16
Rn
Rn << 16
Rn
0100nnnn00101000
--
--
SHLR16
Rn
Rn >> 16
Rn
0100nnnn00101001
--
--
Rev. 3.0, 04/02, page 180 of 1064
Table 7.7
Branch Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
BF
label
When T = 0, disp
2 + PC +
4
PC
When T = 1, nop
10001011dddddddd
--
--
BF/S
label
Delayed branch; when T = 0,
disp
2 + PC + 4
PC
When T = 1, nop
10001111dddddddd
--
--
BT
label
When T = 1, disp
2 + PC +
4
PC
When T = 0, nop
10001001dddddddd
--
--
BT/S
label
Delayed branch; when T = 1,
disp
2 + PC + 4
PC
When T = 0, nop
10001101dddddddd
--
--
BRA
label
Delayed branch, disp
2 +
PC + 4
PC
1010dddddddddddd
--
--
BRAF
Rn
Rn + PC + 4
PC
0000nnnn00100011
--
--
BSR
label
Delayed branch, PC + 4
PR,
disp
2 + PC + 4
PC
1011dddddddddddd
--
--
BSRF
Rn
Delayed branch, PC + 4
PR,
Rn + PC + 4
PC
0000nnnn00000011
--
--
JMP
@Rn
Delayed branch, Rn
PC
0100nnnn00101011
--
--
JSR
@Rn
Delayed branch, PC + 4
PR,
Rn
PC
0100nnnn00001011
--
--
RTS
Delayed branch, PR
PC
0000000000001011
--
--
Rev. 3.0, 04/02, page 181 of 1064
Table 7.8
System Control Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
CLRMAC
0
MACH, MACL
0000000000101000
--
--
CLRS
0
S
0000000001001000
--
--
CLRT
0
T
0000000000001000
--
0
LDC
Rm,SR
Rm
SR
0100mmmm00001110
Privileged
LSB
LDC
Rm,GBR
Rm
GBR
0100mmmm00011110
--
--
LDC
Rm,VBR
Rm
VBR
0100mmmm00101110
Privileged
--
LDC
Rm,SSR
Rm
SSR
0100mmmm00111110
Privileged
--
LDC
Rm,SPC
Rm
SPC
0100mmmm01001110
Privileged
--
LDC
Rm,DBR
Rm
DBR
0100mmmm11111010
Privileged
--
LDC
Rm,Rn_BANK
Rm
Rn_BANK (n = 0 to 7)
0100mmmm1nnn1110
Privileged
--
LDC.L
@Rm+,SR
(Rm)
SR, Rm + 4
Rm
0100mmmm00000111
Privileged
LSB
LDC.L
@Rm+,GBR
(Rm)
GBR, Rm + 4
Rm
0100mmmm00010111
--
--
LDC.L
@Rm+,VBR
(Rm)
VBR, Rm + 4
Rm
0100mmmm00100111
Privileged
--
LDC.L
@Rm+,SSR
(Rm)
SSR, Rm + 4
Rm
0100mmmm00110111
Privileged
--
LDC.L
@Rm+,SPC
(Rm)
SPC, Rm + 4
Rm
0100mmmm01000111
Privileged
--
LDC.L
@Rm+,DBR
(Rm)
DBR, Rm + 4
Rm
0100mmmm11110110
Privileged
--
LDC.L
@Rm+,Rn_BANK
(Rm)
Rn_BANK,
Rm + 4
Rm
0100mmmm1nnn0111
Privileged
--
LDS
Rm,MACH
Rm
MACH
0100mmmm00001010
--
--
LDS
Rm,MACL
Rm
MACL
0100mmmm00011010
--
--
LDS
Rm,PR
Rm
PR
0100mmmm00101010
--
--
LDS.L
@Rm+,MACH
(Rm)
MACH, Rm + 4
Rm
0100mmmm00000110
--
--
LDS.L
@Rm+,MACL
(Rm)
MACL, Rm + 4
Rm
0100mmmm00010110
--
--
LDS.L
@Rm+,PR
(Rm)
PR, Rm + 4
Rm
0100mmmm00100110
--
--
LDTLB
PTEH/PTEL
TLB
0000000000111000
Privileged
--
MOVCA.L R0,@Rn
R0
(Rn) (without fetching
cache block)
0000nnnn11000011
--
--
NOP
No operation
0000000000001001
--
--
OCBI
@Rn
Invalidates operand cache block
0000nnnn10010011
--
--
OCBP
@Rn
Writes back and invalidates
operand cache block
0000nnnn10100011
--
--
OCBWB
@Rn
Writes back operand cache
block
0000nnnn10110011
--
--
PREF
@Rn
(Rn)
operand cache
0000nnnn10000011
--
--
RTE
Delayed branch, SSR/SPC
SR/PC
0000000000101011
Privileged
--
Rev. 3.0, 04/02, page 182 of 1064
Table 7.8
System Control Instructions (cont)
Instruction
Operation
Instruction Code
Privileged
T Bit
SETS
1
S
0000000001011000
--
--
SETT
1
T
0000000000011000
--
1
SLEEP
Sleep or standby
0000000000011011
Privileged
--
STC
SR,Rn
SR
Rn
0000nnnn00000010
Privileged
--
STC
GBR,Rn
GBR
Rn
0000nnnn00010010
--
--
STC
VBR,Rn
VBR
Rn
0000nnnn00100010
Privileged
--
STC
SSR,Rn
SSR
Rn
0000nnnn00110010
Privileged
--
STC
SPC,Rn
SPC
Rn
0000nnnn01000010
Privileged
--
STC
SGR,Rn
SGR
Rn
0000nnnn00111010
Privileged
--
STC
DBR,Rn
DBR
Rn
0000nnnn11111010
Privileged
--
STC
Rm_BANK,Rn
Rm_BANK
Rn (m = 0 to 7)
0000nnnn1mmm0010
Privileged
--
STC.L
SR,@-Rn
Rn 4
Rn, SR
(Rn)
0100nnnn00000011
Privileged
--
STC.L
GBR,@-Rn
Rn 4
Rn, GBR
(Rn)
0100nnnn00010011
--
--
STC.L
VBR,@-Rn
Rn 4
Rn, VBR
(Rn)
0100nnnn00100011
Privileged
--
STC.L
SSR,@-Rn
Rn 4
Rn, SSR
(Rn)
0100nnnn00110011
Privileged
--
STC.L
SPC,@-Rn
Rn 4
Rn, SPC
(Rn)
0100nnnn01000011
Privileged
--
STC.L
SGR,@-Rn
Rn 4
Rn, SGR
(Rn)
0100nnnn00110010
Privileged
--
STC.L
DBR,@-Rn
Rn 4
Rn, DBR
(Rn)
0100nnnn11110010
Privileged
--
STC.L
Rm_BANK,@-Rn
Rn 4
Rn,
Rm_BANK
(Rn) (m = 0 to 7)
0100nnnn1mmm0011
Privileged
--
STS
MACH,Rn
MACH
Rn
0000nnnn00001010
--
--
STS
MACL,Rn
MACL
Rn
0000nnnn00011010
--
--
STS
PR,Rn
PR
Rn
0000nnnn00101010
--
--
STS.L
MACH,@-Rn
Rn 4
Rn, MACH
(Rn)
0100nnnn00000010
--
--
STS.L
MACL,@-Rn
Rn 4
Rn, MACL
(Rn)
0100nnnn00010010
--
--
STS.L
PR,@-Rn
Rn 4
Rn, PR
(Rn)
0100nnnn00100010
--
--
TRAPA
#imm
PC + 2
SPC, SR
SSR,
#imm << 2
TRA,
H'160
EXPEVT,
VBR + H'0100
PC
11000011iiiiiiii
--
--
Rev. 3.0, 04/02, page 183 of 1064
Table 7.9
Floating-Point Single-Precision Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
FLDI0
FRn
H'00000000
FRn
1111nnnn10001101
--
--
FLDI1
FRn
H'3F800000
FRn
1111nnnn10011101
--
--
FMOV
FRm,FRn
FRm
FRn
1111nnnnmmmm1100
--
--
FMOV.S
@Rm,FRn
(Rm)
FRn
1111nnnnmmmm1000
--
--
FMOV.S
@(R0,Rm),FRn
(R0 + Rm)
FRn
1111nnnnmmmm0110
--
--
FMOV.S
@Rm+,FRn
(Rm)
FRn, Rm + 4
Rm
1111nnnnmmmm1001
--
--
FMOV.S
FRm,@Rn
FRm
(Rn)
1111nnnnmmmm1010
--
--
FMOV.S
FRm,@-Rn
Rn-4
Rn, FRm
(Rn)
1111nnnnmmmm1011
--
--
FMOV.S
FRm,@(R0,Rn)
FRm
(R0 + Rn)
1111nnnnmmmm0111
--
--
FMOV
DRm,DRn
DRm
DRn
1111nnn0mmm01100
--
--
FMOV
@Rm,DRn
(Rm)
DRn
1111nnn0mmmm1000
--
--
FMOV
@(R0,Rm),DRn
(R0 + Rm)
DRn
1111nnn0mmmm0110
--
--
FMOV
@Rm+,DRn
(Rm)
DRn, Rm + 8
Rm
1111nnn0mmmm1001
--
--
FMOV
DRm,@Rn
DRm
(Rn)
1111nnnnmmm01010
--
--
FMOV
DRm,@-Rn
Rn-8
Rn, DRm
(Rn)
1111nnnnmmm01011
--
--
FMOV
DRm,@(R0,Rn)
DRm
(R0 + Rn)
1111nnnnmmm00111
--
--
FLDS
FRm,FPUL
FRm
FPUL
1111mmmm00011101
--
--
FSTS
FPUL,FRn
FPUL
FRn
1111nnnn00001101
--
--
FABS
FRn
FRn & H'7FFF FFFF
FRn
1111nnnn01011101
--
--
FADD
FRm,FRn
FRn + FRm
FRn
1111nnnnmmmm0000
--
--
FCMP/EQ
FRm,FRn
When FRn = FRm, 1
T
Otherwise, 0
T
1111nnnnmmmm0100
--
Comparison
result
FCMP/GT
FRm,FRn
When FRn > FRm, 1
T
Otherwise, 0
T
1111nnnnmmmm0101
--
Comparison
result
FDIV
FRm,FRn
FRn/FRm
FRn
1111nnnnmmmm0011
--
--
FLOAT
FPUL,FRn
(float) FPUL
FRn
1111nnnn00101101
--
--
FMAC
FR0,FRm,FRn
FR0*FRm + FRn
FRn
1111nnnnmmmm1110
--
--
FMUL
FRm,FRn
FRn*FRm
FRn
1111nnnnmmmm0010
--
--
FNEG
FRn
FRn
H'80000000
FRn
1111nnnn01001101
--
--
FSQRT
FRn
FRn
FRn
1111nnnn01101101
--
--
FSUB
FRm,FRn
FRn FRm
FRn
1111nnnnmmmm0001
--
--
FTRC
FRm,FPUL
(long) FRm
FPUL
1111mmmm00111101
--
--
Rev. 3.0, 04/02, page 184 of 1064
Table 7.10
Floating-Point Double-Precision Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
FABS
DRn
DRn & H'7FFF FFFF FFFF
FFFF
DRn
1111nnn001011101
--
--
FADD
DRm,DRn
DRn + DRm
DRn
1111nnn0mmm00000
--
--
FCMP/EQ
DRm,DRn
When DRn = DRm, 1
T
Otherwise, 0
T
1111nnn0mmm00100
--
Comparison
result
FCMP/GT
DRm,DRn
When DRn > DRm, 1
T
Otherwise, 0
T
1111nnn0mmm00101
--
Comparison
result
FDIV
DRm,DRn
DRn /DRm
DRn
1111nnn0mmm00011
--
--
FCNVDS
DRm,FPUL
double_to_ float[DRm]
FPUL
1111mmm010111101
--
--
FCNVSD
FPUL,DRn
float_to_ double [FPUL]
DRn
1111nnn010101101
--
--
FLOAT
FPUL,DRn
(float)FPUL
DRn
1111nnn000101101
--
--
FMUL
DRm,DRn
DRn *DRm
DRn
1111nnn0mmm00010
--
--
FNEG
DRn
DRn ^ H'8000 0000 0000 0000
DRn
1111nnn001001101
--
--
FSQRT
DRn
DRn
DRn
1111nnn001101101
--
--
FSUB
DRm,DRn
DRn DRm
DRn
1111nnn0mmm00001
--
--
FTRC
DRm,FPUL
(long) DRm
FPUL
1111mmm000111101
--
--
Table 7.11
Floating-Point Control Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
LDS
Rm,FPSCR
Rm
FPSCR
0100mmmm01101010
--
--
LDS
Rm,FPUL
Rm
FPUL
0100mmmm01011010
--
--
LDS.L
@Rm+,FPSCR
(Rm)
FPSCR, Rm+4
Rm
0100mmmm01100110
--
--
LDS.L
@Rm+,FPUL
(Rm)
FPUL, Rm+4
Rm
0100mmmm01010110
--
--
STS
FPSCR,Rn
FPSCR
Rn
0000nnnn01101010
--
--
STS
FPUL,Rn
FPUL
Rn
0000nnnn01011010
--
--
STS.L
FPSCR,@-Rn
Rn 4
Rn, FPSCR
(Rn)
0100nnnn01100010
--
--
STS.L
FPUL,@-Rn
Rn 4
Rn, FPUL
(Rn)
0100nnnn01010010
--
--
Rev. 3.0, 04/02, page 185 of 1064
Table 7.12
Floating-Point Graphics Acceleration Instructions
Instruction
Operation
Instruction Code
Privileged
T Bit
FMOV
DRm,XDn
DRm
XDn
1111nnn1mmm01100
--
--
FMOV
XDm,DRn
XDm
DRn
1111nnn0mmm11100
--
--
FMOV
XDm,XDn
XDm
XDn
1111nnn1mmm11100
--
--
FMOV
@Rm,XDn
(Rm)
XDn
1111nnn1mmmm1000
--
--
FMOV
@Rm+,XDn
(Rm)
XDn, Rm + 8
Rm
1111nnn1mmmm1001
--
--
FMOV
@(R0,Rm),XDn
(R0 + Rm)
XDn
1111nnn1mmmm0110
--
--
FMOV
XDm,@Rn
XDm
(Rn)
1111nnnnmmm11010
--
--
FMOV
XDm,@-Rn
Rn 8
Rn, XDm
(Rn)
1111nnnnmmm11011
--
--
FMOV
XDm,@(R0,Rn)
XDm
(R0+Rn)
1111nnnnmmm10111
--
--
FIPR
FVm,FVn
inner_product [FVm, FVn]
FR[n+3]
1111nnmm11101101
--
--
FTRV
XMTRX,FVn
transform_vector [XMTRX, FVn]
FVn
1111nn0111111101
--
--
FRCHG
~FPSCR.FR
SPFCR.FR
1111101111111101
--
--
FSCHG
~FPSCR.SZ
SPFCR.SZ
1111001111111101
--
--
Rev. 3.0, 04/02, page 186 of 1064
Rev. 3.0, 04/02, page 187 of 1064
Section 8 Pipelining
The SH7751 Series is a 2-ILP (instruction-level-parallelism) superscalar pipelining
microprocessor. Instruction execution is pipelined, and two instructions can be executed in
parallel. The execution cycles depend on the implementation of a processor. Definitions in this
section may not be applicable to SH-4 Series models other than the SH7751 Series.
8.1
Pipelines
Figure 8.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction
fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA),
and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 8.2
shows the instruction execution patterns.
Rev. 3.0, 04/02, page 188 of 1064
1. General Pipeline
Instruction fetch
Instruction
decode
Issue
Register read
Destination address calculation
for PC-relative branch
Non-memory
data access
Write-back
I
D
EX
Operation
NA
S
2. General Load/Store Pipeline
Instruction fetch
Instruction
decode
Issue
Register read
Memory
data access
Write-back
I
D
EX
Address
calculation
MA
S
3. Special Pipeline
Instruction fetch
Instruction
decode
Issue
Register read
Non-memory
data access
Write-back
I
D
SX
Operation
NA
S
4. Special Load/Store Pipeline
Instruction fetch
Instruction
decode
Issue
Register read
Memory
data access
Write-back
I
D
SX
Address
calculation
MA
S
5. Floating-Point Pipeline
Instruction fetch Instruction
decode
Issue
Register read
Computation 2
Computation 3
Write-back
I
D
F1
Computation 1
F2
FS
6. Floating-Point Extended Pipeline
Instruction fetch
Instruction
decode
Issue
Register read
Computation 1
Computation 3
Write-back
I
D
F0
Computation 0
F1
F2
FS
Computation 2
F3
Computation: Takes several cycles
7. FDIV/FSQRT Pipeline
Figure 8.1 Basic Pipelines
Rev. 3.0, 04/02, page 189 of 1064
1. 1-step operation: 1 issue cycle
EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*,
DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#,
ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT,
LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS,
single-/double-precision FABS/FNEG
I
D
EX
NA
S
2. Load/store: 1 issue cycle
MOV.[BWL], FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR
I
D
EX
MA
S
3. GBR-based load/store: 1 issue cycle
MOV.[BWL]@(d,GBR)
I
D
SX
MA
S
4. JMP, RTS, BRAF: 2 issue cycles
I
D
EX
NA
S
D
EX
NA
S
5. TST.B: 3 issue cycles
I
D
SX
MA
S
D
SX
NA
S
D
SX
NA
S
6. AND.B, OR.B, XOR.B: 4 issue cycles
I
D
SX
MA
S
D
SX
NA
S
D
SX
NA
S
D
SX
MA
S
7. TAS.B: 5 issue cycles
I
D
EX
MA
S
D
EX
MA
S
D
EX
NA
S
D
EX
NA
S
D
EX
MA
S
8. RTE: 5 issue cycles
I
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
9. SLEEP: 4 issue cycles
I
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
Figure 8.2 Instruction Execution Patterns
Rev. 3.0, 04/02, page 190 of 1064
10. OCBI: 1 issue cycle
I
D
EX
MA
S
MA
11. OCBP, OCBWB: 1 issue cycle
I
D
EX
MA
S
MA
MA
MA
MA
12. MOVCA.L: 1 issue cycle
I
D
EX
MA
S
MA
MA
MA
MA
MA
MA
13. TRAPA: 7 issue cycles
I
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
D
EX
NA
S
14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle
I
D
EX
NA
S
SX
SX
15. LDC to GBR: 3 issue cycles
I
D
EX
NA
S
D
D
SX
SX
16. LDC to SR: 4 issue cycles
I
D
EX
NA
S
D
D
D
SX
SX
SX
I
D
EX
MA
S
17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle
SX
SX
18. LDC.L to GBR: 3 issue cycles
I
D
EX
MA
S
D
D
SX
SX
Figure 8.2 Instruction Execution Patterns (cont)
Rev. 3.0, 04/02, page 191 of 1064
19. LDC.L to SR: 4 issue cycles
I
D
EX
MA
S
D
D
D
SX
SX
SX
20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
I
D
SX
NA
S
D
SX
NA
S
21. STC.L from SGR: 3 issue cycles
I
D
SX
NA
S
D
SX
NA
S
D
SX
NA
S
22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
I
D
SX
NA
S
D
SX
MA
S
23. STC.L from SGR: 3 issue cycles
I
D
SX
NA
S
D
SX
NA
S
D
SX
MA
S
24. LDS to PR, JSR, BSRF: 2 issue cycles
I
D
EX
NA
S
D
SX
SX
25. LDS.L to PR: 2 issue cycles
I
D
EX
MA
S
D
SX
SX
26. STS from PR: 2 issue cycles
I
D
SX
NA
S
D
SX
NA
S
27. STS.L from PR: 2 issue cycles
I
D
SX
NA
S
D
SX
MA
S
28. CLRMAC, LDS to MACH/L: 1 issue cycle
I
D
EX
NA
S
F1
F1
F2
FS
29. LDS.L to MACH/L: 1 issue cycle
I
D
EX
MA
S
F1
F1
F2
FS
30. STS from MACH/L: 1 issue cycle
I
D
EX
NA
S
Figure 8.2 Instruction Execution Patterns (cont)
Rev. 3.0, 04/02, page 192 of 1064
31. STS.L from MACH/L: 1 issue cycle
I
D
EX
MA
S
32. LDS to FPSCR: 1 issue cycle
I
D
EX
NA
S
F1
F1
F1
F1
F1
F1
33. LDS.L to FPSCR: 1 issue cycle
I
D
EX
MA
S
34. Fixed-point multiplication: 2 issue cycles
DMULS.L, DMULU.L, MUL.L, MULS.W, MULU.W
I
D
EX
NA
S
(CPU)
D
EX
NA
S
f1
(FPU)
f1
f1
f1
F2
FS
35. MAC.W, MAC.L: 2 issue cycles
I
D
EX
MA
S
(CPU)
D
EX
MA
S
f1
(FPU)
f1
f1
f1
F2
FS
36. Single-precision floating-point computation: 1 issue cycle
FCMP/EQ,FCMP/GT, FADD,FLOAT,FMAC,FMUL,FSUB,FTRC,FRCHG,FSCHG
I
D
F1
F2
FS
37. Single-precision FDIV/SQRT: 1 issue cycle
I
D
F1
F2
FS
F3
F1
F2
FS
38. Double-precision floating-point computation 1: 1 issue cycle
FCNVDS, FCNVSD, FLOAT, FTRC
I
D
F1
F2
FS
d
F1
F2
FS
39. Double-precision floating-point computation 2: 1 issue cycle
FADD, FMUL, FSUB
I
D
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
F1
F2
FS
Figure 8.2 Instruction Execution Patterns (cont)
Rev. 3.0, 04/02, page 193 of 1064
I
D
F1
F2
FS
D
F1
F2
FS
40. Double-precision FCMP: 2 issue cycles
FCMP/EQ,FCMP/GT
I
D
F1
F2
FS
F3
F1
F2
FS
41. Double-precision FDIV/SQRT: 1 issue cycle
FDIV, FSQRT
F1
F2
d
F1
F2
FS
F1
F2
FS
42. FIPR: 1 issue cycle
I
D
F0
F1
F2
FS
43. FTRV: 1 issue cycle
F1
F2
FS
D
F0
I
F1
F2
FS
d
F0
F1
F2
FS
d
F0
F1
F2
FS
d
F0
Notes:
??
: Locks D-stage
: Register read only
: Locks, but no operation is executed.
: Can overlap another f1, but not another F1.
d
D
??
f1
: Cannot overlap a stage of the same kind, except when two instructions are
executed in parallel.
Figure 8.2 Instruction Execution Patterns (cont)
Rev. 3.0, 04/02, page 194 of 1064
8.2
Parallel-Executability
Instructions are categorized into six groups according to the internal function blocks used, as
shown in table 8.1. Table 8.2 shows the parallel-executability of pairs of instructions in terms of
groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel.
Table 8.1
Instruction Groups
1. MT Group
CLRT
CMP/HI
Rm,Rn
MOV
Rm,Rn
CMP/EQ
#imm,R0
CMP/HS
Rm,Rn
NOP
CMP/EQ
Rm,Rn
CMP/PL
Rn
SETT
CMP/GE
Rm,Rn
CMP/PZ
Rn
TST
#imm,R0
CMP/GT
Rm,Rn
CMP/STR
Rm,Rn
TST
Rm,Rn
2. EX Group
ADD
#imm,Rn
MOVT
Rn
SHLL2
Rn
ADD
Rm,Rn
NEG
Rm,Rn
SHLL8
Rn
ADDC
Rm,Rn
NEGC
Rm,Rn
SHLR
Rn
ADDV
Rm,Rn
NOT
Rm,Rn
SHLR16
Rn
AND
#imm,R0
OR
#imm,R0
SHLR2
Rn
AND
Rm,Rn
OR
Rm,Rn
SHLR8
Rn
DIV0S
Rm,Rn
ROTCL
Rn
SUB
Rm,Rn
DIV0U
ROTCR
Rn
SUBC
Rm,Rn
DIV1
Rm,Rn
ROTL
Rn
SUBV
Rm,Rn
DT
Rn
ROTR
Rn
SWAP.B
Rm,Rn
EXTS.B
Rm,Rn
SHAD
Rm,Rn
SWAP.W
Rm,Rn
EXTS.W
Rm,Rn
SHAL
Rn
XOR
#imm,R0
EXTU.B
Rm,Rn
SHAR
Rn
XOR
Rm,Rn
EXTU.W
Rm,Rn
SHLD
Rm,Rn
XTRCT
Rm,Rn
MOV
#imm,Rn
SHLL
Rn
MOVA
@(disp,PC),R0 SHLL16
Rn
3. BR Group
BF
disp
BRA
disp
BT
disp
BF/S
disp
BSR
disp
BT/S
disp
Rev. 3.0, 04/02, page 195 of 1064
Table 8.1
Instruction Groups (cont)
4. LS Group
FABS
DRn
FMOV.S
@Rm+,FRn
MOV.L
R0,@(disp,GBR)
FABS
FRn
FMOV.S
FRm,@(R0,Rn)
MOV.L
Rm,@(disp,Rn)
FLDI0
FRn
FMOV.S
FRm,@-Rn
MOV.L
Rm,@(R0,Rn)
FLDI1
FRn
FMOV.S
FRm,@Rn
MOV.L
Rm,@-Rn
FLDS
FRm,FPUL
FNEG
DRn
MOV.L
Rm,@Rn
FMOV
@(R0,Rm),DRn
FNEG
FRn
MOV.W
@(disp,GBR),R0
FMOV
@(R0,Rm),XDn
FSTS
FPUL,FRn
MOV.W
@(disp,PC),Rn
FMOV
@Rm,DRn
LDS
Rm,FPUL
MOV.W
@(disp,Rm),R0
FMOV
@Rm,XDn
MOV.B
@(disp,GBR),R0 MOV.W
@(R0,Rm),Rn
FMOV
@Rm+,DRn
MOV.B
@(disp,Rm),R0
MOV.W
@Rm,Rn
FMOV
@Rm+,XDn
MOV.B
@(R0,Rm),Rn
MOV.W
@Rm+,Rn
FMOV
DRm,@(R0,Rn)
MOV.B
@Rm,Rn
MOV.W
R0,@(disp,GBR)
FMOV
DRm,@-Rn
MOV.B
@Rm+,Rn
MOV.W
R0,@(disp,Rn)
FMOV
DRm,@Rn
MOV.B
R0,@(disp,GBR) MOV.W
Rm,@(R0,Rn)
FMOV
DRm,DRn
MOV.B
R0,@(disp,Rn)
MOV.W
Rm,@-Rn
FMOV
DRm,XDn
MOV.B
Rm,@(R0,Rn)
MOV.W
Rm,@Rn
FMOV
FRm,FRn
MOV.B
Rm,@-Rn
MOVCA.L
R0,@Rn
FMOV
XDm,@(R0,Rn)
MOV.B
Rm,@Rn
OCBI
@Rn
FMOV
XDm,@-Rn
MOV.L
@(disp,GBR),R0 OCBP
@Rn
FMOV
XDm,@Rn
MOV.L
@(disp,PC),Rn
OCBWB
@Rn
FMOV
XDm,DRn
MOV.L
@(disp,Rm),Rn
PREF
@Rn
FMOV
XDm,XDn
MOV.L
@(R0,Rm),Rn
STS
FPUL,Rn
FMOV.S
@(R0,Rm),FRn
MOV.L
@Rm,Rn
FMOV.S
@Rm,FRn
MOV.L
@Rm+,Rn
Rev. 3.0, 04/02, page 196 of 1064
Table 8.1
Instruction Groups (cont)
5. FE Group
FADD
DRm,DRn
FIPR
FVm,FVn
FSQRT
DRn
FADD
FRm,FRn
FLOAT
FPUL,DRn
FSQRT
FRn
FCMP/EQ
FRm,FRn
FLOAT
FPUL,FRn
FSUB
DRm,DRn
FCMP/GT
FRm,FRn
FMAC
FR0,FRm,FRn FSUB
FRm,FRn
FCNVDS
DRm,FPUL
FMUL
DRm,DRn
FTRC
DRm,FPUL
FCNVSD
FPUL,DRn
FMUL
FRm,FRn
FTRC
FRm,FPUL
FDIV
DRm,DRn
FRCHG
FTRV
XMTRX,FVn
FDIV
FRm,FRn
FSCHG
Rev. 3.0, 04/02, page 197 of 1064
Table 8.1
Instruction Groups (cont)
6. CO Group
AND.B
#imm,@(R0,GBR) LDS
Rm,FPSCR
STC
SR,Rn
BRAF
Rm
LDS
Rm,MACH
STC
SSR,Rn
BSRF
Rm
LDS
Rm,MACL
STC
VBR,Rn
CLRMAC
LDS
Rm,PR
STC.L
DBR,@-Rn
CLRS
LDS.L
@Rm+,FPSCR
STC.L
GBR,@-Rn
DMULS.L
Rm,Rn
LDS.L
@Rm+,FPUL
STC.L
Rp_BANK,@-Rn
DMULU.L
Rm,Rn
LDS.L
@Rm+,MACH
STC.L
SGR,@-Rn
FCMP/EQ
DRm,DRn
LDS.L
@Rm+,MACL
STC.L
SPC,@-Rn
FCMP/GT
DRm,DRn
LDS.L
@Rm+,PR
STC.L
SR,@-Rn
JMP
@Rn
LDTLB
STC.L
SSR,@-Rn
JSR
@Rn
MAC.L
@Rm+,@Rn+
STC.L
VBR,@-Rn
LDC
Rm,DBR
MAC.W
@Rm+,@Rn+
STS
FPSCR,Rn
LDC
Rm,GBR
MUL.L
Rm,Rn
STS
MACH,Rn
LDC
Rm,Rp_BANK
MULS.W
Rm,Rn
STS
MACL,Rn
LDC
Rm,SPC
MULU.W
Rm,Rn
STS
PR,Rn
LDC
Rm,SR
OR.B
#imm,@(R0,GBR) STS.L
FPSCR,@-Rn
LDC
Rm,SSR
RTE
STS.L
FPUL,@-Rn
LDC
Rm,VBR
RTS
STS.L
MACH,@-Rn
LDC.L
@Rm+,DBR
SETS
STS.L
MACL,@-Rn
LDC.L
@Rm+,GBR
SLEEP
STS.L
PR,@-Rn
LDC.L
@Rm+,Rp_BANK STC
DBR,Rn
TAS.B
@Rn
LDC.L
@Rm+,SPC
STC
GBR,Rn
TRAPA
#imm
LDC.L
@Rm+,SR
STC
Rp_BANK,Rn
TST.B
#imm,@(R0,GBR)
LDC.L
@Rm+,SSR
STC
SGR,Rn
XOR.B
#imm,@(R0,GBR)
LDC.L
@Rm+,VBR
STC
SPC,Rn
Rev. 3.0, 04/02, page 198 of 1064
Table 8.2
Parallel-Executability
2nd Instruction
MT
EX
BR
LS
FE
CO
MT
O
O
O
O
O
X
EX
O
X
O
O
O
X
BR
O
O
X
O
O
X
LS
O
O
O
X
O
X
FE
O
O
O
O
X
X
1st
Instruction
CO
X
X
X
X
X
X
O: Can be executed in parallel
X: Cannot be executed in parallel
8.3
Execution Cycles and Pipeline Stalling
There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware
unit operates on one of these clocks, as follows:
I-clock: CPU, FPU, MMU, caches
B-clock: External bus controller
P-clock: Peripheral units
The frequency ratios of the three clocks are determined with the frequency control register
(FRQCR). In this section, machine cycles are based on the I-clock unless otherwise specified. For
details of FRQCR, see section 10, Clock Oscillation Circuits.
Instruction execution cycles are summarized in table 8.3. Penalty cycles due to a pipeline stall or
freeze are not considered in this table.
Issue rate: Interval between the issue of an instruction and that of the next instruction
Latency: Interval between the issue of an instruction and the generation of its result
(completion)
Instruction execution pattern (see figure 8.2)
Lock stage: Locked pipeline stages(see table 8.3)
Lock start: Interval between the issue of an instruction and the start of locking (see table 8.3)
Lock cycle: Lock time (see table 8.3)
Rev. 3.0, 04/02, page 199 of 1064
The instruction execution sequence is expressed as a combination of the execution patterns shown
in figure 8.2. One instruction is separated from the next by the number of machine cycles for its
issue rate. Normally, execution, data access, and write-back stages cannot be overlapped onto the
same stages of another instruction; the only exception is when two instructions are executed in
parallel under parallel-executability conditions. Refer to (a) through (d) in figure 8.3 for some
simple examples.
Latency is the interval between issue and completion of an instruction, and is also the interval
between the execution of two instructions with an interdependent relationship. When there is
interdependency between two instructions fetched simultaneously, the latter of the two is stalled
for the following number of cycles:
(Latency) cycles when there is flow dependency (read-after-write)
(Latency - 1) or (latency - 2) cycles when there is output dependency (write-after-write)
Single/double-precision FDIV, FSQRT is the preceding instruction (latency 1) cycles
The other FE group except above is the preceding instruction (latency 2) cycles
5 or 2 cycles when there is anti-flow dependency (write-after-read), as in the following cases:
FTRV is the preceding instruction (5 cycles)
A double-precision FADD, FSUB, or FMUL is the preceding instruction (2 cycles)
In the case of flow dependency, latency may be exceptionally increased or decreased, depending
on the combination of sequential instructions (figure 8.3 (e)).
When a floating-point computation is followed by a floating-point register store, the latency of
the floating-point computation may be decreased by 1 cycle.
If there is a load of the shift amount immediately before an SHAD/SHLD instruction, the
latency of the load is increased by 1 cycle.
If an instruction with a latency of less than 2 cycles, including write-back to a floating-point
register, is followed by a double-precision floating-point instruction, FIPR, or FTRV, the
latency of the first instruction is increased to 2 cycles.
The number of cycles in a pipeline stall due to flow dependency will vary depending on the
combination of interdependent instructions or the fetch timing (see figure 8.3. (e)).
Output dependency occurs when the destination operands are the same in a preceding FE group
instruction and a following LS group instruction.
For the stall cycles of an instruction with output dependency, the longest latency to the last write-
back among all the destination operands must be applied instead of "latency" (see figure 8.3 (f)).
A stall due to output dependency with respect to FPSCR, which reflects the result of a floating-
point operation, never occurs. For example, when FADD follows FDIV with no dependency
between floating-point registers, FADD is not stalled even if both instructions update the cause
field of FPSCR.
Rev. 3.0, 04/02, page 200 of 1064
Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL,
FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3
(g).
If an executing instruction locks any resource--i.e. a function block that performs a basic
operation--a following instruction that attempts to use the locked resource is stalled (figure 8.3
(h)). This kind of stall can be compensated by inserting one or more instructions independent of
the locked resource to separate the interfering instructions. For example, when a load instruction
and an ADD instruction that references the loaded value are consecutive, the 2-cycle stall of the
ADD is eliminated by inserting three instructions without dependency. Software performance can
be improved by such instruction scheduling.
Other causes of a stall are as follows.
Instruction TLB miss
Instruction access to external memory (instruction cache miss, etc.)
Data access to external memory (operand cache miss, etc.)
Data access to a memory-mapped control register
During the penalty cycles of an instruction TLB miss or external instruction access, no instruction
is issued, but execution of instructions that have already been issued continues. The penalty for a
data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted
until the arrival of the requested data. The number of penalty cycles for instruction and data
accesses is largely dependent on the user's memory subsystems.
Rev. 3.0, 04/02, page 201 of 1064
(a) Serial execution: non-parallel-executable instructions
ADD
R2,R1
MOV.L @R4,R5
MOV
R1,R2
next
SHAD R0,R1
ADD
R2,R3
next
I
D
EX
NA
S
I
D
EX
NA
S
I
D
...
1 stall cycle
(b) Parallel execution: parallel-executable and no dependency
I
D
EX
NA
S
I
D
EX
MA
S
(c) Issue rate: multi-step instruction
AND.B#1,@(R0,GBR)
I
D
SX
MA
S
D
SX
MA
S
D
SX
NA
S
D
SX
NA
S
I
I
(d) Branch
1 issue cycle
1 issue cycle
4 issue cycles
...
I
D
EX
NA
S
I
D
EX
NA
S
2-cycle latency for I-stage of branch destination
1 stall cycle
I
D
I
D
EX
NA
S
I
D
EX
NA
S
I
D
EX
NA
S
BT/S L_far
ADD R0,R1
SUB R2,R3
BT/S L_far
ADD R0,R1
L_far
I
D
EX
NA
S
I
D
I
D
--
--
--
...
No stall
BT L_skip
ADD #1,R0
L_skip:
...
i
D
E
A
S
4 stall cycles
EX-group SHAD and EX-group ADD
cannot be executed in parallel. Therefore,
SHAD is issued first, and the following
ADD is recombined with the next
instruction.
EX-group ADD and LS-group MOV.L can
be executed in parallel. Overlapping of
stages in the 2nd instruction is possible.
AND.B and MOV are fetched
simultaneously, but MOV is stalled due to
resource locking. After the lock is released,
MOV is refetched together with the next
instruction.
No stall occurs if the branch is not taken.
If the branch is taken, the I-stage of the
branch destination is stalled for the period
of latency. This stall can be covered with a
delay slot instruction which is not parallel-
executable with the branch instruction.
Even if the BT/BF branch is taken, the I-
stage of the branch destination is not
stalled if the displacement is zero.
Figure 8.3 Examples of Pipelined Execution
Rev. 3.0, 04/02, page 202 of 1064
(e) Flow dependency
I
D
EX
NA
S
I
D
EX
NA
S
MOV
R0,R1
ADD R2,R1
ADD
R2,R1
MOV.L @R1,R1
next
I
D
EX
NA
S
I
D
EX
MA
S
i
I
...
...
...
Zero-cycle latency
1-cycle latency
1 stall cycle
MOV.L @R1,R1
ADD
R0,R1
next
I
D
EX
MA
S
I
D
I
EX
NA
S
D
EX
NA
S
2-cycle latency
1 stall cycle
MOV.L @R1,R1
SHAD
R1,R2
next
FADD
FR1,FR2
STS
FPUL,R1
STS
FPSCR,R2
I
D
EX
NA
S
I
4-cycle latency for FPSCR
2 stall cycles
I
D
F1
F2
FS
I
D
EX
MA
S
I
D
I
2-cycle latency
2 stall cycles
EX
NA
S
d
1-cycle increase
I
I
I
D
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
F1
F2
FS
d
F1
F2
FS
EX
NA
S
D
EX
NA
S
D
FADD DR0,DR2
7-cycle latency for lower FR
8-cycle latency for upper FR
FMOV
FR3,FR5
FMOV
FR2,FR4
FLOAT
FPUL,DR0
FMOV.S FR0,@-R15
FR3 write
FR2 write
I
D
F1
F2
FS
d
F1
F2
FS
I
D
EX
MA
S
3-cycle latency for upper/lower FR
FR1 write
FR0 write
FLDI1
FR3
FIPR
FV0,FV4
FMOV
@R1,XD14
FTRV
XMTRX,FV0
I
D
EX
NA
S
I
D
d
F0
F1
F2
FS
Zero-cycle latency
3-cycle increase
3 stall cycles
I
D
EX
MA
S
I
D
d
F0
F1
F2
FS
d
F0
F1
FS
F2
d
F0
F2
F1
FS
d
F1
F0
F2
FS
2-cycle latency
1-cycle increase
3 stall cycles
The following instruction, ADD, is not
stalled when executed after an instruction
with zero-cycle latency, even if there is
dependency.
ADD and MOV.L are not executed in
parallel, since MOV.L references the result
of ADD as its destination address.
Because MOV.L and ADD are not fetched
simultaneously in this example, ADD is
stalled for only 1 cycle even though the
latency of MOV.L is 2 cycles.
Due to the flow dependency between the
load and the SHAD/SHLD shift amount,
the latency of the load is increased to 3
cycles.
Figure 8.3 Examples of Pipelined Execution (cont)
Rev. 3.0, 04/02, page 203 of 1064
I
D
EX
NA
S
I
D
EX
NA
S
D
F1
F2
FS
D
F1
F2
FS
(e) Flow dependency (cont)
I
I
LDS
R0,FPUL
FLOAT FPUL,FR0
LDS
R1,FPUL
FLOAT FPUL,FR1
Effectively 1-cycle latency for consecutive LDS/FLOAT instructions
I
D
EX
NA
S
D
F1
F2
FS
I
D
F1
F2
FS
I
I
D
EX
NA
S
Effectively 1-cycle latency for consecutive
FTRC/STS instructions
FTRC
FR0,FPUL
STS
FPUL,R0
FTRC
FR1,FPUL
STS
FPUL,R1
(f) Output dependency
D
F1
F2
FS
I
I
D
F1
F2
FS
F1
F2
FS
11-cycle latency
10 stall cycles = latency (11) - 1
The registers are written-back
in program order.
D
F1
F2
FS
I
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
F1
F2
FS
EX
NA
S
I
D
7-cycle latency for lower FR
8-cycle latency for upper FR
6 stall cycles = longest latency (8) - 2
FR2 write
FR3 write
D
F1
F2
FS
I
d
F1
F2
FS
d
F1
F2
FS
d
F1
F0
F0
F0
F0
F2
FS
(g) Anti-flow dependency
EX
MA
S
I
D
5 stall cycles
D
F1
F2
FS
I
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
EX
NA
S
I
D
2 stall cycles
d
F1
F2
FS
F1
F2
FS
FSQRT FR4
FMOV
FR0,FR4
FADD
DR0,DR2
FMOV
FR0,FR3
FTRV
XMTRX,FV0
FMOV @R1,XD0
FADD
DR0,DR2
FMOV FR4,FR1
F3
Figure 8.3 Examples of Pipelined Execution (cont)
Rev. 3.0, 04/02, page 204 of 1064
(h) Resource conflict
F1 stage locked for 1 cycle
Latency
1 cycle/issue
1 stall cycle (F1 stage resource conflict)
FDIV
FR6,FR7
FMAC FR0,FR8,FR9
FMAC FR0,FR10,FR11
FMAC FR0,FR12,FR13
FIPR
FV8,FV0
FADD
FR15,FR4
I
D
F1
F0
F2
FS
I
D
F1
F2
FS
1 stall cycle
LDS.L @R15+,PR
I
D
EX
MA
FS
D
SX
SX
SX
NA
S
SX
NA
S
D
I
3 stall cycles
STC
GBR,R2
FADD
DR0,DR2
I
D
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
F1
F2
FS
EX
MA
S
f1
EX
MA
S
D
f1
f1
F2
FS
f1
F2
FS
I
D
5 stall cycles
MAC.W @R1+,@R2+
I
D
EX
MA
S
f1
f1
f1
F2
FS
f1
F2
FS
I
f1
D
EX
MA
S
f1
D
EX
MA
S
f1
F2
FS
f1
F2
FS
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
d
F1
F2
FS
F1
...
I
D
3 stall cycles
1 stall
cycle
2 stall cycles
MAC.W @R1+,@R2+
MAC.W @R1+,@R2+
FADD
DR4,DR6
f1 stage can overlap preceding f1,
but F1 cannot overlap f1.
D
EX
MA
S
D
I
D
F1
F2
FS
I
D
F1
F2
FS
F1
F2
FS
F1
F2
I
D
FS
F3
I
D
F1
F2
FS
#1
#2
#3
..................................................
#10
#11
#8
#9
#12
...
:
Figure 8.3 Examples of Pipelined Execution (cont)
Rev. 3.0, 04/02, page 205 of 1064
Table 8.3
Execution Cycles
Lock
Functional
Category
No.
Instruction
Instruc-
tion
Group
Issue
Rate
Latency
Execu-
tion
Pattern Stage Start
Cycles
1
EXTS.B
Rm,Rn
EX
1
1
#1
--
--
--
2
EXTS.W
Rm,Rn
EX
1
1
#1
--
--
--
3
EXTU.B
Rm,Rn
EX
1
1
#1
--
--
--
4
EXTU.W
Rm,Rn
EX
1
1
#1
--
--
--
5
MOV
Rm,Rn
MT
1
0
#1
--
--
--
6
MOV
#imm,Rn
EX
1
1
#1
--
--
--
7
MOVA
@(disp,PC),R0
EX
1
1
#1
--
--
--
8
MOV.W
@(disp,PC),Rn
LS
1
2
#2
--
--
--
9
MOV.L
@(disp,PC),Rn
LS
1
2
#2
--
--
--
10
MOV.B
@Rm,Rn
LS
1
2
#2
--
--
--
11
MOV.W
@Rm,Rn
LS
1
2
#2
--
--
--
12
MOV.L
@Rm,Rn
LS
1
2
#2
--
--
--
13
MOV.B
@Rm+,Rn
LS
1
1/2
#2
--
--
--
14
MOV.W
@Rm+,Rn
LS
1
1/2
#2
--
--
--
15
MOV.L
@Rm+,Rn
LS
1
1/2
#2
--
--
--
16
MOV.B
@(disp,Rm),R0
LS
1
2
#2
--
--
--
17
MOV.W
@(disp,Rm),R0
LS
1
2
#2
--
--
--
18
MOV.L
@(disp,Rm),Rn
LS
1
2
#2
--
--
--
19
MOV.B
@(R0,Rm),Rn
LS
1
2
#2
--
--
--
20
MOV.W
@(R0,Rm),Rn
LS
1
2
#2
--
--
--
21
MOV.L
@(R0,Rm),Rn
LS
1
2
#2
--
--
--
22
MOV.B
@(disp,GBR),R0
LS
1
2
#3
--
--
--
23
MOV.W
@(disp,GBR),R0
LS
1
2
#3
--
--
--
24
MOV.L
@(disp,GBR),R0
LS
1
2
#3
--
--
--
25
MOV.B
Rm,@Rn
LS
1
1
#2
--
--
--
26
MOV.W
Rm,@Rn
LS
1
1
#2
--
--
--
27
MOV.L
Rm,@Rn
LS
1
1
#2
--
--
--
28
MOV.B
Rm,@-Rn
LS
1
1/1
#2
--
--
--
29
MOV.W
Rm,@-Rn
LS
1
1/1
#2
--
--
--
30
MOV.L
Rm,@-Rn
LS
1
1/1
#2
--
--
--
Data transfer
instructions
31
MOV.B
R0,@(disp,Rn)
LS
1
1
#2
--
--
--
Rev. 3.0, 04/02, page 206 of 1064
Table 8.3
Execution Cycles (cont)
Lock
Functional
Category
No.
Instruction
Instruc-
tion
Group
Issue
Rate
Latency
Execu-
tion
Pattern Stage Start
Cycles
32
MOV.W
R0,@(disp,Rn)
LS
1
1
#2
--
--
--
33
MOV.L
Rm,@(disp,Rn)
LS
1
1
#2
--
--
--
34
MOV.B
Rm,@(R0,Rn)
LS
1
1
#2
--
--
--
35
MOV.W
Rm,@(R0,Rn)
LS
1
1
#2
--
--
--
36
MOV.L
Rm,@(R0,Rn)
LS
1
1
#2
--
--
--
37
MOV.B
R0,@(disp,GBR)
LS
1
1
#3
--
--
--
38
MOV.W
R0,@(disp,GBR)
LS
1
1
#3
--
--
--
39
MOV.L
R0,@(disp,GBR)
LS
1
1
#3
--
--
--
40
MOVCA.L R0,@Rn
LS
1
37
#12
MA
4
37
41
MOVT
Rn
EX
1
1
#1
--
--
--
42
OCBI
@Rn
LS
1
12
#10
MA
4
12
43
OCBP
@Rn
LS
1
15
#11
MA
4
15
44
OCBWB
@Rn
LS
1
15
#11
MA
4
15
45
PREF
@Rn
LS
1
1
#2
--
--
--
46
SWAP.B
Rm,Rn
EX
1
1
#1
--
--
--
47
SWAP.W
Rm,Rn
EX
1
1
#1
--
--
--
Data transfer
instructions
48
XTRCT
Rm,Rn
EX
1
1
#1
--
--
--
49
ADD
Rm,Rn
EX
1
1
#1
--
--
--
50
ADD
#imm,Rn
EX
1
1
#1
--
--
--
51
ADDC
Rm,Rn
EX
1
1
#1
--
--
--
52
ADDV
Rm,Rn
EX
1
1
#1
--
--
--
53
CMP/EQ
#imm,R0
MT
1
1
#1
--
--
--
54
CMP/EQ
Rm,Rn
MT
1
1
#1
--
--
--
55
CMP/GE
Rm,Rn
MT
1
1
#1
--
--
--
56
CMP/GT
Rm,Rn
MT
1
1
#1
--
--
--
57
CMP/HI
Rm,Rn
MT
1
1
#1
--
--
--
58
CMP/HS
Rm,Rn
MT
1
1
#1
--
--
--
59
CMP/PL
Rn
MT
1
1
#1
--
--
--
60
CMP/PZ
Rn
MT
1
1
#1
--
--
--
61
CMP/STR Rm,Rn
MT
1
1
#1
--
--
--
Fixed-point
arithmetic
instructions
62
DIV0S
Rm,Rn
EX
1
1
#1
--
--
--
Rev. 3.0, 04/02, page 207 of 1064
Table 8.3
Execution Cycles (cont)
Lock
Functional
Category
No.
Instruction
Instruc-
tion
Group
Issue
Rate
Latency
Execu-
tion
Pattern Stage Start
Cycles
63
DIV0U
EX
1
1
#1
--
--
--
64
DIV1
Rm,Rn
EX
1
1
#1
--
--
--
65
DMULS.L
Rm,Rn
CO
2
4/4
#34
F1
4
2
66
DMULU.L
Rm,Rn
CO
2
4/4
#34
F1
4
2
67
DT
Rn
EX
1
1
#1
--
--
--
68
MAC.L
@Rm+,@Rn+
CO
2
2/2/4/4
#35
F1
4
2
69
MAC.W
@Rm+,@Rn+
CO
2
2/2/4/4
#35
F1
4
2
70
MUL.L
Rm,Rn
CO
2
4/4
#34
F1
4
2
71
MULS.W
Rm,Rn
CO
2
4/4
#34
F1
4
2
72
MULU.W
Rm,Rn
CO
2
4/4
#34
F1
4
2
73
NEG
Rm,Rn
EX
1
1
#1
--
--
--
74
NEGC
Rm,Rn
EX
1
1
#1
--
--
--
75
SUB
Rm,Rn
EX
1
1
#1
--
--
--
76
SUBC
Rm,Rn
EX
1
1
#1
--
--
--
Fixed-point
arithmetic
instructions
77
SUBV
Rm,Rn
EX
1
1
#1
--
--
--
78
AND
Rm,Rn
EX
1
1
#1
--
--
--
79
AND
#imm,R0
EX
1
1
#1
--
--
--
80
AND.B
#imm,@(R0,GBR) CO
4
4
#6
--
--
--
81
NOT
Rm,Rn
EX
1
1
#1
--
--
--
82
OR
Rm,Rn
EX
1
1
#1
--
--
--
83
OR
#imm,R0
EX
1
1
#1
--
--
--
84
OR.B
#imm,@(R0,GBR) CO
4
4
#6
--
--
--
85
TAS.B
@Rn
CO
5
5
#7
--
--
--
86
TST
Rm,Rn
MT
1
1
#1
--
--
--
87
TST
#imm,R0
MT
1
1
#1
--
--
--
88
TST.B
#imm,@(R0,GBR) CO
3
3
#5
--
--
--
89
XOR
Rm,Rn
EX
1
1
#1
--
--
--
90
XOR
#imm,R0
EX
1
1
#1
--
--
--
Logical
instructions
91
XOR.B
#imm,@(R0,GBR) CO
4
4
#6
--
--
--
Rev. 3.0, 04/02, page 208 of 1064
Table 8.3
Execution Cycles (cont)
Lock
Functional
Category
No.
Instruction
Instruc-
tion
Group
Issue
Rate
Latency
Execu-
tion
Pattern Stage Start
Cycles
92
ROTL
Rn
EX
1
1
#1
--
--
--
93
ROTR
Rn
EX
1
1
#1
--
--
--
94
ROTCL
Rn
EX
1
1
#1
--
--
--
95
ROTCR
Rn
EX
1
1
#1
--
--
--
96
SHAD
Rm,Rn
EX
1
1
#1
--
--
--
97
SHAL
Rn
EX
1
1
#1
--
--
--
98
SHAR
Rn
EX
1
1
#1
--
--
--
99
SHLD
Rm,Rn
EX
1
1
#1
--
--
--
100
SHLL
Rn
EX
1
1
#1
--
--
--
101
SHLL2
Rn
EX
1
1
#1
--
--
--
102
SHLL8
Rn
EX
1
1
#1
--
--
--
103
SHLL16
Rn
EX
1
1
#1
--
--
--
104
SHLR
Rn
EX
1
1
#1
--
--
--
105
SHLR2
Rn
EX
1
1
#1
--
--
--
106
SHLR8
Rn
EX
1
1
#1
--
--
--
Shift
instructions
107
SHLR16
Rn
EX
1
1
#1
--
--
--
108
BF
disp
BR
1
2 (or 1)
#1
--
--
--
109
BF/S
disp
BR
1
2 (or 1)
#1
--
--
--
110
BT
disp
BR
1
2 (or 1)
#1
--
--
--
111
BT/S
disp
BR
1
2 (or 1)
#1
--
--
--
112
BRA
disp
BR
1
2
#1
--
--
--
113
BRAF
Rn
CO
2
3
#4
--
--
--
114
BSR
disp
BR
1
2
#14
SX
3
2
115
BSRF
Rn
CO
2
3
#24
SX
3
2
116
JMP
@Rn
CO
2
3
#4
--
--
--
117
JSR
@Rn
CO
2
3
#24
SX
3
2
Branch
instructions
118
RTS
CO
2
3
#4
--
--
--
Rev. 3.0, 04/02, page 209 of 1064
Table 8.3
Execution Cycles (cont)
Lock
Functional
Category
No.
Instruction
Instruc-
tion
Group
Issue
Rate
Latency
Execu-
tion
Pattern Stage Start
Cycles
119
NOP
MT
1
0
#1
--
--
--
120
CLRMAC
CO
1
3
#28
F1
3
2
121
CLRS
CO
1
1
#1
--
--
--
122
CLRT
MT
1
1
#1
--
--
--
123
SETS
CO
1
1
#1
--
--
--
124
SETT
MT
1
1
#1
--
--
--
125
TRAPA
#imm
CO
7
7
#13
--
--
--
126
RTE
CO
5
5
#8
--
--
--
127
SLEEP
CO
4
4
#9
--
--
--
128
LDTLB
CO
1
1
#2
--
--
--
129
LDC
Rm,DBR
CO
1
3
#14
SX
3
2
130
LDC
Rm,GBR
CO
3
3
#15
SX
3
2
131
LDC
Rm,Rp_BANK
CO
1
3
#14
SX
3
2
132
LDC
Rm,SR
CO
4
4
#16
SX
3
2
133
LDC
Rm,SSR
CO
1
3
#14
SX
3
2
134
LDC
Rm,SPC
CO
1
3
#14
SX
3
2
135
LDC
Rm,VBR
CO
1
3
#14
SX
3
2
136
LDC.L
@Rm+,DBR
CO
1
1/3
#17
SX
3
2
137
LDC.L
@Rm+,GBR
CO
3
3/3
#18
SX
3
2
138
LDC.L
@Rm+,Rp_BANK
CO
1
1/3
#17
SX
3
2
139
LDC.L
@Rm+,SR
CO
4
4/4
#19
SX
3
2
140
LDC.L
@Rm+,SSR
CO
1
1/3
#17
SX
3
2
141
LDC.L
@Rm+,SPC
CO
1
1/3
#17
SX
3
2
142
LDC.L
@Rm+,VBR
CO
1
1/3
#17
SX
3
2
143
LDS
Rm,MACH
CO
1
3
#28
F1
3
2
144
LDS
Rm,MACL
CO
1
3
#28
F1
3
2
145
LDS
Rm,PR
CO
2
3
#24
SX
3
2
146
LDS.L
@Rm+,MACH
CO
1
1/3
#29
F1
3
2
147
LDS.L
@Rm+,MACL
CO
1
1/3
#29
F1
3
2
148
LDS.L
@Rm+,PR
CO
2
2/3
#25
SX
3
2
149
STC
DBR,Rn
CO
2
2
#20
--
--
--
System
control
instructions
150
STC
SGR,Rn
CO
3
3
#21
--
--
--
Rev. 3.0, 04/02, page 210 of 1064
Table 8.3
Execution Cycles (cont)
Lock
Functional
Category
No.
Instruction
Instruc-
tion
Group
Issue
Rate
Latency
Execu-
tion
Pattern Stage Start
Cycles
151
STC
GBR,Rn
CO
2
2
#20
--
--
--
152
STC
Rp_BANK,Rn
CO
2
2
#20
--
--
--
153
STC
SR,Rn
CO
2
2
#20
--
--
--
154
STC
SSR,Rn
CO
2
2
#20
--
--
--
155
STC
SPC,Rn
CO
2
2
#20
--
--
--
156
STC
VBR,Rn
CO
2
2
#20
--
--
--
157
STC.L
DBR,@-Rn
CO
2
2/2
#22
--
--
--
158
STC.L
SGR,@-Rn
CO
3
3/3
#23
--
--
--
159
STC.L
GBR,@-Rn
CO
2
2/2
#22
--
--
--
160
STC.L
Rp_BANK,@-Rn
CO
2
2/2
#22
--
--
--
161
STC.L
SR,@-Rn
CO
2
2/2
#22
--
--
--
162
STC.L
SSR,@-Rn
CO
2
2/2
#22
--
--
--
163
STC.L
SPC,@-Rn
CO
2
2/2
#22
--
--
--
164
STC.L
VBR,@-Rn
CO
2
2/2
#22
--
--
--
165
STS
MACH,Rn
CO
1
3
#30
--
--
--
166
STS
MACL,Rn
CO
1
3
#30
--
--
--
167
STS
PR,Rn
CO
2
2
#26
--
--
--
168
STS.L
MACH,@-Rn
CO
1
1/1
#31
--
--
--
169
STS.L
MACL,@-Rn
CO
1
1/1
#31
--
--
--
System
control
instructions
170
STS.L
PR,@-Rn
CO
2
2/2
#27
--
--
--
171
FLDI0
FRn
LS
1
0
#1
--
--
--
172
FLDI1
FRn
LS
1
0
#1
--
--
--
173
FMOV
FRm,FRn
LS
1
0
#1
--
--
--
174
FMOV.S
@Rm,FRn
LS
1
2
#2
--
--
--
175
FMOV.S
@Rm+,FRn
LS
1
1/2
#2
--
--
--
176
FMOV.S
@(R0,Rm),FRn
LS
1
2
#2
--
--
--
177
FMOV.S
FRm,@Rn
LS
1
1
#2
--
--
--
178
FMOV.S
FRm,@-Rn
LS
1
1/1
#2
--
--
--
179
FMOV.S
FRm,@(R0,Rn)
LS
1
1
#2
--
--
--
180
FLDS
FRm,FPUL
LS
1
0
#1
--
--
--
Single-
precision
floating-point
instructions
181
FSTS
FPUL,FRn
LS
1
0
#1
--
--
--
Rev. 3.0, 04/02, page 211 of 1064
Table 8.3
Execution Cycles (cont)
Lock
Functional
Category
No.
Instruction
Instruc-
tion
Group
Issue
Rate
Latency
Execu-
tion
Pattern Stage Start
Cycles
182
FABS
FRn
LS
1
0
#1
--
--
--
183
FADD
FRm,FRn
FE
1
3/4
#36
--
--
--
184
FCMP/EQ FRm,FRn
FE
1
2/4
#36
--
--
--
185
FCMP/GT FRm,FRn
FE
1
2/4
#36
--
--
--
186
FDIV
FRm,FRn
FE
1
12/13
#37
F3
2
10
F1
11
1
187
FLOAT
FPUL,FRn
FE
1
3/4
#36
--
--
--
188
FMAC
FR0,FRm,FRn
FE
1
3/4
#36
--
--
--
189
FMUL
FRm,FRn
FE
1
3/4
#36
--
--
--
190
FNEG
FRn
LS
1
0
#1
--
--
--
191
FSQRT
FRn
FE
1
11/12
#37
F3
2
9
F1
10
1
192
FSUB
FRm,FRn
FE
1
3/4
#36
--
--
--
193
FTRC
FRm,FPUL
FE
1
3/4
#36
--
--
--
194
FMOV
DRm,DRn
LS
1
0
#1
--
--
--
195
FMOV
@Rm,DRn
LS
1
2
#2
--
--
--
196
FMOV
@Rm+,DRn
LS
1
1/2
#2
--
--
--
197
FMOV
@(R0,Rm),DRn
LS
1
2
#2
--
--
--
198
FMOV
DRm,@Rn
LS
1
1
#2
--
--
--
199
FMOV
DRm,@-Rn
LS
1
1/1
#2
--
--
--
Single-
precision
floating-point
instructions
200
FMOV
DRm,@(R0,Rn)
LS
1
1
#2
--
--
--
201
FABS
DRn
LS
1
0
#1
--
--
--
202
FADD
DRm,DRn
FE
1
(7, 8)/9
#39
F1
2
6
203
FCMP/EQ DRm,DRn
CO
2
3/5
#40
F1
2
2
204
FCMP/GT DRm,DRn
CO
2
3/5
#40
F1
2
2
205
FCNVDS
DRm,FPUL
FE
1
4/5
#38
F1
2
2
206
FCNVSD
FPUL,DRn
FE
1
(3, 4)/5
#38
F1
2
2
F3
2
23
F1
22
3
207
FDIV
DRm,DRn
FE
1
(24, 25)/
26
#41
F1
2
2
208
FLOAT
FPUL,DRn
FE
1
(3, 4)/5
#38
F1
2
2
Double-
precision
floating-point
instructions
209
FMUL
DRm,DRn
FE
1
(7, 8)/9
#39
F1
2
6
Rev. 3.0, 04/02, page 212 of 1064
Table 8.3
Execution Cycles (cont)
Lock
Functional
Category
No.
Instruction
Instruc-
tion
Group
Issue
Rate
Latency
Execu-
tion
Pattern Stage Start
Cycles
210
FNEG
DRn
LS
1
0
#1
--
--
--
F3
2
22
F1
21
3
211
FSQRT
DRn
FE
1
(23, 24)/
25
#41
F1
2
2
212
FSUB
DRm,DRn
FE
1
(7, 8)/9
#39
F1
2
6
Double-
precision
floating-point
instructions
213
FTRC
DRm,FPUL
FE
1
4/5
#38
F1
2
2
214
LDS
Rm,FPUL
LS
1
1
#1
--
--
--
215
LDS
Rm,FPSCR
CO
1
4
#32
F1
3
3
216
LDS.L
@Rm+,FPUL
CO
1
1/2
#2
--
--
--
217
LDS.L
@Rm+,FPSCR
CO
1
1/4
#33
F1
3
3
218
STS
FPUL,Rn
LS
1
3
#1
--
--
--
219
STS
FPSCR,Rn
CO
1
3
#1
--
--
--
220
STS.L
FPUL,@-Rn
CO
1
1/1
#2
--
--
--
FPU system
control
instructions
221
STS.L
FPSCR,@-Rn
CO
1
1/1
#2
--
--
--
222
FMOV
DRm,XDn
LS
1
0
#1
--
--
--
223
FMOV
XDm,DRn
LS
1
0
#1
--
--
--
224
FMOV
XDm,XDn
LS
1
0
#1
--
--
--
225
FMOV
@Rm,XDn
LS
1
2
#2
--
--
--
226
FMOV
@Rm+,XDn
LS
1
1/2
#2
--
--
--
227
FMOV
@(R0,Rm),XDn
LS
1
2
#2
--
--
--
228
FMOV
XDm,@Rn
LS
1
1
#2
--
--
--
229
FMOV
XDm,@-Rm
LS
1
1/1
#2
--
--
--
230
FMOV
XDm,@(R0,Rn)
LS
1
1
#2
--
--
--
231
FIPR
FVm,FVn
FE
1
4/5
#42
F1
3
1
232
FRCHG
FE
1
1/4
#36
--
--
--
233
FSCHG
FE
1
1/4
#36
--
--
--
F0
2
4
Graphics
acceleration
instructions
234
FTRV
XMTRX,FVn
FE
1
(5, 5, 6,
7)/8
#43
F1
3
4
Notes: 1. See table 8.1 for the instruction groups.
2. Latency "L1/L2...": Latency corresponding to a write to each register, including
MACH/MACL/FPSCR
Example: MOV.B @Rm+, Rn "1/2": The latency for Rm is 1 cycle, and the latency for
Rn is 2 cycles.
3. Branch latency: Interval until the branch destination instruction is fetched
4. Conditional branch latency "2 (or 1)": The latency is 2 for a nonzero displacement, and
1 for a zero displacement.
Rev. 3.0, 04/02, page 213 of 1064
5. Double-precision floating-point instruction latency "(L1, L2)/L3": L1 is the latency for FR
[n+1], L2 that for FR [n], and L3 that for FPSCR.
6. FTRV latency "(L1, L2, L3, L4)/L5": L1 is the latency for FR [n], L2 that for FR [n+1], L3
that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR.
7. Latency "L1/L2/L3/L4" of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2
that for Rn, L3 that for MACH, and L4 that for MACL.
8. Latency "L1/L2" of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions:
L1 is the latency for MACH, and L2 that for MACL.
9. Execution pattern: The instruction execution pattern number (see figure 8.2)
10. Lock/stage: Stage locked by the instruction
11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction.
12. Lock/cycles: Number of cycles locked
Exceptions:
1. When a floating-point computation instruction is followed by an FMOV store, an STS
FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, the latency of the floating-
point computation is decreased by 1 cycle.
2. When the preceding instruction loads the shift amount of the following SHAD/SHLD, the
latency of the load is increased by 1 cycle.
3. When an LS group instruction with a latency of less than 3 cycles is followed by a
double-precision floating-point instruction, FIPR, or FTRV, the latency of the first
instruction is increased to 3 cycles.
Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2
cycles.
4. When MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is followed by an
STS.L MACH/MACL, @-Rn instruction, the latency of
MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is 5 cycles.
5. In the case of consecutive executions of
MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L, the latency is
decreased to 2 cycles.
6. When an LDS to MACH/MACL is followed by an STS.L MACH/MACL, @-Rn
instruction, the latency of the LDS to MACH/MACL is 4 cycles.
7. When an LDS to MACH/MACL is followed by
MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L, the latency of the LDS
to MACH/MACL is 1 cycle.
8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that
reads or writes to a floating-point register, the preceding LS group instruction[s] cannot
be executed in parallel.
9. When a single-precision FTRC instruction is followed by an STS FPUL, Rn instruction,
the latency of the single-precision FTRC instruction is 1 cycle.
Rev. 3.0, 04/02, page 214 of 1064
Rev. 3.0, 04/02, page 215 of 1064
Section 9 Power-Down Modes
9.1
Overview
In the power-down modes, some of the on-chip peripheral modules and the CPU functions are
halted, enabling power consumption to be reduced.
9.1.1
Types of Power-Down Modes
The following power-down modes and functions are provided:
Sleep mode
Deep sleep mode
Standby mode
Hardware standby mode
Module standby function (TMU, RTC, SCI/SCIF, and DMAC on-chip peripheral modules)
Table 9.1 shows the conditions for entering these modes from the program execution state, the
status of the CPU and peripheral modules in each mode, and the method of exiting each mode.
Rev. 3.0, 04/02, page 216 of 1064
Table 9.1
Status of CPU and Peripheral Modules in Power-Down Modes
Status
Power-
Down
Mode
Entering
Conditions CPG
CPU
On-Chip
Memory
On-chip
Peripheral
Modules
Pins
External
Memory
Exiting
Method
Sleep
SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR
Operating Halted
(registers
held)
Held
Operating
Held
Refresh-
ing
Interrupt
Reset
Deep
sleep
SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR,
and DSLP
bit is 1 in
STBCR2
Operating Halted
(registers
held)
Held
Operating
(DMA
halted)
Held
Self-
refresh-
ing
Interrupt
Reset
Standby SLEEP
instruction
executed
while STBY
bit is 1 in
STBCR
Halted
Halted
(registers
held)
Held
Halted*
Held
Self-
refresh-
ing
Interrupt
Reset
Hard-
ware
standby
Setting CA
pin to low
level
Halted
Halted
Unde-
fined
Halted*
High-
imped-
ance
state
Unde-
fined
Power-on
reset
Module
standby
Setting
MSTP bit to
1 in STBCR
Operating Operating Held
Specified
modules
halted*
Held
Refresh-
ing
Clearing
MSTP bit
to 0
Reset
Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC)).
Rev. 3.0, 04/02, page 217 of 1064
9.1.2
Register Configuration
Table 9.2 shows the registers used for power-down mode control.
Table 9.2
Power-Down Mode Registers
Name
Abbreviation
R/W
Initial Value P4 Address
Area 7
Address
Access
Size
Standby control
register
STBCR
R/W
H'00
H'FFC00004
H'1FC00004
8
Standby control
register 2
STBCR2
R/W
H'00
H'FFC00010
H'1FC00010
8
Clock stop register
CLKSTP00
R/W
H'00000000
H'FE0A0000
H'1E0A0000
32
Clock stop clear
register
CLKSTPCLR00
W
H'00000000
H'FE0A0008
H'1E0A0008
32
9.1.3
Pin Configuration
Table 9.3 shows the pins used for power-down mode control.
Table 9.3
Power-Down Mode Pins
Pin Name
Abbreviation
I/O
Function
Processor status 1
Processor status 0
STATUS1
STATUS0
Output
Indicate the processor's operating status
(STATUS1, STATUS0).
HH: Reset
HL: Sleep mode
LH: Standby mode
LL: Normal operation
Sleep request
6/((3
Input
A transition to sleep mode is effected by
inputting a low-level to the pin.
Hardware standby
request
CA
Input
A transition to hardware standby mode is
effected by inputting a low-level to the
pin.
Notes: H: High level
L: Low level
Rev. 3.0, 04/02, page 218 of 1064
9.2
Register Descriptions
9.2.1
Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit readable/writable register that specifies the
power-down mode status. It is initialized to H'00 by a power-on reset via the
5(6(7 pin or due to
watchdog timer overflow.
Bit:
7
6
5
4
3
2
1
0
STBY
PHZ
PPU
MSTP4
MSTP3
MSTP2
MSTP1
MSTP0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7--Standby (STBY): Specifies a transition to standby mode.
Bit 7: STBY
Description
0
Transition to sleep mode on execution of SLEEP instruction
(Initial value)
1
Transition to standby mode on execution of SLEEP instruction
Bit 6--Peripheral Module Pin High Impedance Control (PHZ): Controls the state of
peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module
related pins go to the high-impedance state in standby mode.
For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control.
Bit 6: PHZ
Description
0
Peripheral module related pins are in normal state
(Initial value)
1
Peripheral module related pins go to high-impedance state
Bit 5--Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module
related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral
module related pins in the input or high-impedance state.
For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control.
Bit 5: PPU
Description
0
Peripheral module related pin pull-up resistors are on
(Initial value)
1
Peripheral module related pin pull-up resistors are off
Rev. 3.0, 04/02, page 219 of 1064
Bit 4--Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the
on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set
to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA
transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again.
Bit 4: MSTP4
Description
0
DMAC operates
(Initial value)
1
DMAC clock supply is stopped
Bit 3--Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication
interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is
stopped when the MSTP3 bit is set to 1.
Bit 3: MSTP3
Description
0
SCIF operates
(Initial value)
1
SCIF clock supply is stopped
Bit 2--Module Stop 2 (MSTP2): Specifies stopping of the clock supply to the timer unit channel
0 to 2 (TMU) among the on-chip peripheral modules. The clock supply to the TMU is stopped
when the MSTP2 bit is set to 1.
Bit 2: MSTP2
Description
0
TMU channel 0 to 2 operates
(Initial value)
1
TMU channel 0 to 2 clock supply is stopped
Bit 1--Module Stop 1 (MSTP1): Specifies stopping of the clock supply to the realtime clock
(RTC) among the on-chip peripheral modules. The clock supply to the RTC is stopped when the
MSTP1 bit is set to 1. When the clock supply is stopped, RTC registers cannot be accessed but the
counters continue to operate.
Bit 1: MSTP1
Description
0
RTC operates
(Initial value)
1
RTC clock supply is stopped
Bit 0--Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication
interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is
stopped when the MSTP0 bit is set to 1.
Rev. 3.0, 04/02, page 220 of 1064
Bit 0: MSTP0
Description
0
SCI operates
(Initial value)
1
SCI clock supply is stopped
9.2.2
Peripheral Module Pin High Impedance Control
When bit 6 in the standby control register (STBCR) is set to 1, peripheral module related pins go
to the high-impedance state in standby mode.
Relevant Pins
SCI related pins
SCK
MD0/SCK2
TXD
MD1/TXD2
MD7/
&76
MD8/
576
DMA related pins
DACK0
DRAK0
DACK1
DRAK1
Other Information
The setting in this register is invalid when the above pins are used as port output pins.
For details of pin states, see Appendix D, Pin Functions.
9.2.3
Peripheral Module Pin Pull-Up Control
When bit 5 in the standby control register (STBCR) is cleared to 0, peripheral module related pins
are pulled up when in the input or high-impedance state.
Relevant Pins
SCI related pins
MD0/SCK2
MD1/TXD2
MD2/RXD2
MD7/
&76
MD8/
576
SCK
RXD
TXD
DMA related pins
'5(4
DACK0
DRAK0
'5(4
DACK1
DRAK1
TMU related pin
TCLK
Rev. 3.0, 04/02, page 221 of 1064
9.2.4
Standby Control Register 2 (STBCR2)
Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep
mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via
the
5(6(7 pin or due to watchdog timer overflow.
Bit:
7
6
5
4
3
2
1
0
DSLP
STHZ
--
--
--
--
MSTP6
MSTP5
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R
R
R
R
R/W
R/W
Bit 7--Deep Sleep (DSLP): Specifies a transition to deep sleep mode
Bit 7: DSLP
Description
0
Transition to sleep mode or standby mode on execution of SLEEP
instruction, according to setting of STBY bit in STBCR register (Initial value)
1
Transition to deep sleep mode on execution of SLEEP instruction*
Note: * When the STBY bit in the STBCR register is 0
Bit 6--STATUS Pin High-Impedance Control (STHZ): This bit selects whether the STATUS0
and 1 pins are set to high-impedance when in hardware standby mode.
Bit 6: STHZ
Description
0
Sets STATUS0, 1 pins to high-impedance when in hardware standby mode
(Initial value)
1
Drives STATUS0, 1 pins to LH when in hardware standby mode
Bits 5 to 2--Reserved: Only 0 should only be written to these bits; operation cannot be
guaranteed if 1 is written. These bits are always read as 0.
Bit 1--Module Stop 6 (MSTP6): Specifies that the clock supply to the store queue (SQ) in the
cache controller (CCN) is stopped. Setting the MSTP6 bit to 1 stops the clock supply to the SQ,
and the SQ functions are therefore unavailable.
Bit 1: MSTP6
Description
0
SQ operating
(Initial value)
1
Clock supply to SQ stopped
Rev. 3.0, 04/02, page 222 of 1064
Bit 0--Module Stop 5 (MSTP5): Specifies stopping of the clock supply to the user break
controller (UBC) among the on-chip peripheral modules. See section 20.6, User Break Controller
Stop Function for how to set the clock supply.
Bit 0: MSTP5
Description
0
UBC operating
(Initial value)
1
Clock supply to UBC stopped
9.2.5
Clock Stop Register 00 (CLKSTP00)
Clock stop register 00 (CLKSTP00) is a 32-bit readable/writable register that controls the
operating clock for peripheral modules.
The clock supply is restarted by writing 1 to the corresponding bit in the CLKSTPCLR00 register.
Writing 0 to CLKSTP00 will not change the bit value.
CLKSTP00 is initialized to H'00000000 by a reset. It is not initialized in standby mode.
Bit:
31
30
29
...
11
10
9
8
--
--
--
...
--
--
--
--
Initial value:
0
0
0
...
0
0
0
0
R/W:
R
R
R
...
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
--
--
--
--
--
CSTP2
CSTP1
CSTP0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
Bits 31 to 3--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2--Clock Stop 2 (CSTP2): Specifies stopping of the peripheral clock supply to the PCI bus
controller (PCIC). For details see section 22, PCI Controller (PCIC).
Bit 2: CSTP2
Description
0
Peripheral clock is supplied to PCIC
(Initial value)
1
Peripheral clock supply to PCIC is stopped
Rev. 3.0, 04/02, page 223 of 1064
Bit 1--Clock Stop 1 (CSTP1): Specifies stopping of the peripheral clock supply to timer unit
(TMU) channels 3 and 4.
Bit 1: CSTP1
Description
0
Peripheral clock is supplied to TMU channels 3 and 4
(Initial value)
1
Peripheral clock supply to TMU channels 3 and 4 is stopped
Bit 0--Clock Stop 0 (CSTP0): Specifies stopping of the peripheral clock supply to the interrupt
controller (INTC). When this bit is set, PCIC and TMU channel 3 and 4 interrupts are not
detected.
Bit 0: CSTP0
Description
0
INTC detects PCIC and TMU channel 3 and 4 interrupts
(Initial value)
1
INTC does not detect PCIC and TMU channel 3 and 4 interrupts
9.2.6
Clock Stop Clear Register 00 (CLKSTPCLR00)
Clock stop clear register 00 (CLKSTPCLR00) is a 32-bit write-only register that is used to clear
corresponding bits in the CLKSTP00 register.
Bit:
31
30
29
...
11
10
9
8
...
Initial value:
0
0
0
...
0
0
0
0
R/W:
W
W
W
...
W
W
W
W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
W
W
W
W
W
W
W
W
Bits 31 to 0--Clock Stop Clear: The value of a Clock Stop Clear bit indicates whether the
corresponding Clock Stop bit is to be cleared. See section 9.2.5, Clock Stop Register 00
(CLKSTP00), for the correspondence between bits and the clocks stopped.
Bits 31 to 0
Description
0
Corresponding Clock Stop bit is not changed
(Initial value)
1
Corresponding Clock Stop bit is cleared
Rev. 3.0, 04/02, page 224 of 1064
9.3
Sleep Mode
9.3.1
Transition to Sleep Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0, the chip switches
from the program execution state to sleep mode. After execution of the SLEEP instruction, the
CPU halts but its register contents are retained. The on-chip peripheral modules continue to
operate, and the clock continues to be output from the CKIO pin.
In sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at the
STATUS0 pin.
9.3.2
Exit from Sleep Mode
Sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a
reset. In sleep mode, interrupts are accepted even if the BL bit in the SR register is 1. If necessary,
SPC and SSR should be saved to the stack before executing the SLEEP instruction.
Exit by Interrupt: When an NMI, IRL, or on-chip peripheral module interrupt is generated, sleep
mode is exited and interrupt exception handling is executed. The code corresponding to the
interrupt source is set in the INTEVT register.
Exit by Reset: Sleep mode is exited by means of a power-on or manual reset via the
5(6(7 pin,
or a power-on or manual reset executed when the watchdog timer overflows.
9.4
Deep Sleep Mode
9.4.1
Transition to Deep Sleep Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is cleared to 0 and the DSLP bit
in STBCR2 is set to 1, the chip switches from the program execution state to deep sleep mode.
After execution of the SLEEP instruction, the CPU halts but its register contents are retained.
Except for the DMAC*, on-chip peripheral modules continue to operate. The clock continues to
be output to the CKIO pin, but all bus access (including auto refresh) stops. When using memory
that requires refreshing, set the self-refresh function prior to making the transition to deep sleep
mode.
In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at
the STATUS0 pin.
Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you make a
transition to deep sleep mode while DMA transfers are in progress, the results of those
transfers cannot be guaranteed.
Rev. 3.0, 04/02, page 225 of 1064
9.4.2
Exit from Deep Sleep Mode
As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip
peripheral module) or a reset.
9.5
Pin Sleep Mode
9.5.1
Transition to Pin Sleep Mode
Changing the
6/((3 pin to the low level causes the SH7751 Series to make a transition to sleep
mode.
To ensure that memory is correctly refreshed, use this function when the DSLP bit of STBCR2 is
set to 0.
9.5.2
Exit from Pin Sleep Mode
Setting the
6/((3 pin level high causes the SH7751 Series to return to the normal state. The pin
sleep mode is also canceled when the conditions specified in section 9.3.2, "Exit From Sleep
Mode" are satisfied.
In a power-on reset, the
6/((3 pin should be fixed high.
9.6
Standby Mode
9.6.1
Transition to Standby Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches
from the program execution state to standby mode. In standby mode, the on-chip peripheral
modules halt as well as the CPU. Clock output from the CKIO pin is also stopped.
The CPU and cache register contents are retained. Some on-chip peripheral module registers are
initialized. The state of the peripheral module registers in standby mode is shown in table 9.4.
Rev. 3.0, 04/02, page 226 of 1064
Table 9.4
State of Registers in Standby Mode
Module
Initialized Registers
Registers That Retain
Their Contents
Interrupt controller
--
All registers
User break controller
--
All registers
Bus state controller
--
All registers
On-chip oscillation circuits
--
All registers
Timer unit
TSTR register*
All registers except TSTR
Realtime clock
--
All registers
Direct memory access controller
--
All registers
Serial communication interface
See Appendix A, Address List See Appendix A, Address List
Notes: DMA transfer should be terminated before making a transition to standby mode. Transfer
results are not guaranteed if standby mode is entered during transfer.
* Not initialized when the realtime clock (RTC) is in use (see section 12, Timer Unit (TMU)).
The procedure for a transition to standby mode is shown below.
1. Clear the TME bit in the WDT timer control register (WTCSR) to 0, and stop the WDT.
Set the initial value for the up-count in the WDT timer counter (WTCNT), and set the clock to
be used for the up-count in bits CKS2CKS0 in the WTCSR register.
2. Set the STBY bit in the STBCR register to 1, then execute a SLEEP instruction.
3. When standby mode is entered and the chip's internal clock stops, a low-level signal is output
at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
9.6.2
Exit from Standby Mode
Standby mode is exited by means of an interrupt (NMI, IRL, or on-chip peripheral module) or a
reset via the
5(6(7 and 05(6(7 pins.
Exit by Interrupt: A hot start can be performed by means of the on-chip WDT. When an NMI,
IRL*
1
, RTC, or GPIO*
2
interrupt is detected, the WDT starts counting. After the count overflows,
clocks are supplied to the entire chip, standby mode is exited, and the STATUS1 and STATUS0
pins both go low. Interrupt exception handling is then executed, and the code corresponding to the
interrupt source is set in the INTEVT register. In standby mode, interrupts are accepted even if the
BL bit in the SR register is 1, and so, if necessary, SPC and SSR should be saved to the stack
before executing the SLEEP instruction.
The phase of the CKIO pin clock output may be unstable immediately after an interrupt is
detected, until standby mode is exited.
Rev. 3.0, 04/02, page 227 of 1064
Notes: *1 Only when the RTC clock (32.768 kHz) is operating (see section 19.2.2, IRL
Interrupts), standby mode can be exited by means of IRL3IRL0 (when the IRL3
IRL0 level is higher than the SR register I3I0 mask level).
*2 GPIC can be used to cancel standby mode when the RTC clock (32.768 kHz) is
operating (when the GPIC level is higher than the SR register I3I0 mask level).
Exit by Reset: Standby mode is exited by means of a reset (power-on or manual) via the
5(6(7
pin. The
5(6(7 pin should be held low until clock oscillation stabilizes. The internal clock
continues to be output at the CKIO pin.
9.6.3
Clock Pause Function
In standby mode, it is possible to stop or change the frequency of the clock input from the EXTAL
pin. This function is used as follows.
1. Enter standby mode following the transition procedure described above.
2. When standby mode is entered and the chip's internal clock stops, a low-level signal is output
at the STATUS1 pin, and a high-level signal at the STATUS0 pin.
3. The input clock is stopped, or its frequency changed, after the STATUS1 pin goes low and the
STATUS0 pin high.
4. When the frequency is changed, input an NMI or IRL interrupt after the change. When the
clock is stopped, input an NMI or IRL interrupt after applying the clock.
5. After the time set in the WDT, clock supply begins inside the chip, the STATUS1 and
STATUS0 pins both go low, and operation is resumed from interrupt exception handling.
9.7
Module Standby Function
9.7.1
Transition to Module Standby Function
Setting the MSTP6MSTP0 and CSTP2CSTP0 bits in the standby control register, standby
control register 2, and clock stop clear register 00 to 1 enables the clock supply to the
corresponding on-chip peripheral modules to be halted. Use of this function allows power
consumption in sleep mode to be further reduced.
In the module standby state, the on-chip peripheral module external pins retain their states prior to
halting of the modules, and most registers retain their states prior to halting of the modules.
Rev. 3.0, 04/02, page 228 of 1064
Bit
Description
CSTP2
0
Peripheral clock is supplied to PCIC
1
Peripheral clock supply to PCIC is stopped
CSTP1
0
Peripheral clock is supplied to TMU channels 3 and 4
1
Peripheral clock supply to TMU channels 3 and 4 is stopped
CSTP0
0
INTC detects PCIC and TMU channel 3 and 4 interrupts
1
INTC does not detect PCIC and TMU channel 3 and 4 interrupts
MSTP6
0
SQ operates
1
Clock supplied to SQ is stopped
MSTP5
0
UBC operates
1
Clock supplied to UBC is stopped*
3
MSTP4
0
DMAC operates
1
Clock supplied to DMAC is stopped*
4
MSTP3
0
SCIF operates
1
Clock supplied to SCIF is stopped
MSTP2
0
TMU operates
1
Clock supplied to TMU is stopped, and register is initialized*
1
MSTP1
0
RTC operates
1
Clock supplied to RTC is stopped*
2
MSTP0
0
SCI operates
1
Clock supplied to SCI is stopped
Notes: *1 The register initialized is the same as in standby mode, but initialization is not
performed if the RTC clock is not in use (see section 12, Timer Unit (TMU)).
*2 The counter operates when the START bit in RCR2 is 1 (see section 11, Realtime
Clock (RTC)).
*3 For details, see section 20.6, User Break Controller Stop Function.
*4 Terminate DMA transfers prior to making the transition to module standby mode. If you
make a transition to module standby mode while DMA transfers are in progress, the
results of those transfers cannot be guaranteed.
9.7.2
Exit from Module Standby Function
In the case of the standby control register and standby control register 2, the module standby
function is exited by writing 0 to the MSTP6MSTP0 bits. In the case of clock stop register 00,
the module standby function is exited by writing 1 to the corresponding bit in clock stop clear
register 00.
The module standby function is not exited by means of a power-on reset via the
5(6(7 pin or a
power-on reset caused by watchdog timer overflow.
Rev. 3.0, 04/02, page 229 of 1064
9.8
Hardware Standby Mode
9.8.1
Transition to Hardware Standby Mode
Setting the CA pin level low effects a transition to hardware standby mode. In this mode, all
modules other than the RTC stop, as in the standby mode selected using the SLEEP command.
Hardware standby mode differs from standby mode as follows:
1. Interrupts and manual resets are not available;
2. All output pins other than the STATUS pin are in the high-impedance state and the pull-up
resistance is off.
3. Even when no power is supplied to power pins other than the RTC power supply pin, the RTC
continues to operate.
The status of the STATUS pin is determined by the STHZ bit of STBCR2. See section D, Pin
Functions, for details of output pin states.
Operation when a low-level is input to the CA pin when in the standby mode depends on the CPG
status, as follows:
1. In standby mode
The clock remains stopped and a transition is made to the hardware standby state.
Interrupts and manual resets are disabled, but the output pins remain in the same state as in
standby mode.
2. When WDT is operating when standby mode is exited by interrupt
Standby mode is momentarily exited, the CPU restarts, and then a transition is made to
hardware standby mode.
Note that the level of the CA pin must be kept low while in hardware standby mode.
9.8.2
Exit from Hardware Standby Mode
In the case of the standby control register and standby control register 2, the module standby
function is exited by writing 0 to the MSTP6MSTP0 bits. In the case of clock stop register 00,
the module standby function is exited by writing 1 to the corresponding bit in clock stop clear
register 00.
The module standby function is not exited by means of a power-on reset via the
5(6(7 pin or a
power-on reset caused by watchdog timer overflow.
Rev. 3.0, 04/02, page 230 of 1064
9.8.3
Usage Notes
The CA pin level must be kept high during the power-on oscillation settling period when the RTC
power supply is started (figure 9.15).
9.9
STATUS Pin Change Timing
The STATUS1 and STATUS0 pin change timing is shown below.
The meaning of the STATUS pin settings is as follows:
Reset:
HH (STATUS1 high, STATUS0 high)
Sleep:
HL (STATUS1 high, STATUS0 low)
Standby:
LH (STATUS1 low, STATUS0 high)
Normal:
LL (STATUS1 low, STATUS0 low)
The meaning of the clock units is as follows:
Bcyc: Bus clock cycle
Pcyc: Peripheral clock cycle
9.9.1
In Reset
Power-On Reset
CKIO
STATUS
Normal
Reset
Normal
05 Bcyc
030 Bcyc
PLL stabilization
time
Figure 9.1 STATUS Output in Power-On Reset
Rev. 3.0, 04/02, page 231 of 1064
Manual Reset
CKIO
(High)
*
STATUS
Normal
Reset
Normal
030 Bcyc
0 Bcyc
Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting
until the end of the currently executing bus cycle.
Figure 9.2 STATUS Output in Manual Reset
9.9.2
In Exit from Standby Mode
Standby
Interrupt
CKIO
STATUS
Normal
Standby
Normal
WDT count
Oscillation stops
Interrupt request
WDT overflow
Figure 9.3 STATUS Output in Standby
Interrupt Sequence
Rev. 3.0, 04/02, page 232 of 1064
Standby
Power-On Reset
Reset
CKIO
*
1
STATUS
Normal
Reset
Normal
010 Bcyc
Standby
Oscillation stops
*
2
030 Bcyc
Notes: *1 When standby mode is exited by means of a power-on reset, a WDT count is not
performed. Hold
low for the PLL oscillation stabilization time.
*2 Undefined
Figure 9.4 STATUS Output in Standby
Power-On Reset Sequence
Rev. 3.0, 04/02, page 233 of 1064
Standby
Manual Reset
CKIO
(High)
STATUS
Normal
Reset
*
Undefined
Standby
Normal
020 Bcyc
030 Bcyc
Note: * When standby mode is exited by means of a manual reset, a WDT count is not performed.
Hold
low for the PLL oscillation stabilization time.
Reset
Oscillation stops
Figure 9.5 STATUS Output in Standby
Manual Reset Sequence
9.9.3
In Exit from Sleep Mode
Sleep
Interrupt
CKIO
STATUS
Normal
Sleep
Normal
Interrupt request
Figure 9.6 STATUS Output in Sleep
Interrupt Sequence
Rev. 3.0, 04/02, page 234 of 1064
Sleep
Power-On Reset
Reset
CKIO
STATUS
Normal
Reset
Sleep
Normal
010 Bcyc
030 Bcyc
*
1
*
2
Notes: *1 When sleep mode is exited by means of a power-on reset, hold
low for the
oscillation stabilization time.
*2 Undefined
Figure 9.7 STATUS Output in Sleep
Power-On Reset Sequence
Rev. 3.0, 04/02, page 235 of 1064
Sleep
Manual Reset
Reset
STATUS
Normal
Reset
*
Sleep
Normal
CKIO
(High)
030 Bcyc
030 Bcyc
Note: * Hold
low until STATUS = reset.
Figure 9.8 STATUS Output in Sleep
Manual Reset Sequence
Rev. 3.0, 04/02, page 236 of 1064
9.9.4
In Exit from Deep Sleep Mode
Deep Sleep
Interrupt
CKIO
STATUS
Normal
Sleep
Normal
Interrupt request
Figure 9.9 STATUS Output in Deep Sleep
Interrupt Sequence
Deep Sleep
Power-On Reset
Reset
CKIO
STATUS
Normal
Sleep
Reset
Normal
010 Bcyc
030 Bcyc
RESET*
1
*
2
Notes: *1 When deep sleep mode is exited by means of a power-on reset, hold RESET low for the
oscillation stabilization time.
*2 Undefined
Figure 9.10 STATUS Output in Deep Sleep
Power-On Reset Sequence
Rev. 3.0, 04/02, page 237 of 1064
Deep Sleep
Manual Reset
Reset
STATUS
Normal
Sleep
Reset
*
Normal
CKIO
(High)
030 Bcyc
030 Bcyc
Note: * Hold
low until STATUS = reset.
Figure 9.11 STATUS Output in Deep Sleep
Manual Reset Sequence
Rev. 3.0, 04/02, page 238 of 1064
9.9.5
Hardware Standby Mode Timing
Figure 9.12 shows the timing of the signals of the respective pins in hardware standby mode.
The CA pin level must be kept low while in hardware standby mode.
After setting the
5(6(7 pin level low, the clock starts when the CA pin level is switched to high.
CKIO
CA
STATUS
Reset
010 Bcyc
010 Bcyc
Standby
*2
Waiting for end of bus cycle
Undefined
Notes: *1 Same at sleep and reset
*2 High impedance when STBCR2. STHZ = 0
Normal
*1
Figure 9.12 Hardware Standby Mode Timing
(When CA = Low in Normal Operation)
Rev. 3.0, 04/02, page 239 of 1064
CKIO
(High)
CA
STATUS
Standby
010 Bcyc
Normal
Standby*
WDT count
WDT overflow
Interrupt request
Note: * High impedance when STBCR2. STHZ = 0
Figure 9.13 Hardware Standby Mode Timing
(When CA = Low in WDT Operation)
V
DDQ
*
V
DD
CA
Min 0s
Min 0s
Max 50
s
Note: * V
DDQ
, V
DD-CPG
V
DD
min
Figure 9.14 Timing When Power Other than VDD-RTC is Off
Rev. 3.0, 04/02, page 240 of 1064
CA
V
DD-RTC
V
DD
, V
DDQ
*
Min 0s
Note: * V
DD
, V
DD-PLL1/2
, V
DDQ
, V
DD-CPG
Power-on oscillation
settling time
Figure 9.15 Timing When VDD-RTC Power is Off
On
Rev. 3.0, 04/02, page 241 of 1064
Section 10 Clock Oscillation Circuits
10.1
Overview
The on-chip oscillation circuits comprise a clock pulse generator (CPG) and a watchdog timer
(WDT).
The CPG generates the clocks supplied inside the processor and performs power-down mode
control.
The WDT is a single-channel timer used to count the clock stabilization time when exiting standby
mode or the frequency is changed. It can be used as a normal watchdog timer or an interval timer.
10.1.1
Features
The CPG has the following features:
Three clocks
The CPG can generate independently the CPU clock (I
) used by the CPU, FPU, caches, and
TLB, the peripheral module clock (P
) used by the peripheral modules, and the bus clock
(CKIO) used by the external bus interface.
Six clock modes
Any of six clock operating modes can be selected, with different combinations of CPU clock,
bus clock, and peripheral module clock division ratios after a power-on reset.
Frequency change function
PLL (phase-locked loop) circuits and a frequency divider in the CPG enable the CPU clock,
bus clock, and peripheral module clock frequencies to be changed independently. Frequency
changes are performed by software in accordance with the settings in the frequency control
register (FRQCR).
PLL on/off control
Power consumption can be reduced by stopping the PLL circuits during low-frequency
operation.
Power-down mode control
It is possible to stop the clock in sleep mode and standby mode, and to stop specific modules
with the module standby function.
Rev. 3.0, 04/02, page 242 of 1064
The WDT has the following features
Can be used to secure clock stabilization time
Used when exiting standby mode or a temporary standby state when the clock frequency is
changed.
Can be switched between watchdog timer mode and interval timer mode
Internal reset generation in watchdog timer mode
An internal reset is executed on counter overflow.
Power-on reset or manual reset can be selected.
Interrupt generation in interval timer mode
An interval timer interrupt is generated on counter overflow.
Selection of eight counter input clocks
Any of eight clocks can be selected, scaled from the
1 clock of frequency divider 2 shown in
figure 10.1.
The CPG is described in sections 10.2 to 10.6, and the WDT in sections 10.7 to 10.9.
Rev. 3.0, 04/02, page 243 of 1064
10.2
Overview of CPG
10.2.1
Block Diagram of CPG
Figures 10.1(1) and 10.1(2) show a block diagram of the CPG in the SH7751 and SH7751R.
FRQCR:
Frequency control register
STBCR:
Standby control register
STBCR2: Standby control register 2
Oscillator circuit
PLL circuit 1
Frequency
divider 2
Crystal
oscillator
Frequency
divider 1
PLL circuit 2
CPU clock (I)
cycle Icyc
Peripheral module
clock (P) cycle
Pcyc
Bus clock (B)
cycle Bcyc
CPG control unit
Clock frequency
control circuit
Standby control
circuit
Bus interface
Internal bus
XTAL
EXTAL
MD8
CKIO
MD2
MD1
MD0
FRQCR
STBCR2
1
1/2
1/3
1/4
1/6
1/8
6
1/2
1
STBCR
Figure 10.1(1) Block Diagram of CPG (SH7751)
Rev. 3.0, 04/02, page 244 of 1064
FRQCR:
STBCR:
STBCR2:
Frequency control register
Standby control register
Standby control register 2
Oscillator circuit
PLL circuit 1
Frequency
divider 2
Crystal
oscillator
CPU clock (I)
cycle Icyc
Peripheral module
clock (P) cycle
Pcyc
Bus clock (B)
cycle Bcyc
CPG control unit
Clock frequency
control circuit
Standby control
circuit
Bus interface
Internal bus
XTAL
EXTAL
MD8
CKIO
MD2
MD1
MD0
FRQCR
STBCR2
1
1/2
1/3
1/4
1/6
1/8
6
12
PLL circuit 2
1
STBCR
Figure 10.1(2) Block Diagram of CPG (SH7751R)
Rev. 3.0, 04/02, page 245 of 1064
The function of each of the CPG blocks is described below.
PLL Circuit 1: PLL circuit 1 has a function for multiplying the clock frequency from the EXTAL
pin or crystal oscillator by 6 or 12. Starting and stopping is controlled by a frequency control
register setting. Control is performed so that the internal clock rising edge phase matches the input
clock rising edge phase.
PLL Circuit 2: PLL circuit 2, according to the output clock feedback from the CKIO pin,
coordinates the phases of the bus clock and the CKIO pin output clock. Starting and stopping is
controlled by a frequency control register setting.
Crystal Oscillator: This is the oscillator circuit used when a crystal resonator is connected to the
XTAL and EXTAL pins. Use of the crystal oscillator can be selected with the MD8 pin.
Frequency Divider 1 (SH7751R only): Frequency divider 1 has a function for adjusting the clock
waveform duty to 50% by halving the input clock frequency when clock input from the EXTAL
pin is supplied internally without using PLL circuit 1.
Frequency Divider 2: Frequency divider 2 generates the CPU clock (I
), bus clock (B
), and
peripheral module clock (P
). The division ratio is set in the frequency control register.
Clock Frequency Control Circuit: The clock frequency control circuit controls the clock
frequency by means of the MD pins and frequency control register.
Standby Control Circuit: The standby control circuit controls the state of the on-chip oscillation
circuits and other modules when the clock is switched and in sleep and standby modes.
Frequency Control Register (FRQCR): The frequency control register contains control bits for
clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU clock, bus clock,
and peripheral module clock frequency division ratios.
Standby Control Register (STBCR): The standby control register contains power save mode
control bits. For further information on the standby control register, see section 9, Power-Down
Modes.
Standby Control Register 2 (STBCR2): Standby control register 2 contains a power save mode
control bit. For further information on standby control register 2, see section 9, Power-Down
Modes.
Rev. 3.0, 04/02, page 246 of 1064
10.2.2
CPG Pin Configuration
Table 10.1 shows the CPG pins and their functions.
Table 10.1
CPG Pins
Pin Name
Abbreviation
I/O
Function
Mode control pins
MD0
Input
Set clock operating mode
MD1
MD2
XTAL
Output
Connects crystal resonator
EXTAL
Input
Connects crystal resonator, or used as
external clock input pin
Crystal I/O pins
(clock input pins)
MD8
Input
Selects use/non-use of crystal resonator
When MD8 = 0, external clock is input from
EXTAL
When MD8 = 1, crystal resonator is
connected directly to EXTAL and XTAL
Clock output pin
CKIO
Output
Used as external clock output pin
Level can also be fixed
CKIO enable pin
CKE
Output
0 when CKIO output clock is unstable and in
case of synchronous DRAM self-refreshing*
Note: * Set to 1 in a power-on reset.
For details of synchronous DRAM self-refreshing, see section 13.3.5, Synchronous DRAM
Interface.
10.2.3
CPG Register Configuration
Table 10.2 shows the CPG register configuration.
Table 10.2
CPG Register
Name
Abbreviation
R/W
Initial Value
P4 Address
Area 7
Address
Access
Size
Frequency control
register
FRQCR
R/W
Undefined
H'FFC00000
H'1FC00000
16
Rev. 3.0, 04/02, page 247 of 1064
10.3
Clock Operating Modes
Tables 10.3(1) and 10.3(2) show the clock operating modes corresponding to various
combinations of mode control pin (MD2MD0) settings (initial settings such as the frequency
division ratio).
Table 10.4 shows FRQCR settings and internal clock frequencies.
Table 10.3(1) Clock Operating Modes (SH7751)
External
Pin Combination
Frequency
(vs. Input Clock)
Clock
Operating
Mode
MD2
MD1
MD0
1/2
Frequency
Divider
PLL1
PLL2
CPU
Clock
Bus
Clock
Peripheral
Module
Clock
FRQCR
Initial Value
0
0
Off
On
On
6
3/2
3/2
H'0E1A
1
0
1
Off
On
On
6
1
1
H'0E23
2
0
On
On
On
3
1
1/2
H'0E13
3
0
1
1
Off
On
On
6
2
1
H'0E13
4
0
On
On
On
3
3/2
3/4
H'0E0A
5
1
0
1
Off
On
On
6
3
3/2
H'0E0A
Notes: 1. The clock operating mode is the only factor to determine whether to turn the 1/2
frequency divider on or off.
2. For the frequency range of the input clock, see the EXTAL clock input frequency (f
EX
)
and CKIO clock output (f
OP
) in section 23.3.1, Clock and Control Signal Timing.
Table 10.3(2) Clock Operating Modes (SH7751R)
External
Pin Combination
Frequency
(vs. Input Clock)
Clock
Operating
Mode
MD2
MD1
MD0
PLL1
PLL2
CPU
Clock
Bus
Clock
Peripheral
Module Clock
FRQCR
Initial Value
0
0
On (
12)
On
12
3
3
H'0E1A
1
0
1
On (
12)
On
12
3/2
3/2
H'0E2C
2
0
On (
6)
On
6
2
1
H'0E13
3
0
1
1
On (
12)
On
12
4
2
H'0E13
4
0
On (
6)
On
6
3
3/2
H'0E0A
5
0
1
On (
12)
On
12
6
3
H'0E0A
6
1
1
0
OFF (
6)
OFF
1
1/2
1/2
H'0808
Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode.
2. For the ranges input clock frequency, see the description of the EXTAL clock input
frequency (f
EX
) and the CKIO clock output (f
OP
) in section 23.3.1, Clock and Control
Signal Timing.
Rev. 3.0, 04/02, page 248 of 1064
Table 10.4
FRQCR Settings and Internal Clock Frequencies
Frequency Division Ratio
FRQCR
(Lower 9 Bits)
CPU Clock
Bus Clock
Peripheral Module Clock
9'h000
1/2
9'h002
1/4
9'h004
1
1/8
9'h008
1/2
9'h00a
1/4
9'h00c
1/2
1/8
9'h011
1/3
9'h013
1/3
1/6
9'h01a
1/4
9'h01c
1/4
1/8
9'h023
1/6
1/6
9'h02c
1
1/8
1/8
9'h048
1/2
9'h04a
1/4
9'h04c
1/2
1/8
9'h05a
1/4
9'h05c
1/4
1/8
9'h063
1/6
1/6
9'h06c
1/2
1/8
1/8
9'h091
1/3
9'h093
1/3
1/6
9'h0a3
1/3
1/6
1/6
9'h0da
1/4
9'h0dc
1/4
9'h0ec
1/4
1/8
1/8
9'h123
1/6
1/6
1/6
9'h16c
1/8
1/8
1/8
Note: Do not set values other than those shown in the table for the lower 9 bits of FRQCR.
Rev. 3.0, 04/02, page 249 of 1064
10.4
CPG Register Description
10.4.1
Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit readable/writable register that specifies
use/non-use of clock output from the CKIO pin, PLL circuit 1 and 2 on/off control, and the CPU
clock, bus clock, and peripheral module clock frequency division ratios. Only word access can be
used on FRQCR.
FRQCR is initialized only by a power-on reset via the
#$% pin. The initial value of each bit is
determined by the clock operating mode.
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
CKOEN
PLL1EN PLL2EN
IFC2
Initial value:
0
0
0
0
1
1
1
--
R/W:
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
IFC1
IFC0
BFC2
BFC1
BFC0
PFC2
PFC1
PFC0
Initial value:
--
--
--
--
--
--
--
--
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 12--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 11--Clock Output Enable (CKOEN): Specifies whether a clock is output from the CKIO
pin or the CKIO pin is placed in the high-impedance state. When the CKIO pin goes to the high-
impedance state, operation continues at the operating frequency before this state was entered.
When the CKIO pin becomes high-impedance, it is pulled up.
Bit 11: CKOEN
Description
0
CKIO pin goes to high-impedance state (pulled up*)
1
Clock is output from CKIO pin
(Initial value)
Note: * It is not pulled up in hardware standby mode.
Bit 10--PLL Circuit 1 Enable (PLL1EN): Specifies whether PLL circuit 1 is on or off.
Bit 10: PLL1EN
Description
0
PLL circuit 1 is not used
1
PLL circuit 1 is used
(Initial value)
Rev. 3.0, 04/02, page 250 of 1064
Bit 9--PLL Circuit 2 Enable (PLL2EN): Specifies whether PLL circuit 2 is on or off.
Bit 9: PLL2EN
Description
0
PLL circuit 2 is not used
1
PLL circuit 2 is used
(Initial value)
Bits 8 to 6--CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock
frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1
output frequency.
Bit 8: IFC2
Bit 7: IFC1
Bit 6: IFC0
Description
0
0
0
1
1
1/2
1
0
1/3
1
1/4
1
0
0
1/6
1
1/8
Other than the above
Setting prohibited (Do not set)
Bits 5 to 3--Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock
frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1
output frequency.
Bit 5: BFC2
Bit 4: BFC1
Bit 3: BFC0
Description
0
0
0
1
1
1/2
1
0
1/3
1
1/4
1
0
0
1/6
1
1/8
Other than the above
Setting prohibited (Do not set)
Bits 2 to 0--Peripheral Module Clock Frequency Division Ratio (PFC): These bits specify the
peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency
divider, or PLL circuit 1 output frequency.
Rev. 3.0, 04/02, page 251 of 1064
Bit 2: PFC2
Bit 1: PFC1
Bit 0: PFC0
Description
0
0
0
1/2
1
1/3
1
0
1/4
1
1/6
1
0
0
1/8
Other than the above
Setting prohibited (Do not set)
10.5
Changing the Frequency
There are two methods of changing the internal clock frequency: by changing stopping and
starting of PLL circuit 1, and by changing the frequency division ratio of each clock. In both
cases, control is performed by software by means of the frequency control register. These methods
are described below.
10.5.1
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off)
When PLL circuit 1 is changed from the stopped to started state, a PLL circuit 1 oscillation
stabilization time is required. The oscillation stabilization time count is performed by the on-chip
WDT.
1. Set a value in WDT to provide the specified oscillation stabilization time, and stop the WDT.
The following settings are necessary:
WTCSR register TME bit = 0: WDT stopped
WTCSR register CKS2CKS0 bits: WDT count clock division ratio
WTCNT counter: Initial counter value
2. Set the PLL1EN bit to 1.
3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal
clock stops and an unstable clock is output to the CKIO pin.
4. After the WDT count overflows, clock supply begins within the chip and the processor
resumes operation. The WDT stops after overflowing.
10.5.2
Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On)
When PLL circuit 2 is on, a PLL circuit 1 and PLL circuit 2 oscillation stabilization time is
required.
1. Make WDT settings as in 10.5.1.
2. Set the PLL1EN bit to 1.
Rev. 3.0, 04/02, page 252 of 1064
3. Internal processor operation stops temporarily, PLL circuit 1 oscillates, and the WDT starts
counting up. The internal clock stops and an unstable clock is output to the CKIO pin.
4. After the WDT count overflows, PLL circuit 2 starts oscillating. The WDT resumes its up-
count from the value set in step 1 above. During this time, also, the internal clock is stopped
and an unstable clock is output to the CKIO pin.
5. After the WDT count overflows, clock supply begins within the chip and the processor
resumes operation. The WDT stops after overflowing.
10.5.3
Changing Bus Clock Division Ratio (When PLL Circuit 2 is On)
If PLL circuit 2 is on when the bus clock frequency division ratio is changed, a PLL circuit 2
oscillation stabilization time is required.
1. Make WDT settings as in 10.5.1.
2. Set the BFC2BFC0 bits to the desired value.
3. Internal processor operation stops temporarily, and the WDT starts counting up. The internal
clock stops and an unstable clock is output to the CKIO pin.
4. After the WDT count overflows, clock supply begins within the chip and the processor
resumes operation. The WDT stops after overflowing.
10.5.4
Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off)
If PLL circuit 2 is off when the bus clock frequency division ratio is changed, a WDT count is not
performed.
1. Set the BFC2BFC0 bits to the desired value.
2. The set clock is switched to immediately.
10.5.5
Changing CPU or Peripheral Module Clock Division Ratio
When the CPU or peripheral module clock frequency division ratio is changed, a WDT count is
not performed.
1. Set the IFC2IFC0 or PFC2PFC0 bits to the desired value.
2. The set clock is switched to immediately.
Rev. 3.0, 04/02, page 253 of 1064
10.6
Output Clock Control
The CKIO pin can be switched between clock output and a high-impedance state by means of the
CKOEN bit in the FRQCR register. When the CKIO pin goes to the high-impedance state, it is
pulled up.
10.7
Overview of Watchdog Timer
10.7.1
Block Diagram
Figure 10.2 shows a block diagram of the WDT.
Standby
release
Internal reset
request
Interrupt
request
Standby
control
Reset
control
Interrupt
control
WTCSR
WTCNT
Bus interface
Clock selection
Overflow
Frequency divider
Clock selector
Clock
WDT
WTCSR: Watchdog timer control/status register
WTCNT: Watchdog timer counter
Standby
mode
Frequency
divider 2
1
clock
Figure 10.2 Block Diagram of WDT
Rev. 3.0, 04/02, page 254 of 1064
10.7.2
Register Configuration
The WDT has the two registers summarized in table 10.5. These registers control clock selection
and timer mode switching.
Table 10.5
WDT Registers
Name
Abbreviation
R/W
Initial
Value
P4 Address
Area 7
Address
Access Size
Watchdog timer
counter
WTCNT
R/W*
H'00
H'FFC00008
H'1FC00008
R: 8, W: 16*
Watchdog timer
control/status
register
WTCSR
R/W*
H'00
H'FFC0000C
H'1FC0000C
R: 8, W: 16*
Note: * Use word-size access when writing. Perform the write with the upper byte set to H'5A or
H'A5, respectively. Byte- and longword-size writes cannot be used.
Use byte access when reading.
10.8
WDT Register Descriptions
10.8.1
Watchdog Timer Counter (WTCNT)
The watchdog timer counter (WTCNT) is an 8-bit readable/writable counter that counts up on the
selected clock. When WTCNT overflows, a reset is generated in watchdog timer mode, or an
interrupt in interval timer mode. WTCNT is initialized to H'00 only by a power-on reset via the
#$% pin.
To write to the WTCNT counter, use a word-size access with the upper byte set to H'5A. To read
WTCNT, use a byte-size access.
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 255 of 1064
10.8.2
Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register
containing bits for selecting the count clock and timer mode, and overflow flags.
WTCSR is initialized to H'00 only by a power-on reset via the
#$% pin. It retains its value in
an internal reset due to WDT overflow. When used to count the clock stabilization time when
exiting standby mode, WTCSR retains its value after the counter overflows.
To write to the WTCSR register, use a word-size access with the upper byte set to H'A5. To read
WTCSR, use a byte-size access.
Bit:
7
6
5
4
3
2
1
0
TME
WT/
,7
RSTS
WOVF
IOVF
CKS2
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7--Timer Enable (TME): Specifies starting and stopping of timer operation. Clear this bit to
0 when using the WDT in standby mode or to change a clock frequency.
Bit 7: TME
Description
0
Up-count stopped, WTCNT value retained
(Initial value)
1
Up-count started
Bit 6--Timer Mode Select (WT/
,7
,7): Specifies whether the WDT is used as a watchdog timer or
interval timer.
Bit 6: WT/
,7
,7
Description
0
Interval timer mode
(Initial value)
1
Watchdog timer mode
Note: The up-count may not be performed correctly if WT/
,7
is modified while the WDT is running.
Bit 5--Reset Select (RSTS): Specifies the kind of reset to be performed when WTCNT
overflows in watchdog timer mode. This setting is ignored in interval timer mode.
Bit 5: RSTS
Description
0
Power-on reset
(Initial value)
1
Manual reset
Rev. 3.0, 04/02, page 256 of 1064
Bit 4--Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in
watchdog timer mode. This flag is not set in interval timer mode.
Bit 4: WOVF
Description
0
No overflow
(Initial value)
1
WTCNT has overflowed in watchdog timer mode
Bit 3--Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in
interval timer mode. This flag is not set in watchdog timer mode.
Bit 3: IOVF
Description
0
No overflow
(Initial value)
1
WTCNT has overflowed in interval timer mode
Bits 2 to 0--Clock Select 2 to 0 (CKS2CKS0): These bits select the clock used for the WTCNT
count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow
periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1
off, and PLL circuit 1 on (
6).
Note: * When PLL1 is switched on or off, the clock following the switch is used.
Description
Bit 2: CKS2
Bit 1: CKS1
Bit 0: CKS0
Clock Division Ratio
Overflow Period
0
0
0
1/32
(Initial value)
41
s
1
1/64
82
s
1
0
1/128
164
s
1
1/256
328
s
1
0
0
1/512
656
s
1
1/1024
1.31 ms
1
0
1/2048
2.62 ms
1
1/4096
5.25 ms
Note: The up-count may not be performed correctly if bits CKS2CKS0 are modified while the
WDT is running. Always stop the WDT before modifying these bits.
Rev. 3.0, 04/02, page 257 of 1064
10.8.3
Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR)
differ from other registers in being more difficult to write to. The procedure for writing to these
registers is given below.
Writing to WTCNT and WTCSR: These registers must be written to with a word transfer
instruction. They cannot be written to with a byte or longword transfer instruction. When writing
to WTCNT, perform the transfer with the upper byte set to H'5A and the lower byte containing the
write data. When writing to WTCSR, perform the transfer with the upper byte set to H'A5 and the
lower byte containing the write data. This transfer procedure writes the lower byte data to
WTCNT or WTCSR. The write formats are shown in figure 10.3.
15
8
7
0
H'5A
Write data
Address: H'FFC00008
(H'1FC00008)
15
8
7
0
H'A5
Write data
Address: H'FFC0000C
(H'1FC0000C)
WTCSR write
WTCNT write
Figure 10.3 Writing to WTCNT and WTCSR
Rev. 3.0, 04/02, page 258 of 1064
10.9
Using the WDT
10.9.1
Standby Clearing Procedure
The WDT is used when clearing standby mode by means of an NMI or other interrupt. The
procedure is shown below. (As the WDT does not operate when standby mode is cleared with a
reset, the
5(6(7 pin should be held low until the clock stabilizes.)
1. Be sure to clear the TME bit in the WTCSR register to 0 before making a transition to standby
mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused
when the count overflows.
2. Select the count clock to be used with bits CKS2CKS0 in the WTCSR register, and set the
initial value in the WTCNT counter. Make these settings so that the time until the count
overflows is at least as long as the clock oscillation stabilization time.
3. Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction.
4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt.
5. When the WDT count overflows, the CPG starts clock supply and the processor resumes
operation. The WOVF flag in the WTCSR register is not set at this time.
6. The counter stops at a value of H'00H'01. The value at which the counter stops depends on
the clock ratio.
10.9.2
Frequency Changing Procedure
The WDT is used in a frequency change using the PLL. It is not used when the frequency is
changed simply by making a frequency divider switch.
1. Be sure to clear the TME bit in the WTCSR register to 0 before making a frequency change. If
the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the
count overflows.
2. Select the count clock to be used with bits CKS2CKS0 in the WTCSR register, and set the
initial value in the WTCNT counter. Make these settings so that the time until the count
overflows is at least as long as the clock oscillation stabilization time.
3. When the frequency control register (FRQCR) is modified, the clock stops. The WDT starts
counting.
4. When the WDT count overflows, the CPG starts clock supply and the processor resumes
operation. The WOVF flag in the WTCSR register is not set at this time.
5.
The counter stops at a value of H'00H'01. The value at which the counter stops depends on
the clock ratio.
6.
When re-setting WTCNT immediately after modifying the frequency control register
(FRQCR), first read the counter and confirm that its value is as described in step 5 above.
Rev. 3.0, 04/02, page 259 of 1064
10.9.3
Using Watchdog Timer Mode
1. Set the WT/
,7 bit in the WTCSR register to 1, select the type of reset with the RSTS bit, and
the count clock with bits CKS2CKS0, and set the initial value in the WTCNT counter.
2. When the TME bit in the WTCSR register is set to 1, the count starts in watchdog timer mode.
3. During operation in watchdog timer mode, write H'00 to the counter periodically so that it does
not overflow.
4. When the counter overflows, the WDT sets the WOVF flag in the WTCSR register to 1, and
generates a reset of the type specified by the RSTS bit. The counter then continues counting.
10.9.4
Using Interval Timer Mode
When the WDT is operating in interval timer mode, an interval timer interrupt is generated each
time the counter overflows. This enables interrupts to be generated at fixed intervals.
1. Clear the WT/
,7 bit in the WTCSR register to 0, select the count clock with bits CKS2CKS0,
and set the initial value in the WTCNT counter.
2. When the TME bit in the WTCSR register is set to 1, the count starts in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in the WTCSR register to 1, and
sends an interval timer interrupt request to INTC. The counter continues counting.
Rev. 3.0, 04/02, page 260 of 1064
10.10
Notes on Board Design
When Using a Crystal Resonator: Place the crystal resonator and capacitors close to the EXTAL
and XTAL pins. To prevent induction from interfering with correct oscillation, ensure that no
other signal lines cross the signal lines for these pins.
EXTAL
XTAL
SH7751 Series
CL1
CL2
R
Avoid crossing signal lines
Recommended values
CL1 = CL2 = 033 pF
R = 0
Note: The values for CL1, CL2, and the damping resistance should be determined after
consultation with the crystal resonator manufacturer.
Figure 10.4 Points for Attention when Using Crystal Resonator
When Inputting External Clock from EXTAL Pin: Make no connection to the XTAL pin.
Rev. 3.0, 04/02, page 261 of 1064
When Using a PLL Oscillator Circuit: Separate VDD-CPG and VSS-CPG from the other VDD
and VSS lines at the board power supply source, and insert resistors RCB and RB, and decoupling
capacitors CPB and CB, close to the pins.
VDD-PLL1
CPB1
CPB2
CB
RCB1
Recommended values
RCB1 = RCB2 = 10
CPB1 = CPB2 = 10
F
RB = 10
CB = 10
F
RCB2
RB
1.8 V
3.3 V
VSS-PLL1
VDD-PLL2
SH7751
Series
VSS-PLL2
VDD-CPG
VSS-CPG
Figure 10.5 Points for Attention when Using PLL Oscillator Circuit
Rev. 3.0, 04/02, page 262 of 1064
Rev. 3.0, 04/02, page 263 of 1064
Section 11 Realtime Clock (RTC)
11.1
Overview
The SH7751 Series includes an on-chip realtime clock (RTC) and a 32.768 kHz crystal oscillator
for use by the RTC.
11.1.1
Features
The RTC has the following features.
Clock and calendar functions (BCD display)
Counts seconds, minutes, hours, day-of-week, days, months, and years.
1 to 64 Hz timer (binary display)
The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider
Start/stop function
30-second adjustment function
Alarm interrupts
Comparison with second, minute, hour, day-of-week, day, month, or year (SH7751R only) can
be selected as the alarm interrupt condition
Periodic interrupts
An interrupt period of 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1
second, or 2 seconds can be selected
Carry interrupt
Carry interrupt function indicating a second counter carry, or a 64 Hz counter carry when the
64 Hz counter is read
Automatic leap year adjustment
Rev. 3.0, 04/02, page 264 of 1064
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the RTC.
R64CNT
RTCCLK
16.384 kHz
32.768 kHz
128 Hz
ATI
PRI
CUI
RCR1
RCR2
RCR3
RYRCNT
RYRAR
RMONCNT
RWKCNT
RDAYCNT
RHRCNT
RMINCNT
RSECCNT
RSECAR
RMINAR
RHRAR
RDAYAR
RWKAR
RMONAR
Prescaler
RTC crystal
oscillator
RTC operation
control unit
RESET, STBY, etc
Counter unit
Interrupt
control unit
To registers
Bus interface
Internal peripheral module bus
*
*
Note:
*
SH7751R only
Figure 11.1 Block Diagram of RTC
Rev. 3.0, 04/02, page 265 of 1064
11.1.3
Pin Configuration
Table 11.1 shows the RTC pins.
Table 11.1
RTC Pins
Pin Name
Abbreviation
I/O
Function
RTC oscillator crystal pin
EXTAL2
Input
Connects crystal to RTC oscillator
RTC oscillator crystal pin
XTAL2
Output
Connects crystal to RTC oscillator
Clock input/clock output
TCLK
I/O
External clock input pin/input capture
control input pin/RTC output pin
(shared with TMU)
Dedicated RTC power
supply
V
DD
(RTC)
--
RTC oscillator power supply pin*
Dedicated RTC GND pin
V
SS
(RTC)
--
RTC oscillator GND pin*
Note: * Power must be supplied to the RTC power supply pins even when the RTC is not used.
11.1.4
Register Configuration
Table 11.2 summarizes the RTC registers.
Table 11.2
RTC Registers
Initialization
Name
Abbrevia-
tion
R/W
Power-
On
Reset
Manual
Reset
Standby
Mode
Initial
Value
P4 Address
Area 7
Address
Access
Size
64 Hz
counter
R64CNT
R
Counts Counts Counts
Undefined
H'FFC80000 H'1FC80000
8
Second
counter
RSECCNT
R/W
Counts Counts Counts
Undefined
H'FFC80004 H'1FC80004
8
Minute
counter
RMINCNT
R/W
Counts Counts Counts
Undefined
H'FFC80008 H'1FC80008
8
Hour
counter
RHRCNT
R/W
Counts Counts Counts
Undefined
H'FFC8000C H'1FC8000C 8
Day-of-
week
counter
RWKCNT
R/W
Counts Counts Counts
Undefined
H'FFC80010 H'1FC80010
8
Day
counter
RDAYCNT
R/W
Counts Counts Counts
Undefined
H'FFC80014 H'1FC80014
8
Rev. 3.0, 04/02, page 266 of 1064
Table 11.2
RTC Registers (cont)
Initialization
Name
Abbrevia-
tion
R/W
Power-On
Reset
Manual
Reset
Standby
Mode
Initial
Value
P4 Address
Area 7
Address
Access
Size
Month
counter
RMONCNT R/W
Counts
Counts
Counts
Undefined
H'FFC80018 H'1FC80018 8
Year
counter
RYRCNT
R/W
Counts
Counts
Counts
Undefined
H'FFC8001C H'1FC8001C 16
Second
alarm
register
RSECAR
R/W
Initialized*
1
Held
Held
Undefined*
1
H'FFC80020 H'1FC80020 8
Minute
alarm
register
RMINAR
R/W
Initialized*
1
Held
Held
Undefined*
1
H'FFC80024 H'1FC80024 8
Hour
alarm
register
RHRAR
R/W
Initialized*
1
Held
Held
Undefined*
1
H'FFC80028 H'1FC80028 8
Day-of-
week
alarm
register
RWKAR
R/W
Initialized*
1
Held
Held
Undefined*
1
H'FFC8002C H'1FC8002C 8
Day
alarm
register
RDAYAR
R/W
Initialized*
1
Held
Held
Undefined*
1
H'FFC80030 H'1FC80030 8
Month
alarm
register
RMONAR
R/W
Initialized*
1
Held
Held
Undefined*
1
H'FFC80034 H'1FC80034 8
RTC
control
register
1
RCR1
R/W
Initialized
Initialized
Held
H'00*
3
H'FFC80038 H'1FC80038 8
RTC
control
register
2
RCR2
R/W
Initialized
Initialized*
2
Held
H'09*
4
H'FFC8003C H'1FC8003C 8
RTC
control
register
3*
5
RCR3
R/W
Initialized
Held
Held
H'00
H'FFC80050 H'1FC80050 8
Year
alarm
register*
5
RYRAR
R/W
Held
Held
Held
Undefined
H'FFC80054 H'1FC80054 16
Notes: *1 The ENB bit in each register is initialized.
*2 Bits other than the RTCEN bit and START bit are initialized.
*3 The value of the CF bit and AF bit is undefined.
*4 The value of the PEF bit is undefined.
*5 SH7751R only
Rev. 3.0, 04/02, page 267 of 1064
11.2
Register Descriptions
11.2.1
64 Hz Counter (R64CNT)
R64CNT is an 8-bit read-only register that indicates a state of 64 Hz to 1 Hz within the RTC
frequency divider.
If this register is read when a carry is generated from the 128 kHz frequency division stage, bit 7
(CF) in RTC control register 1 (RCR1) is set to 1, indicating the simultaneous occurrence of the
carry and the 64 Hz counter read. In this case, the read value is not valid, and so R64CNT must be
read again after first writing 0 to the CF bit in RCR1 to clear it.
When the RESET bit or ADJ bit in RTC control register 2 (RCR2) is set to 1, the RTC frequency
divider is initialized and R64CNT is initialized to H'00.
R64CNT is not initialized by a power-on or manual reset, or in standby mode.
Bit 7 is always read as 0 and cannot be modified.
Bit:
7
6
5
4
3
2
1
0
--
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
Initial value:
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R
R
R
R
R
R
R
R
11.2.2
Second Counter (RSECCNT)
RSECCNT is an 8-bit readable/writable register used as a counter for setting and counting the
BCD-coded second value in the RTC. It counts on the carry (transition of the R69CNT.1Hz bit
from 0 to 1) generated once per second by the 64 Hz counter.
The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set.
Write processing should be performed after stopping the count with the START bit in RCR2, or
by using the carry flag.
RSECCNT is not initialized by a power-on or manual reset, or in standby mode.
Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit:
7
6
5
4
3
2
1
0
--
10-second units
1-second units
Initial value:
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 268 of 1064
11.2.3
Minute Counter (RMINCNT)
RMINCNT is an 8-bit readable/writable register used as a counter for setting and counting the
BCD-coded minute value in the RTC. It counts on the carry generated once per minute by the
second counter.
The setting range is decimal 00 to 59. The RTC will not operate normally if any other value is set.
Write processing should be performed after stopping the count with the START bit in RCR2, or
by using the carry flag.
RMINCNT is not initialized by a power-on or manual reset, or in standby mode.
Bit 7 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit:
7
6
5
4
3
2
1
0
--
10-minute units
1-minute units
Initial value:
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11.2.4
Hour Counter (RHRCNT)
RHRCNT is an 8-bit readable/writable register used as a counter for setting and counting the
BCD-coded hour value in the RTC. It counts on the carry generated once per hour by the minute
counter.
The setting range is decimal 00 to 23. The RTC will not operate normally if any other value is set.
Write processing should be performed after stopping the count with the START bit in RCR2, or
by using the carry flag.
RHRCNT is not initialized by a power-on or manual reset, or in standby mode.
Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always
be 0.
Bit:
7
6
5
4
3
2
1
0
--
--
10-hour units
1-hour units
Initial value:
0
0
Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 269 of 1064
11.2.5
Day-of-Week Counter (RWKCNT)
RWKCNT is an 8-bit readable/writable register used as a counter for setting and counting the
BCD-coded day-of-week value in the RTC. It counts on the carry generated once per day by the
hour counter.
The setting range is decimal 0 to 6. The RTC will not operate normally if any other value is set.
Write processing should be performed after stopping the count with the START bit in RCR2, or
by using the carry flag.
RWKCNT is not initialized by a power-on or manual reset, or in standby mode.
Bits 7 to 3 are always read as 0. A write to these bits is invalid, but the write value should always
be 0.
Bit:
7
6
5
4
3
2
1
0
--
--
--
--
--
Day-of-week code
Initial value:
0
0
0
0
0
Undefined Undefined Undefined
R/W:
R
R
R
R
R
R/W
R/W
R/W
Day-of-week code
0
1
2
3
4
5
6
Day of week
Sun
Mon
Tue
Wed
Thu
Fri
Sat
Rev. 3.0, 04/02, page 270 of 1064
11.2.6
Day Counter (RDAYCNT)
RDAYCNT is an 8-bit readable/writable register used as a counter for setting and counting the
BCD-coded day value in the RTC. It counts on the carry generated once per day by the hour
counter.
The setting range is decimal 01 to 31. The RTC will not operate normally if any other value is set.
Write processing should be performed after stopping the count with the START bit in RCR2, or
by using the carry flag.
RDAYCNT is not initialized by a power-on or manual reset, or in standby mode.
The setting range for RDAYCNT depends on the month and whether the year is a leap year, so
care is required when making the setting. Taking the year counter (RYRCNT) value as the year,
leap year calculation is performed according to whether or not the value is divisible by 400, 100,
and 4.
Bits 7 and 6 are always read as 0. A write to these bits is invalid, but the write value should always
be 0.
Bit:
7
6
5
4
3
2
1
0
--
--
10-day units
1-day units
Initial value:
0
0
Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
11.2.7
Month Counter (RMONCNT)
RMONCNT is an 8-bit readable/writable register used as a counter for setting and counting the
BCD-coded month value in the RTC. It counts on the carry generated once per month by the day
counter.
The setting range is decimal 01 to 12. The RTC will not operate normally if any other value is set.
Write processing should be performed after stopping the count with the START bit in RCR2, or
by using the carry flag.
RMONCNT is not initialized by a power-on or manual reset, or in standby mode.
Bits 7 to 5 are always read as 0. A write to these bits is invalid, but the write value should always
be 0.
Rev. 3.0, 04/02, page 271 of 1064
Bit:
7
6
5
4
3
2
1
0
--
--
--
10-month
unit
1-month units
Initial value:
0
0
0
Undefined Undefined Undefined Undefined Undefined
R/W:
R
R
R
R/W
R/W
R/W
R/W
R/W
11.2.8
Year Counter (RYRCNT)
RYRCNT is a 16-bit readable/writable register used as a counter for setting and counting the
BCD-coded year value in the RTC. It counts on the carry generated once per year by the month
counter.
The setting range is decimal 0000 to 9999. The RTC will not operate normally if any other value
is set. Write processing should be performed after stopping the count with the START bit in
RCR2, or by using the carry flag.
RYRCNT is not initialized by a power-on or manual reset, or in standby mode.
Bit:
15
14
13
12
11
10
9
8
1000-year units
100-year units
Initial value:
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
10-year units
1-year units
Initial value:
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 272 of 1064
11.2.9
Second Alarm Register (RSECAR)
RSECAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded
second value counter, RSECCNT. When the ENB bit is set to 1, the RSECAR value is compared
with the RSECCNT value. Comparison between the counter and the alarm register is performed
for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in
which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other
value is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset. The other fields in RSECAR are
not initialized by a power-on or manual reset, or in standby mode.
Bit:
7
6
5
4
3
2
1
0
ENB
10-second units
1-second units
Initial value:
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
11.2.10
Minute Alarm Register (RMINAR)
RMINAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-
coded minute value counter, RMINCNT. When the ENB bit is set to 1, the RMINAR value is
compared with the RMINCNT value. Comparison between the counter and the alarm register is
performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and
RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective
values all match.
The setting range is decimal 00 to 59 + ENB bit. The RTC will not operate normally if any other
value is set.
The ENB bit in RMINAR is initialized by a power-on reset. The other fields in RMINAR are not
initialized by a power-on or manual reset, or in standby mode.
Bit:
7
6
5
4
3
2
1
0
ENB
10-minute units
1-minute units
Initial value:
0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 273 of 1064
11.2.11
Hour Alarm Register (RHRAR)
RHRAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded
hour value counter, RHRCNT. When the ENB bit is set to 1, the RHRAR value is compared with
the RHRCNT value. Comparison between the counter and the alarm register is performed for
those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in
which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective values all match.
The setting range is decimal 00 to 23 + ENB bit. The RTC will not operate normally if any other
value is set.
The ENB bit in RHRAR is initialized by a power-on reset. The other fields in RHRAR are not
initialized by a power-on or manual reset, or in standby mode.
Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit:
7
6
5
4
3
2
1
0
ENB
--
10-hour units
1-hour units
Initial value:
0
0
Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
11.2.12
Day-of-Week Alarm Register (RWKAR)
RWKAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-coded
day-of-week value counter, RWKCNT. When the ENB bit is set to 1, the RWKAR value is
compared with the RWKCNT value. Comparison between the counter and the alarm register is
performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and
RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective
values all match.
The setting range is decimal 0 to 6 + ENB bit. The RTC will not operate normally if any other
value is set.
The ENB bit in RWKAR is initialized by a power-on reset. The other fields in RWKAR are not
initialized by a power-on or manual reset, or in standby mode.
Bits 6 to 3 are always read as 0. A write to these bits is invalid, but the write value should always
be 0.
Rev. 3.0, 04/02, page 274 of 1064
Bit:
7
6
5
4
3
2
1
0
ENB
--
--
--
--
Day-of-week code
Initial value:
0
0
0
0
0
Undefined Undefined Undefined
R/W:
R/W
R
R
R
R
R/W
R/W
R/W
Day-of-week code
0
1
2
3
4
5
6
Day of week
Sun
Mon
Tue
Wed
Thu
Fri
Sat
11.2.13
Day Alarm Register (RDAYAR)
RDAYAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-
coded day value counter, RDAYCNT. When the ENB bit is set to 1, the RDAYAR value is
compared with the RDAYCNT value. Comparison between the counter and the alarm register is
performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and
RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective
values all match.
The setting range is decimal 01 to 31 + ENB bit. The RTC will not operate normally if any other
value is set. The setting range for RDAYAR depends on the month and whether the year is a leap
year, so care is required when making the setting.
The ENB bit in RDAYAR is initialized by a power-on reset. The other fields in RDAYAR are not
initialized by a power-on or manual reset, or in standby mode.
Bit 6 is always read as 0. A write to this bit is invalid, but the write value should always be 0.
Bit:
7
6
5
4
3
2
1
0
ENB
--
10-day units
1-day units
Initial value:
0
0
Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 275 of 1064
11.2.14
Month Alarm Register (RMONAR)
RMONAR is an 8-bit readable/writable register used as an alarm register for the RTC's BCD-
coded month value counter, RMONCNT. When the ENB bit is set to 1, the RMONAR value is
compared with the RMONCNT value. Comparison between the counter and the alarm register is
performed for those registers among RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, and
RMONAR in which the ENB bit is set to 1, and the RCR1 alarm flag is set when the respective
values all match.
The setting range is decimal 01 to 12 + ENB bit. The RTC will not operate normally if any other
value is set.
The ENB bit in RMONAR is initialized by a power-on reset. The other fields in RMONAR are
not initialized by a power-on or manual reset, or in standby mode.
Bits 6 and 5 are always read as 0. A write to these bits is invalid, but the write value should always
be 0.
Bit:
7
6
5
4
3
2
1
0
ENB
--
--
10-month
unit
1-month units
Initial value:
0
0
0
Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R
R
R/W
R/W
R/W
R/W
R/W
11.2.15
RTC Control Register 1 (RCR1)
RCR1 is an 8-bit readable/writable register containing a carry flag and alarm flag, plus flags to
enable or disable interrupts for these flags.
The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value of bits other
than CIE and AIE is undefined. In standby mode RCR1 is not initialized, and retains its current
value.
Bit:
7
6
5
4
3
2
1
0
CF
--
--
CIE
AIE
--
--
AF
Initial value:
Undefined Undefined Undefined
0
0
Undefined Undefined Undefined
R/W:
R/W
R
R
R/W
R/W
R
R
R/W
Rev. 3.0, 04/02, page 276 of 1064
Bit 7--Carry Flag (CF): This flag is set to 1 on generation of a second counter carry, or a 64 Hz
counter carry when the 64 Hz counter is read. The count register value read at this time is not
guaranteed, and so the count register must be read again.
Bit 7: CF
Description
0
No second counter carry, or 64 Hz counter carry when 64 Hz counter is read
[Clearing condition]
When 0 is written to CF
1
Second counter carry, or 64 Hz counter carry when 64 Hz counter is read
[Setting conditions]
Generation of a second counter carry, or a 64 Hz counter carry when the
64 Hz counter is read
When 1 is written to CF
Bit 4--Carry Interrupt Enable Flag (CIE): Enables or disables interrupt generation when the
carry flag (CF) is set to 1.
Bit 4: CIE
Description
0
Carry interrupt is not generated when CF flag is set to 1
(Initial value)
1
Carry interrupt is generated when CF flag is set to 1
Bit 3--Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the
alarm flag (AF) is set to 1.
Bit 3: AIE
Description
0
Alarm interrupt is not generated when AF flag is set to 1
(Initial value)
1
Alarm interrupt is generated when AF flag is set to 1
Rev. 3.0, 04/02, page 277 of 1064
Bit 0--Alarm Flag (AF): Set to 1 when the alarm time set in those registers among RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, and RMONAR in which the ENB bit is set to 1
matches the respective counter values.
Bit 0: AF
Description
0
Alarm registers and counter values do not match
(Initial value)
[Clearing condition]
When 0 is written to AF
1
Alarm registers and counter values match*
[Setting condition]
When alarm registers in which the ENB bit is
set to 1 and counter values
match*
Note: * Writing 1 does not change the value.
Bits 6, 5, 2, and 1--Reserved. The initial value of these bits is undefined. A write to these bits is
invalid, but the write value should always be 0.
11.2.16
RTC Control Register 2 (RCR2)
RCR2 is an 8-bit readable/writable register used for periodic interrupt control, 30-second
adjustment, and frequency divider RESET and RTC count control.
RCR2 is basically initialized to H'09 by a power-on reset, except that the value of the PEF bit is
undefined. In a manual reset, bits other than RTCEN and START are initialized, while the value
of the PEF bit is undefined. In standby mode RCR2 is not initialized, and retains its current value.
Bit:
7
6
5
4
3
2
1
0
PEF
PES2
PES1
PES0
RTCEN
ADJ
RESET
START
Initial value:
Undefined
0
0
0
1
0
0
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 278 of 1064
Bit 7--Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by
bits PES2PES0. When this flag is set to 1, a periodic interrupt is generated.
Bit 7: PEF
Description
0
Interrupt is not generated at interval specified by bits PES2PES0
[Clearing condition]
When 0 is written to PEF
1
Interrupt is generated at interval specified by bits PES2PES0
[Setting conditions]
Generation of interrupt at interval specified by bits PES2PES0
When 1 is written to PEF
Bits 6 to 4--Periodic Interrupt Enable (PES2PES0): These bits specify the period for periodic
interrupts.
Bit 6: PES2
Bit 5: PES1
Bit 4: PES0
Description
0
0
0
No periodic interrupt generation
(Initial value)
1
Periodic interrupt generated at 1/256-second intervals
1
0
Periodic interrupt generated at 1/64-second intervals
1
Periodic interrupt generated at 1/16-second intervals
1
0
0
Periodic interrupt generated at 1/4-second intervals
1
Periodic interrupt generated at 1/2-second intervals
1
0
Periodic interrupt generated at 1-second intervals
1
Periodic interrupt generated at 2-second intervals
Bit 3--Oscillator Enable (RTCEN): Controls the operation of the RTC's crystal oscillator.
Bit 3: RTCEN
Description
0
RTC crystal oscillator is halted
1
RTC crystal oscillator is operated
(Initial value)
Rev. 3.0, 04/02, page 279 of 1064
Bit 2--30-Second Adjustment (ADJ): Used for 30-second adjustment. When 1 is written to this
bit, a value up to 29 seconds is rounded down to 00 seconds, and a value of 30 seconds or more is
rounded up to 1 minute. The frequency divider circuits (RTC prescaler and R64CNT) are also
reset at this time. This bit always returns 0 if read.
Bit 2: ADJ
Description
0
Normal clock operation
(Initial value)
1
30-second adjustment performed
Bit 1--Reset (RESET): The frequency divider circuits are initialized by writing 1 to this bit.
When 1 is written to the RESET bit, the frequency divider circuits (RTC prescaler and R64CNT)
are reset and the RESET bit is automatically cleared to 0 (i.e. does not need to be written with 0).
Bit 1: RESET
Description
0
Normal clock operation
(Initial value)
1
Frequency divider circuits are reset
Bit 0--Start Bit (START): Stops and restarts counter (clock) operation.
Bit 0: START
Description
0
Second, minute, hour, day, day-of-week, month, and year counters are
stopped*
1
Second, minute, hour, day, day-of-week, month, and year counters operate
normally*
(Initial value)
Note: * The 64 Hz counter continues to operate unless stopped by means of the RTCEN bit.
Rev. 3.0, 04/02, page 280 of 1064
11.2.17
RTC Control Register (RCR3) and Year-Alarm Register (RYRAR)
(SH7751R Only)
RCR3 and RYRAR are readable/writable registers. RYRAR is the alarm register for the RTC's
BCD-coded year-value counter RYRCNT. When the YENB bit of RCR3 is set to 1, the RYRCNT
value is compared with the RYRAR value. Comparison between the counter and the alarm register
only takes place with the alarm registers in which the ENB and YENB bits are set to 1. The alarm
flag of RCR1 is only set to 1 when the respective values all match.
The setting range of RYRAR is decimal 0000 to 9999, and normal operation is not obtained if a
value beyond this range is set here.
RCR3 is initialized by a power-on reset, but RYRAR will not be initialized by a power-on or
manual reset, or by the device entering standby mode.
Bits 6 to 0 of RCR3 are always read as 0. A write to these bits is invalid. If a value is written to
these bits, it should always be 0.
RCR3
Bit:
7
6
5
4
3
2
1
0
YENB
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R
R
R
R
R
R
R
RYRAR
Bit:
15
14
13
12
11
10
9
8
1000 years
100 years
Initial value:
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
10 years
1 year
Initial value:
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 281 of 1064
11.3
Operation
Examples of the use of the RTC are shown below.
11.3.1
Time Setting Procedures
Figure 11.2 shows examples of the time setting procedures.
Stop clock
Reset frequency divider
Set second/minute/hour/day/
day-of-week/month/year
Start clock operation
Set RCR2.RESET to 1
Clear RCR2.START to 0
In any order
Set RCR2.START to 1
(a) Setting time after stopping clock
Clear carry flag
Write to counter register
Carry flag = 1?
No
Yes
Clear RCR1.CF to 0
(Write 1 to RCR1.AF so that alarm flag
is not cleared)
Set RYRCNT first and RSECCNT last
Read RCR1 register and check CF bit
(b) Setting time while clock is running
Figure 11.2 Examples of Time Setting Procedures
The procedure for setting the time after stopping the clock is shown in figure 11.2 (a). The
programming for this method is simple, and it is useful for setting all the counters, from second to
year.
Rev. 3.0, 04/02, page 282 of 1064
The procedure for setting the time while the clock is running is shown in figure 11.2 (b). This
method is useful for modifying only certain counter values (for example, only the second data or
hour data). If a carry occurs during the write operation, the write data is automatically updated and
there will be an error in the set data. The carry flag should therefore be used to check the write
status. If the carry flag (RCR1.CF) is set to 1, the write must be repeated.
The interrupt function can also be used to determine the carry flag status.
11.3.2
Time Reading Procedures
Figure 11.3 shows examples of the time reading procedures.
Rev. 3.0, 04/02, page 283 of 1064
Disable carry interrupts
Clear carry flag
Read counter register
Carry flag = 1?
Clear RCR1.CIE to 0
Clear RCR1.CF to 0
(Write 1 to RCR1.AF so that alarm flag
is not cleared)
Read RCR1 register and check CF bit
(a) Reading time without using interrupts
No
Yes
Clear carry flag
Enable carry interrupts
Clear carry flag
Read counter register
Interrupt generated?
Yes
Disable carry interrupts
No
(b) Reading time using interrupts
Set RCR1.CIE to 1
Clear RCR1.CF to 0
(Write 1 to RCR1.AF so that alarm flag
is not cleared)
Clear RCR1.CIE to 0
Figure 11.3 Examples of Time Reading Procedures
If a carry occurs while the time is being read, the correct time will not be obtained and the read
must be repeated. The procedure for reading the time without using interrupts is shown in figure
11.3 (a), and the procedure using carry interrupts in figure 11.3 (b). The method without using
interrupts is normally used to keep the program simple.
Rev. 3.0, 04/02, page 284 of 1064
11.3.3
Alarm Function
The use of the alarm function is illustrated in figure 11.4.
Clock running
Disable alarm interrupts
Set alarm time
Clear alarm flag
Enable alarm interrupts
Monitor alarm time
(Wait for interrupt or check
alarm flag)
Clear RCR1.AIE to prevent erroneous interrupts
Be sure to reset the flag as it may have been
set during alarm time setting
Set RCR1.AIE to 1
Figure 11.4 Example of Use of Alarm Function
An alarm can be generated by the second, minute, hour, day-of-week, day, month, or year
(SH7751R only) value, or a combination of these. Write 1 to the ENB bit in the alarm registers
involved in the alarm setting, and set the alarm time in the lower bits. Write 0 to the ENB bit in
registers not involved in the alarm setting.
When the counter and the alarm time match, RCR1.AF is set to 1. Alarm detection can be
confirmed by reading this bit, but normally an interrupt is used. If 1 has been written to
RCR1.AIE, an alarm interrupt is generated in the event of alarm, enabling the alarm to be
detected.
The alarm flag remains set while the counter and alarm time match. If the alarm flag is cleared by
writing 0 during this period, it will therefore be set again immediately afterward. This needs to be
taken into consideration when writing the program.
Rev. 3.0, 04/02, page 285 of 1064
11.4
Interrupts
There are three kinds of RTC interrupt: alarm interrupts, periodic interrupts, and carry interrupts.
An alarm interrupt request (ATI) is generated when the alarm flag (AF) in RCR1 is set to 1 while
the alarm interrupt enable bit (AIE) is also set to 1.
A periodic interrupt request (PRI) is generated when the periodic interrupt enable bits (PES2
PES0) in RCR2 are set to a value other than 000 and the periodic interrupt flag (PEF) is set to 1.
A carry interrupt request (CUI) is generated when the carry flag (CF) in RCR1 is set to 1 while the
carry interrupt enable bit (CIE) is also set to 1.
11.5
Usage Notes
11.5.1
Register Initialization
After powering on and making the RCR1 register settings, reset the frequency divider (by setting
RCR2.RESET to 1) and make initial settings for all the other registers.
11.5.2
Carry Flag and Interrupt Flag in Standby Mode
When the carry flag or interrupt flag is set to 1 at the same time this LSI transits to normal mode
from standby mode by a reset or interrupt, the flag may not be set to 1. After exiting standby
mode, check the counters to judge the flag states if necessary.
11.5.3
Crystal Oscillator Circuit
Crystal oscillator circuit constants (recommended values) are shown in table 11.3, and the RTC
crystal oscillator circuit in figure 11.5.
Table 11.3
Crystal Oscillator Circuit Constants (Recommended Values)
f
osc
C
in
C
out
32.768 kHz
1022 pF
1022 pF
Rev. 3.0, 04/02, page 286 of 1064
SH7751
Series
EXTAL2
XTAL2
XTAL
C
in
C
out
R
f
R
D
Noise filter
C
RTC
R
RTC
3.3 V
VDD-RTC
VSS-RTC
Notes: 1. Select either the C
in
or C
out
side for the frequency adjustment variable capacitor according to
requirements such as the adjustment range, degree of stability, etc.
2. Built-in resistance value R
f
(typ. value) = 10 M
, R
D
(typ. value) = 400 k
3. C
in
and C
out
values include floating capacitance due to the wiring. Take care when using a solid-
earth board.
4. The crystal oscillation stabilization time depends on the mounted circuit constants, floating
capacitance, etc., and should be decided after consultation with the crystal resonator
manufacturer.
5. Place the crystal resonator and load capacitors C
in
and C
out
as close as possible to the chip.
(Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and
XTAL2 pins.)
6. Ensure that the crystal resonator connection pin (EXTAL2 and XTAL2) wiring is routed as far away
as possible from other power lines (except GND) and signal lines.
7. Insert a noise filter in the RTC power supply.
Figure 11.5 Example of Crystal Oscillator Circuit Connection
Rev. 3.0, 04/02, page 287 of 1064
Section 12 Timer Unit (TMU)
12.1
Overview
The SH7751 Series includes an on-chip 32-bit timer unit (TMU) comprising five 32-bit timer
channels (channels 0 to 4).
12.1.1
Features
The TMU has the following features.
Auto-reload type 32-bit down-counter provided for each channel
Input capture function provided in channel 2
Selection of rising edge or falling edge as external clock input edge when external clock is
selected or input capture function is used
32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit
down-counter provided for each channel
Selection of seven counter input clocks for channels 0 to 2
External clock (TCLK), on-chip RTC output clock, five internal clocks (P
/4, P
/16, P
/64,
P
/256, P
/1024) (P
is the peripheral module clock)
Selection of five internal clocks for channels 3 and 4
Channels 0 to 2 can also operate in module standby mode when the on-chip RTC output clock
is selected as the counter input clock; that is, timer operation continues even when the clock
has been stopped for the TMU.
Timer count operations using an external or internal clock are only possible when a clock is
supplied to the timer unit.
Two interrupt sources
One underflow source (channels 0 to 4) and one input capture source (channel 2)
DMAC data transfer request capability
On channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is
generated.
Rev. 3.0, 04/02, page 288 of 1064
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the TMU.
RESET, STBY,
etc.
TUNI0,1
PCLK/4, 16, 64*
TUNI2
TICPI2
TCLK RTCCLK
TUNI3, TUNI4
TOCR
TSTR
TSTR2
TCNT
TCOR
TCR
TCPR2
TCNT2
TCOR2
TCR2
TCNT
TCOR
TCR
Bus interface
Internal peripheral module bus
Note: * Signals with 1/4, 1/16, and 1/64 the P
frequency, supplied to the on-chip peripheral functions.
Counter unit
Interrupt
control unit
Counter unit
Interrupt
control unit
Counter unit
Interrupt
control unit
Ch 0,1
Ch 2
Ch 3,4
TMU
operation
control unit
Prescaler
TCLK
control unit
To chan-
nels
0 to 4
To chan-
nels
0 to 2
Figure 12.1 Block Diagram of TMU
12.1.3
Pin Configuration
Table 12.1 shows the TMU pins.
Table 12.1
TMU Pins
Pin Name
Abbreviation
I/O
Function
Clock input/clock output
TCLK
I/O
External clock input pin/input capture
control input pin/RTC output pin
(shared with RTC)
Rev. 3.0, 04/02, page 289 of 1064
12.1.4
Register Configuration
Table 12.2 summarizes the TMU registers.
Table 12.2
TMU Registers
Initialization
Chan-
nel
Name
Abbre-
viation R/W
Power-
On
Reset
Manual
Reset
Stand-
by
Mode
Initial Value P4 Address
Area 7
Address
Access
Size
Com-
mon
Timer
output
control
register
TOCR
R/W Ini-
tialized
Ini-
tialized
Held
H'00
H'FFD80000 H'1FD80000 8
Timer
start
register
TSTR
R/W Ini-
tialized
Ini-
tialized
Ini-
tialized*
1
H'00
H'FFD80004 H'1FD80004 8
Timer
start
register 2
TSTR2 R/W Ini-
tialized
Held
Held
H'00
H'FE100004 H'1E100004
8
0
Timer
constant
register 0
TCOR0 R/W Ini-
tialized
Ini-
tialized
Held
H'FFFFFFFF H'FFD80008 H'1FD80008 32
Timer
counter 0
TCNT0 R/W Ini-
tialized
Ini-
tialized
Held*
2
H'FFFFFFFF H'FFD8000C H'1FD8000C 32
Timer
control
register 0
TCR0
R/W Ini-
tialized
Ini-
tialized
Held
H'0000
H'FFD80010 H'1FD80010 16
1
Timer
constant
register 1
TCOR1 R/W Ini-
tialized
Ini-
tialized
Held
H'FFFFFFFF H'FFD80014 H'1FD80014 32
Timer
counter 1
TCNT1 R/W Ini-
tialized
Ini-
tialized
Held*
2
H'FFFFFFFF H'FFD80018 H'1FD80018 32
Timer
control
register 1
TCR1
R/W Ini-
tialized
Ini-
tialized
Held
H'0000
H'FFD8001C H'1FD8001C 16
2
Timer
constant
register 2
TCOR2 R/W Ini-
tialized
Ini-
tialized
Held
H'FFFFFFFF H'FFD80020 H'1FD80020 32
Timer
counter 2
TCNT2 R/W Ini-
tialized
Ini-
tialized
Held*
2
H'FFFFFFFF H'FFD80024 H'1FD80024 32
Timer
control
register 2
TCR2
R/W Ini-
tialized
Ini-
tialized
Held
H'0000
H'FFD80028 H'1FD80028 16
Input
capture
register
TCPR2 R
Held
Held
Held
Undefined
H'FFD8002C H'1FD8002C 32
Rev. 3.0, 04/02, page 290 of 1064
Table 12.2
TMU Registers (cont)
Initialization
Chan-
nel
Name
Abbre-
viation R/W
Power-
On
Reset
Manual
Reset
Stand-
by
Mode
Initial Value P4 Address
Area 7
Address
Access
Size
3
Timer
constant
register 3
TCOR3 R/W Ini-
tialized
Held
Held
H'FFFFFFFF H'FE100008 H'1E100008
32
Timer
counter 3
TCNT3 R/W Ini-
tialized
Held
Held
H'FFFFFFFF H'FE10000C H'1E10000C 32
Timer
control
register 3
TCR3
R/W Ini-
tialized
Held
Held
H'0000
H'FE100010 H'1E100010
16
4
Timer
constant
register 4
TCOR4 R/W Ini-
tialized
Held
Held
H'FFFFFFFF H'FE100014 H'1E100014
32
Timer
counter 4
TCNT4 R/W Ini-
tialized
Held
Held
H'FFFFFFFF H'FE100018 H'1E100018
32
Timer
control
register 4
TCR4
R/W Ini-
tialized
Held
Held
H'0000
H'FE10001C H'1E10001C 16
Notes: *1 Not initialized in module standby mode when the input clock is the on-chip RTC output
clock.
*2 Counts in module standby mode when the input clock is the on-chip RTC output clock.
12.2
Register Descriptions
12.2.1
Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable register that specifies whether external pin TCLK is used as
the external clock or input capture control input pin, or as the on-chip RTC output clock output
pin.
TOCR is initialized to H'00 by a power-on or manual reset, but is not initialized in standby mode.
Bit:
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
TCOE
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bits 7 to 1--Reserved: These bits are always read as 0. A write to these bits is invalid, but the
write value should always be 0.
Rev. 3.0, 04/02, page 291 of 1064
Bit 0--Timer Clock Pin Control (TCOE): Specifies whether timer clock pin TCLK is used as
the external clock or input capture control input pin, or as the on-chip RTC output clock output
pin.
Bit 0: TCOE
Description
0
Timer clock pin (TCLK) is used as external clock input or input capture
control input pin
(Initial value)
1
Timer clock pin (TCLK) is used as on-chip RTC output clock output pin*
Note: * Low-level output in standby mode; high-impedance output in hardware standby mode.
12.2.2
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that specifies whether the channel 02 timer counters
(TCNT) are operated or stopped.
TSTR is initialized to H'00 by a power-on or manual reset. In module standby mode, TSTR is not
initialized when the input clock selected by each channel is the on-chip RTC output clock
(RTCCLK), and is initialized only when the input clock is the external clock (TCLK) or internal
clock (P
).
Bit:
7
6
5
4
3
2
1
0
--
--
--
--
--
STR2
STR1
STR0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
Bits 7 to 3--Reserved: These bits are always read as 0. A write to these bits is invalid, but the
write value should always be 0.
Bit 2--Counter Start 2 (STR2): Specifies whether timer counter 2 (TCNT2) is operated or
stopped.
Bit 2: STR2
Description
0
TCNT2 count operation is stopped
(Initial value)
1
TCNT2 performs count operation
Rev. 3.0, 04/02, page 292 of 1064
Bit 1--Counter Start 1 (STR1): Specifies whether timer counter 1 (TCNT1) is operated or
stopped.
Bit 1: STR1
Description
0
TCNT1 count operation is stopped
(Initial value)
1
TCNT1 performs count operation
Bit 0--Counter Start 0 (STR0): Specifies whether timer counter 0 (TCNT0) is operated or
stopped.
Bit 0: STR0
Description
0
TCNT0 count operation is stopped
(Initial value)
1
TCNT0 performs count operation
12.2.3
Timer Start Register 2 (TSTR2)
TSTR2 is an 8-bit readable/writable register that specifies whether the channel 3 and 4 timer
counters (TCNT) are operated or stopped.
TSTR2 is initialized to H'00 by a power-on reset. TSTR retain their contents in standby mode.
When standby mode is entered when the value of either STR3 or STR4 is 1, the count halts when
the peripheral module clock stops and restarts when the clock supply is resumed.
Bit:
7
6
5
4
3
2
1
0
--
--
--
--
--
--
STR4
STR3
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R/W
R/W
Bits 7 to 2--Reserved: These bits are always read as 0. A write to these bits is invalid, but the
write value should always be 0.
Bit 1--Counter Start 4 (STR4): Specifies whether timer counter 4 (TCNT4) is operated or
stopped.
Bit 1: STR4
Description
0
TCNT4 count operation is stopped
(Initial value)
1
TCNT4 performs count operation
Rev. 3.0, 04/02, page 293 of 1064
Bit 0--Counter Start 3 (STR3): Specifies whether timer counter 3 (TCNT3) is operated or
stopped.
Bit 0: STR3
Description
0
TCNT3 count operation is stopped
(Initial value)
1
TCNT3 performs count operation
12.2.4
Timer Constant Registers (TCOR)
The TCOR registers are 32-bit readable/writable registers. There are five TCOR registers, one for
each channel.
When a TCNT counter underflows while counting down, the TCOR value is set in that TCNT,
which continues counting down from the set value.
The TCOR registers in channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual
reset, but are not initialized and retain their contents in standby mode.
The TCOR registers in channels 3 and 4 are initialized to H'FFFFFFFF by a power-on reset, but
are not initialized and retain their contents by a manual reset or in standby mode.
Bit:
31
30
29
2
1
0
Initial value:
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
12.2.5
Timer Counters (TCNT)
The TCNT registers are 32-bit readable/writable registers. There are five TCNT registers, one for
each channel.
Each TCNT counts down on the input clock selected by TPSC2TPSC0 in the timer control
register (TCR).
When a TCNT counter underflows while counting down, the underflow flag (UNF) is set in the
corresponding timer control register (TCR). At the same time, the timer constant register (TCOR)
value is set in TCNT, and the count-down operation continues from the set value.
The TCNT registers in channels 0 to 2 are initialized to H'FFFFFFFF by a power-on or manual
reset, but are not initialized and retain their contents in standby mode.
Rev. 3.0, 04/02, page 294 of 1064
The TCNT registers in channels 3 and 4 are initialized to H'FFFFFFFF by a power-on reset, but
are not initialized and retain their contents by a manual reset or in standby mode.
Bit:
31
30
29
2
1
0
Initial value:
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
In channels 0 to 2, when the input clock is the on-chip RTC output clock (RTCCLK), TCNT
counts even in module standby mode (that is, when the clock for the TMU is stopped). When the
input clock is the external clock (TCLK) or internal clock (P
), TCNT contents are retained in
standby mode.
12.2.6
Timer Control Registers (TCR)
The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for
each channel.
Each TCR selects the count clock, specifies the edge when an external clock is selected in
channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT)
underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of
interrupt generation in the event of input capture.
The TCR registers in channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but
are not initialized in standby mode.
The TCR registers in channels 3 and 4 are initialized to H'0000 by a power-on reset, but are not
initialized by a manual reset or in standby mode.
1. Channel 0 and 1 TCR bit configuration
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
UNF
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
--
--
UNIE
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 295 of 1064
2. Channel 2 TCR bit configuration
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
ICPF
UNF
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
ICPE1
ICPE0
UNIE
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3. Channel 3 and 4 TCR bit configuration
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
UNF
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
--
--
UNIE
--
--
TPSC2
TPSC1
TPSC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R/W
R
R
R/W
R/W
R/W
Bits 15 to 9, 7, and 6 (Channels 0 and 1); Bits 15 to 10 (Channel 2)--Reserved: These bits are
always read as 0. A write to these bits is invalid, but the write value should always be 0.
Bit 9--Input Capture Interrupt Flag (ICPF) (Channel 2 Only): Status flag, provided in
channel 2 only, that indicates the occurrence of input capture.
Bit 9: ICPF
Description
0
Input capture has not occurred
(Initial value)
[Clearing condition]
When 0 is written to ICPF
1
Input capture has occurred
[Setting condition]
When input capture occurs*
Note: * Writing 1 does not change the value.
Rev. 3.0, 04/02, page 296 of 1064
Bit 8--Underflow Flag (UNF): Status flag that indicates the occurrence of underflow.
Bit 8: UNF
Description
0
TCNT has not underflowed
(Initial value)
[Clearing condition]
When 0 is written to UNF
1
TCNT has underflowed
[Setting condition]
When TCNT underflows*
Note: * Writing 1 does not change the value.
Bits 7 and 6--Input Capture Control (ICPE1, ICPE0) (Channel 2 Only): These bits, provided
in channel 2 only, specify whether the input capture function is used, and control enabling or
disabling of interrupt generation when the function is used.
When the input capture function is used, a data transfer request is sent to the DMAC in the event
of input capture.
When using the input capture function, the TCLK pin must be designated as an input pin with the
TCOE bit in the TOCR register. The CKEG bits specify whether the rising edge or falling edge of
the TCLK signal is used to set the TCNT2 value in the input capture register (TCPR2).
The TCNT2 value is set in TCPR2 only when the TCR2.ICPF bit is 0. When the TCR2.ICPF bit is
1, TCPR2 is not set in the event of input capture. When input capture occurs, a DMAC transfer
request is generated regardless of the value of the TCR2.ICPF bit. However, a new DMAC
transfer request is not generated until processing of the previous request is finished.
Bit 7: ICPE1
Bit 6: ICPE0
Description
0
0
Input capture function is not used
(Initial value)
1
Reserved (Do not set)
1
0
Input capture function is used, but interrupt due to input capture
(TICPI2) is not enabled
Data transfer request is sent to DMAC in the event of input
capture
1
Input capture function is used, and interrupt due to input
capture (TICPI2) is enabled
Data transfer request is sent to DMAC in the event of input
capture
Bit 5--Underflow Interrupt Control (UNIE): Controls enabling or disabling of interrupt
generation when the UNF status flag is set to 1, indicating TCNT underflow.
Rev. 3.0, 04/02, page 297 of 1064
Bit 5: UNIE
Description
0
Interrupt due to underflow (TUNI) is not enabled
(Initial value)
1
Interrupt due to underflow (TUNI) is enabled
Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): In channels 0 to 2, these bits select the
external clock input edge when an external clock is selected or the input capture function is used.
Bit 4: CKEG1
Bit 3: CKEG0
Description
0
0
Count/input capture register set on rising edge
(Initial value)
1
Count/input capture register set on falling edge
1
X
Count/input capture register set on both rising and falling edges
Note: X: 0 or 1 (don't care)
Bits 2 to 0--Timer Prescaler 2 to 0 (TPSC2TPSC0): In channels 0 to 2, these bits select the
TCNT count clock.
When the on-chip RTC output clock is selected as the count clock for a channel, that channel can
operate even in module standby mode. When another clock is selected, the channel does not
operate in standby mode.
Bit 2: TPSC2
Bit 1: TPSC1
Bit 0: TPSC0
Description
0
0
0
Counts on P
/4
(Initial value)
1
Counts on P
/16
1
0
Counts on P
/64
1
Counts on P
/256
1
0
0
Counts on P
/1024
1
Reserved (Do not set)
1
0
Counts on on-chip RTC output clock (Do not
set in channels 3 and 4)
1
Counts on external clock (Do not set in
channels 3 and 4)
12.2.7
Input Capture Register (TCPR2)
TCPR2 is a 32-bit read-only register for use with the input capture function, provided only in
channel 2.
The input capture function is controlled by means of the input capture control bits (ICPE1, ICPE0)
and clock edge bits (CKEG1, CKEG0) in TCR2. When input capture occurs, the TCNT2 value is
copied into TCPR2. The value is set in TCPR2 only when the ICPF bit in TCR2 is 0.
Rev. 3.0, 04/02, page 298 of 1064
TCPR2 is not initialized by a power-on or manual reset, or in standby mode.
Bit:
31
30
29
2
1
0
Initial value:
Undefined
R/W:
R
R
R
R
R
R
12.3 Operation
Each channel has a 32-bit timer counter (TCNT) that performs count-down operations, and a 32-
bit timer constant register (TCOR). The channels have an auto-reload function that allows cyclic
count operations, and can also perform external event counting. Channel 2 also has an input
capture function.
12.3.1
Counter Operation
When one of bits STR0STR4 is set to 1 in the timer start register (TSTR, TSTR2), the timer
counter (TCNT) for the corresponding channel starts counting. When TCNT underflows, the UNF
flag is set in the corresponding timer control register (TCR). If the UNIE bit in TCR is set to 1 at
this time, an interrupt request is sent to the CPU. At the same time, the value is copied from
TCOR into TCNT, and the count-down continues (auto-reload function).
Example of Count Operation Setting Procedure: Figure 12.2 shows an example of the count
operation setting procedure.
1. Select the count clock with bits TPSC2TPSC0 in the timer control register (TCR). When an
external clock in channels 0 to 2 is selected, set the TCLK pin to input mode with the TCOE
bit in TOCR, and select the external clock edge with bits CKEG1 and CKEG0 in TCR.
2. Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR.
3. When the input capture function is used, set the ICPE bits in TCR, including specification of
whether the interrupt function is to be used.
4. Set a value in the timer constant register (TCOR).
5. Set the initial value in the timer counter (TCNT).
6. Set the STR bit to 1 in the timer start register (TSTR, TSTR2) to start the count.
Rev. 3.0, 04/02, page 299 of 1064
1
2
Operation selection
Select count clock
Underflow interrupt
generation setting
When input capture
function is used
3
4
5
6
Input capture interrupt
generation setting
Timer constant
register setting
Set initial timer
counter value
Start count
Note: When an interrupt is generated, clear the source flag in the interrupt handler. If the interrupt
enabled state is set without clearing the flag, another interrupt will be generated.
Figure 12.2 Example of Count Operation Setting Procedure
Auto-Reload Count Operation: Figure 12.3 shows the TCNT auto-reload operation.
TCOR
H'00000000
STR0STR4
UNF
TCNT value
TCOR value set in TCNT
on underflow
Time
Figure 12.3 TCNT Auto-Reload Operation
Rev. 3.0, 04/02, page 300 of 1064
TCNT Count Timing:
Operating on internal clock
Any of five count clocks (P
/4, P
/16, P
/64, P
/256, or P
/1024) scaled from the peripheral
module clock can be selected as the count clock by means of the TPSC2TPSC0 bits in TCR.
Figure 12.4 shows the timing in this case.
P
Internal clock
TCNT
N + 1
N
N 1
Figure 12.4 Count Timing when Operating on Internal Clock
Operating on external clock
In channels 0 to 2, external clock pin (TCLK) input can be selected as the timer clock by
means of the TPSC2TPSC0 bits in TCR. The detected edge (rising, falling, or both edges)
can be selected with the CKEG1 and CKEG0 bits in TCR.
Figure 12.5 shows the timing for both-edge detection.
N + 1
N 1
N
P
External clock
input pin
TCNT
Figure 12.5 Count Timing when Operating on External Clock
Operating on on-chip RTC output clock
In channels 0 to 2, the on-chip RTC output clock can be selected as the timer clock by means
of the TPSC2TPSC0 bits in TCR. Figure 12.6 shows the timing in this case.
Rev. 3.0, 04/02, page 301 of 1064
N + 1
N
N 1
RTC output clock
TCNT
Figure 12.6 Count Timing when Operating on On-Chip RTC Output Clock
12.3.2
Input Capture Function
Channel 2 has an input capture function.
The procedure for using the input capture function is as follows:
1. Use the TCOE bit in the timer output control register (TOCR) to set the TCLK pin to input
mode.
2. Use bits TPSC2TPSC0 in the timer control register (TCR) to set an internal clock or the on-
chip RTC output clock as the timer operating clock.
3. Use bits IPCE1 and IPCE0 in TCR to specify use of the input capture function, and whether
interrupts are to generated when this function is used.
4. Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the
TCLK signal is to be used to set the timer counter (TCNT) value in the input capture register
(TCPR2).
This function cannot be used in standby mode.
When input capture occurs, the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is
0. Also, a new DMAC transfer request is not generated until processing of the previous request is
finished.
Figure 12.7 shows the operation timing when the input capture function is used (with TCLK rising
edge detection).
Rev. 3.0, 04/02, page 302 of 1064
TCOR
H'00000000
TCLK
TCPR2
TICPI2
TCNT value
TCOR value set in TCNT
on underflow
TCNT value set
Time
Figure 12.7 Operation Timing when Using Input Capture Function
12.4
Interrupts
There are four TMU interrupt sources, comprising underflow interrupts and the input capture
interrupt (when the input capture function is used). Underflow interrupts are generated on
channels 0 to 4, and input capture interrupts on channel 2 only.
An underflow interrupt request is generated (on an individual channel basis) when TCR.UNF = 1
and the channel's interrupt enable bit is 1.
When the input capture function is used and an input capture request is generated, an interrupt is
requested if the input capture input flag (ICPF) in TCR2 is 1 and the input capture control bits
(ICPE1, ICPE0) in TCR2 are 11.
The TMU interrupt sources are summarized in table 12.3.
Rev. 3.0, 04/02, page 303 of 1064
Table 12.3
TMU Interrupt Sources
Channel
Interrupt Source
Description
0
TUNI0
Underflow interrupt 0
1
TUNI1
Underflow interrupt 1
2
TUNI2
Underflow interrupt 2
TICPI2
Input capture interrupt 2
3
TUNI3
Underflow interrupt 3
4
TUNI4
Underflow interrupt 4
12.5
Usage Notes
12.5.1
Register Writes
When performing a TMU register write, timer count operation must be stopped by clearing the
start bit (STR0STR4) for the relevant channel in the timer start register (TSTR, TSTR2).
Note that the timer start register (TSTR, TSTR2) can be written to, and the underflow flag (UNF)
and input capture flag (ICPF) of the timer control registers (TRCR0 to TCR4) can be cleared
while the count is in progress. When the flags (UNF and ICPF) are cleared while the count is in
progress, make sure not to change the values of bits other than those being cleared.
12.5.2
TCNT Register Reads
When performing a TCNT register read, processing for synchronization with the timer count
operation is performed. If a timer count operation and register read processing are performed
simultaneously, the TCNT counter value prior to the count-down operation is read by means of the
synchronization processing.
12.5.3
Resetting the RTC Frequency Divider
When the on-chip RTC output clock is selected as the count clock, the RTC frequency divider
should be reset.
12.5.4
External Clock Frequency
Ensure that the external clock frequency for any channel does not exceed P
/4.
Rev. 3.0, 04/02, page 304 of 1064
Rev. 3.0, 04/02, page 305 of 1064
Section 13 Bus State Controller (BSC)
13.1
Overview
The functions of the bus state controller (BSC) include division of the external memory space, and
output of control signals in accordance with various types of memory and bus interface
specifications. The BSC functions allow DRAM, synchronous DRAM, SRAM, ROM, etc., to be
connected to the SH7751 Series and also support the PCMCIA interface protocol, enabling system
design to be simplified and data transfers to be carried out at high speed by a compact system.
13.1.1
Features
The BSC has the following features:
External memory space is managed as 7 independent areas
Maximum 64 Mbytes for each of areas 0 to 6
Bus width of each area can be set in a register (except area 0, which uses an external pin
setting)
Wait state insertion by
5'< pin
Wait state insertion can be controlled by program
Specification of types of memory connectable to each area
Output the control signals of memory to each area
Automatic wait cycle insertion to prevent data bus collisions in case of consecutive
memory accesses to different areas, or a read access followed by a write access to the same
area
Write strobe setup time and hold time periods can be inserted in a write cycle to enable
connection to low-speed memory
SRAM interface
Wait state insertion can be controlled by program
Wait state insertion by
5'< pin
Connectable areas: 0 to 6
Settable bus widths: 32, 16, 8
DRAM interface
Row address/column address multiplexing according to DRAM capacity
Burst operation (fast page mode, EDO mode)
CAS-before-RAS refresh and self-refresh
4-CAS byte control for power-down operation
DRAM control signal timing can be controlled by register settings
Rev. 3.0, 04/02, page 306 of 1064
Consecutive accesses to the same row address
Connectable area: 3
Settable bus widths: 32, 16
Synchronous DRAM interface
Row address/column address multiplexing according to synchronous DRAM capacity
Burst operation
Auto-refresh and self-refresh
Synchronous DRAM control signal timing can be controlled by register settings
Consecutive accesses to the same row address
Connectable areas: 2, 3
Settable bus widths: 32
Burst ROM interface
Wait state insertion can be controlled by program
Burst operation, executing the number of transfers set in a register
Connectable areas: 0, 5, 6
Settable bus widths: 32, 16, 8
MPX interface
Address/data multiplexing
Connectable areas: 0 to 6
Settable bus widths: 32
Byte control SRAM interface
SRAM interface with byte control
Connectable areas: 1, 4
Settable bus widths: 32, 16
PCMCIA interface
Wait state insertion can be controlled by program
Bus sizing function for I/O bus width
Fine refreshing control
Supports refresh operation immediately after self-refresh operation in low-power DRAM
by means of refresh counter overflow interrupt function
Refresh counter can be used as interval timer
Interrupt request generated by compare-match
Interrupt request generated by refresh counter overflow
Rev. 3.0, 04/02, page 307 of 1064
13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the BSC.
RD/
,
CKE
,
Internal bus
Bus
interface
WCR1
RTCNT
RTCOR
RTCSR
Comparator
Refresh
control unit
Memory
control unit
Area
control unit
Wait
control unit
Interrupt
controller
BSC
Peripheral bus
WCR: Wait control register
BCR: Bus control register
MCR: Memory control register
PCR: PCMCIA control register
Note:
*
SH7751R only
WCR2
WCR3
BCR1
BCR2
BCR3
*
BCR4
*
PCR
RFCR
MCR
Module bus
RFCR:
Refresh count register
RTCNT: Refresh timer count register
RTCOR: Refresh time constant register
RTCSR: Refresh timer control/status register
Figure 13.1 Block Diagram of BSC
Rev. 3.0, 04/02, page 308 of 1064
13.1.3
Pin Configuration
Table 13.1 shows the BSC pin configuration.
Table 13.1
BSC Pins
Name
Signals
I/O
Description
Address bus
A25
A0
O
Address output
Data bus
D31
D0
I/O
Data input/output
Bus cycle start
%6
O
Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface or MPX
interface: asserted once for a burst transfer
For other burst transfers: asserted each data cycle
Chip select 60
&6&6
O
Chip select signals that indicate the area being
accessed
&6
and
&6
are also used as PCMCIA
&($
and
&(%
Read/write
RD/
:5
O
Data bus input/output direction designation signal
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal
Row address
strobe
5$6
O
5$6
signal when setting DRAM/synchronous DRAM
interface
Read/column
address strobe/
cycle frame
5'
/
&$66
/
)5$0(
O
Strobe signal that indicates a read cycle
When setting synchronous DRAM interface:
&$6
signal
When setting MPX interface:
)5$0(
signal
Data enable 0
:(
/
5(*
O
When setting PCMCIA interface:
5(*
signal
When setting SRAM interface: write strobe signal for
D7D0
Data enable 1
:(
O
When setting PCMCIA interface: write strobe signal
When setting SRAM interface: write strobe signal for
D15D8
Data enable 2
:(
/
,&,25'
O
When setting PCMCIA interface:
,&,25'
signal
When setting SRAM interface: write strobe signal for
D23D16
Data enable 3
:(
/
,&,2:5
O
When setting PCMCIA interface:
,&,2:5
signal
When setting SRAM interface: write strobe signal for
D31D24
Rev. 3.0, 04/02, page 309 of 1064
Table 13.1
BSC Pins (cont)
Name
Signals
I/O
Description
Column address
strobe 0
&$6
/DQM0
O
When setting DRAM interface:
&$6
signal for
D7D0
When setting synchronous DRAM interface:
selection signal for D7D0
Column address
strobe 1
&$6
/DQM1
O
When setting DRAM interface:
&$6
signal for
D15D8
When setting synchronous DRAM interface:
selection signal for D15D8
Column address
strobe 2
&$6
/DQM2
O
When setting DRAM interface:
&$6
signal for
D23D16
When setting synchronous DRAM interface:
selection signal for D23D16
Column address
strobe 3
&$6
/DQM3
O
When setting DRAM interface:
&$6
signal for
D31D24
When setting synchronous DRAM interface:
selection signal for D31D24
Ready
5'<
I
Wait state request signal
Area 0 MPX
interface
specification/
16-bit I/O
MD6/
,2,6
I
In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
Clock enable
CKE
O
Synchronous DRAM clock enable control signal
Bus release
request
%5(4
/
%6$&.
I
Bus release request signal/bus acknowledge signal
Bus use
permission
%$&.
/
%65(4
O
Bus use permission signal/bus request
Area 0 bus
width/PCMCIA
card select
MD3/
&($
*
1
MD4/
&(%
*
2
I/O
In power-on reset: area 0 bus width specification
signal
When using PCMCIA:
&($
,
&(%
Endian switchover MD5
I
Endian specification in a power-on reset
Master/slave
switchover
MD7/
&76
I/O
Indicates master/slave status in a power-on reset
Serial interface
&76
DMAC0
acknowledge
signal
DACK0
O
DMAC channel 0 data acknowledge
DMAC1
acknowledge
signal
DACK1
O
DMAC channel 1 data acknowledge
Rev. 3.0, 04/02, page 310 of 1064
Notes: *1 MD3/
&($
input/output switching is performed by BCR1.A56PCM. Output is selected
when BCR1.A56PCM = 1.
*2 MD4/
&(%
input/output switching is performed by BCR1.A56PCM. Output is selected
when BCR1.A56PCM = 1.
13.1.4
Register Configuration
The BSC has the 11 registers shown in table 13.2. In addition, the synchronous DRAM mode
register incorporated in synchronous DRAM can also be accessed as an SH7751 Series register.
The functions of these registers include control of interfaces to various types of memory, wait
states, and refreshing.
Table 13.2
BSC Registers
Name
Abbrevia-
tion
R/W
Initial
Value
P4
Address
Area 7
Address
Access
Size
Bus control register 1
BCR1
R/W
H'0000 0000 H'FF80 0000 H'1F80 0000
32
Bus control register 2
BCR2
R/W
H'3FFC
H'FF80 0004 H'1F80 0004
16
Bus control register 3*
2
BCR3
R/W
H'0000
H'FF80 0050 H'1F80 0050
16
Bus control register 4*
2
BCR4
R/W
H'0000 0000 H'FE0A 00F0 H'1E0A 00F0 32
Wait state control
register 1
WCR1
R/W
H'7777 7777 H'FF80 0008 H'1F80 0008
32
Wait state control
register 2
WCR2
R/W
H'FFFE EFFF H'FF80 000C H'1F80 000C 32
Wait state control
register 3
WCR3
R/W
H'0777 7777 H'FF80 0010 H'1F80 0010
32
Memory control register MCR
R/W
H'0000 0000 H'FF80 0014 H'1F80 0014
32
PCMCIA control register PCR
R/W
H'0000
H'FF80 0018 H'1F80 0018
16
Refresh timer
control/status register
RTCSR
R/W
H'0000
H'FF80 001C H'1F80 001C 16
Refresh timer counter
RTCNT
R/W
H'0000
H'FF80 0020 H'1F80 0020
16
Refresh time constant
counter
RTCOR
R/W
H'0000
H'FF80 0024 H'1F80 0024
16
Refresh count register
RFCR
R/W
H'0000
H'FF80 0028 H'1F80 0028
16
For
area 2
SDMR2
W
--
H'FF90 xxxx*
1
H'1F90 xxxx
8
Synchronous
DRAM mode
registers
For
area 3
SDMR3
H'FF94 xxxx*
1
H'1F94 xxxx
Notes: *1 For details, see section 13.2.10, Synchronous DRAM Mode Register (SDMR).
*2 SH7751R only
Rev. 3.0, 04/02, page 311 of 1064
13.1.5
Overview of Areas
Space Divisions: The architecture of the SH7751 Series provides a 32-bit virtual address space.
The virtual address space is divided into five areas according to the upper address value. External
memory space comprises a 29-bit address space, divided into eight areas.
The virtual address can be allocated to any external address by means of the memory management
unit (MMU). Details are given in section 3, Memory Management Unit (MMU). This section
describes the areas into which the external address is divided.
With the SH7751 Series, various kinds of memory or PC cards can be connected to the seven
areas of external address as shown in table 13.3, and chip select signals (
&6&6, &($, &(%)
are output for each of these areas.
&6 is asserted when accessing area 0, and &6 when accessing
area 6. When DRAM or synchronous DRAM is connected to area 2 or 3, signals such as
5$6,
&$6, RD/:5, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or
6,
&($, &(% is asserted in addition to &6, &6 for the byte to be accessed.
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
H'E400 0000
H'0000 0000
H'0400 0000
H'0800 0000
H'0C00 0000
H'1000 0000
H'1400 0000
H'1800 0000
H'1FFF FFFF
H'1C00 0000
Area 0 (
)
Area 1 (
)
Area 2 (
)
Area 3 (
)
Area 4 (
)
Area 5 (
)
Area 6 (
)
Area 7 (reserved area)
P0 and
U0 areas
P1 area
P2 area
P3 area
Physical address
space
(MMU off)
Virtual address
space
(MMU on)
External memory
space
Store queue area
P4 area
P0 and
U0 areas
256
P1 area
P2 area
P3 area
Store queue area
P4 area
Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and
memory is mapped onto a fixed 29-bit external address.
2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be
mapped onto any external space using the TLB.
For details, see section 3, Memory Management Unit (MMU).
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space
Rev. 3.0, 04/02, page 312 of 1064
Table 13.3
External Memory Space Map
Area
External
Addresses
Size
Connectable
Memory
Settable Bus
Widths
Access Size
0
64 Mbytes
SRAM
8, 16, 32*
1
Burst ROM
8, 16, 32*
1
H'00000000
H'03FFFFFF
MPX
32*
1
8
,
16
,
32
,
64*
6
bits,
32 bytes
1
64 Mbytes
SRAM
8, 16, 32*
2
MPX
32*
2
H'04000000
H'07FFFFFF
Byte control SRAM
16, 32*
2
8
,
16
,
32
,
64*
6
bits,
32 bytes
2
64 Mbytes
SRAM
8, 16, 32*
2
Synchronous DRAM 32*
2
,
*
3
H'08000000
H'0BFFFFFF
MPX
32*
2
8
,
16
,
32
,
64*
6
bits,
32 bytes
3
64 Mbytes
SRAM
8, 16, 32*
2
Synchronous DRAM 32*
2
,
*
3
DRAM
16, 32*
2
,
*
3
H'0C000000
H'0FFFFFFF
MPX
32*
2
8
,
16
,
32
,
64*
6
bits,
32 bytes
4
64 Mbytes
SRAM
8, 16, 32*
2
MPX
32*
2
H'10000000
H'13FFFFFF
Byte control RAM
16, 32*
2
8
,
16
,
32
,
64*
6
bits,
32 bytes
5
64 Mbytes
SRAM
8, 16, 32*
2
MPX
32*
2
Burst ROM
8, 16, 32*
2
H'14000000
H'17FFFFFF
PCMCIA
8, 16*
2
,
*
4
8
,
16
,
32
,
64*
6
bits,
32 bytes
6
64 Mbytes
SRAM
8, 16, 32*
2
MPX
32*
2
Burst ROM
8,16, 32*
2
H'18000000
H'1BFFFFFF
PCMCIA
8,16*
2
,
*
4
8
,
16
,
32
,
64*
6
bits,
32 bytes
7*
5
H'1C000000
H'1FFFFFFF
64 Mbytes
--
--
Notes: *1 Memory bus width specified by external pins
*2 Memory bus width specified by register
*3 With synchronous DRAM interface, bus width is 32 bits only
With DRAM interface, bus width is 16 or 32 bits only
*4 With PCMCIA interface, bus width is 8 or 16 bits only
*5 Do not access a reserved area, as operation cannot be guaranteed in this case
*6 A 64-bit access size applies only to transfer by the DMAC (CHCRn.TS = 000).
In the case of access to external memory by means of FMOV (FPSCR.SZ = 1), two
32-bit access size transfers are performed.
Rev. 3.0, 04/02, page 313 of 1064
Area 0: H'00000000
Area 1: H'04000000
Area 2: H'08000000
Area 3: H'0C000000
Area 4: H'10000000
Area 5: H'14000000
Area 6: H'18000000
SRAM/burst ROM/MPX
SRAM/MPX/byte control SRAM
SRAM/synchronous DRAM/MPX
SRAM/synchronous DRAM/DRAM/
MPX
SRAM/MPX/byte control SRAM
SRAM/burst ROM/PCMCIA/MPX
SRAM/burst ROM/PCMCIA/MPX
The PCMCIA interface is
for memory and I/O card use
Figure 13.3 External Memory Space Allocation
Memory Bus Width: In the SH7751 Series, the memory bus width can be set independently for
each space. For area 0, a bus size of 8, 16, or 32 bits can be selected in a power-on reset by means
of the
5(6(7 pin, using external pins. The relationship between the external pins (MD4 and
MD3) and the bus width in a power-on reset is shown below.
MD4
MD3
Bus Width
0
0
Reserved
1
8 bits
1
0
16 bits
1
32 bits
When SRAM interface or ROM is used in areas 1 to 6, a bus width of 8, 16, or 32 bits can be
selected with bus control register 2 (BCR2). When burst ROM is used, a bus width of 8, 16, or 32
bits can be selected. When byte control SRAM interface is used, a bus width of 16, or 32 bits can
be selected. When the MPX interface is used, a bus width of 32 bit can be set. When the DRAM
interface is used, a bus width of 16, or 32 bits can be selected with the memory control register
(MCR). For the synchronous DRAM interface, set a bus width of 32 bit in the MCR register.
When using the PCMCIA interface, set a bus width of 8 or 16 bits. For details, see section 13.3.7,
PCMCIA Interface.
Rev. 3.0, 04/02, page 314 of 1064
For details, see section 13.2.2, Bus Control Register 2 (BCR2), and section 13.2.8, Memory
Control Register (MCR).
The area 7 address range, H'1C000000 to H'1FFFFFFFF, is a reserved space and must not be used.
13.1.6
PCMCIA Support
The SH7751 Series supports PCMCIA interface specifications for external memory space areas 5
and 6.
The interfaces supported are the IC memory card interface and I/O card interface stipulated in
JEIDA specifications version 4.2 (PCMCIA2.1).
External memory space areas 5 and 6 support both the IC memory card interface and the I/O card
interface.
The PCMCIA interface is supported only in little-endian mode.
Table 13.4
PCMCIA Interface Features
Item
Features
Access
Random access
Data bus
8/16 bits
Memory type
Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM
Common memory capacity
Max. 64 Mbytes
Attribute memory capacity
Max. 64 Mbytes
Others
Dynamic bus sizing for I/O bus width, access to PCMCIA interface
from address translation areas
Rev. 3.0, 04/02, page 315 of 1064
Table 13.5
PCMCIA Support Interfaces
IC Memory Card Interface
I/O Card Interface
Pin
Signal
Name
I/O
Function
Signal
Name
I/O
Function
Corresponding
SH7751 Series
Pin
1
GND
Ground
GND
Ground
--
2
D3
I/O
Data
D3
I/O
Data
D3
3
D4
I/O
Data
D4
I/O
Data
D4
4
D5
I/O
Data
D5
I/O
Data
D5
5
D6
I/O
Data
D6
I/O
Data
D6
6
D7
I/O
Data
D7
I/O
Data
D7
7
&(
I
Card enable
&(
I
Card enable
&6
or
&6
8
A10
I
Address
A10
I
Address
A10
9
2(
I
Output enable
2(
I
Output enable
5'
10
A11
I
Address
A11
I
Address
A11
11
A9
I
Address
A9
I
Address
A9
12
A8
I
Address
A8
I
Address
A8
13
A13
I
Address
A13
I
Address
A13
14
A14
I
Address
A14
I
Address
A14
15
:(
/
3*0
I
Write enable
:(
/
3*0
I
Write enable
:(
16
5'<
/
%6<
O
Ready/busy
,5(4
O
Interrupt request
Sensed on port
17
VCC
Operating power
supply
VCC
Operating power
supply
--
18
VPP1
Programming
power supply
VPP1
Programming/
peripheral power
supply
--
19
A16
I
Address
A16
I
Address
A16
20
A15
I
Address
A15
I
Address
A15
21
A12
I
Address
A12
I
Address
A12
22
A7
I
Address
A7
I
Address
A7
23
A6
I
Address
A6
I
Address
A6
24
A5
I
Address
A5
I
Address
A5
25
A4
I
Address
A4
I
Address
A4
26
A3
I
Address
A3
I
Address
A3
27
A2
I
Address
A2
I
Address
A2
28
A1
I
Address
A1
I
Address
A1
Rev. 3.0, 04/02, page 316 of 1064
Table 13.5
PCMCIA Support Interfaces (cont)
IC Memory Card Interface
I/O Card Interface
Pin
Signal
Name
I/O
Function
Signal
Name
I/O
Function
Corresponding
SH7751 Series
Pin
29
A0
I
Address
A0
I
Address
A0
30
D0
I/O
Data
D0
I/O
Data
D0
31
D1
I/O
Data
D1
I/O
Data
D1
32
D2
I/O
Data
D2
I/O
Data
D2
33
:3
*
O
Write protect
,2,6
O
16-bit I/O port
,2,6
34
GND
Ground
GND
Ground
--
35
GND
Ground
GND
Ground
--
36
&'
O
Card detection
&'
O
Card detection
Sensed on port
37
D11
I/O
Data
D11
I/O
Data
D11
38
D12
I/O
Data
D12
I/O
Data
D12
39
D13
I/O
Data
D13
I/O
Data
D13
40
D14
I/O
Data
D14
I/O
Data
D14
41
D15
I/O
Data
D15
I/O
Data
D15
42
&(
I
Card enable
&(
I
Card enable
&($
or
&(%
43
RFSH
I
Refresh request
RFSH
I
Refresh request
Output from
port
44
RFU
Reserved
,25'
I
I/O read
,&,25'
45
RFU
Reserved
,2:5
I
I/O write
,&,2:5
46
A17
I
Address
A17
I
Address
A17
47
A18
I
Address
A18
I
Address
A18
48
A19
I
Address
A19
I
Address
A19
49
A20
I
Address
A20
I
Address
A20
50
A21
I
Address
A21
I
Address
A21
51
VCC
Power supply
VCC
Power supply
--
52
VPP2
Programming
power supply
VPP2
Programming/
peripheral power
supply
--
53
A22
I
Address
A22
I
Address
A22
54
A23
I
Address
A23
I
Address
A23
55
A24
I
Address
A24
I
Address
A24
56
A25
I
Address
A25
I
Address
A25
Rev. 3.0, 04/02, page 317 of 1064
Table 13.5
PCMCIA Support Interfaces (cont)
IC Memory Card Interface
I/O Card Interface
Pin
Signal
Name
I/O
Function
Signal
Name
I/O
Function
Corresponding
SH7751 Series
Pin
57
RFU
Reserved
RFU
Reserved
--
58
RESET
I
Reset
RESET
I
Reset
Output from
port
59
:$,7
O
Wait request
:$,7
O
Wait request
5'<
60
RFU
Reserved
,13$&.
O
Input acknowledge
--
61
5(*
I
Attribute memory
space select
5(*
I
Attribute memory
space select
5(*
62
BVD2
O
Battery voltage
detection
63.5
O
Digital speech
signal
Sensed on port
63
BVD1
O
Battery voltage
detection
676&+*
O
Card status
change
Sensed on port
64
D8
I/O
Data
D8
I/O
Data
D8
65
D9
I/O
Data
D9
I/O
Data
D9
66
D10
I/O
Data
D10
I/O
Data
D10
67
&'
O
Card detection
&'
O
Card detection
Sensed on port
68
GND
Ground
GND
Ground
--
Note: *
:3
is not supported.
Rev. 3.0, 04/02, page 318 of 1064
13.2
Register Descriptions
13.2.1
Bus Control Register 1 (BCR1)
Bus control register 1 (BCR1) is a 32-bit readable/writable register that specifies the function, bus
cycle status, etc., of each area.
BCR1 is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or
in standby mode. External memory space other than area 0 should not be accessed until register
initialization is completed.
Bit:
31
30
29
28
27
26
25
24
ENDIAN
MASTER
A0MPX
--
--
DPUP
IPUP
OPUP
Initial value:
0/1*
0/1*
0/1*
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
Bit:
23
22
21
20
19
18
17
16
--
--
A1MBC
A4MBC
BREQEN
--
MEMMPX
DMABST
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R/W
R/W
R/W
R
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
HIZMEM
HIZCNT
A0BST2
A0BST1
A0BST0
A5BST2
A5BST1
A5BST0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
A6BST2
A6BST1
A6BST0
DRAMTP2 DRAMTP1 DRAMTP0
--
A56PCM
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Note: * These bits sample external pin values in a power-on reset by means of the
5(6(7
pin.
Rev. 3.0, 04/02, page 319 of 1064
Bit 31--Endian Flag (ENDIAN): Samples the value of the endian specification external pin
(MD5) in a power-on reset by means of the
5(6(7 pin. The endian mode of all spaces is
determined by this bit. ENDIAN is a read-only bit.
Bit 31: ENDIAN
Description
0
In a power-on reset, the endian setting external pin (MD5) is low,
designating big-endian mode for the SH7751 Series
1
In a power-on reset, the endian setting external pin (MD5) is high,
designating little-endian mode for the SH7751 Series
Bit 30--Master/Slave Flag (MASTER): Samples the value of the master/slave specification
external pin (MD7) in a power-on reset by means of the
5(6(7 pin. The master/slave status of all
spaces is determined by this bit. MASTER is a read-only bit.
Bit 30: MASTER
Description
0
In a power-on reset, the master/slave setting external pin (MD7) is high,
designating master mode for the SH7751 Series
1
In a power-on reset, the master/slave setting external pin (MD7) is low,
designating slave mode for the SH7751 Series
Bit 29--Area 0 Memory Type (A0MPX): Samples the value of the area 0 memory type
specification external pin (MD6) in a power-on reset by means of the
5(6(7 pin. The memory
type of area 0 is determined by this bit. A0MPX is a read-only bit.
Bit 29: A0MPX
Description
0
In a power-on reset, the external pin specifying the area 0 memory type
(MD6) is high, designating the area 0 as SRAM interface
1
In a power-on reset, the external pin specifying the area 0 memory type
(MD6) is low, designating the area 0 as MPX interface
Bits 28, 27, 23, 22, 18, and 1--Reserved: These bits are always read as 0, and the write value
should always be 0.
Bit 26--Data pin Pullup Resistor Control (DPUP): Controls the pullup resistance of the data
pins (D31 to D0). It is initialized at a power-on reset. The pins are not pulled up when access is
performed or when the bus is released, even if the ON setting is selected.
Bit 26: DPUP
Description
0
Sets pullup resistance of data pins (D31 to D0) ON
(Initial value)
1
Sets pullup resistance of data pins (D31 to D0) OFF
Rev. 3.0, 04/02, page 320 of 1064
Bit 25--Control Input Pin Pull-Up Resistor Control (IPUP): Specifies the pull-up resistor
status for control input pins (NMI,
,5/,5/, %5(4, MD6/,2,6, 6/((3, 5'<). IPUP is
initialized by a power-on reset.
Bit 25: IPUP
Description
0
Pull-up resistor is on for control input pins (NMI,
,5/
,5/
,
%5(4
,
MD6/
,2,6
,
6/((3
,
5'<
)
(Initial value)
1
Pull-up resistor is off for control input pins (NMI,
,5/
,5/
,
%5(4
,
MD6/
,2,6
,
6/((3
,
5'<
)
Bit 24--Control Output Pin Pull-Up Resistor Control (OPUP): Specifies the pull-up resistor
status for control output pins (A[25:0],
%6, &6Q, 5', :(Q, &$6Q, RD/:5, 5$6, &($, &(%,
MD5) when high-impedance. OPUP is initialized by a power-on reset.
Bit 24: OPUP
Description
0
Pull-up resistor is on for control output pins (A[25:0],
%6
,
&6Q
,
5'
,
:(Q
,
&$6Q
, RD/
:5
,
5$6
,
&($
,
&(%
, MD5)
(Initial value)
1
Pull-up resistor is off for control output pins (A[25:0],
%6
,
&6Q
,
5'
,
:(Q
,
&$6Q
, RD/
:5
,
5$6
,
&($
,
&(%
, MD5)
Bit 21--Area 1 SRAM Byte Control Mode (A1MBC): MPX interface has priority when an
MPX interface is set. This bit is initialized by a power-on reset.
Bit 21: A1MBC
Description
0
Area 1 SRAM is set to normal mode
(Initial value)
1
Area 1 SRAM is set to byte control mode
Bit 20--Area 4 SRAM Byte Control Mode (A4MBC): MPX interface has priority when an
MPX interface is set. This bit is initialized by a power-on reset.
Bit 20: A4MBC
Description
0
Area 4 SRAM is set to normal mode
(Initial value)
1
Area 4 SRAM is set to byte control mode
Rev. 3.0, 04/02, page 321 of 1064
Bit 19--BREQ Enable (BREQEN): Indicates whether external requests and bus requests from
PCIC can be accepted. BREQEN is initialized to the external request and bus request from PCIC
acceptance disabled state by a power-on reset. It is ignored in the case of a slave mode startup.
The bus request from the PCIC is always accepted in a slave mode start up.
Bit 19: BREQEN
Description
0
External requests and bus requests from PCIC are not accepted
(Initial value)
1
External requests and bus requests from PCIC are accepted
Bit 17--Area 1 to 6 MPX Bus Specification (MEMMPX): Sets the MPX interface when areas 1
to 6 are set as SRAM interface (or burst ROM interface). MEMMPX is initialized by a power-on
reset.
Bit 17: MEMMPX
Description
0
SRAM interface (or burst ROM interface) is selected when areas 1 to 6 are
set as SRAM interface (or burst ROM interface)
(Initial value)
1
MPX interface is selected when areas 1 to 6 are set as SRAM interface (or
burst ROM interface)
Bit 16--DMAC Burst Mode Transfer Priority Setting (DMABST): Specifies the priority of
burst mode transfers by the DMAC. When OFF, the priority is as follows: bus privilege released,
refresh, DMAC, CPU. When ON, the bus privileges are released and refresh operations are not
performed until the end of the DMAC's burst transfer. This bit is initialized at a power-on reset.
Bit 16: DMABST
Description
0
DMAC burst mode transfer priority specification OFF
(Initial value)
1
DMAC burst mode transfer priority specification ON
Bit 15--High Impedance Control (HIZMEM): Specifies the state of address and other signals
(A[25:0],
%6, &6Q, RD/:5, &($, &(%) in standby mode.
Bit 15: HIZMEM
Description
0
The A[25:0],
%6
,
&6Q
, RD/
:5
,
&($
, and
&(%
signals go to high-
impedance (High-Z) in standby mode and when the bus is released
(Initial value)
1
The A[25:0],
%6
,
&6Q
, RD/
:5
,
&($
, and
&(%
signals drive in standby
mode
Rev. 3.0, 04/02, page 322 of 1064
Bit 14--High Impedance Control (HIZCNT): Specifies the state of the
5$6 and &$6 signals in
standby mode and when the bus is released.
Bit 14: HIZCNT
Description
0
The
5$6
,
:(Q
,
&$6Q
/DQMn, and
5'
/
&$66
/
)5$0(
signals go to high-
impedance (Hi-Z) in standby mode and when the bus is released
(Initial value)
1
The
5$6
,
:(Q
,
&$6Q
/DQMn, and
5'
/
&$66
/
)5$0(
signals drive in
standby mode and when the bus is released
Bits 13 to 11--Area 0 Burst ROM Control (A0BST2A0BST0): These bits specify whether
burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the
number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored.
Bit 13: A0BST2
Bit 12: A0BST1
Bit 11: A0BST0
Description
0
0
0
Area 0 is accessed as SRAM interface
(Initial value)
1
Area 0 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
1
0
Area 0 is accessed as burst ROM
interface (8 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
1
Area 0 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
1
0
0
Area 0 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
1
Reserved
1
0
Reserved
1
Reserved
Rev. 3.0, 04/02, page 323 of 1064
Bits 10 to 8--Area 5 Burst Enable (A5BST2A5BST0): These bits specify whether burst ROM
interface is used in area 5. When burst ROM interface is used, they also specify the number of
accesses in a burst. If area 5 is an MPX interface area, these bits are ignored.
Bit 10: A5BST2
Bit 9: A5BST1
Bit 8: A5BST0
Description
0
0
0
Area 5 is accessed as SRAM interface
(Initial value)
1
Area 5 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
1
0
Area 5 is accessed as burst ROM
interface (8 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
1
Area 5 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
1
0
0
Area 5 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
1
Reserved
1
0
Reserved
1
Reserved
Note: Clear to 0 when PCMCIA interface is set.
Rev. 3.0, 04/02, page 324 of 1064
Bits 7 to 5--Area 6 Burst Enable (A6BST2A6BST0): These bits specify whether burst ROM
interface is used in area 6. When burst ROM is used, they also specify the number of accesses in a
burst. If area 6 is an MPX interface area, these bits are ignored.
Bit 7: A6BST2
Bit 6: A6BST1
Bit 5: A6BST0
Description
0
0
0
Area 6 is accessed as SRAM interface
(Initial value)
1
Area 6 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
1
0
Area 6 is accessed as burst ROM
interface (8 consecutive accesses)
Can be used with 8-, 16-, or 32-bit bus
width
1
Area 6 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
1
0
0
Area 6 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
1
Reserved
1
0
Reserved
1
Reserved
Note: Clear to 0 when PCMCIA is used.
Rev. 3.0, 04/02, page 325 of 1064
Bits 4 to 2--Area 2 and 3 Memory Type (DRAMTP2DRAMTP0): These bits specify the type
of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as
SRAM interface. DRAM and synchronous DRAM can also be directly connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
0
0
Areas 2 and 3 are accessed as SRAM
interface or MPX interface*
(Initial value)
1
Reserved (Cannot be set)
1
0
Area 2 is accessed as SRAM interface or
MPX interface*, area 3 is synchronous
DRAM interface
1
Areas 2 and 3 are accessed as
synchronous DRAM interface
1
0
0
Area 2 is accessed as SRAM interface or
MPX interface*, area 3 is DRAM interface
1
Reserved (Cannot be set)
1
0
Reserved (Cannot be set)
1
Reserved (Cannot be set)
Note: * Selection of SRAM interface or MPX interface is determined by the setting of the MEMMPX
bit
Bit 0--Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as
PCMCIA interface. The setting of these bits has priority over the MEMMPX and AnBST bit
settings.
Bit 0: A56PCM
Description
0
Areas 5 and 6 are accessed as SRAM interface
(Initial value)
1
Areas 5 and 6 are accessed as PCMCIA interface*
Note: * The MD3 pin is designated for output as the
&($
pin.
The MD4 pin is designated for output as the
&(%
pin.
Rev. 3.0, 04/02, page 326 of 1064
13.2.2
Bus Control Register 2 (BCR2)
Bus control register 2 (BCR2) is a 32-bit readable/writable register that specifies the bus width for
each area, and whether a 16-bit port is used.
BCR2 is initialized to H'3FFC by a power-on reset, but is not initialized by a manual reset or in
standby mode. External memory space other than area 0 should not be accessed until register
initialization is completed.
Bit:
15
14
13
12
11
10
9
8
A0SZ1
A0SZ0
A6SZ1
A6SZ0
A5SZ1
A5SZ0
A4SZ1
A4SZ0
Initial value:
0/1*
0/1*
1
1
1
1
1
1
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
A3SZ1
A3SZ0
A2SZ1
A2SZ0
A1SZ1
A0SZ0
--
PORTEN
Initial value:
1
1
1
1
1
1
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
--
R/W
Note: * These bits sample the values of the external pins that specify the area 0 bus size.
Bits 15 and 14--Area 0 Bus Width (A0SZ1, A0SZ0): These bits sample the external pins (MD3
and MD4) that specify the bus size in a power-on reset. They are read-only bits.
Bit 15: MD4
Bit 14: MD3
Bus Width
0
0
Reserved (Setting prohibited)
1
8 bits
1
0
16 bits
1
32 bits
Rev. 3.0, 04/02, page 327 of 1064
Bits 2n + 1, 2n--Area n (1 to 6) Bus Width Specification (AnSZ1, AnSZ0): These bits specify
the bus width of area n (n = 1 to 6).
(Bit 0): PORTEN Bit 2n + 1: AnSZ1
Bit 2n: AnSZ0
Description
0
0
0
Reserved (Setting prohibited)
1
Bus width is 8 bits
1
0
Bus width is 16 bits
1
Bus width is 32 bits
(Initial value)
1
0
0
Reserved (Setting prohibited)
1
Bus width is 8 bits
1
0
Bus width is 16 bits
1
Bus width is 32 bits
Bit 1--Reserved: This bit is always read as 0, and should only be written with 0.
Bit 0--Port Function Enable (PORTEN): Specifies whether pins AD31 to AD0 are used as a
32-bit port. However, select PCI-disable mode when using this function.
Bit 0: PORTEN
Description
0
AD31 to AD0 are not used as a port
(Initial value)
1
AD31 to AD0 are used as a port
13.2.3
Bus Control Register 3 (BCR3) (SH7751R Only)
Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of
either the MPX interface or the SRAM interface and specifies the burst length when the
synchronous DRAM interface is used.
BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. No external memory space other than area 0 should be accessed before register
initialization has been completed.
Rev. 3.0, 04/02, page 328 of 1064
Bit:
15
14
13
12
11
10
9
8
Bit name:
MEMMODE
A1MPX
A4MPX
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
Bit name:
--
--
--
--
--
--
--
SDBL
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit 15
A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of
either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by
MEMMPX.
Bit 15: MEMMODE
Description
0
MPX or SRAM interface is selected by MEMMPX
(Initial value)
1
MPX or SRAM interface is selected by A1MPX and A4MPX
Bits 14, 13
MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These bits
specify the types of memory connected to areas 1 and 4. These settings are validated by
MEMMODE.
Bit 14: A1MPX
Description
0
SRAM/byte control SRAM interface is selected for area 1
(Initial value)
1
MPX interface is selected for area 1
Bit 13: A4MPX
Description
0
SRAM/byte control SRAM interface is selected for area 4
(Initial value)
1
MPX interface is selected for area 4
Bit 0
Burst Length (SDBL): Sets the burst length when the synchronous DRAM interface is
used. The burst-length setting is only valid when the bus width is 32 bits.
Bit 0: SDBL
Description
0
Burst length is 8
1
Burst length is 4
(Initial value)
Rev. 3.0, 04/02, page 329 of 1064
13.2.4
Bus Control Register 4 (BCR4) (SH7751R Only)
Bus control register 4 (BCR4) is a register that enables asynchronous input for pins corresponding
to individual bits.
The BCR4 register is a 32-bit readable/writable register. It is initialized to H'00000000 by a
power-on reset, but is not initialized by a manual reset or in standby mode.
When asynchronous input is set (ASYNCn = 1), the sampling timing is one cycle earlier than
when synchronous input is set (ASYNCn = 0)* (see figure 13.4)
The timings shown in this section and section 23, Electrical Characteristics, are all for the case
where synchronous input is set (ASYNCn = 0).
Note: * With the synchronous input setting, ensure that setup and hold times are observed.
Bit:
31
30
29
28
27
26
25
24
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
23
22
21
20
19
18
17
16
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
--
--
--
ASYNC4 ASYNC3 ASYNC2 ASYNC1 ASYNC0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R/W
R/W
R/W
R/W
Bits 31 to 5--Reserved: These bits are always read as 0, and the write value should always be 0.
Rev. 3.0, 04/02, page 330 of 1064
Bits 4 to 0--Asynchronous Input: These bits enable asynchronous input for the corresponding
pins.
Bit 40: ASYNCn
Description
0
Corresponding pin is synchronous input with respect to CKIO (Initial value)
1
Asynchronous input with respect to CKIO is enabled for corresponding pin
Bit
4
,2,6
3
'5(4
2
'5(4
1
%5(4
0
5'<
T1
Tw
Tw
Twe
T2
CKIO
(BCR4.ASYNC0 = 0)
(BCR4.ASYNC0 = 1)
Figure 13.4 Example of
5'<
5'< Sampling Timing at which BCR4 is Set
(Two Wait Cycles are Inserted by WCR2)
Rev. 3.0, 04/02, page 331 of 1064
13.2.5
Wait Control Register 1 (WCR1)
Wait control register 1 (WCR1) is a 32-bit readable/writable register that specifies the number of
idle state insertion cycles for each area. With some kinds of memory, data bus drive does not go
off immediately after the read signal from off-chip goes off. As a result, there is a possibility of a
data bus collision when consecutive memory accesses are performed on memory in different
areas, or when a memory write is performed immediately after a read. In the SH7751 Series, the
number of idle cycles set in the WCR1 register are inserted automatically if there is a possibility of
this kind of data bus collision.
WCR1 is initialized to H'77777777 by a power-on reset, but is not initialized by a manual reset or
in standby mode.
Bit:
31
30
29
28
27
26
25
24
--
DMAIW2 DMAIW1 DMAIW0
--
A6IW2
A6IW1
A6IW0
Initial value:
0
1
1
1
0
1
1
1
R/W:
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit:
23
22
21
20
19
18
17
16
--
A5IW2
A5IW1
A5IW0
--
A4IW2
A4IW1
A4IW0
Initial value:
0
1
1
1
0
1
1
1
R/W:
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
--
A3IW2
A3IW1
A3IW0
--
A2IW2
A2IW1
A2IW0
Initial value:
0
1
1
1
0
1
1
1
R/W:
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
--
A1IW2
A1IW1
A1IW0
--
A0IW2
A0IW1
A0IW0
Initial value:
0
1
1
1
0
1
1
1
R/W:
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bits 31, 27, 23, 19, 15, 11, 7, and 3--Reserved: These bits are always read as 0, and the write
value should always be 0.
Bits 30 to 28-- DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2
DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when
switching from a DACK device to another space, or from a read access to a write access on the
Rev. 3.0, 04/02, page 332 of 1064
same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual
address transfer, inter-area idle cycles are inserted.
Bits 4n + 2 to 4n--Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2AnlW0): These bits
specify the number of idle cycles between bus cycles to be inserted when switching from external
memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the
same space.
DMAIW2/AnIW2
DMAIW1/AnIW1
DMAIW0/AnIW0
Inserted Idle Cycles
0
0
0
0
1
1
1
0
2
1
3
1
0
0
6
1
9
1
0
12
1
15
(Initial value)
Rev. 3.0, 04/02, page 333 of 1064
Table 13.6
Idle Insertion between Accesses
Following Cycle
Same Area
Different Area
Same
Area
Different
Area
Read
Write
Read
Write
Preceding
Cycle
CPU
DMA
CPU
DMA
CPU
DMA
CPU
DMA
MPX
Address
Output
MPX
Address
Output
Read
M
M
M
M
M
M
M (1)
M (1)
Write
M
M
M
M
*
2
M
DMA read
(memory
device)
M
M
M
M
M
M
--
M (1)
DMA write
(device
memory)
D
D
D
D*
1
D
D
D
D
--
D (1)
"DMA" in the table indicates DMA single-address transfer. DMA dual-address transfer is in
accordance with the CPU.
M, D : Idle wait always inserted by WCR1
(M(1): Once cycle inserted in MPX access even if WCR1 is cleared to 0)
M
: Idle cycles according to setting of AnIW2-AnIW0 (areas 0 to 6)
D
: Idle cycles according to setting of DMAIW2-DMAIW0
Notes: *1: Inserted when device is switched
*2: On the MPX interface, a WCR1 idle wait may be inserted before an access (either read
or write) to the same area after a write access. The specific conditions for idle wait
insertion in accesses to the same area are shown below.
(a) Synchronous DRAM set to RAS down mode
(b) Synchronous DRAM accessed by on-chip DMAC
Apart from use under above conditions (a) and (b), an idle wait is also inserted between
an MPX interface write access and a following access to the same area. Even under
the above conditions, an idle wait may be inserted in a same-area access following an
interface write access, depending on the synchronous DRAM pipeline access situation.
An idle wait is not inserted when the WCR1 register setting is 0. The setting for the
number of idle state cycles inserted after a power-on reset is the default value of 15 (the
maximum value), so ensure that the optimum value is set.
When synchronous DRAM is used in RAS down mode, set bits DMAIW2-DMAIW0 to
000 and bits A3IW2-A3IW0 to 000.
Rev. 3.0, 04/02, page 334 of 1064
13.2.6
Wait Control Register 2 (WCR2)
Wait control register 2 (WCR2) is a 32-bit readable/writable register that specifies the number of
wait states to be inserted for each area. It also specifies the data access pitch when performing
burst memory access. This enables low-speed memory to be connected without using external
circuitry.
WCR2 is initialized to H'FFFEEFFF by a power-on reset, but is not initialized by a manual reset
or in standby mode.
Bit:
31
30
29
28
27
26
25
24
A6W2
A6W1
A6W0
A6B2
A6B1
A6B0
A5W2
A5W1
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
23
22
21
20
19
18
17
16
A5W0
A5B2
A5B1
A5B0
A4W2
A4W1
A4W0
--
Initial value:
1
1
1
1
1
1
1
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Bit:
15
14
13
12
11
10
9
8
A3W2
A3W1
A3W0
--
A2W2
A2W1
A2W0
A1W2
Initial value:
1
1
1
0
1
1
1
1
R/W:
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
A1W1
A1W0
A0W2
A0W1
A0W0
A0B2
A0B1
A0B0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 335 of 1064
Bits 31 to 29--Area 6 Wait Control (A6W2A6W0): These bits specify the number of wait
states to be inserted for area 6. For the case where an MPX interface setting is made, see table
13.7.
Description
First Cycle
Bit 31: A6W2
Bit 30: A6W1
Bit 29: A6W0
Inserted Wait States
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
6
Enabled
1
9
Enabled
1
0
12
Enabled
1
15 (Initial value)
Enabled
Bits 28 to 26--Area 6 Burst Pitch (A6B2A6B0): These bits specify the number of wait states to
be inserted from the second data access onward at the time of setting the burst ROM in a burst
transfer.
Description
Burst Cycle (Excluding First Cycle)
Bit 28: A6B2
Bit 27: A6B1
Bit 26: A6B0
Wait States Inserted
from Second Data
Access Onward
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
4
Enabled
1
5
Enabled
1
0
6
Enabled
1
7 (Initial value)
Enabled
Rev. 3.0, 04/02, page 336 of 1064
Bits 25 to 23--Area 5 Wait Control (A5W2A5W0): These bits specify the number of wait
states to be inserted for area 5. For the case where an MPX interface setting is made, see table
13.7.
Description
First Cycle
Bit 25: A5W2
Bit 24: A5W1
Bit 23: A5W0
Inserted Wait States
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
6
Enabled
1
9
Enabled
1
0
12
Enabled
1
15 (Initial value)
Enabled
Bits 22 to 20--Area 5 Burst Pitch (A5B2A5B0): These bits specify the number of wait states to
be inserted from the second data access onward at the time of setting the burst ROM in a burst
transfer.
Description
Burst Cycle (Excluding First Cycle)
Bit 22: A5B2
Bit 21: A5B1
Bit 20: A5B0
Wait States Inserted from
Second Data Access Onward
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
4
Enabled
1
5
Enabled
1
0
6
Enabled
1
7 (Initial value)
Enabled
Rev. 3.0, 04/02, page 337 of 1064
Bits 19 to 17--Area 4 Wait Control (A4W2A4W0): These bits specify the number of wait
states to be inserted for area 4. For the case where an MPX interface setting is made, see table
13.7.
Description
Bit 19: A4W2
Bit 18: A4W1
Bit 17: A4W0
Inserted Wait States
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
6
Enabled
1
9
Enabled
1
0
12
Enabled
1
15 (Initial value)
Enabled
Bits 16 and 12--Reserved: These bits are always read as 0, and should only be written with 0.
Bits 15 to 13--Area 3 Wait Control (A3W2A3W0): These bits specify the number of wait
states to be inserted for area 3. External wait input is only enabled when the SRAM interface or
MPX interface is used, and is ignored when DRAM or synchronous DRAM is used. For the case
where an MPX interface setting is made, see table 13.7.
When SRAM Interface is Set
Description
Bit 15: A3W2
Bit 14: A3W1
Bit 13: A3W0
Inserted Wait States
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
6
Enabled
1
9
Enabled
1
0
12
Enabled
1
15 (Initial value)
Enabled
Rev. 3.0, 04/02, page 338 of 1064
When DRAM or Synchronous DRAM Interface is Set*
Note: * External wait input is always ignored
Description
Bit 15: A3W2
Bit 14: A3W1
Bit 13: A3W0
DRAM
&$6
&$6
Assertion Width
Synchronous DRAM
&$6
&$6
Latency Cycles
0
0
0
1
Inhibited
1
2
1*
1
0
3
2
1
4
3
1
0
0
7
4*
1
10
5*
1
0
13
Inhibited
1
16
Inhibited
Note: * Inhibited in RAS down mode
Bits 11 to 9--Area 2 Wait Control (A2W2A2W0): These bits specify the number of wait states
to be inserted for area 2. External wait input is only enabled when the SRAM interface or MPX
interface is used, and is ignored when synchronous DRAM is used. For the case where an MPX
interface setting is made, see table 13.7.
When SRAM Interface is Set
Description
Bit 11: A2W2
Bit 10: A2W1
Bit 9: A2W0
Inserted Wait States
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
6
Enabled
1
9
Enabled
1
0
12
Enabled
1
15 (Initial value)
Enabled
Rev. 3.0, 04/02, page 339 of 1064
When Synchronous DRAM Interface is Set*
1
Description
Bit 11: A2W2
Bit 10: A2W1
Bit 9: A2W0
Synchronous DRAM
&$6
&$6
Latency Cycles
0
0
0
Inhibited
1
1*
2
1
0
2
1
3
1
0
0
4*
2
1
5*
2
1
0
Inhibited
1
Inhibited
Notes: *1 External wait input is always ignored
*2 Inhibited in RAS down mode
Bits 8 to 6--Area 1 Wait Control (A1W2A1W0): These bits specify the number of wait states
to be inserted for area 1. For the case where an MPX interface setting is made, see table 13.7.
Description
Bit 8: A1W2
Bit 7: A1W1
Bit 6: A1W0
Inserted Wait States
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
6
Enabled
1
9
Enabled
1
0
12
Enabled
1
15 (Initial value)
Enabled
Rev. 3.0, 04/02, page 340 of 1064
Bits 5 to 3--Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait
states to be inserted for area 0. For the case where an MPX interface setting is made, see table
13.7.
Description
First Cycle
Bit 5: A0W2
Bit 4: A0W1
Bit 3: A0W0
Inserted Wait States
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
6
Enabled
1
9
Enabled
1
0
12
Enabled
1
15 (Initial value)
Enabled
Bits 2 to 0--Area 0 Burst Pitch (A0B2A0B0): These bits specify the number of wait states to
be inserted from the second data access onward at the time of setting the burst ROM in a burst
transfer.
Description
Burst Cycle (Excluding First Cycle)
Bit 2: A0B2
Bit 1: A0B1
Bit 0: A0B0
Wait States Inserted from
Second Data Access Onward
5'<
5'<
Pin
0
0
0
0
Ignored
1
1
Enabled
1
0
2
Enabled
1
3
Enabled
1
0
0
4
Enabled
1
5
Enabled
1
0
6
Enabled
1
7 (Initial value)
Enabled
Rev. 3.0, 04/02, page 341 of 1064
Table 13.7
When MPX Interface is Set (Areas 0 to 6)
Description
Inserted Wait States
1st Data
AnW2
AnW1
AnW0
Read
Write
2nd Data
Onward
5'<
5'<
Pin
0
0
0
1
0
0
Enabled
1
1
Enabled
1
0
2
2
Enabled
1
3
3
Enabled
1
0
0
1
0
1
Enabled
1
1
Enabled
1
0
2
2
Enabled
1
3
3
Enabled
(n = 6 to 0)
Rev. 3.0, 04/02, page 342 of 1064
13.2.7
Wait Control Register 3 (WCR3)
Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles
inserted in the setup time from the address until assertion of the write strobe, and the data hold
time from negation of the strobe, for each area. This enables low-speed memory to be connected
without using external circuitry.
WCR3 is initialized to H'07777777 by a power-on reset, but is not initialized by a manual reset or
in standby mode.
Bit:
31
30
29
28
27
26
25
24
--
--
--
--
--
A6S0
A6H1
A6H0
Initial value:
0
0
0
0
0
1
1
1
R/W:
R
R
R
R
R
R/W
R/W
R/W
Bit:
23
22
21
20
19
18
17
16
--
A5S0
A5H1
A5H0
A4RDH*
A4S0
A4H1
A4H0
Initial value:
0
1
1
1
0
1
1
1
R/W:
R
R/W
R/W
R/W
R/W*
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
Bit name:
--
A3S0
A3H1
A3H0
--
A2S0
A2H1
A2H0
Initial value:
0
1
1
1
0
1
1
1
R/W:
R
R/W
R/W
R/W
R
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
A1RDH*
A1S0
A1H1
A0H0
--
A0S0
A0H1
A0H0
Initial value:
0
1
1
1
0
1
1
1
R/W:
R/W*
R/W
R/W
R/W
R
R/W
R/W
R/W
Note: * These bits can be set only in the SH7751R.
Bits 31 to 27, 23, 19*, 15, 11, 7*, and 3 (SH7751)
Bits 31 to 27, 23, 15, 11, and 3 (SH7751R)
Reserved: These bits are always read as 0, and should only be written with 0.
Note: * These bits can be set only in the SH7751R.
Rev. 3.0, 04/02, page 343 of 1064
Bit 4n + 2--Area n (6 to 0) Write Strobe Setup Time (AnS0): Specifies the number of cycles
inserted in the setup time from the address until assertion of the read/write strobe. Valid only for
SRAM interface, byte control SRAM interface, and burst ROM interface:
Bit 4n + 2: AnS0
Waits Inserted in Setup
0
0
1
1
(Initial value)
(n = 6 to 0)
Bits 4n + 1 and 4n--Area n (6 to 0) Data Hold Time (AnH1, AnH0): When writing, these bits
specify the number of cycles to be inserted in the hold time from negation of the write strobe.
When reading, they specify the number of cycles to be inserted in the hold time from the data
sampling timing. Valid only for SRAM interface, byte control SRAM interface, and burst ROM
interface:
Bit 4n + 1: AnH1
Bit 4n: AnH0
Waits Inserted in Hold
0
0
0
1
1
1
0
2
1
3
(Initial value)
(n = 6 to 0)
Bits 4n+3
Area n (4 or 1) Read-Strobe Negate Timing (AnRDH) (Setting Only Possible in
the SH7751R): When reading, these bits specify the timing for the negation of read strobe. These
bits should be cleared to 0 when a byte control SRAM setting is made. When reading in area 1 or
4, AnRDH bits specify the number of cycles to be inserted in the hold time from the time at which
the data is sampled or from the negation of the read strobe. Valid only for the SRAM interface.
Bit 4n + 3: AnRDH
Waits Inserted in Hold
0
0
(Initial value)
1
1
Rev. 3.0, 04/02, page 344 of 1064
13.2.8
Memory Control Register (MCR)
The memory control register (MCR) is a 32-bit readable/writable register that specifies
5$6 and
&$6 timing and burst control for DRAM and synchronous DRAM (areas 2 and 3), address
multiplexing, and refresh control. This enables DRAM and synchronous DRAM to be connected
without using external circuitry.
MCR is initialized to H'00000000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits RASD, MRSET, TRC20, TPC20, RCD10, TRWL20, TRAS20, BE,
SZ10, AMXEXT, AMX20, and EDOMODE are written in the initialization following a power-
on reset, and should not be modified subsequently. When writing to bits RFSH and RMODE, the
same values should be written to the other bits so that they remain unchanged. When using DRAM
or synchronous DRAM, areas 2 and 3 should not be accessed until register initialization is
completed.
Bit:
31
30
29
28
27
26
25
24
RASD
MRSET
TRC2
TRC1
TRC0
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R
R
R
Bit:
23
22
21
20
19
18
17
16
TCAS
--
TPC2
TPC1
TPC0
--
RCD1
RCD0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R
R/W
R/W
R/W
R
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
TRWL2
TRWL1
TRWL0
TRAS2
TRAS1
TRAS0
BE
SZ1
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
SZ0
AMXEXT
AMX2
AMX1
AMX0
RFSH
RMODE
EDO
MODE
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 345 of 1064
Bit 31--RAS Down (RASD): Sets RAS down mode. When RAS down mode is used, set BE to 1.
Do not set RAS down mode in slave mode or partial-sharing mode, or when areas 2 and 3 are both
designated as synchronous DRAM interface.
Bit 31: RASD
Description
0
Normal mode
(Initial value)
1
RAS down mode
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2DMAIW0 to 000
and bits A3IW2A3IW0 to 000.
Bit 30--Mode Register Set (MRSET): Set when a synchronous DRAM mode register setting is
used. See Power-On Sequence in section 13.3.5, Synchronous DRAM Interface.
Bit 30: MRSET
Description
0
All-bank precharge
(Initial value)
1
Mode register setting
Bits 26 to 24, 22, and 18--Reserved: These bits should only be written with 0.
Bits 29 to 27--RAS Precharge Time at End of Refresh (TRC2TRC0)
(Synchronous DRAM: auto- and self-refresh both enabled, DRAM: auto- and self-refresh both
enabled)
Bit 29: TRC2
Bit 28: TRC1
Bit 27: TRC0
RAS Precharge Time
Immediately after Refresh
0
0
0
0
(Initial value)
1
3
1
0
6
1
9
1
0
0
12
1
15
1
0
18
1
21
Bit 23--CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set.
Bit 23: TCAS
CAS Negation Period
0
1
(Initial value)
1
2
Rev. 3.0, 04/02, page 346 of 1064
Bits 21 to 19--RAS Precharge Period (TPC2TPC0): When the DRAM interface is set, these
bits specify the minimum number of cycles until
5$6 is asserted again after being negated. When
the synchronous DRAM interface is set, these bits specify the minimum number of cycles until the
next bank active command is output after precharging.
RAS Precharge Time
Bit 21: TPC2
Bit 20: TPC1
Bit 19: TPC0
DRAM
Synchronous DRAM
0
0
0
0
1* (Initial value)
1
1
2
1
0
2
3
1
3
4*
1
0
0
4
5*
1
5
6*
1
0
6
7*
1
7
8*
Note: * Inhibited in RAS down mode
Bits 17 and 16--RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits
set the
5$6-&$6 assertion delay time. When the synchronous DRAM interface is set, these bits
set the bank active-read/write command delay time.
Description
Bit 17: RCD1
Bit 16: RCD0
DRAM
Synchronous DRAM
0
0
2 cycles
Reserved (Setting prohibited)
1
3 cycles
2 cycles
1
0
4 cycles
3 cycles
1
5 cycles
4 cycles*
Note: * Inhibited in RAS down mode
Bits 15 to 13--Write Precharge Delay (TRWL2TRWL0): These bits set the synchronous
DRAM write precharge delay time. In auto-precharge mode, they specify the time until the next
bank active command is issued after a write cycle. After a write cycle, the next active command is
not issued for a period of TPC + TRWL. In RAS down mode, they specify the time until the next
precharge command is issued. After a write cycle, the next precharge command is not issued for a
period of TRWL. This setting is valid only when synchronous DRAM interface is set.
For the setting values and delay time when no command is issued, refer to section 23.3.3, Bus
Timing.
Rev. 3.0, 04/02, page 347 of 1064
Bit 15: TRWL2
Bit 14: TRWL1
Bit 13: TRWL0
Write Precharge ACT Delay Time
0
0
0
1 (Initial value)
1
2
1
0
3*
1
4*
1
0
0
5*
1
Reserved (Setting prohibited)
1
0
Reserved (Setting prohibited)
1
Reserved (Setting prohibited)
Note: * Inhibited in RAS down mode
Bits 12 to 10--CAS-Before-RAS Refresh
5$6
5$6 Assertion Period (TRAS2TRAS0): When the
DRAM interface is set, these bits set the
5$6 assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active command is not issued for a period
of TRC* + TRAS after an auto-refresh command is issued.
Bit 12: TRAS2
Bit 11: TRAS1
Bit 10: TRAS0
5$6
5$6
/DRAM
Assertion Time
Command
Interval after
Synchronous
DRAM Refresh
0
0
0
2
4 + TRC*
(Initial value)
1
3
5 + TRC
1
0
4
6 + TRC
1
5
7 + TRC
1
0
0
6
8 + TRC
1
7
9 + TRC
1
0
8
10 + TRC
1
9
11 + TRC
Note: * Bits 29 to 27: RAS precharge interval at end of refresh
Bit 9--Burst Enable (BE): Specifies whether burst access is performed on DRAM interface. In
synchronous DRAM access, burst access is always performed regardless of the specification of
this bit. The DRAM transfer mode depends on EDOMODE.
Rev. 3.0, 04/02, page 348 of 1064
BE
EDOMODE
8/16/32/64-Bit Transfer
32-Byte Transfer
0
0
Single
Single
1
Setting prohibited
Setting prohibited
1
0
Single/fast page*
Fast page
1
EDO
EDO
Note: * In fast page mode, 32-bit or 64-bit transfer with a 16-bit bus, 64-bit transfer with a 32-bit bus
Bits 8 and 7--Memory Data Size (SZ1, SZ0): These bits specify the bus width of DRAM and
synchronous DRAM. This setting has priority over the BCR2 register setting.
Description
Bit 8: SZ1
Bit 7: SZ0
DRAM
SDRAM
0
0
Reserved (Setting prohibited)
Reserved (Setting prohibited)
1
Reserved (Setting prohibited)
Reserved (Setting prohibited)
1
0
16 bits
Reserved (Setting prohibited)
1
32 bits
32 bits
Bits 6 to 3--Address Multiplexing (AMXEXT, AMX2AMX0): These bits specify address
multiplexing for DRAM and synchronous DRAM. The address shift value is different for the
DRAM interface and the synchronous DRAM interface.
For DRAM Interface:
Description
Bit 6:
AMXEXT
Bit 5:
AMX2
Bit 4:
AMX1
Bit 3:
AMX0
DRAM
0*
0
0
0
8-bit column address product
(Initial value)
1
9-bit column address product
1
0
10-bit column address product
1
11-bit column address product
1
0
0
12-bit column address product
1
Reserved (Setting prohibited)
1
0
Reserved (Setting prohibited)
1
Reserved (Setting prohibited)
Note: * When the DRAM interface is used, clear the AMXEXT bit to 0.
Rev. 3.0, 04/02, page 349 of 1064
For Synchronous DRAM Interface:
AMX
AMXEXT
SZ
Example Synchronous DRAM
Configurations
BANK
0
0
(16M: 512k
16 bits
2)
2
a[21]*
1
(16M: 512k
16 bits
2)
2
a[20]*
1
0
(16M: 1M
8 bits
2)
4
a[22]*
1
(16M: 1M
8 bits
2)
4
a[21]*
2
--
(64M: 1M
16 bits
4)
2
a[23:22]*
3
--
(64M: 2M
8 bits
4)
4
a[24:23]*
4
--
(64M: 512k
32 bits
4)
1
a[22:21]*
5
--
(64M: 1M
32 bits
2)
1
a[22]*
6
0
(64M: 4M
4 bits
4)
8
a[25:24]*
1
(256M: 4M
16 bits
4)
2
a[25:24]*
7
--
32
(16M: 256k
32 bits
2)
1
a[20]*
Note: a[x]: External address, not address pin
Bit 2--Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is
performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh
request cycle generation timer can be used as an interval timer.
Bit 2: RFSH
Description
0
Refreshing is not performed
(Initial value)
1
Refreshing is performed
Bit 1--Refresh Mode (RMODE): Specifies whether normal refreshing or self-refreshing is
performed when the RFSH bit is set to 1. When the RFSH bit is 1 and this bit is cleared to 0, CAS-
before-RAS refreshing or auto-refreshing is performed for DRAM and synchronous DRAM, using
the cycle set by refresh-related registers RTCNT, RTCOR, and RTCSR. If a refresh request is
issued during an external bus cycle, the refresh cycle is executed when the bus cycle ends. When
the RFSH bit is 1 and this bit is set to 1, the self-refresh state is set for DRAM and synchronous
DRAM, after waiting for the end of any currently executing external bus cycle. All refresh
requests for memory in the self-refresh state are ignored.
Bit 1: RMODE
Description
0
CAS-before-RAS refreshing is performed (when RFSH = 1)
(Initial value)
1
Self-refreshing is performed (when RFSH = 1)
Rev. 3.0, 04/02, page 350 of 1064
Bit 0--EDO Mode (EDOMODE): Used to specify the data sampling timing for data reads when
using EDO mode DRAM interface. The setting of this bit does not affect the operation timing of
memory other than DRAM. Set this bit to 1 only when DRAM is used.
13.2.9
PCMCIA Control Register (PCR)
The PCMCIA control register (PCR) is a 16-bit readable/writable register that specifies the
2(
and
:( signal assertion/negation timing for the PCMCIA interface connected to areas 5 and 6.
The
2( and :( signal assertion width is set by the wait control bits in the WCR2 register.
PCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit:
15
14
13
12
11
10
9
8
Bit name: A5PCW1 A5PCW0 A6PCW1 A6PCW0 A5TED2 A5TED1 A5TED0 A6TED2
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Bit name:
A6TED1 A6TED0 A5TEH2 A5TEH1 A5TEH0 A6TEH2 A6TEH1 A6TEH0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 and 14--PCMCIA Wait (A5PCW1, A5PCW0): These bits specify the number of waits
to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The
setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 15: A5PCW1
Bit 14: A5PCW0
Waits Inserted
0
0
0 (Initial value)
1
15
1
0
30
1
50
Bits 13 and 12--PCMCIA Wait (A6PCW1, A6PCW0): These bits specify the number of waits
to be added to the number of waits specified by WCR2 in a low-speed PCMCIA wait cycle. The
setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Rev. 3.0, 04/02, page 351 of 1064
Bit 13: A6PCW1
Bit 12: A6PCW0
Waits Inserted
0
0
0 (Initial value)
1
15
1
0
30
1
50
Bits 11 to 9--Address-OE/WE Assertion Delay (A5TED2A5TED0): These bits set the delay
time from address output to
2(/:( assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 11: A5TED2
Bit 10: A5TED1
Bit 9: A5TED0
Waits Inserted
0
0
0
0 (Initial value)
1
1
1
0
2
1
3
1
0
0
6
1
9
1
0
12
1
15
Bits 8 to 6--Address-OE/WE Assertion Delay (A6TED2A6TED0): These bits set the delay
time from address output to
2(/:( assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 8: A6TED2
Bit 7: A6TED1
Bit 6: A6TED0
Waits Inserted
0
0
0
0 (Initial value)
1
1
1
0
2
1
3
1
0
0
6
1
9
1
0
12
1
15
Bits 5 to 3--OE/WE Negation-Address Delay (A5TEH2A5TEH0): These bits set the address
hold delay time from
2(/:( negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Rev. 3.0, 04/02, page 352 of 1064
Bit 5: A5TEH2
Bit 4: A5TEH1
Bit 3: A5TEH0
Waits Inserted
0
0
0
0 (Initial value)
1
1
1
0
2
1
3
1
0
0
6
1
9
1
0
12
1
15
Bits 2 to 0--OE/WE Negation-Address Delay (A6TEH2A6TEH0): These bits set the address
hold delay time from
2(/:( negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 2: A6TEH2
Bit 1: A6TEH1
Bit 0: A6TEH0
Waits Inserted
0
0
0
0 (Initial value)
1
1
1
0
2
1
3
1
0
0
6
1
9
1
0
12
1
15
13.2.10
Synchronous DRAM Mode Register (SDMR)
The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is
written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3
synchronous DRAM.
Settings for the SDMR register must be made before accessing synchronous DRAM.
Rev. 3.0, 04/02, page 353 of 1064
Bit:
15
14
13
12
11
10
9
8
Initial value:
--
--
--
--
--
--
--
--
R/W:
W
W
W
W
W
W
W
W
Bit:
7
6
5
4
3
2
1
0
Initial value:
--
--
--
--
--
--
--
--
R/W:
W
W
W
W
W
W
W
W
Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register,
if the value to be set is "X" and the SDMR register address is "Y", value "X" is written to the
synchronous DRAM mode register by performing a write to address X + Y. When the
synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to
A2 of the SH7751 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7751
Series, the value actually written to the synchronous DRAM is the value of "X" shifted 2 bits to
the right.
For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address
H'FF900000 (address "Y") + H'08C0 (value "X") (= H'FF9008C0). As a result, H'0230 is written
to the SDMR register. The range of value "X" is H'0000 to H'0FFC.
Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address
H'FF940000 (address "Y") + H'08C0 (value "X") (= H'FF9408C0). As a result, H'0230 is written
to the SDMR register. The range of value "X" is H'0000 to H'0FFC.
The lower 16 bits of the address are set in the synchronous DRAM mode register.
The burst length is 4 and 8*. Setting to SDMR writes into the following addresses in byte size.
Note: * SH7751R only
Bus Width
CAS Latency
Area 2
Area 3
32
4
1
H'FF900048
H'FF940048
2
H'FF900088
H'FF940088
3
H'FF9000C8
H'FF9400C8
32
8*
1
H'FF90004C
H'FF94004C
2
H'FF90008C
H'FF94008C
3
H'FF9000CC
H'FF9400CC
Rev. 3.0, 04/02, page 354 of 1064
For a 32-bit bus:
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
0
0
0
0
0
0
0
0
0
LMO
DE2
LMO
DE1
LMO
DE0
WT BL2 BL1 BL0
10 bits set in case of 32-bit bus width
LMODE: RAS-CAS latency
BL:
Burst length
WT:
Wrap type (0: Sequential)
BL
LMODE
000: Reserved
000: Reserved
001: Reserved
001: 1
010: 4
010: 2
011: 8*
011: 3
100: Reserved
100: Reserved
101: Reserved
101: Reserved
110: Reserved
110: Reserved
111: Reserved
111: Reserved
Note: * SH7751R only
13.2.11
Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that
specifies the refresh cycle and whether interrupts are to be generated.
RTSCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
--
--
--
--
--
--
--
--
Bit:
7
6
5
4
3
2
1
0
CMF
CMIE
CKS2
CKS1
CKS0
OVF
OVIE
LMTS
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 355 of 1064
Bits 15 to 8--Reserved: These bits are always read as 0. For the write values, see section 13.2.15,
Notes on Accessing Refresh Control Registers.
Bit 7--Compare-Match Flag (CMF): Status flag that indicates a match between the refresh
timer counter (RTCNT) and refresh time constant register (RTCOR) values.
Bit 7: CMF
Description
0
RTCNT and RTCOR values do not match
(Initial value)
[Clearing condition]
When 0 is written to CMF
1
RTCNT and RTCOR values match
[Setting condition]
When RTCNT = RTCOR*
Note: * If 1 is written, the original value is retained.
Bit 6--Compare-Match Interrupt Enable (CMIE): Controls generation or suppression of an
interrupt request when the CMF flag is set to 1 in RTCSR. Do not set this bit to 1 when CAS-
before-RAS refreshing or auto-refreshing is used.
Bit 6: CMIE
Description
0
Interrupt requests initiated by CMF are disabled
(Initial value)
1
Interrupt requests initiated by CMF are enabled
Bits 5 to 3--Clock Select Bits (CKS2CKS0): These bits select the input clock for RTCNT. The
base clock is the external bus clock (CKIO). The RTCNT count clock is obtained by scaling CKIO
by the specified factor.
Bit 5: CKS2
Bit 4: CKS1
Bit 3: CKS0
Description
0
0
0
Clock input disabled
(Initial value)
1
Bus clock (CKIO)/4
1
0
CKIO/16
1
CKIO/64
1
0
0
CKIO/256
1
CKIO/1024
1
0
CKIO/2048
1
CKIO/4096
Rev. 3.0, 04/02, page 356 of 1064
Bit 2--Refresh Count Overflow Flag (OVF): Status flag that indicates that the number of
refresh requests indicated by the refresh count register (RFCR) has exceeded the number specified
by the LMTS bit in RTCSR.
Bit 2: OVF
Description
0
RFCR has not overflowed the count limit indicated by LMTS
(Initial value)
[Clearing condition]
When 0 is written to OVF
1
RFCR has overflowed the count limit indicated by LMTS
[Setting condition]
When RFCR overflows the count limit set by LMTS*
Note: * If 1 is written, the original value is retained.
Bit 1--Refresh Count Overflow Interrupt Enable (OVIE): Controls generation or suppression
of an interrupt request when the OVF flag is set to 1 in RTCSR.
Bit 1: OVIE
Description
0
Interrupt requests initiated by OVF are disabled
(Initial value)
1
Interrupt requests initiated by OVF are enabled
Bit 0--Refresh Count Overflow Limit Select (LMTS): Specifies the count limit to be compared
with the refresh count indicated by the refresh count register (RFCR). If the RFCR register value
exceeds the value specified by LMTS, the OVF flag is set.
Bit 0: LMTS
Description
0
Count limit is 1024
(Initial value)
1
Count limit is 512
13.2.12
Refresh Timer Counter (RTCNT)
The refresh timer counter (RTCNT) is an 8-bit readable/writable counter that is incremented by
the input clock (selected by bits CKS2CKS0 in the RTCSR register). When the RTCNT counter
value matches the RTCOR register value, the CMF bit is set in the RTCSR register and the
RTCNT counter is cleared.
RTCNT is initialized to H'0000 by a power-on reset, but continues to count when a manual reset is
performed. In standby mode, RTCNT is not initialized, and retains its contents.
Rev. 3.0, 04/02, page 357 of 1064
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
--
--
--
--
--
--
--
--
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
13.2.13
Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a readable/writable register that specifies the upper
limit of the RTCNT counter. The RTCOR register and RTCNT counter values (lower 8 bits) are
constantly compared, and when they match the CMF bit is set in the RTCSR register and the
RTCNT counter is cleared to 0. If the refresh bit (RFSH) has been set to 1 in the memory control
register (MCR) and CAS-before-RAS has been selected as the refresh mode, a memory refresh
cycle is generated when the CMF bit is set.
RTCOR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents,
in a manual reset and in standby mode.
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
--
--
--
--
--
--
--
--
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.0, 04/02, page 358 of 1064
13.2.14
Refresh Count Register (RFCR)
The refresh count register (RFCR) is a 10-bit readable/writable counter that counts the number of
refreshes by being incremented each time the RTCOR register and RTCNT counter values match.
If the RFCR register value exceeds the count limit specified by the LMTS bit in the RTCSR
register, the OVF flag is set in the RTCSR register and the RFCR register is cleared.
RFCR is initialized to H'0000 by a power-on reset, but is not initialized, and retains its contents, in
a manual reset and in standby mode.
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
--
--
--
--
--
--
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
13.2.15
Notes on Accessing Refresh Control Registers
When the refresh timer control/status register (RTCSR), refresh timer counter (RTCNT), refresh
time constant register (RTCOR), and refresh count register (RFCR) are written to, a special code
is added to the data to prevent inadvertent rewriting in the event of program runaway, etc. The
following procedures should be used for read/write operations.
Writing to RTCSR, RTCNT, RTCOR, and RFCR: A word transfer instruction must always be
used when writing to RTCSR, RTCNT, RTCOR, or RFCR. A write cannot be performed with a
byte transfer instruction.
When writing to RTCSR, RTCNT, or RTCOR, set B'10100101 in the upper byte and the write
data in the lower byte, as shown in figure 13.5. When writing to RFCR, set B'101001 in the 6 bits
starting from the MSB in the upper byte, and the write data in the remaining bits.
Rev. 3.0, 04/02, page 359 of 1064
15
14
13
12
11
10
9
8
1
0
1
0
0
1
0
1
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
1
0
1
0
0
1
7
6
5
4
3
2
1
0
Write data
Write data
RTCSR,
RTCNT,
RTCOR
RFCR
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when
reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0.
13.3
Operation
13.3.1
Endian/Access Size and Data Alignment
The SH7751 Series supports both big-endian mode, in which the most significant byte (MSByte)
is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant
byte (LSByte) is at the 0 address end. The mode is set by means of the MD5 external pin in a
power-on reset by means of the
5(6(7 pin, big-endian mode being set if the MD5 pin is low, and
little-endian mode if it is high.
A data bus width of 8, 16, or 32 bits can be selected for normal memory, 16 or 32 bits for DRAM,
32 bit for synchronous DRAM, and 8 or 16 bits for the PCMCIA interface. Data alignment is
carried out according to the data bus width and endian mode of each device. Accordingly, when
the data bus width is narrower than the access size, multiple bus cycles are automatically
generated to reach the access size. In this case, access is performed by automatically incrementing
addresses to the bus width. For example, when a long word access is performed at the area with an
8-bit bus width in the SRAM interface, each address is incremented one by one, and then access is
performed four times. In the 32-byte transfer, a total of 32-byte data is continuously transferred
according to the set bus width. The first access is performed on the data for which there was an
access request, and the remaining accesses are performed in 32-byte boundary data using
waparound. During these transfers, the bus is not released and refresh operation is not performed.
In the SH7751 Series, data alignment and data length conversion between the different interfaces
is performed automatically. Quadword access is used only in transfer by the DMAC.
The relationship between the endian mode, device data length, and access unit, is shown in tables
13.8 to 13.13.
Rev. 3.0, 04/02, page 360 of 1064
Data Configuration
MSB
LSB
Byte
Data 70
MSB
LSB
Word
Data 158
Data 70
MSB
LSB
Longword
Data 3124
Data 2316
Data 158
Data 70
MSB
LSB
Quadword
Data
6356
Data
5548
Data
4740
Data
3932
Data
3124
Data
2316
Data
158
Data
70
Table 13.8
32-Bit External Device/Big-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
Access
Size
Address No.
D31D24
D23D16 D15D8
D7D0
:(
:(
,
&$6
&$6
,
DQM3
:(
:(
,
&$6
&$6
,
DQM2
:(
:(
,
&$6
&$6
,
DQM1
:(
:(
,
&$6
&$6
,
DQM0
Byte
4n
1
Data
70
--
--
--
Asserted
4n+1
1
--
Data
70
--
--
Asserted
4n+2
1
--
--
Data
70
--
Asserted
4n+3
1
--
--
--
Data
70
Asserted
Word
4n
1
Data
158
Data
70
--
--
Asserted Asserted
4n+2
1
--
--
Data
158
Data
70
Asserted Asserted
Long-
word
4n
1
Data
3124
Data
2316
Data
158
Data
70
Asserted Asserted Asserted Asserted
Quad-
word
8n
1
Data
6356
Data
5548
Data
4740
Data
3932
Asserted Asserted Asserted Asserted
8n+4
2
Data
3124
Data
2316
Data
158
Data
70
Asserted Asserted Asserted Asserted
Rev. 3.0, 04/02, page 361 of 1064
Table 13.9
16-Bit External Device/Big-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
Access
Size
Address No. D31D24 D23D16 D15D8
D7D0
:(
:(
,
&$6
&$6
,
DQM3
:(
:(
,
&$6
&$6
,
DQM2
:(
:(
,
&$6
&$6
,
DQM1
:(
:(
,
&$6
&$6
,
DQM0
Byte
2n
1
--
--
Data
70
--
Asserted
2n+1
1
--
--
--
Data
70
Asserted
Word
2n
1
--
--
Data
158
Data
70
Asserted Asserted
Long-
word
4n
1
--
--
Data
3124
Data
2316
Asserted Asserted
4n+2
2
--
--
Data
158
Data
70
Asserted Asserted
Quad-
word
8n
1
--
--
Data
6356
Data
5548
Asserted Asserted
8n+2
2
--
--
Data
4740
Data
3932
Asserted Asserted
8n+4
3
--
--
Data
3124
Data
2316
Asserted Asserted
8n+6
4
--
--
Data
158
Data
70
Asserted Asserted
Rev. 3.0, 04/02, page 362 of 1064
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
Access
Size
Address No. D31D24 D23D16 D15D8
D7D0
:(
:(
,
&$6
&$6
,
DQM3
:(
:(
,
&$6
&$6
,
DQM2
:(
:(
,
&$6
&$6
,
DQM1
:(
:(
,
&$6
&$6
,
DQM0
Byte
n
1
--
--
--
Data
70
Asserted
Word
2n
1
--
--
--
Data
158
Asserted
2n+1
2
--
--
--
Data
70
Asserted
Long-
word
4n
1
--
--
--
Data
3124
Asserted
4n+1
2
--
--
--
Data
2316
Asserted
4n+2
3
--
--
--
Data
158
Asserted
4n+3
4
--
--
--
Data
70
Asserted
Quad-
word
8n
1
--
--
--
Data
6356
Asserted
8n+1
2
--
--
--
Data
5548
Asserted
8n+2
3
--
--
--
Data
4740
Asserted
8n+3
4
--
--
--
Data
3932
Asserted
8n+4
5
--
--
--
Data
3124
Asserted
8n+5
6
--
--
--
Data
2316
Asserted
8n+6
7
--
--
--
Data
158
Asserted
8n+7
8
--
--
--
Data
70
Asserted
Rev. 3.0, 04/02, page 363 of 1064
Table 13.11 32-Bit External Device/Little-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
Access
Size
Address No.
D31D24
D23D16
D15D8
D7D0
:(
:(
,
&$6
&$6
,
DQM3
:(
:(
,
&$6
&$6
,
DQM2
:(
:(
,
&$6
&$6
,
DQM1
:(
:(
,
&$6
&$6
,
DQM0
Byte
4n
1
--
--
Data
70
Asserted
4n+1
1
--
--
Data
70
--
Asserted
4n+2
1
--
Data
70
--
--
Asserted
4n+3
1
Data
70
--
--
--
Asserted
Word
4n
1
--
--
Data
158
Data
70
Asserted Asserted
4n+2
1
Data
158
Data
70
--
--
Asserted Asserted
Long-
word
4n
1
Data
3124
Data
2316
Data
158
Data
70
Asserted Asserted Asserted Asserted
Quad-
word
8n
1
Data
3124
Data
2316
Data
158
Data
70
Asserted Asserted Asserted Asserted
8n+4
2
Data
6356
Data
5548
Data
4740
Data
3932
Asserted Asserted Asserted Asserted
Rev. 3.0, 04/02, page 364 of 1064
Table 13.12 16-Bit External Device/Little-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
Access
Size
Address No. D31D24 D23D16 D15D8 D7D0
:(
:(
,
&$6
&$6
,
DQM3
:(
:(
,
&$6
&$6
,
DQM2
:(
:(
,
&$6
&$6
,
DQM1
:(
:(
,
&$6
&$6
,
DQM0
Byte
2n
1
--
--
--
Data
70
Asserted
2n+1
1
--
--
Data
70
--
Asserted
Word
2n
1
--
--
Data
158
Data
70
Asserted Asserted
Long-
word
4n
1
--
--
Data
158
Data
70
Asserted Asserted
4n+2
2
--
--
Data
3124
Data
2316
Asserted Asserted
Quad-
word
8n
1
--
--
Data
158
Data
70
Asserted Asserted
8n+2
2
--
--
Data
3124
Data
2316
Asserted Asserted
8n+4
3
--
--
Data
4740
Data
3932
Asserted Asserted
8n+6
4
--
--
Data
6356
Data
5548
Asserted Asserted
Rev. 3.0, 04/02, page 365 of 1064
Table 13.13 8-Bit External Device/Little-Endian Access and Data Alignment
Operation
Data Bus
Strobe Signals
Access
Size
Address No. D31D24 D23D16 D15D8
D7D0
:(
:(
,
&$6
&$6
,
DQM3
:(
:(
,
&$6
&$6
,
DQM2
:(
:(
,
&$6
&$6
,
DQM1
:(
:(
,
&$6
&$6
,
DQM0
Byte
n
1
--
--
--
Data
70
Asserted
Word
2n
1
--
--
--
Data
70
Asserted
2n+1
2
--
--
--
Data
158
Asserted
Long-
word
4n
1
--
--
--
Data
70
Asserted
4n+1
2
--
--
--
Data
158
Asserted
4n+2
3
--
--
--
Data
2316
Asserted
4n+3
4
--
--
--
Data
3124
Asserted
Quad-
word
8n
1
--
--
--
Data
70
Asserted
8n+1
2
--
--
--
Data
158
Asserted
8n+2
3
--
--
--
Data
2316
Asserted
8n+3
4
--
--
--
Data
3124
Asserted
8n+4
5
--
--
--
Data
3932
Asserted
8n+5
6
--
--
--
Data
4740
Asserted
8n+6
7
--
--
--
Data
5548
Asserted
8n+7
8
--
--
--
Data
6356
Asserted
Rev. 3.0, 04/02, page 366 of 1064
13.3.2
Areas
Area 0: For area 0, external address bits A28 to A26 are 000.
SRAM, MPX, and burst ROM can be set for this area.
A bus width of 8, 16, or 32 bits can be selected in a power-on reset by means of external pins
MD4 and MD3. For details, see Memory Bus Width in section 13.1.5.
When area 0 is accessed, the
&6 signal is asserted. In addition, the 5' signal, which can be used
as
2(, and write control signals :( to :(, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A0W2 to A0W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (
5'<).
When the burst ROM interface is used, the number of burst cycle transfer states is selected in the
range 2 to 9 according to the number of waits.
The read/write strobe signal address and the CS setup/hold time can be set, respectively, to 0 or 1
and to 0 to 3 cycles using the A0S0, A0H1, and A0H0 bits in the WCR3 register.
Area 1: For area 1, external address bits A28 to A26 are 001.
SRAM, MPX, and byte control SRAM can be set for this area.
A bus width of 8, 16, or 32 bits can be selected with bits A1SZ1 and A1SZ0 in the BCR2 register.
When MPX interface is set, a bus width of 32 bit should be selected with bits A1SZ1 and A1SZ0
in the BCR2 register. When byte control SRAM interface is set, select a bus width of 16 or 32 bits.
When area 1 is accessed, the
&6 signal is asserted. In addition, the 5' signal, which can be used
as
2(, and write control signals :( to :(, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A1W2 to A1W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (
5'<).
The read/write strobe signal address and
&6 setup and hold times can be set within a range of 01
and 03 cycles, respectively, by means of bit A1S0 and bits A1H1 and A1H0 in the WCR3
register.
Rev. 3.0, 04/02, page 367 of 1064
Area 2: For area 2, external address bits A28 to A26 are 010.
SRAM, MPX, and synchronous DRAM can be set to this area.
When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A2SZ1 and
A2SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 bit should be selected
with bits A2SZ1 and A2SZ0 in the BCR2 register. When synchronous DRAM interface is set,
select 32 bit with the SZ bits in the MCR register. For details, see Memory Bus Width in section
13.1.5.
When area 2 is accessed, the
&6 signal is asserted.
When SRAM interface is set, the
5' signal, which can be used as 2(, and write control signals
:( to :(, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A2W2 to A2W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (
5'<).
The read/write strobe signal address and
&6 setup and hold times can be set within a range of 01
and 03 cycles, respectively, by means of bit A2S0 and bits A2H1 and A2H0 in the WCR3
register.
When synchronous DRAM interface is set, the
5$6 and &$6 signals, RD/:5 signal, and byte
control signals DQM0 to DQM3 are asserted, and address multiplexing is performed.
5$6, &$6,
and data timing control, and address multiplexing control, can be set using the MCR register.
Area 3: For area 3, external address bits A28 to A26 are 011.
SRAM, MPX, DRAM, and synchronous DRAM, can be set to this area.
When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A3SZ1 and
A3SZ0 in the BCR2 register. When MPX interface is set, a bus width of 32 bit should be selected
with bits A3SZ1 and A3SZ0 in the BCR2 register. When DRAM interface is set, 16 or 32 bits can
be selected with the SZ bits in the MCR register. When synchronous DRAM interface is set, select
32 bit with the SZ bits in MCR. For details, see Memory Bus Width in section 13.1.5.
When area 3 is accessed, the
&6 signal is asserted.
When SRAM interface is set, the
5' signal, which can be used as 2(, and write control signals
:( to :(, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A3W2 to A3W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (
5'<).
Rev. 3.0, 04/02, page 368 of 1064
The read/write strobe signal address and
&6 setup and hold times can be set within a range of 01
and 03 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3
register.
When synchronous DRAM interface is set, the
5$6 and &$6 signals, RD/:5 signal, and byte
control signals DQM0 to DQM3 are asserted, and address multiplexing is performed. When
DRAM interface is set, the
5$6 signal, &$6 to &$6 signals, and RD/:5 signal are asserted,
and address multiplexing is performed.
5$6, &$6, and data timing control, and address
multiplexing control, can be set using the MCR register.
Area 4: For area 4, physical address bits A28 to A26 are 100.
SRAM, MPX, and byte control SRAM can be set to this area.
A bus width of 8, 16, or 32 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2 register.
When MPX interface is set, a bus width of 32 bit should be selected with bits A4SZ1 and A4SZ0
in the BCR2 register. When byte control SRAM interface is set, select a bus width of 16 or 32 bits.
For details, see Memory Bus Width in section 13.1.5.
When area 4 is accessed, the
&6 signal is asserted, and the 5' signal, which can be used as 2(,
and write control signals
:( to :(, are also asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A4W2 to A4W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (
5'<).
The read/write strobe signal address and
&6 setup and hold times can be set within a range of 01
and 03 cycles, respectively, by means of bit A4S0 and bits A4H1 and A4H0 in the WCR3
register.
Area 5: For area 5, external address bits A28 to A26 are 101.
SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area.
When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A5SZ1 and
A5SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can
be selected with bits A5SZ1 and A5SZ0 in BCR2. When MPX interface is set, a bus width of 32
bit should be selected with bits A5SZ1 and A5SZ0 in BCR2. When a PCMCIA interface is set,
either 8 or 16 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. For details, see
Memory Bus Width in section 13.1.5.
When area 5 is accessed with SRAM interface set, the
&6 signal is asserted. In addition, the 5'
signal, which can be used as
2(, and write control signals :( to :(, are asserted. When a
PCMCIA interface is connected, the
&($ and &($ signals, the 5' signal, which can be used
Rev. 3.0, 04/02, page 369 of 1064
as
2(, and the :(, :(, :(, and :( signals, which can be used as :(, ,&,25',
,&,2:5, and 5(*, respectively, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A5W2 to A5W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (
5'<).
When the burst function is used, the number of burst cycle transfer states is determined in the
range 2 to 9 according to the number of waits.
The read/write strobe signal address and
&6 setup and hold times can be set within a range of 01
and 03 cycles, respectively, by means of bit A5S0 and bits A5H1 and A5H0 in the WCR3
register.
When a PCMCIA interface is used, the address
&($ and &($ setup and hold times with
respect to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1
and AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of
wait cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits
set in PCR is added to the number of waits set in WCR2.
Area 6: For area 6, external address bits A28 to A26 are 110.
SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area.
When SRAM interface is set, a bus width of 8, 16, or 32 bits can be selected with bits A6SZ1 and
A6SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits can
be selected with bits A6SZ1 and A6SZ0 in BCR2. When MPX interface is set, a bus width of 32
bit should be selected with bits A6SZ1 and A6SZ0 in BCR2. When a PCMCIA interface is set,
either 8 or 16 bits should be selected with bits A6SZ1 and A6SZ0 in BCR2. For details, see
Memory Bus Width in section 13.1.5.
When area 6 space is accessed with SRAM interface set, the
&6 signal is asserted. In addition,
the
5' signal, which can be used as 2(, and write control signals :( to :(, are asserted.
When a PCMCIA interface is connected, the
&(% and &(% signals, the 5' signal, which can
be used as
2(, and the :(, :(, :(, and :( signals, which can be used as :(, ,&,25',
,&,2:5, and 5(*, respectively, are asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A6W2 to A6W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (
5'<).
When the burst function is used, the number of burst cycle transfer states is determined in the
range 2 to 9 according to the number of waits.
Rev. 3.0, 04/02, page 370 of 1064
The read/write strobe signal address and
&6 setup and hold times can be set within a range of 01
and 03 cycles, respectively, by means of bit A6S0 and bits A6H1 and A6H0 in the WCR3
register.
When a PCMCIA interface is used, the address
&(% and &(% setup and hold times with respect
to the read/write strobe signals can be set in the range of 0 to 15 cycles with bits AnTED1 and
AnTED0, and bits AnTEH1 and AnTEH0, in the PCR register. In addition, the number of wait
cycles can be set in the range 0 to 50 with bits AnPCW1 and AnPCW0. The number of waits set in
PCR is added to the number of waits set in WCR2.
13.3.3
SRAM Interface
Basic Timing: The SRAM interface of the SH7751 Series uses strobe signal output in
consideration of the fact that mainly SRAM will be connected. Figure 13.6 shows the SRAM
timing of normal space accesses. A no-wait normal access is completed in two cycles. The
%6
signal is asserted for one cycle to indicate the start of a bus cycle. The
&6Q signal is asserted on
the T1 rising edge, and negated on the next T2 clock rising edge. Therefore, there is no negation
period in case of access at minimum pitch.
There is no access size specification when reading. The correct access address is output to the
address pins (A[25:0]), but since there is no access size specification, 32 bits are always read in
the case of a 32-bit device, and 16 bits in the case of a 16-bit device. When writing, only the
:(
signal for the byte to be written is asserted. For details, see section 13.3.1, Endian/Access Size and
Data Alignment.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not
released during this transfer.
Rev. 3.0, 04/02, page 371 of 1064
T1
CKIO
A25A0
RD/
D31D0
(read)
D31D0
(write)
T2
DACKn
(SA: IO
memory)
DACKn
(SA: IO
memory)
DACKn
(DA)
SA:
DA:
Single address DMA
Dual address DMA
Figure 13.6 Basic Timing of SRAM Interface
Rev. 3.0, 04/02, page 372 of 1064
Figures 13.7, 13.8, and 13.9 show examples of connection to 32-, 16-, and 8-bit data width
SRAM.
A16
A0
I/O7
I/O0
A18
A2
D31
D24
D23
D16
D15
D8
D7
D0
SH7751 Series
128k
8-bit
SRAM
A16
A0
I/O7
I/O0
A16
A0
I/O7
I/O0
A16
A0
I/O7
I/O0
Figure 13.7 Example of 32-Bit Data Width SRAM Connection
Rev. 3.0, 04/02, page 373 of 1064
A16
A0
I/O7
I/O0
A17
A1
D15
D8
D7
D0
SH7751 Series
128k
8-bit
SRAM
A16
A0
I/O7
I/O0
Figure 13.8 Example of 16-Bit Data Width SRAM Connection
Rev. 3.0, 04/02, page 374 of 1064
A16
A0
D7
D0
SH7751 Series
128k
8-bit
SRAM
A16
A0
I/O7
I/O0
Figure 13.9 Example of 8-Bit Data Width SRAM Connection
Wait State Control: Wait state insertion on the SRAM interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 13.2.5, Wait
Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the SRAM interface wait
timing shown in figure 13.10.
Rev. 3.0, 04/02, page 375 of 1064
T1
CKIO
A25A0
RD/
D31D0
(read)
D31D0
(write)
Tw
T2
DACKn
(SA: IO
memory)
DACKn
(SA: IO
memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.10 SRAM Interface Wait Timing (Software Wait Only)
Rev. 3.0, 04/02, page 376 of 1064
When software wait insertion is specified by WCR2, the external wait input
5'< signal is also
sampled.
5'< signal sampling is shown in figure 13.11. A single-cycle wait is specified as a
software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore,
the
5'< signal has no effect if asserted in the T1 cycle or the first Tw cycle. The 5'< signal is
sampled on the rising edge of the clock.
T1
CKIO
A25A0
RD/
(read)
D31D0
(read)
(write)
D31D0
(write)
Tw
Twe
T2
DACKn
(SA: IO
memory)
DACKn
(SA: IO
memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by
5'<
5'< Signal)
Rev. 3.0, 04/02, page 377 of 1064
Read-Strobe Negate Timing (Setting Only Possible in the SH7751R): When the SRAM
interface is used, timing for the negation of the strobe during read operations can be specified by
the setting of the A1RDH and A4RDH bits of the WCR3 register. For information about this
setting, see the description of the WCR3 register. When a byte control SRAM setting is made,
AnRDH should be cleared to 0.
TS1
CKIO
A25A0
RD/
RD
D31D0
T1
Tw
Tw
Tw
Tw
T2
TH1
TH2
*
TS1: Setup wait
WCR3.AnS
(0 to 1)
Tw: Access wait
WCR2.AnW
(0 to 15)
TH1, TH2: Hold wait
WCR3.AnH
(0 to 3)
Note:
*
When AnRDH is set to 1
Figure 13.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting)
Rev. 3.0, 04/02, page 378 of 1064
13.3.4
DRAM Interface
Direct Connection of DRAM: When the memory type bits (DRAMTP20) in BCR1 are set to
100, area 3 becomes DRAM interface. The DRAM interface function can then be used to connect
DRAM to the SH7751 Series.
16 or 32 bits can be selected as the interface data width.
2-CAS 16-bit DRAMs can be connected, since
&$6 is used to control byte access.
Signals used for connection are
&6, 5$6, &$6 to &$6, and RD/:5. &$6 to &$6 are not
used when the data width is 16 bits.
In addition to normal read and write access modes, fast page mode is supported for burst access.
EDO mode, which enables the DRAM access time to be increased, is supported.
A10
A2
RD/
D31
D16
D15
D0
SH7751 Series
256k
16-bit
DRAM
A8
A0
I/O15
I/O0
A8
A0
I/O15
I/O0
Figure 13.13 Example of DRAM Connection (32-Bit Data Width, Area 3)
Rev. 3.0, 04/02, page 379 of 1064
Address Multiplexing: When area 3 is designated as DRAM interface, address multiplexing is
always performed in accesses to DRAM. This enables DRAM, which requires row and column
address multiplexing, to be connected to the SH7751 Series without using an external address
multiplexer circuit. Any of the five multiplexing methods shown below can be selected, by setting
bits AMXEXT and AMX20 in MCR. The relationship between the AMXEXT and AMX20 bits
and address multiplexing is shown in table 13.14. The address output pins subject to address
multiplexing are A17 to A1. The address signals output by pins A25 to A18 are undefined.
Table 13.14 Relationship between AMXEXT and AMX20 Bits and Address Multiplexing
Setting
External Address Pins
AMXEXT
AMX2
AMX1
AMX0
Number
of Column
Address
Bits
Output Timing
A1A13
A14
A15
A16
A17
0
0
0
0
8 bits
Column address
A1A13
A14
A15
A16
A17
Row address
A9A21
A22
A23
A24
A25
1
9 bits
Column address
A1A13
A14
A15
A16
A17
Row address
A10A22
A23
A24
A25
A17
1
0
10 bits
Column address
A1A13
A14
A15
A16
A17
Row address
A11A23
A24
A25
A16
A17
1
11 bits
Column address
A1A13
A14
A15
A16
A17
Row address
A12A24
A25
A15
A16
A17
1
0
0
12 bits
Column address
A1A13
A14
A15
A16
A17
Row address
A13A25
A14
A15
A16
A17
Other settings
Reserved
--
--
--
--
--
--
Rev. 3.0, 04/02, page 380 of 1064
Basic Timing: The basic timing for DRAM access is 4 cycles. This basic timing is shown in
figure 13.14. Tpc is the precharge cycle, Tr the
5$6 assert cycle, Tc1 the &$6 assert cycle, and
Tc2 the read data latch cycle.
Tr1
CKIO
Address
RD/
D31D0
(read)
D31D0
(write)
Tr2
Tc1
Tc2
Tpc
Row
Column
DACKn
(SA: IO
memory)
DACKn
(SA: IO
memory)
Notes: IO : DACK device
SA : Single address DMA transfer
DA : Dual address DMA transfer
The DACK is in the high-active setting
For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.14 Basic DRAM Access Timing
Rev. 3.0, 04/02, page 381 of 1064
Wait State Control: As the clock frequency increases, it becomes impossible to complete all
states in one cycle as in basic access. Therefore, provision is made for state extension by using the
setting bits in WCR2 and MCR. The timing with state extension using these settings is shown in
figure 13.15. Additional Tpc cycles (cycles used to secure the
5$6 precharge time) can be
inserted by means of the TPC bit in MCR, giving from 1 to 7 cycles. The number of cycles from
5$6 assertion to &$6 assertion can be set to between 2 and 5 by inserting Trw cycles by means of
the RCD bit in MCR. Also, the number of cycles from
&$6 assertion to the end of the access can
be varied between 1 and 16 according to the setting of A3W2 to A3W0 in WCR2.
Tr1
CKIO
Address
RD/
D31D0
(read)
D31D0
(write)
Tr2
Trw
Tc1
Tcw
Tc2
Tpc
Tpc
DACKn
(SA: IO
memory)
DACKn
(SA: IO
memory)
Column
Row
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.15 DRAM Wait State Timing
Rev. 3.0, 04/02, page 382 of 1064
Burst Access: In addition to the normal DRAM access mode in which a row address is output in
each data access, a fast page mode is also provided for the case where consecutive accesses are
made to the same row. This mode allows fast access to data by outputting the row address only
once, then changing only the column address for each subsequent access. Normal access or burst
access using fast page mode can be selected by means of the burst enable (BE) bit in MCR. The
timing for burst access using fast page mode is shown in figure 13.16.
If the access size exceeds the set bus width, burst access is performed. In a 32-byte transfer, the
first access comprises a longword that includes the data requiring access. The remaining accesses
are performed on 32-byte boundary data that includes the relevant data. In burst transfer,
wraparound writing is performed for 32-byte data.
Tr2
Tc1
Tc2
Tc1
Tc2
Tc2
Tr1
Row
c1
c2
c8
Tc1
Tpc
Tc2
Tc1
CKIO
Address
RD/
D31D0
(read)
D31D0
(write)
DACKn
(SA: IO
memory)
DACKn
(SA: IO
memory)
d8
d2
d2
d1
d1
d8
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.16 DRAM Burst Access Timing
Rev. 3.0, 04/02, page 383 of 1064
EDO Mode: With DRAM, in addition to the mode in which data is output to the data bus only
while the
&$6 signal is asserted in a data read cycle, an EDO (extended data out) mode is also
provided in which, once the
&$6 signal is asserted while the 5$6 signal is asserted, even if the
&$6 signal is negated, data is output to the data bus until the &$6 signal is next asserted. In the
SH7751 Series, the EDO mode bit (EDOMODE) in MCR enables either normal access/burst
access using fast page mode, or EDO mode normal access/burst access, to be selected for DRAM.
When EDO mode is set, BE must be set to 1 in MCR. EDO mode normal access is shown in
figure 13.17, and burst access in figure 13.18.
CAS Negation Period: The CAS negation period can be set to 1 or 2 by means of the TCAS bit in
the MCR register.
Tr1
Tc1
Tc2
Tce
Tpc
Tr2
CKIO
Address
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
Row
Column
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.17 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)
Rev. 3.0, 04/02, page 384 of 1064
Tr1
c1
c2
c8
Tc1
Tc2
Tc1
Tc2
Tc1
Tc1
Tr2
Tc2
Tc2
Tpc
Tce
CKIO
Address
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
d8
d2
d1
Row
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.18 Burst Access Timing in DRAM EDO Mode
RAS Down Mode: The SH7751 Series has an address comparator for detecting row address
matches in burst mode. By using this address comparator, and also setting RAS down mode
specification bit RASD to 1, it is possible to select RAS down mode, in which
5$6 remains
asserted after the end of an access. When RAS down mode is used, if the refresh cycle is longer
than the maximum DRAM
5$6 assert time, the refresh cycle must be decreased to or below the
maximum value of t
RAS
.
In RAS down mode, in the event of an access to an address with a different row address, an access
to a different area, a refresh request, or a bus release request,
5$6 is negated and the necessary
operation is performed. When DRAM access is resumed after this, since this is the start of RAS
down mode, the operation starts with row address output. Timing charts are shown in figures
13.19 (1), (2), (3), and (4).
Rev. 3.0, 04/02, page 385 of 1064
Tr1
Tr2
Tc1
Tc2
Tc1
Tc1
Tpc
Row
c1
c2
c8
Tc2
Tc2
Tc1
Tc2
CKIO
Address
RD/
D31D0
(read)
D31D0
(write)
DACKn
(SA: IO
memory)
DACKn
(SA: IO
memory)
d8
d2
d1
d8
d2
d1
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19(1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0)
Rev. 3.0, 04/02, page 386 of 1064
Tnop
Tc1
Tc2
Tc1
Tc2
Tc1
Tc1
Tc2
Tc2
CKIO
Address
RD/
D31D0
(read)
D31D0
(write)
DACKn
(SA: IO
memory)
DACKn
(SA: IO
memory)
c1
c2
c8
d1
d1
d2
d8
d2
d8
End of RAS down mode
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19(2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(Fast Page Mode, RCD = 0, AnW = 0)
Rev. 3.0, 04/02, page 387 of 1064
Tpc
Tr2
Tc1
Tc2
Tc1
Tc2
Tc2
Tr1
c1
c2
c8
Tc1
Tc1
Tce
Tc2
CKIO
Address
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
d8
d2
d1
Row
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19(3) DRAM Burst Bus Cycle, RAS Down Mode Start
(EDO Mode, RCD = 0, AnW = 0)
Rev. 3.0, 04/02, page 388 of 1064
Tc2
Tc1
Tc2
Tc1
Tc2
Tc2
Tc1
c1
c2
c8
Tc1
Tnop
Tce
CKIO
Address
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
d8
d2
d1
End of RAS down mode
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19(4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0)
Rev. 3.0, 04/02, page 389 of 1064
Refresh: The bus state controller includes a function for controlling DRAM refreshing.
Distributed refreshing using a CAS-before-RAS cycle can be performed for DRAM by clearing
the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. Self-refresh mode is also supported.
CAS-before-RAS Refresh
When CAS-before-RAS refresh cycles are executed, refreshing is performed at intervals
determined by the input clock selected by bits CKS2CKS0 in RTCSR, and the value set in
RTCOR. The value of bits CKS2CKS0 in RTCOR should be set so as to satisfy the
specification for the DRAM refresh interval. First make the settings for RTCOR, RTCNT, and
the RMODE and RFSH bits in MCR, then make the CKS2CKS0 setting. When the clock is
selected by CKS2CKS0, RTCNT starts counting up from the value at that time. The RTCNT
value is constantly compared with the RTCOR value, and if the two values are the same, a
refresh request is generated and the
%$&. pin goes high. If the SH7751 Series external bus
can be used, CAS-before-RAS refreshing is performed. At the same time, RTCNT is cleared to
zero and the count-up is restarted. Figure 13.20 shows the operation of CAS-before-RAS
refreshing.
RTCNT value
RTCOR-1
H'00000000
RTCSR.CKS20
External bus
Refresh request cleared
by start of refresh cycle
= 000
000
RTCNT cleared to 0 when
RTCNT = RTCOR
CAS-before-RAS refresh cycle
Time
Refresh
request
Figure 13.20 CAS-Before-RAS Refresh Operation
Figure 13.21 shows the timing of the CAS-before-RAS refresh cycle.
The number of RAS assert cycles in the refresh cycle is specified by bits TRAS2TRAS0 in
MCR. The specification of the RAS precharge time in the refresh cycle is determined by the
setting of bits TRC2TRC0 in MCR.
Rev. 3.0, 04/02, page 390 of 1064
TRr2
TRr3
TRr4
TRr5
Trc
TRr1
Trc
Trc
CKIO
A25A0
RD/
D31D0
Figure 13.21 DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)
Self-Refresh
The self-refreshing supported by the SH7751 Series is shown in figure 13.22.
After the self-refresh is cleared, the refresh controller immediately generates a refresh request.
The RAS precharge time immediately after the end of the self-refreshing can be set by bits
TRC2TRC0 in MCR.
DRAMs include low-power products (L versions) with a long refresh cycle time (for example,
the HM51W4160AL L version has a refresh cycle of 1024 cycles/128 ms compared with 1024
cycles/16 ms for the normal version). With these DRAMs, however, the same refresh cycle as
for the normal version is requested only in the case of refreshing immediately following self-
refreshing. To ensure efficient DRAM refreshing, therefore, processing is needed to generate
an overflow interrupt and restore the refresh cycle to the proper value, after CAS-before-RAS
refreshing has been performed following self-refreshing of an L-version DRAM, using the
OVF, OVIE, and LMTS bits in RTCSR and the refresh controller's refresh count register
(RFCR). The necessary procedure is as follows.
Rev. 3.0, 04/02, page 391 of 1064
1. Normally, set the refresh counter count cycle to the optimum value for the L version (e.g.
1024 cycles/128 ms).
2. When a transition is made to self-refreshing:
a. Provide an interrupt handler to restore the refresh counter count value to the optimum
value for the L version (e.g. 1024 cycles/128 ms) when a refresh counter overflow
interrupt is generated.
b. Re-set the refresh counter count cycle to the requested short cycle (e.g. 1024 cycles/16
ms), set refresh controller overflow interruption, and clear the refresh controller's
refresh count register (RFCR) to 0.
c. Set self-refresh mode.
By using this procedure, the refreshing immediately following a self-refresh will be performed
in a short cycle, and when adequate refreshing ends, an interrupt is generated and the setting
can be restored to the original refresh cycle.
CAS-before-RAS refreshing is performed in normal operation, in sleep mode, and in the case
of a manual reset.
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the
case of a manual reset.
When the bus has been released in response to a bus arbitration request, or when a transition is
made to standby mode, signals generally become high-impedance, but whether the
5$6 and
&$6 signals become high-impedance or continue to be output can be controlled by the
HIZCNT bit in BCR1. This enables the DRAM to be kept in the self-refreshing state.
Relationship between Refresh Requests and Bus Cycle Requests
If a refresh request is generated during execution of a bus cycle, execution of the refresh is
deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus
cycles generated because the data bus width is smaller than the access size (for example, when
performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as
a cache fill or write-back, and also between read and write cycles during execution of a TAS
instruction, and between read and write cycles when DMAC dual address transfer is executed.
If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution
is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a
refresh is waiting to be executed, so that a new refresh request is generated, the previous
refresh request is eliminated. In order for refreshing to be performed normally, care must be
taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh
interval. When a refresh request is generated, the
%$&. pin is negated (driven high).
Therefore, normal refreshing can be performed by having the
%$&. pin monitored by a bus
master other than the SH7751 Series requesting the bus, or the bus arbiter, and returning the
bus to the SH7751 Series.
Rev. 3.0, 04/02, page 392 of 1064
TRr2
TRr3
TRr4
TRr5
Trc
TRr1
Trc
Trc
CKIO
A25A0
RD/
D63D0
Figure 13.22 DRAM Self-Refresh Cycle Timing
Power-On Sequence: Regarding use of DRAM after powering on, it is requested that a wait time
(at least 100
s or 200
s) during which no access can be performed be provided, followed by at
least the prescribed number (usually 8) of dummy CAS-before-RAS refresh cycles. As the bus
state controller does not perform any special operations for a power-on reset, the necessary power-
on sequence must be carried out by the initialization program executed after a power-on reset.
Rev. 3.0, 04/02, page 393 of 1064
13.3.5
Synchronous DRAM Interface
Direct Connection of Synchronous DRAM: Since synchronous DRAM can be selected by the
&6 signal, it can be connected to external memory space areas 2 and 3 using 5$6 and other
control signals in common. If the memory type bits (DRAMTP20) in BCR1 are set to 010, area 3
is synchronous DRAM interface; if set to 011, areas 2 and 3 are both synchronous DRAM
interface.
The SH7751 Series supports burst read and burst write operations with a burst length of 4 as a
synchronous DRAM operating mode. The data bus width is 32 bit, and the SZ size bits in MCR
must be set to 11. The burst enable bit (BE) in MCR is ignored, a 32-byte burst transfer is
performed in a cache fill/copy-back cycle. In write-through area write operations and non-
cacheable area read/write operations, 16-byte data is read even in a single read because accessing
synchronous DRAM is by burst-length 4 burst read/write operations. 16-byte data transfer is also
performed in a single write, but DQMn is not asserted when unnecessary data is transferred.
In the SH7751R, an 8-burst-length burst read/burst write mode is also supported as a synchronous
DRAM operating mode. The data bus width is 32 bits, and the SZ size bits in MCR must be set to
11. Burst enable bit BE in MCR is ignored, and a 32-byte burst transfer is performed in a cache
fill/copy-back cycle. For write-through area writes and non-cacheable area reads/writes,
synchronous DRAM is accessed with an 8-burst-length burst read/write, and therefore 32 bytes of
data are read even in the case of a single read. In the case of a single write, 32-byte data transfer is
performed but DQMn is not asserted in the case of an unnecessary data transfer. For a description
of the case where an 8-burst-length setting is made, see section 13.3.6, Burst ROM Interface. For
information on the burst length, see section 13.2.10, Synchronous DRAM Mode Register
(SDMR), and section 13.3.5, Power-On Sequence.
The control signals for connection of synchronous DRAM are
5$6, &$6, RD/:5, &6 or &6,
DQM0 to DQM3, and CKE. All the signals other than
&6 and &6 are common to all areas, and
signals other than CKE are valid and latched only when
&6 or &6 is asserted. Synchronous
DRAM can therefore be connected in parallel to a number of areas. CKE is negated (driven low)
when the frequency is changed, when the clock is unstable after the clock supply is stopped and
restarted, or when self-refreshing is performed, and is always asserted (high) at other times.
Commands for synchronous DRAM are specified by
5$6, &$6, RD/:5, and specific address
signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks
(PALL), precharge specified bank (PRE), row address strobe bank active (ACTV), read (READ),
read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register
setting (MRS).
Byte specification is performed by DQM0 to DQM3. A read/write is performed for the byte for
which the corresponding DQM signal is low. When the bus width is 32 bits, in big-endian mode
DQM3 specifies an access to address 4n, and DQM0 specifies an access to address 4n + 3. In
Rev. 3.0, 04/02, page 394 of 1064
little-endian mode, DQM3 specifies an access to address 4n + 3, and DQM0 specifies an access to
address 4n.
Figure 13.23 shows examples of the connection of 16M
16-bit synchronous DRAMs.
A11A2
CKIO
CKE
RD/
D31D16
DQM3
DQM2
SH7751 Series
512k
16-bit
2-bank
synchronous DRAM
A9A0
CLK
CKE
I/O15I/O0
DQMU
DQML
D15D0
DQM1
DQM0
A9A0
CLK
CKE
I/O15I/O0
DQMU
DQML
Figure 13.23 Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3)
Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMXEXT and AMX2
AMX0 in MCR. Table 13.15 shows the relationship between the address multiplex specification
bits and the bits output at the address pins. See Appendix E, Synchronous DRAM Address
Multiplexing Tables.
The address signals output at address pins A25A18, A1, and A0 are not guaranteed.
When A0, the LSB of the synchronous DRAM address, is connected to the SH7751 Series, it
makes a longword address specification. Connection should therefore be made in this order:
connect pin A0 of the synchronous DRAM to pin A2 of the SH7751 Series, then connect pin A1
to pin A3.
Rev. 3.0, 04/02, page 395 of 1064
Table 13.15 Example of Correspondence between SH7751 Series and Synchronous DRAM
Address Pins (32-Bit Bus Width, AMX2AMX0 = 000, AMXEXT = 0)
SH7751 Series Address Pin
Synchronous DRAM Address Pin
RAS Cycle
CAS Cycle
Function
A13
A21
A21
A11
BANK select bank address
A12
A20
H/L
A10
Address precharge setting
A11
A19
0
A9
Address
A10
A18
0
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
Not used
Not used
Not used
A0
Not used
Not used
Not used
Burst Read: The timing chart for a burst read is shown in figure 13.24. In the following example
it is assumed that two 512k
16-bit
2-bank synchronous DRAMs are connected, and a 32-bit
data width is used. The burst length is 4. After the Tr cycle in which the ACTV command is
output, a READ command is issued in the Tc1 cycle and, 4 cycles after that, a READA command
is issued and read data is fetched on the rising edge of the external command clock (CKIO) from
cycle Td1 to cycle Td8. The Tpc cycle is used to wait for completion of auto-precharge based on
the READA command inside the synchronous DRAM; no new access command can be issued to
the same bank during this cycle. In the SH7751 Series, the number of Tpc cycles is determined by
the specification of bits TPC2TPC0 in MCR, and commands are not issued for the synchronous
DRAM during this interval.
The example in figure 13.24 shows the basic cycle. To connect slower synchronous DRAM, the
cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by bits
RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case
of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous
DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READ
command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles
independently for areas 2 and 3 by means of bits A2W2A2W0 and A3W2A3W0 in WCR2.
This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
Rev. 3.0, 04/02, page 396 of 1064
Tr
Trw
Tc1
Tc2
Tc3
Tc4/Td1
Td3
Td2
Td4
CKIO
Bank
Precharge-sel
Address
RD/
D31D0
(read)
DQMn
DACKn
(SA: IO
memory)
CKE
H/L
c5
Td5
Td6
Td8
Td7
Tpc
c1
c1
c2
c3
c4
c5
c6
Row
Row
Row
c7
c8
H/L
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.24 Basic Timing for Synchronous DRAM Burst Read
Rev. 3.0, 04/02, page 397 of 1064
In a synchronous DRAM cycle, the
%6 signal is asserted for one cycle at the beginning of each
data transfer cycle that is in response to a READ or READA command. Data are accessed in the
following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that
include the missing data are first read by the initial READ command; after that, the data between
16-bit boundaries data that include the missing data are read in a wraparound way. The
subsequently issued READA command reads the 16 bytes of data, which is the remainder of the
data between 32-byte boundaries.
Single Read: With the SH7751 Series, as synchronous DRAM is set to burst read/burst write
mode, read data output continues after the required data has been read. To prevent data collisions,
after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and the
SH7751 Series waits for the end of the synchronous DRAM operation. The
%6 signal is asserted
only in Td1.
There are 4 burst transfers in a read. In cache-through and other DMA read cycles, of cycles Td1
to Td4.
Since such empty cycles increase the memory access time, and tend to reduce program execution
speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area
accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to
be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM
specified as the source.
Rev. 3.0, 04/02, page 398 of 1064
Tr
Tc1
Tc2
c1
Tc3 Tc4/Td1 Td2
Td4
Trw
c1
Td3
Tpc
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(read)
CKE
DACKn
(SA: IO
memory)
Row
Row
Row
H/L
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.25 Basic Timing for Synchronous DRAM Single Read
Burst Write: The timing chart for a burst write is shown in figure 13.26. In the SH7751 Series, a
burst write occurs only in the event of 32-byte transfer. In a burst write operation, the WRIT
command is issued in the Tc1 cycle following the Tr cycle in which the ACTV command is output
and, 4 cycles later, the WRITA command is issued. In the write cycle, the write data is output at
the same time as the write command. In the case of the write with auto-precharge command,
precharging of the relevant bank is performed in the synchronous DRAM after completion of the
write command, and therefore no command can be issued for the same bank until precharging is
completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle
Trwl is also added as a wait interval until precharging is started following the write command.
Issuance of a new command for the synchronous DRAM is postponed during this interval. The
number of Trwl cycles can be specified by bits TRWL2TRWL0 in MCR. Access starts from 16-
byte boundary data, and 32-byte boundary data is written in wraparound mode. DACK is asserted
two cycles before the data write cycle.
Rev. 3.0, 04/02, page 399 of 1064
Tr
Tc1
Tc2
Tc3
Tc4
Tc5
Tc7
Trw
c1
Tc6
CKIO
Bank
Precharge-sel
Address
CSn
DQMn
RD/WR
RAS
CASS
D31D0
(write)
BS
CKE
DACKn
(SA: IO
memory)
c1
c2
c3
c4
c5
c6
c7
c8
Row
Row
Tc8
Trw1
Tpc
Trw1
H/L
H/L
c5
Row
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.26 Basic Timing for Synchronous DRAM Burst Write
Rev. 3.0, 04/02, page 400 of 1064
Single Write: The basic timing chart for write access is shown in figure 13.27. In a single write
operation, following the Tr cycle in which ACTV command output is performed, a WRITA
command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data
is output at the same time as the write command. In the case of a write with auto-precharge,
precharging of the relevant bank is performed in the synchronous DRAM after completion of the
write command, and therefore no command can be issued for the synchronous DRAM until
precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a
read access, cycle Trwl is also added as a wait interval until precharging is started following the
write command. Issuance of a new command for the same bank is postponed during this interval.
The number of Trwl cycles can be specified by bits TRWL2TRWL0 in MCR. DACK is asserted
two cycles before the data write cycle.
The SH7751 Series supports burst-length 4 burst read and burst write operations of synchronous
DRAM. A wait cycle is therefore generated even with single write operations.
Rev. 3.0, 04/02, page 401 of 1064
Tr
Tc1
Tc2
Tc3
Tc4
Trw1
Tpc
Trw
H/L
c1
Trw1
CKIO
Bank
Precharge-sel
Address
CSn
DQMn
RD/WR
RAS
CASS
D31D0
(write)
BS
CKE
DACKn
(SA: IO
memory)
c1
Row
Row
Row
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.27 Basic Timing for Synchronous DRAM Single Write
Rev. 3.0, 04/02, page 402 of 1064
RAS Down Mode: The synchronous DRAM bank function is used to support high-speed accesses
to the same row address. When the RASD bit in MCR is 1, read/write command accesses are
performed using commands without auto-precharge (READ, WRIT). In this case, precharging is
not performed when the access ends. When accessing the same row address in the same bank, it is
possible to issue the READ or WRIT command immediately, without issuing an ACTV command,
in the same way as in the DRAM RAS down state. As synchronous DRAM is internally divided
into two or four banks, it is possible to activate one row address in each bank. If the next access is
to a different row address, a PRE command is first issued to precharge the relevant bank, then
when precharging is completed, the access is performed by issuing an ACTV command followed
by a READ or WRIT command. If this is followed by an access to a different row address, the
access time will be longer because of the precharging performed after the access request is issued.
In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl +
Tpc cycles after issuance of the WRITA command. When RAS down mode is used, READ or
WRIT commands can be issued successively if the row address is the same. The number of cycles
can thus be reduced by Trwl + Tpc cycles for each write. The number of cycles between issuance
of the PRE command and the ACTV command is determined by bits TPC2TPC0 in MCR.
There is a limit on t
RAS
, the time for placing each bank in the active state. If there is no guarantee
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of t
RAS
. In this way, it is possible to observe the
restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures
must be taken in the program to ensure that the banks do not remain active for longer than the
prescribed time.
A burst read cycle without auto-precharge is shown in figure 13.28, a burst read cycle for the same
row address in figure 13.29, and a burst read cycle for different row addresses in figure 13.30.
Similarly, a burst write cycle without auto-precharge is shown in figure 13.31, a burst write cycle
for the same row address in figure 13.32, and a burst write cycle for different row addresses in
figure 13.33.
When synchronous DRAM is read, there is a 2-cycle latency for the DMQn signal that performs
the byte specification. As a result, when the READ command is issued in figure 13.28, if the Tc
cycle is executed immediately, the DMQn signal specification for Td1 cycle data output cannot be
carried out. Therefore, the CAS latency should not be set to 1.
When RAS down mode is set, if only accesses to the respective banks in area 3 are considered, as
long as accesses to the same row address continue, the operation starts with the cycle in figure
13.28 or 13.31, followed by repetition of the cycle in figure 13.29 or 13.32. An access to a
different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 13.30 or 13.33 is executed instead of
that in figure 13.29 or 13.32. In RAS down mode, too, a PALL command is issued before a refresh
cycle or before bus release due to bus arbitration.
Rev. 3.0, 04/02, page 403 of 1064
c2
c3
c4
Tr
Tc1
Tc2
c1
c6
c7
c8
c5
Tc3
Tc4/Td1
Td2
Td4
Td5
Trw
H/L
c1
H/L
c5
Td3
Td6
Td8
Td7
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(read)
CKE
DACKn
(SA: IO
memory)
Row
Row
Row
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.28 Burst Read Timing
Rev. 3.0, 04/02, page 404 of 1064
c2
c3
c4
Tc1
Tc3 Tc4/Td1
c1
c5
c6
c7
c8
Td2
Td3
Td4
Tc2
H/L
c1
H/L
c5
Td5
Td6
Td7
Td8
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(read)
CKE
DACKn
(SA: IO
memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.29 Burst Read Timing (RAS Down, Same Row Address)
Rev. 3.0, 04/02, page 405 of 1064
Tpr
Tr
Trw
c1
c2
c3
c4
c5
c6
c7
c8
Tc1
Tc2
Tc3
Td2
Tpc
H/L
H/L
c1
c5
Tc4/Td1
Td3
Td4
Td5
Td6
Td7
Td8
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(read)
CKE
DACKn
(SA: IO
memory)
Row
Row
Row
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.30 Burst Read Timing (RAS Down, Different Row Addresses)
Rev. 3.0, 04/02, page 406 of 1064
Tr
Tc1
Tc2
Tc3
Tc4
Tc5
Trw
H/L
H/L
c1
c5
Tc6
Tc7
Tc8
Trw1
Trw1
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(read)
CKE
c1
c2
c3
c4
c5
c6
c7
c8
Row
Row
Row
DACKn
(SA: IO
memory)
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.31 Burst Write Timing
Rev. 3.0, 04/02, page 407 of 1064
(Tnop)
Tc2
Tc3
Tc4
Tc5
Tc6
Tc1
H/L
H/L
c1
c5
Tnop
Tc7
Tc8
Trw1
Trw1
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(write)
CKE
c1
c2
c3
c4
c5
c6
DACKn
(SA: IO
memory)
Note:
c8
c7
Normal write
Single address DMA
The (Tnop) cycle is inserted only for SA-DMA. The DACKn signal is output as indicated by the solid line.
In the case of a normal write, the (Tnop) cycle is deleted and the DACKn signal is output as indicated by the dotted line.
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.32 Burst Write Timing (Same Row Address)
Rev. 3.0, 04/02, page 408 of 1064
Tpr
Tr
Trw
Tc1
Tc2
Tc3
Tpc
H/L
H/L
c1
c5
Tc4
Tc5
Tc6
Tc7
Tc8
Trw1
Trw1
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(write)
CKE
DACKn
(SA: IO
memory)
c1
c2
c3
c4
c5
c6
c7
c8
Row
H/L
Row
Row
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.33 Burst Write Timing (Different Row Addresses)
Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between
an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the
DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally
divided into two or four banks, after a READ or WRIT command is issued for one bank it is
Rev. 3.0, 04/02, page 409 of 1064
possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch
cycle, or during the data write cycle, and so shorten the access cycle.
When a read access is followed by another read access to the same row address, after a READ
command has been issued, another READ command is issued before the end of the data latch
cycle, so that there is read data on the data bus continuously. When an access is made to another
row address and the bank is different, the PRE command or ACTV command can be issued during
the CAS latency cycle or data latch cycle. If there are consecutive access requests for different row
addresses in the same bank, the PRE command cannot be issued until the last-but-one data latch
cycle. If a read access is followed by a write access, it may be possible to issue a PRE or ACTV
command, depending on the bank and row address, but since the write data is output at the same
time as the WRIT command, the PRE, ACTV, and WRIT commands are issued in such a way that
one or two empty cycles occur automatically on the data bus. Similarly, with a read access
following a write access, or a write access following a write access, the PRE, ACTV, READ, or
WRIT command is issued during the data write cycle for the preceding access; however, in the
case of different row addresses in the same bank, a PRE command cannot be issued, and so in this
case the PRE command is issued following the number of Trwl cycles specified by the TRWL bits
in MCR, after the end of the last data write cycle.
Figure 13.34 shows a burst read cycle for a different bank and row address following a preceding
burst read cycle.
Pipelined access is enabled only for consecutive access to area 3, and will be discontinued in the
event of an access to another area. Pipelined access is also discontinued in the event of a refresh
cycle, or bus release due to bus arbitration. The cases in which pipelined access is available are
shown in table 13.16. In this table, "DMAC dual" indicates transfer in DMAC dual address mode,
and "DMAC single", transfer in DMAC single address mode.
Table 13.16 Cycles in Which Pipelined Access Can Be Used
Following Access
CPU
DMAC Dual
DMAC Single
Preceding Access
Read
Write
Read
Write
Read
Write
CPU
Read
X
X
O
X
O
O
Write
X
X
O
X
O
O
DMAC dual
Read
X
X
X
X
X
X
Write
O
O
O
X
O
O
DMAC single
Read
O
O
O
X
O
O
Write
O
O
O
X
O
O
O: Pipelined access possible
X: Pipelined access not possible
Rev. 3.0, 04/02, page 410 of 1064
Tc1_A
Tc1_B
H/L
H/L
H/L
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(read)
CKE
a1
a2
a3
a4
a5
a6
a7
a8
b1
b2
c1_A
c5_A
c1_B
c5_B
H/L
Figure 13.34 Burst Read Cycle for Different Bank and Row Address Following Preceding
Burst Read Cycle
Rev. 3.0, 04/02, page 411 of 1064
Refreshing: The bus state controller is provided with a function for controlling synchronous
DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting
the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh
mode, in which the power consumption for data retention is low, can be activated by setting both
the RMODE bit and the RFSH bit to 1.
Auto-Refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS2
CKS0 in RTCSR, and the value set in RTCOR. The value of bits CKS2CKS0 in RTCOR
should be set so as to satisfy the refresh interval specification for the synchronous DRAM
used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR,
then make the CKS2CKS0 setting last of all. When the clock is selected by CKS2CKS0,
RTCNT starts counting up from the value at that time. The RTCNT value is constantly
compared with the RTCOR value, and if the two values are the same, a refresh request is
generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and
the count-up is restarted. Figure 13.36 shows the auto-refresh cycle timing.
First, an REF command is issued in the TRr cycle. After the TRr cycle, new command output
cannot be performed for the duration of the number of cycles specified by bits TRAS2TRAS0
in MCR plus the number of cycles specified by bits TRC2TRC0 in MCR. The TRAS2
TRAS0 and TRC2TRC0 bits must be set so as to satisfy the synchronous DRAM refresh
cycle time specification (active/active command delay time).
Auto-refreshing is performed in normal operation, in sleep mode, and in the case of a manual
reset. When both areas 2 and 3 are set to the synchronous DRAM, auto-refreshing of area 2 is
performed subsequent to area 3.
RTCNT value
RTCOR-1
H'00000000
RTCSR.CKS20
External bus
Refresh request cleared
by start of refresh cycle
= 000
000
RTCNT cleared to 0 when
RTCNT = RTCOR
Auto-refresh cycle
Time
Refresh
request
Figure 13.35 Auto-Refresh Operation
Rev. 3.0, 04/02, page 412 of 1064
TRr2
TRr3
TRr4
TRr5
Trc
TRr1
Trc
TRrw
Trc
CKIO
RD/
CKE
D63D0
Figure 13.36 Synchronous DRAM Auto-Refresh Timing
Self-Refreshing
Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses
are generated within the synchronous DRAM. Self-refreshing is activated by setting both the
RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal
is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh
mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared,
command issuance is disabled for the number of cycles specified by bits TRC2TRC0 in
MCR. Self-refresh timing is shown in figure 13.37. Settings must be made so that self-refresh
clearing and data retention are performed correctly, and auto-refreshing is performed at the
correct intervals. When self-refreshing is activated from the state in which auto-refreshing is
set, or when exiting standby mode other than through a power-on reset, auto-refreshing is
restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If
the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this
time should be taken into consideration when setting the initial value of RTCNT. Making the
RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state
is entered using the SH7751 Series standby function, and is maintained even after recovery
from standby mode other than through a power-on reset.
In the case of a power-on reset, the bus state controller's registers are initialized, and therefore
the self-refresh state is cleared.
Rev. 3.0, 04/02, page 413 of 1064
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in the
case of a manual reset.
TRs2
TRs3
TRs4
TRs5
Trc
TRs1
Trc
Trc
CKIO
RD/
DQMn
CKE
D63D0
Figure 13.37 Synchronous DRAM Self-Refresh Timing
Relationship between Refresh Requests and Bus Cycle Requests
If a refresh request is generated during execution of a bus cycle, execution of the refresh is
deferred until the bus cycle is completed. Refresh operations are deferred during multiple bus
cycles generated because the data bus width is smaller than the access size (for example, when
performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as
a cache fill or write-back, and also between read and write cycles during execution of a TAS
instruction, and between read and write cycles when DMAC dual address transfer is executed.
If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution
is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a
refresh is waiting to be executed, so that a new refresh request is generated, the previous
refresh request is eliminated. In order for refreshing to be performed normally, care must be
taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh
interval. When a refresh request is generated, the
%$&. pin is negated (driven high).
Therefore, normal refreshing can be performed by having the
%$&. pin monitored by a bus
master other than the SH7751 Series requesting the bus, or the bus arbiter, and returning the
bus to the SH7751 Series.
Rev. 3.0, 04/02, page 414 of 1064
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed
after powering on. To perform synchronous DRAM initialization correctly, the bus state controller
registers must first be set, followed by a write to the synchronous DRAM mode register. In
synchronous DRAM mode register setting, the address signal value at that time is latched by a
combination of the
5$6, &$6, and RD/:5 signals. If the value to be set is X, the bus state
controller provides for value X to be written to the synchronous DRAM mode register by
performing a write to address H'FF900000 + X for area 2 synchronous DRAM, and to address
H'FF940000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the
mode write is performed as a byte-size access. To set burst read/burst write, CAS latency 1 to 3,
wrap type = sequential, and burst length 4, 8*, supported by the SH7751 Series, arbitrary data is
written by byte-size access to the following addresses.
Bus Width
CAS Latency
Area 2
Area 3
32
4
1
H'FF900048
H'FF940048
2
H'FF900088
H'FF940088
3
H'FF9000C8
H'FF9400C8
32
8*
1
H'FF90004C
H'FF94004C
2
H'FF90008C
H'FF94008C
3
H'FF9000CC
H'FF9400CC
Note: * SH7751R only
The value set in MCR.MRSET is used to select whether a precharge all banks command or a
mode register setting command is issued. The timing for the precharge all banks command is
shown in figure 13.38(1), and the timing for the mode register setting command in figure 13.38(2).
Before mode register, a 200 s idle time (depending on the memory manufacturer) must be
guaranteed after the power required for the synchronous DRAM is turned on. If the reset signal
pulse width is greater than this idle time, there is no problem in making the precharge all banks
setting immediately.
First, a precharge all banks (PALL) command is issued in the TRp1 cycle by performing a write to
address H'FF900000 + X or H'FF940000 + X while MCR.MRSET = 0. Next, the number of
dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed.
This is achieved automatically while various kinds of initialization are being performed after auto-
refresh setting, but a way of carrying this out more dependably is to change the RTCOR register
value to set a short refresh request generation interval just while these dummy cycles are being
executed. With simple read or write access, the address counter in the synchronous DRAM used
for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh cycle. After
auto-refreshing has been executed at least the prescribed number of times, a mode register setting
command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and performing a write to
address H'FF900000 + X or H'FF940000 + X.
Rev. 3.0, 04/02, page 415 of 1064
Synchronous DRAM mode register setting should be executed once only after power-on reset and
before synchronous DRAM access, and no subsequent changes should be made.
CKIO
Bank
Precharge-sel
Address
RD/
D31D0
CKE
TRp1
TRp2
TRp3
TRp4
TMw1
TMw2
TMw3
TMw4
(High)
TMw5
Figure 13.38(1) Synchronous DRAM Mode Write Timing (PALL)
Rev. 3.0, 04/02, page 416 of 1064
CKIO
Bank
Precharge-sel
Address
RD/
D31D0
CKE
TRp1
TRp2
TRp3
TRp4
TMw1
TMw2
TMw3
TMw4
(High)
TMw5
Figure 13.38(2) Synchronous DRAM Mode Write Timing (Mode Register Setting)
Changing the Burst Length (SH7751R Only): When synchronous DRAM is connected with the
32-bit memory bus of the SH7751R, a burst length of either 4 or 8 can be selected by the setting of
the SDBL bit of the BCR3 register. For more details, see the description of the BCR3 register.
Burst Read
Figure 13.39 is the timing chart for burst-read operations. For the example shown below, we
assume that two synchronous DRAMs of 512k
16 bits
2 banks are connected and are used
with a 32-bit data width and a burst length of 8. Following the Tr cycle, during which an
ACTV command is output, a READA command is issued during cycle Tc1. During the Td1 to
Td8 cycles, the read data are accepted on the rising edges of the external command clock
(CKIO). Tpc is the cycle used to wait for auto-precharging, which is triggered by the READA
command, to be completed in the synchronous DRAM. During this cycle, no new command
that accesses the same bank can be issued. In this LSI, the number of Tpc cycles is determined
Rev. 3.0, 04/02, page 417 of 1064
by the setting of the TPC2 to TPC0 bits of the MCR, and no command that operates on the
synchronous DRAM is issued during these cycles.
Figure 13.39 shows an example of the basic timing of a burst-read. To allow the connection of
a lower-speed DRAM, the cycle's period can be extended by the settings of the bits in WCR2
and MCR. The number of cycles from cycle Tr on which the ACTV command is output to
cycle Tc1 on which the READA command is output can be specified by the RCD1 and RCD0
bits in MCR: the number of cycles is 2, 3, or 4 for the setting value of 1, 2, or 3, respectively.
When two or more cycles are specified, the Trw cycle, which is for the issuing of NOP
commands to the synchronous DRAM, is inserted between the Tr and Tc cycles. The number
of cycles from cycle Tc1 on which the READA command is output until cycle Td1, in which
the first part of the data to be read is received, can be set by the bits A2W2 to A2W0 and
A3W2 to A3W0 of WCR2. These independently select a number of cycles between 1 and 5 for
areas 2 and 3. Note that this number of cycles is equal to the number of CAS latency cycles of
the synchronous DRAM.
Tr
Trw
Tc1
Tc2
Tc3
Tc4/Td1
Td3
Td2
Td4
CKIO
Bank
Precharge-sel
Address
RD/
D31D0
(read)
DQMn
CKE
Td5
Td6
Td8
Td7
Tpc
H/L
c1
c1
c2
c3
c4
c7
c8
c5
c6
DACKn
(SA: IO
memory)
Row
Row
Row
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)
Rev. 3.0, 04/02, page 418 of 1064
In a cycle of access to synchronous DRAM, the
%6 signal is asserted for one clock cycle at the
beginning of a bus cycle. Data are accessed in the following sequence: in the fill operation for
a cache miss, the data between the 32-bit boundaries that include the missed data are first read;
after that, the data between 32-byte boundaries that include the missed data are read in a
wraparound way.
Burst Write
Figure 13.40 is the timing chart for a burst-write operation with a burst length of 8. In this LSI,
a burst write takes place when a copy-back of the cache or a 32-byte transfer of data by the
DMAC takes place. In a burst-write operation, a WRITA command that include auto
precharging, is issued during the Tc1 cycle that follows the Tr cycle in which the ACTV
command is output. During the write cycle, the data to be written is output along with the write
command. With a write command that includes an auto precharge, precharging is of the
relevant bank of the synchronous DRAM and takes place on completion of the write
command, so no new command that accesses the same bank can be issued until precharging
has been completed. For this reason, the Trwl cycles are added as a period of waiting for
precharging to start after the write command has been issued. This is additional to the
precharge-waiting cycle as used in read access. The Trwl cycles delay the issuing of new
commands to the same bank. The setting of the TRWL2 to TRWL0 bits of MCR selects the
number of Trwl cycles. The data between 32-byte boundaries are written in a wraparound way.
Tr
Tc1
Tc2
Tc3
Tc4
Tc5
Tc7
Trw
c1
Tc6
DACKn
(SA: IO
memory)
c1
c2
c3
c4
c5
c6
c7
c8
Row
Row
Tc8
Trw1
Tpc
Trw1
H/L
Row
CKIO
Bank
Precharge-sel
Address
DQMn
RD/
D31D0
(write)
CKE
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM
Rev. 3.0, 04/02, page 419 of 1064
13.3.6
Burst ROM Interface
Setting bits A0BST2A0BST0, A5BST2A5BST0, and A6BST2A6BST0 in BCR1 to a non-
zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface
provides high-speed access to ROM that has a burst access function. The timing for burst access to
burst ROM is shown in figure 13.41. Two wait cycles are set. Basically, access is performed in the
same way as for SRAM interface, but when the first cycle ends, only the address is changed before
the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses
can be set as 4, 8, 16, or 32 with bits A0BST2A0BST0, A5BST2A5BST0, or A6BST2
A6BST0. When 16-bit ROM is connected, 4, 8, or 16 can be set in the same way. When 32-bit
ROM is connected, 4 or 8 can be set.
5'< pin sampling is always performed when one or more wait states are set.
The second and subsequent access cycles also comprise two cycles when a burst ROM setting is
made and the wait specification is 0. The timing in this case is shown in figure 13.42.
In a burst ROM interface write operation is performed as SRAM interface.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed on the data at the 32-byte boundary. The bus is not released during this
period.
Figure 13.43 shows the timing when a burst ROM setting is made, and setup/hold is specified in
WCR3.
Rev. 3.0, 04/02, page 420 of 1064
T1
TB1
TB2
TB1
TB2
TB1
TB2
T2
CKIO
A25A5
A4A0
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.41 Burst ROM Basic Access Timing
Rev. 3.0, 04/02, page 421 of 1064
T1
Twe
TB2
TB1
Tw
TB2
Tw
Tw
TB1
TB2
Tw
T2
TB1
CKIO
A25A5
A4A0
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.42 Burst ROM Wait Access Timing
CKIO
A25A5
A4A0
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
TS1
TB2
TH1
TS1
TB1
TB2
TS1
T1
TH1
TB1
TH1
TS1
TB1
T2
TH1
TB2
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.43 Burst ROM Wait Access Timing
Rev. 3.0, 04/02, page 422 of 1064
13.3.7
PCMCIA Interface
In the SH7751 Series, setting the A56PCM bit in BCR1 to 1 makes the bus interface for external
memory space areas 5 and 6 an IC memory card interface or I/O card interface as stipulated in
JEIDA specification version 4.2 (PCMCIA2.1).
Figure 13.44 shows an example of PCMCIA card connection to the SH7751 Series. To enable
active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being
supplied), a 3-state buffer must be connected between the SH7751 Series bus interface and the
PCMCIA cards.
As operation in big endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard, this
LSI supports only little-endian mode setting and the little-endian mode PCMCIA interface.
When the MMU is on, PCMCIA interface can be set in MMU page units, and there is a choice of
8-bit common memory, 16-bit common memory, 8-bit attribute memory, 16-bit attribute memory,
8-bit I/O space, 16-bit I/O space, or dynamic bus sizing. See section 3, Memory Management Unit
(MMU), for details of the setting method. When the MMU is off, the setting of bits SA2 to SA0 of
PTEA is always used for access.
SA2
SA1
SA0
Description
0
0
0
Reserved (Setting prohibited)
1
Dynamic I/O bus sizing
1
0
8-bit I/O space
1
16-bit I/O space
1
0
0
8-bit common memory
1
16-bit common memory
1
0
8-bit attribute memory
1
16-bit attribute memory
When the MMU is on, wait cycles in a bus access can be set in MMU page units. See section 3,
Memory Management Unit (MMU), for details of the setting method. When the MMU is off,
access is always performed according to the setting of the TC bit in PTEA. When TC is cleared to
0, bits A5W2A5W0 in wait control register 2 (WCR2) and bits A5PCW1A5PCW0, A5TED2
A5TED0, and A5TEH2A5TEH0 in the PCMCIA control register (PCR) are selected. When TC
is set to 1, bits A6W2A6W0 in WCR2 and bits A6PCW1A6PCW0, A6TED2A6TED0, and
A6TEH2A6TEH0 in PCR are selected.
Access to a PCMCIA interface area by the DMAC is always performed using the DMAC's
CHCRn.SSAn, CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values.
AnPCW1AnPCW0 specify the number of wait states to be inserted in a low-speed bus cycle; a
value of 0, 15, 30, or 50 can be set, and this value is added to the number of wait states for
Rev. 3.0, 04/02, page 423 of 1064
insertion specified by WCR2. AnTED2AnTED0 can be set to a value from 0 to 15, enabling the
address,
&6, &($, &(%, and 5(* setup times with respect to the 5' and :( signals to be
secured. AnTEH2AnTEH0 can also be set to a value from 0 to 15, enabling the address,
&6,
&($, &(%, and 5(* data hold times with respect to the 5' and :( signals to be secured.
Wait cycles between cycles are set with bits A5IW2A5IW0 and A6IW2A6IW0 in wait control
register 1 (WCR1). The inter-cycle write cycles selected depend only on the area accessed (area 5
or 6): when area 5 is accessed, bits A5IW2A5IW0 are selected, and when area 6 is accessed, bits
A6IW2A6IW0 are selected.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not
released during this operation.
Rev. 3.0, 04/02, page 424 of 1064
Table 13.17 Relationship between Address and CE When Using PCMCIA Interface
Bus
Width
(Bits)
Read/
Write
Access
Size
(Bits)*
1
Odd/
Even
IOIS16
Access CE2
CE1
A0
D15D8
D7D0
8
Read
8
Even
Don't
care
--
1
0
0
Invalid
Read data
Odd
Don't
care
--
1
0
1
Invalid
Read data
16
Even
Don't
care
First
1
0
0
Invalid
Lower read data
Even
Don't
care
Second
1
0
1
Invalid
Upper read data
Odd
Don't
care
--
--
--
--
--
--
Write
8
Even
Don't
care
--
1
0
0
Invalid
Write data
Odd
Don't
care
--
1
0
1
Invalid
Write data
16
Even
Don't
care
First
1
0
0
Invalid
Lower write data
Even
Don't
care
Second
1
0
1
Invalid
Upper write data
Odd
Don't
care
--
--
--
--
--
--
16
Read
8
Even
Don't
care
--
1
0
0
Invalid
Read data
Odd
Don't
care
--
0
1
1
Read data
Invalid
16
Even
Don't
care
--
0
0
0
Upper read data Lower read data
Odd
Don't
care
--
--
--
--
--
--
Write
8
Even
Don't
care
--
1
0
0
Invalid
Write data
Odd
Don't
care
--
0
1
1
Write data
Invalid
16
Even
Don't
care
--
0
0
0
Upper write data Lower write data
Odd
Don't
care
--
--
--
--
--
--
Rev. 3.0, 04/02, page 425 of 1064
Table 13.17 Relationship between Address and CE When Using PCMCIA Interface (cont)
Bus
Width
(Bits)
Read/
Write
Access
Size
(Bits)*
1
Odd/
Even
IOIS16
Access CE2
CE1
A0
D15D8
D7D0
Read
8
Even
0
--
1
0
0
Invalid
Read data
Odd
0
--
0
1
1
Read data
Invalid
Dynamic
bus
sizing*
2
16
Even
0
--
0
0
0
Upper read data Lower read data
Odd
0
--
--
--
--
--
--
Write
8
Even
0
--
1
0
0
Invalid
Write data
Odd
0
--
0
1
1
Write data
Invalid
16
Even
0
--
0
0
0
Upper write data Lower write data
Odd
0
--
--
--
--
--
--
Read
8
Even
1
--
1
0
0
Invalid
Read data
Odd
1
First
0
1
1
Ignored
Invalid
Odd
1
Second
1
0
1
Invalid
Read data
16
Even
1
First
0
0
0
Invalid
Lower read data
Even
1
Second
1
0
1
Invalid
Upper read data
Odd
1
--
--
--
--
--
--
Write
8
Even
1
--
1
0
0
Invalid
Write data
Odd
1
First
0
1
1
Invalid
Write data
Odd
1
Second
1
0
1
Invalid
Write data
16
Even
1
First
0
0
0
Upper write data Lower write data
Even
1
Second
1
0
1
Invalid
Upper write data
Odd
1
--
--
--
--
--
--
Notes: *1 In 32-bit/64-bit/32-byte transfer, the above accesses are repeated, with address
incrementing performed automatically according to the bus width, until the transfer data
size is reached.
*2 PCMCIA I/O card interface only
Rev. 3.0, 04/02, page 426 of 1064
A25A0
D15D0
CD1, CD2
/
(
)
(
)
(
)
A25A0
D15D0
CD1, CD2
/
A25A0
SH7751 Series
D15D0
RD/
/(
)
/(
)
DIR
D7D0
D15D8
DIR
DIR
DIR
D7D0
D15D8
PC card
(memory I/O)
PC card
(memory I/O)
Card
detection
circuit
Card
detection
circuit
Figure 13.44 Example of PCMCIA Interface
Rev. 3.0, 04/02, page 427 of 1064
Memory Card Interface Basic Timing: Figure 13.45 shows the basic timing for the PCMCIA
memory card interface, and figure 13.46 shows the wait timing for the PCMCIA memory card
interface.
CKIO
Tpcm1
Tpcm2
A25A0
RD/
D15D0
(read)
D15D0
(write)
(read)
(write)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.45 Basic Timing for PCMCIA Memory Card Interface
Rev. 3.0, 04/02, page 428 of 1064
CKIO
Tpcm0
A25A0
RD/
REG
(read)
D15D0
(read)
D15D0
(write)
(write)
DACKn
(DA)
Tpcm0w
Tpcm1
Tpcm1w Tpcm1w
Tpcm2
Tpcm2w
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.46 Wait Timing for PCMCIA Memory Card Interface
Rev. 3.0, 04/02, page 429 of 1064
Common
memory 1
Common memory
(64 MB)
Attribute memory
(64 MB)
I/O space
(64 MB)
Attribute memory
I/O space 1
I/O space 2
Virtual
address space
Card 1
on CS5
Card 2
on CS6
Access
by CS5 wait
controller
Virtual
address space
External I/O
addresses
IO 1
IO 1
Different virtual pages
mapped to the same
physical page
Example of I/O spaces with different cycle times
(less than 1 kB)
The page size can be 1 kB, 4 kB, 64 kB, or 1 MB.
Example of PCMCIA interface mapping
IO 2
IO 2
1 kB
page
1 kB
page
Common
memory 2
Access
by CS6 wait
controller
.
.
.
.
.
.
Figure 13.47 PCMCIA Space Allocation
I/O Card Interface Timing: Figures 13.48 and 13.49 show the timing for the PCMCIA I/O card
interface.
When an I/O card interface access is made to a PCMCIA card, dynamic sizing of the I/O bus
width is possible using the
,2,6 pin. When a 16-bit bus width is set, if the ,2,6 signal is high
during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits in width. In this case, a
data access for only 8 bits is performed in the I/O bus cycle being executed, followed
automatically by a data access for the remaining 8 bits. Dynamic bus sizing is also performed in
the case of byte-size access to address 2n + 1.
Figure 13.50 shows the basic timing for dynamic bus sizing.
Rev. 3.0, 04/02, page 430 of 1064
CKIO
Tpci1
Tpci2
A25A0
RD/
(read)
D15D0
(read)
(write)
D15D0
(write)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.48 Basic Timing for PCMCIA I/O Card Interface
Rev. 3.0, 04/02, page 431 of 1064
CKIO
A25A0
RD/
(read)
(write)
DACKn
(DA)
D15D0
(read)
D15D0
(write)
Tpci0
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci2
Tpci2w
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.49 Wait Timing for PCMCIA I/O Card Interface
Rev. 3.0, 04/02, page 432 of 1064
Tpci
Tpci0
Tpci1w
Tpci2
Tpci2w
Tpci0
Tpci
Tpci2
Tpci1w
Tpci2w
CKIO
A25A1
A0
RD/
(
)
(read)
(
)
(write)
D15D0
(write)
D15D0
(read)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.50 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
Rev. 3.0, 04/02, page 433 of 1064
13.3.8
MPX Interface
If the MD6 pin is cleared to 0 in a power-on reset by means of the
5(6(7 pin, the MPX interface
is selected for area 0. The MPX interface is selected for areas 1 to 6 by means of the MPX bit in
BCR1 and MEMMODE, A4MPX, and A1MPX in BCR3. The MPX interface offers a multiplexed
address/data type bus protocol, and permits easy connection to an external memory controller chip
that uses a single 32-bit multiplexed address/data bus. A bus cycle consists of an address phase
and a data phase, with address information output to D25D0 and the access size output to D31
D29 in the address phase. The
%6 signal is asserted for one cycle to indicate the address phase.
The
&6Q signal is asserted at the rise of Tm1 and negated after the end of the last data transfer in
the data phase. Therefore, a negation period does not occur in the case of minimum pitch access.
The
)5$0( signal is asserted at the rise of Tm1 and negated when the last data transfer cycle
starts in the data phase. Therefore, an external device for the MPX interface must hold the address
information and access size output in the address phase within itself, and peripheral function data
input/output for the data phase. For details of access sizes and data alignment, see section 13.3.1,
Endian/Access Size and Data Alignment.
Values output to address pins A25A20 are not guaranteed.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed on 32-byte boundary data. If the access size exceeds the set bus width in
this case, burst access is performed with a number of data cycles following one address output.
The bus is not released during this period.
D31
D30
D29
Access Size
0
0
0
Byte
1
Word
1
0
Longword
1
Quadword
1
X
X
32-byte burst
X: Don't care
Rev. 3.0, 04/02, page 434 of 1064
CKIO
RD/
D31D0
SH7751 Series
MPX device
CLK
I/O31I/O0
Figure 13.51 Example of 32-Bit Data Width MPX Connection
The MPX interface timing is shown below.
When the MPX interface is used for areas 1 to 6, a bus size of 32 bit should be specified in BCR2.
For wait control, waits specified by WCR2 and wait insertion by means of the
5'< pin can be
used.
In a read, one wait cycle is automatically inserted after address output, even if WCR2 is cleared to
0.
Rev. 3.0, 04/02, page 435 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1
DACKn
(DA)
D0
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.52 MPX Interface Timing 1 (Single Read Cycle, AnW = 0, No External Wait)
Rev. 3.0, 04/02, page 436 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1w
Tmd1
DACKn
(DA)
D0
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.53 MPX Interface Timing 2 (Single Read, AnW = 0, One External Wait Inserted)
Rev. 3.0, 04/02, page 437 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1
DACKn
(DA)
D0
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait)
Rev. 3.0, 04/02, page 438 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1w
Tmd1
DACKn
(DA)
D0
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait
Inserted)
Rev. 3.0, 04/02, page 439 of 1064
Tm1
CKIO
/
RD/
D31D0
Tmd1w
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
DACKn
(DA)
D2
D3
D4
D6
D7
D8
D5
A
D1
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.56 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait)
Rev. 3.0, 04/02, page 440 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd7
Tmd8w
Tmd8
DACKn (DA)
D7
D8
D2
D3
D1
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.57 MPX Interface Timing 6 (Burst Read Cycle, AnW = 0, External Wait Control)
Rev. 3.0, 04/02, page 441 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
DACKn
(DA)
D1
D2
D3
D4
D5
D6
D7
D8
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.58 MPX Interface Timing 7 (Burst Write Cycle, AnW = 0, No External Wait)
Rev. 3.0, 04/02, page 442 of 1064
D3
D2
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd7
Tmd8w
Tmd8
DACKn (DA)
D1
D7
D8
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.59 MPX Interface Timing 8 (Burst Write Cycle, AnW = 1, External Wait
Control)
Rev. 3.0, 04/02, page 443 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1
Tmd2
DACKn
(DA)
D0
D1
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.60 MPX Interface Timing 1
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)
Rev. 3.0, 04/02, page 444 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1w
Tmd1
Tmd2
DACKn
(DA)
D0
D1
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.61 MPX Interface Timing 2
(Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)
Rev. 3.0, 04/02, page 445 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1
Tmd2
DACKn
(DA)
D0
D1
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.62 MPX Interface Timing 3
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)
Rev. 3.0, 04/02, page 446 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1w
Tmd1
Tmd2
DACKn
(DA)
D0
D1
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.63 MPX Interface Timing 4
(Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)
Rev. 3.0, 04/02, page 447 of 1064
Tm1
CKIO
/
RD/
D31D0
Tmd1w
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
DACKn
(DA)
D2
D3
D4
D6
D7
D8
D5
A
D1
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.64 MPX Interface Timing 5 (Burst Read Cycle, AnW = 0, No External Wait,
Bus Width: 32 Bits, Transfer Data Size: 32 Bytes)
Rev. 3.0, 04/02, page 448 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd7
Tmd8w
Tmd8
DACKn (DA)
D7
D8
D2
D3
D1
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.65 MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes)
Rev. 3.0, 04/02, page 449 of 1064
Tm1
CKIO
A
/
RD/
D31D0
Tmd1
Tmd2
Tmd3
Tmd4
Tmd5
Tmd6
Tmd7
Tmd8
DACKn
(DA)
D1
D2
D3
D4
D5
D6
D7
D8
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.66 MPX Interface Timing 7
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes)
Rev. 3.0, 04/02, page 450 of 1064
D3
D2
Tm1
CKIO
A
/
RD/
D31D0
Tmd1w
Tmd1
Tmd2w
Tmd2
Tmd3
Tmd7
Tmd8w
Tmd8
DACKn (DA)
D1
D7
D8
Note:
F
or D
A
CKn, an e
xample is sho
wn where CHCRn.AL (access le
v
el) = 0 f
or the DMA
C
.
Figure 13.67 MPX Interface Timing 8
(Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes)
Rev. 3.0, 04/02, page 451 of 1064
13.3.9
Byte Control SRAM Interface
The byte control SRAM interface is a memory interface that outputs a byte select strobe (
:(Q) in
both read and write bus cycles. It has 16 bit data pins, and can be connected to SRAM which has
an upper byte select strobe and lower byte select strobe function such as UB and LB.
Areas 1 and 4 can be designated as byte control SRAM interface. However, when these areas are
set to MPX mode, MPX mode has priority.
The byte control SRAM interface write timing is the same as for the normal SRAM interface.
In read operations, the
:(Q pin timing is different. In a read access, only the :( signal for the
byte being read is asserted. Assertion is synchronized with the fall of the CKIO clock, as for the
:( signal, while negation is synchronized with the rise of the CKIO clock, using the same timing
as the
5' signal.
32-byte transfer is performed consecutively for a total of 32 bytes according to the set bus width.
The first access is performed on the data for which there was an access request. The remaining
accesses are performed in wrap-around fashion on the data at the 32-byte boundary. The bus is not
released during this period.
Figure 13.68 shows an example of byte control SRAM connection to the SH7751 Series, and
figures 13.69 to 13.71 show examples of byte control SRAM read cycles.
A18A3
CSn
RD
RD/WR
SH7751 Series
64k
16-bit
SRAM
D15D0
WE1
WE0
A15A0
CS
OE
WE
I/O15I/O0
UB
LB
A15A0
CS
OE
WE
I/O15I/O0
UB
LB
D31D16
WE3
WE2
Figure 13.68 Example of 52-Bit Data Width Byte Control SRAM
Rev. 3.0, 04/02, page 452 of 1064
T1
T2
CKIO
A25A0
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.69 Byte Control SRAM Basic Read Cycle (No Wait)
Rev. 3.0, 04/02, page 453 of 1064
T1
Tw
T2
CKIO
A25A0
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.70 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)
Rev. 3.0, 04/02, page 454 of 1064
T1
Tw
Twe
T2
CKIO
A25A0
RD/
D31D0
(read)
DACKn
(SA: IO
memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.71 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External
Wait)
Rev. 3.0, 04/02, page 455 of 1064
13.3.10
Waits between Access Cycles
A problem associated with higher external memory bus operating frequencies is that data buffer
turn-off on completion of a read from a low-speed device may be too slow, causing a collision
with the data in the next access, and so resulting in lower reliability or incorrect operation. To
avoid this problem, a data collision prevention feature has been provided. This memorizes the
preceding access area and the kind of read/write, and if there is a possibility of a bus collision
when the next access is started, inserts a wait cycle before the access cycle to prevent a data
collision. Wait cycle insertion consists of inserting idle cycles between access cycles, as shown in
section 13.2.5, Wait Control Register 1 (WCR1). When the SH7751 Series performs consecutive
write cycles, the data transfer direction is fixed (from the SH7751 Series to other memory) and
there is no problem. With read accesses to the same area, also, in principle data is output from the
same data buffer, and wait cycle insertion is not performed. If there is originally space between
accesses, according to the setting of bits AnIW2AnIW0 (n = 0 to 6) in WCR1, the number of idle
cycles inserted is the specified number of idle cycles minus the number of empty cycles.
When bus arbitration is performed, the bus is released after waits are inserted between cycles.
In single address mode DMA transfer, when data transfer is performed from an I/O device to
memory the data on the bus is determined by the speed of the I/O device. With a low-speed I/O
device, an inter-cycle idle wait equivalent to the output buffer turn-off time must be inserted. Even
with high-speed memory, when DMA transfer is considered, it may be necessary to insert an inter-
cycle wait to adjust to the speed of a low-speed device, preventing the memory from being used at
full speed.
Bits DMAIW2DMAIW0 in wait control register 1 (WCR1) allow an inter-cycle wait setting to
be made when transferring data from an I/O device to memory using single address mode DMA
transfer. From 0 to 15 waits can be inserted. The number of waits specified by DMAIW2
DMAIW0 are inserted in single address DMA transfers to all areas.
In dual address mode DMA transfer, the normal inter-cycle wait specified by AnIW2AnIW0 (n =
0 to 6) is inserted.
Rev. 3.0, 04/02, page 456 of 1064
T1
A25A0
RD/
D31D0
T2
Twait
T1
T2
Twait
T1
T2
Area m space read
Area m inter-access wait specification
Area n inter-access wait specification
Area n space read
Area n space write
Figure 13.72 Waits between Access Cycles
Rev. 3.0, 04/02, page 457 of 1064
13.3.11
Bus Arbitration
The SH7751 Series is provided with a bus arbitration function that grants the bus to an external
device when it makes a bus request.
There are three bus arbitration modes: master mode, partial-sharing master mode, and slave mode.
In master mode the bus is held on a constant basis, and is released to another device in response to
a bus request. In slave mode the bus is not held on a constant basis; a bus request is issued each
time an external bus cycle occurs, and the bus is released again at the end of the access. In partial-
sharing master mode, only area 2 is shared with external devices; slave mode is in effect for area
2, while for other spaces, bus arbitration is not performed and the bus is held constantly. The area
in the master mode chip to which area 2 in the partial-sharing master mode chip is allocated is
determined by an external circuit.
Master mode and slave mode can be specified by the external mode pins. Partial-sharing master
mode is entered from master mode by means of a software setting. See Appendix C, Mode Pin
Settings, for the external mode pin settings. In master mode and slave mode, the bus goes to the
high-impedance state when not being held. In partial-sharing master mode, the bus is constantly
driven, and therefore an external buffer is necessary for connection to the master bus. In master
mode, it is possible to connect an external device that issues bus requests. Instead of a slave mode
chip. In the following description, an external device that issues bus requests is also referred to as
a slave.
The SH7751 Series has three internal bus masters: the CPU, DMAC, and PCIC. When
synchronous DRAM or DRAM is connected and refresh control is performed, refresh requests
constitute a fourth bus master. In addition to these are bus requests from external devices in master
mode. If requests occur simultaneously, priority is given, in high-to-low order, to a bus request
from an external device, a refresh request, the DMAC, and the CPU. See section 13.3.15, Notes on
Usage.
To prevent incorrect operation of connected devices when the bus is transferred between master
and slave, all bus control signals are negated before the bus is released. When mastership of the
bus is received, also, bus control signals begin driving the bus from the negated state. Since
signals are driven to the same value by the master and slave exchanging the bus, output buffer
collisions can be avoided. By turning off the output buffer on the side releasing the bus, and
turning on the output buffer on the side receiving the bus, simultaneously with respect to the bus
control signals, it is possible to eliminate the signal high-impedance period. It is not necessary to
provide the pull-up resistors usually inserted in these control signal lines to prevent incorrect
operation due to external noise in the high-impedance state.
Bus transfer is executed between bus cycles.
When the bus release request signal (
%5(4) is asserted, the SH7751 Series releases the bus as
soon as the currently executing bus cycle ends, and outputs the bus use permission signal (
%$&.).
Rev. 3.0, 04/02, page 458 of 1064
However, bus release is not performed during multiple bus cycles generated because the data bus
width is smaller than the access size (for example, when performing longword access to 8-bit bus
width memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus
release is not performed between read and write cycles during execution of a TAS instruction, or
between read and write cycles when DMAC dual address transfer is executed. When
%5(4 is
negated,
%$&. is negated and use of the bus is resumed. See appendix D, Pin Functions, for the
pin states when the bus is released.
When a refresh request is generated, the SH7751 Series performs a refresh operation as soon as
the currently executing bus cycle ends. However, refresh operations are deferred during multiple
bus cycles generated because the data bus width is smaller than the access size (for example, when
performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a
cache fill or write-back, and also between read and write cycles during execution of a TAS
instruction, and between read and write cycles when DMAC dual address transfer is executed.
Refresh operations are also deferred in the bus-released state.
If the synchronous DRAM interface is set to the RAS down mode the PALL command is issued
before a refresh cycle occurs or before the bus is released by bus arbitration.
As the CPU in the SH7751 Series is connected to cache memory by a dedicated internal bus,
reading from cache memory can still be carried out when the bus is being used by another bus
master inside or outside the SH7751 Series. When writing from the CPU, an external write cycle
is generated when write-through has been set for the cache in the SH7751 Series, or when an
access is made to a cache-off area. There is consequently a delay until the bus is returned.
When the SH7751 Series wants to take back the bus in response to an internal memory refresh
request, it negates
%$&.. On receiving the %$&. negation, the device that asserted the external
bus release request negates
%5(4 to release the bus. The bus is thereby returned to the SH7751
Series, which then carries out the necessary processing.
Rev. 3.0, 04/02, page 459 of 1064
Asserted for at least 2 cycles
*
Master mode device access
CKIO
A25A0
RD/
/
/
A25A0
RD/
D31D0
(read)
HiZ
HiZ
HiZ
HiZ
HiZ
HiZ
Negated within 2 cycles
Asserted for at least 2 cycles
Slave mode device access
Negated within 2 cycles
HiZ
HiZ
HiZ
HiZ
HiZ
Master access
Master access
Slave access
Note:
*
For the SH7751, refer to the Usage Note in section 13.3.15.
Figure 13.73 Arbitration Sequence
Rev. 3.0, 04/02, page 460 of 1064
13.3.12
Master Mode
The master mode processor holds the bus itself unless it receives a bus request.
On receiving an assertion (low level) of the bus request signal (
%5(4) from off-chip, the master
mode processor releases the bus and asserts (drives low) the bus use permission signal (
%$&.) as
soon as the currently executing bus cycle ends. If a bus release request due to a refresh request has
not been issued, on receiving the
%5(4 negation (high level) indicating that the slave has released
the bus, the processor negates (drives high) the
%$&. signal and resumes use of the bus.
If a bus request is issued due to a memory refresh request in the bus-released state, the processor
negates the bus use permission signal (
%$&.), and on receiving the %5(4 negation indicating
that the slave has released the bus, resumes use of the bus.
When the bus is released, all bus interface related output signals and input/output signals go to the
high-impedance state, except for the synchronous DRAM interface CKE signal and bus arbitration
%$&. signal, and DACK0 and DACK1 which control DMA transfers.
With DRAM, the bus is released after precharging is completed. With synchronous DRAM, also,
a precharge command is issued for the active bank and the bus is released after precharging is
completed.
The actual bus release sequence is as follows.
First, the bus use permission signal is asserted in synchronization with the rising edge of the clock.
The address bus and data bus go to the high-impedance state in synchronization after this
%$&.
assertion. At the same time, the bus control signals (
%6, &6Q, 5$6, :(Q, 5', RD/:5, &($,
and
&(%) go to the high-impedance state. These bus control signals are negated no later than one
cycle before going to high-impedance. Bus request signal sampling is performed on the rising
edge of the clock.
The sequence for re-acquiring the bus from the slave is as follows.
As soon as
%5(4 negation is detected on the rising edge of the clock, %$&. is negated and from
next rising edge of the clock, bus control signal driving is started. Driving of the address bus and
data bus starts at the next rising edge of an in-phase clock. The bus control signals are asserted and
the bus cycle is actually started, at the earliest, at the clock rising edge at which the address and
data signals are driven.
In order to reacquire the bus and start execution of a refresh operation or bus access, the
%5(4
signal must be negated for at least two cycles.
If a refresh request is generated when
%$&. has been asserted and the bus has been released, the
%$&. signal is negated even while the %5(4 signal is asserted to request the slave to relinquish
the bus. When the SH7751 Series is used in master mode, consecutive bus accesses may be
Rev. 3.0, 04/02, page 461 of 1064
attempted to reduce the overhead due to arbitration in the case of a slave designed independently
by the user. When connecting a slave for which the total duration of consecutive accesses exceeds
the refresh cycle, the design should provide for the bus to be released as soon as possible after
negation of the
%$&. signal is detected.
13.3.13
Slave Mode
In slave mode, the bus is normally in the released state, and an external device cannot be accessed
unless the bus is acquired through execution of the bus arbitration sequence. In a reset, also, the
bus-released state is established and the bus arbitration sequence is started from the reset vector
fetch.
To acquire the bus, the slave device asserts (drives low) the
%65(4 signal in synchronization
with the rising edge of the clock. The bus use permission
%6$&. signal is sampled for assertion
(low level) in synchronization with the rising edge of the clock. When
%6$&. assertion is
detected, the bus control signals are driven at the negated level after two cycles. The bus cycle is
started at the next rising edge of the clock. The last signal negated at the end of the access cycle is
synchronized with the rising edge of the clock. When the bus cycle ends, the
%65(4 signal is
negated and the release of the bus is reported to the master. On the next rising edge of the clock,
the control signals are set to high-impedance.
In order for the slave mode processor to begin access, the
%6$&. signal must be asserted for at
least two cycles.
For a slave access cycle in DRAM or synchronous DRAM, the bus is released on completion of
precharging, as in the case of the master.
Refresh control is left to the master mode device, and any refresh control settings made in slave
mode are ignored.
Do not use DRAM/synchronous DRAM RAS down mode in slave mode.
Synchronous DRAM mode register settings should be made by the master mode device. Do not
use the DMAC's DDT mode in slave mode.
13.3.14
Cooperation between Master and Slave
To enable system resources to be controlled in a harmonious fashion by master and slave, their
respective roles must be clearly defined. Before DRAM or synchronous DRAM is used,
initialization operations must be carried out. Responsibility must also be assigned when a standby
operation is performed to implement the power-down state.
The design of the SH7751 Series provides for all control, including initialization, refreshing, and
standby control, to be carried out by the master mode device.
Rev. 3.0, 04/02, page 462 of 1064
If the SH7751 Series is specified as the master in a power-on reset, it will not accept bus requests
from the slave until the
%5(4 enable bit (BCR1.BREQEN) is set to 1.
To ensure that the slave processor does not access memory requiring initialization before use, such
as DRAM and synchronous DRAM, until initialization is completed, write 1 to the
%5(4 enable
bit after initialization ends.
Before setting self-refresh mode in standby mode, etc., write 0 to the
%5(4 enable bit to
invalidate the
%5(4 signal from the slave. Write 1 to the %5(4 enable bit only after the master
has performed the necessary processing (refresh settings, etc.) for exiting self-refresh mode.
13.3.15
Notes on Usage
Refresh: Auto refresh operations stop when a transition is made to standby mode or deep-sleep
mode. If the memory system requires refresh operations, set the memory in the self-refresh state
prior to making the transition to standby mode or deep-sleep mode.
Bus Arbitration: On transition to standby mode or deep-sleep mode, the processor in master
mode does not release bus privileges. In systems performing bus arbitration, make the transition to
standby mode or deep-sleep mode only after setting the bus privilege release enable bit
(BCR1.BREQEN) to 0 for the processor in master mode. If the bus privilege release enable bit
remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or
deep-sleep mode.
Simultaneous Use of Refresh and Bus Arbitration: With the SH7751, when performing bus
arbitration using the external device and
%5(4 signal, the following two failures may occur.
When a
%5(4 signal is input from the external device while using DMA transfer or target
transfer by the PCIC, and DRAM/synchronous DRAM is set to CAS-before-RAS refresh and
auto-refresh in master mode (MD7 = 1), bus arbitration may not be performed correctly and
this LSI may hang up.
When a
%5(4 signal is input from the external device while DRAM/synchronous DRAM is
set to CAS-before-RAS refresh and auto-refresh in master mode (MD7 = 1), assertion of the
%$&. signal (low-level) in response to the %5(4 signal may be for only one cycle at CKIO.
Both above phenomena can be avoided by not using the
%5(4 signal. If the %5(4 signal is to be
used, disable refresh operations during normal operation. If refresh operations are required, carry
them out at one time with the BREQEN bit in BCR1 cleared to 0.
Rev. 3.0, 04/02, page 463 of 1064
Section 14 Direct Memory Access Controller (DMAC)
14.1
Overview
The SH7751 Series includes an on-chip four-channel direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed data transfers among external
devices equipped with DACK (DMA transfer end notification), external memories, memory-
mapped external devices, and on-chip peripheral modules (TMU, RTC, SCI, SCIF, CPG, and
INTC). Using the DMAC reduces the burden on the CPU and increases the operating efficiency of
the chip. When using the SH7751R, see section 14.6, Configuration of the DMAC (SH7751R),
section 14.7, Register Descriptions (SH7751R), and section 14.8, Operation (SH7751R).
14.1.1
Features
The DMAC has the following features.
Four channels (SH7751), eight channels (SH7751R)
Physical address space
Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
Maximum of 16 M (16,777,216) transfers
Choice of single or dual address mode
Single address mode: Either the transfer source or the transfer destination (external device)
is accessed by a DACK signal while the other is accessed by address. One data transfer is
completed in one bus cycle.
Dual address mode: Both the transfer source and transfer destination are accessed by
address. Values set in DMAC internal registers indicate the accessed address for both the
transfer source and the transfer destination. Two bus cycles are required for one data
transfer.
Choice of bus mode: cycle steal mode or burst mode
Two types of DMAC channel priority ranking:
Fixed priority mode: Channel priorities are permanently fixed.
Round robin mode: Sets the lowest priority for the channel that last received an execution
request.
An interrupt request can be sent to the CPU on completion of the specified number of
transfers.
Rev. 3.0, 04/02, page 464 of 1064
The following kinds of DMAC transfer activation requests are provided
External request
(1) Normal DMA mode
Two
'5(4 pins. Low level detection or falling edge detection can be specified.
External requests can only be accepted on channel 0 and channel 1.
(2) On-demand data transfer mode (DDT mode)
The SH7551 performs interfacing between an external device and the DMAC using the
'%5(4, %$9/, 75, 7'$&., ID [1:0], and D[31:0] pins. The SH7551R performs
interfacing between an external device and the DMAC using the
'%5(4, %$9/, 75,
7'$&., ID [2:0], and D[31:0] pins. External requests can be accepted on all eight
channels.
Channel 0 does not have a request queue, but channels 1 to 3 in the SH7751 and
channels 1 to 7 in the SH7751R each have four request queues.
On-chip peripheral modules
Transfer requests from the SCI, SCF, and TMU. These can be accepted on all channels.
Auto-request
A transfer request is generated automatically within the DMAC.
Channel functions: Transfer modes that can be set are different for each channel.
(1) Normal DMA mode
Channel 0: Single or dual address mode. External requests are accepted.
Channel 1: Single or dual address mode. External requests are accepted.
Channel 2: Dual address mode only
Channel 3: Dual address mode only
Channel 4 (SH7751R only): Dual address mode only
Channel 5 (SH7751R only): Dual address mode only
Channel 6 (SH7751R only): Dual address mode only
Channel 7 (SH7751R only): Dual address mode only
(2) DDT mode
Channel 0: Single or dual address mode. External requests are accepted.
Channel 1: Single or dual address mode. External requests are accepted.
Channel 2: Single or dual address mode. External requests are accepted.
Channel 3: Single or dual address mode. External requests are accepted.
Channel 4 (SH7751R only): Single or dual address mode. External requests are
accepted.
Channel 5 (SH7751R only): Single or dual address mode. External requests are
accepted.
Channel 6 (SH7751R only): Single or dual address mode. External requests are
accepted.
Rev. 3.0, 04/02, page 465 of 1064
Channel 7 (SH7751R only): Single or dual address mode. External requests are
accepted.
In DDT mode, data transfer is carried out by the SH7751 using the
'%5(4, %$9/, 75,
7'$&K, ID [1:0], and D[31:0] signals to perform handshaking between the external
device and the DMAC, and data transfer is carried out by the SH7751R using the
'%5(4,
%$9/, 75, 7'$&., ID [2:0], and D[31:0] signals to perform handshaking between the
external device and the DMAC.
Request-queue clear for each channel (SH7751R only)
Request queues can be cleared on a channel-by-channel basis in either of the following two
ways.
Clearing a request queue by DTR format
The request queues of the relevant channel are cleared when it receives DTR.SZ = 110,
DTR.ID = 00, DTR.MD = 11, and DTR.COUNT [7:4]* = [18].
Using software to clear the request queue
The request queues of the relevant channel are cleared by writing a 1 to the CHCRn.QCL
bit (request-queue clear bit) of each channel.
Note: * DTR.COUNT [7:4] (DTR [23:20]): Sets the port as not used.
Rev. 3.0, 04/02, page 466 of 1064
14.1.2
Block Diagram (SH7751)
Figure 14.1 shows a block diagram of the DMAC.
SARn
DARn
DMATCRn
CHCRn
DMAOR
TMU
SCI, SCIF
DACK0, DACK1
DRAK0, DRAK1
DMAOR:
DMAC operation register
SARn:
DMAC source address
register
DARn:
DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn:
DMAC channel control register
(n: 0 to 3)
On-chip
peripheral
module
Peripheral bus
Internal bus
DMAC module
Count
control
Register
control
Activation
control
Request
priority
control
Bus
interface
32B data
buffer
Bus state
controller
CH0
CH1
CH2
CH3
Request controller
DTR command buffer
DDT module
SAR0, DAR0, DMATCR0,
CHCR0 only
External bus
ID[1:0]
D[31:0]
DDTMODE
DBREQ
BAVL
dreq0-3
4
48 bits
tdack
id[1:0]
DDTD
,
Exter
nal address/on-chip
per
ipher
al module address
Figure 14.1 Block Diagram of DMAC
Rev. 3.0, 04/02, page 467 of 1064
14.1.3
Pin Configuration (SH7751)
Tables 14.1 and 14.2 show the DMAC pins.
Table 14.1
DMAC Pins
Channel
Pin Name
Abbreviation
I/O
Function
0
DMA transfer
request
'5(4
Input
DMA transfer request input from
external device to channel 0
'5(4
acceptance
confirmation
DRAK0
Output
Acceptance of request for DMA
transfer from channel 0 to external
device
Notification to external device of start
of execution
DMA transfer end
notification
DACK0
Output
Strobe output to external device of
DMA transfer request from channel 0
to external device
1
DMA transfer
request
'5(4
Input
DMA transfer request input from
external device to channel 1
'5(4
acceptance
confirmation
DRAK1
Output
Acceptance of request for DMA
transfer from channel 1 to external
device
Notification to external device of start
of execution
DMA transfer end
notification
DACK1
Output
Strobe output to external device of
DMA transfer request from channel 1
to external device
Rev. 3.0, 04/02, page 468 of 1064
Table 14.2
DMAC Pins in DDT Mode
Pin Name
Abbreviation
I/O
Function
Data bus request
'%5(4
(
'5(4
)
Input
Data bus release request from external
device for DTR format input
Data bus available
%$9/
(DRAK0)
Output
Data bus release notification
Data bus can be used 2 cycles after
%$9/
is asserted
Transfer request signal
75
(
'5(4
)
Input
If asserted 2 cycles after
%$9/
assertion, DTR format is sent
Only
75
asserted: DMA request
'%5(4
and
75
asserted
simultaneously: Direct request to
channel 2
DMAC strobe
7'$&.
(DACK0)
Output
Reply strobe signal for external device
from DMAC
Channel number
notification
ID [1:0]
(DRAK1, DACK1)
Output
Notification of channel number to
external device at same time as
7'$&.
output
(ID [1] = DRAK1, ID [0] = DACK1)
14.1.4
Register Configuration (SH7751)
Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers
are allocated to each channel, and an additional control register is shared by all four channels.
Table 14.3
DMAC Registers
Chan-
nel
Name
Abbre-
viation
Read/
Write
Initial Value P4 Address
Area 7
Address
Access
Size
0
DMA source
address register 0
SAR0
R/W
Undefined
H'FFA00000 H'1FA00000 32
DMA destination
address register 0
DAR0
R/W
Undefined
H'FFA00004 H'1FA00004 32
DMA transfer
count register 0
DMATCR0 R/W
Undefined
H'FFA00008 H'1FA00008 32
DMA channel
control register 0
CHCR0
R/W*
H'00000000 H'FFA0000C H'1FA0000C 32
Rev. 3.0, 04/02, page 469 of 1064
Table 14.3
DMAC Registers (cont)
Chan-
nel
Name
Abbre-
viation
Read/
Write
Initial Value P4 Address
Area 7
Address
Access
Size
1
DMA source
address register 1
SAR1
R/W
Undefined
H'FFA00010 H'1FA00010 32
DMA destination
address register 1
DAR1
R/W
Undefined
H'FFA00014 H'1FA00014 32
DMA transfer
count register 1
DMATCR1 R/W
Undefined
H'FFA00018 H'1FA00018 32
DMA channel
control register 1
CHCR1
R/W*
H'00000000 H'FFA0001C H'1FA0001C 32
2
DMA source
address register 2
SAR2
R/W
Undefined
H'FFA00020 H'1FA00020 32
DMA destination
address register 2
DAR2
R/W
Undefined
H'FFA00024 H'1FA00024 32
DMA transfer
count register 2
DMATCR2 R/W
Undefined
H'FFA00028 H'1FA00028 32
DMA channel
control register 2
CHCR2
R/W*
H'00000000 H'FFA0002C H'1FA0002C 32
3
DMA source
address register 3
SAR3
R/W
Undefined
H'FFA00030 H'1FA00030 32
DMA destination
address register 3
DAR3
R/W
Undefined
H'FFA00034 H'1FA00034 32
DMA transfer
count register 3
DMATCR3 R/W
Undefined
H'FFA00038 H'1FA00038 32
DMA channel
control register 3
CHCR3
R/W*
H'00000000 H'FFA0003C H'1FA0003C 32
Com-
mon
DMA operation
register
DMAOR
R/W*
H'00000000 H'FFA00040 H'1FA00040 32
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
* Bit 1 of CHCR0CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
Rev. 3.0, 04/02, page 470 of 1064
14.2
Register Descriptions
14.2.1
DMA Source Address Registers 03 (SAR0SAR3)
Bit:
31
30
29
28
27
26
25
24
Initial value:
--
--
--
--
--
--
--
--
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
23
0
Initial value:
--
--
R/W:
R/W
R/W
DMA source address registers 03 (SAR0SAR3) are 32-bit readable/writable registers that
specify the source address of a DMA transfer. These registers have a counter feedback function,
and during a DMA transfer they indicate the next source address. In single address mode, the SAR
value is ignored when a device with DACK has been specified as the transfer source.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Rev. 3.0, 04/02, page 471 of 1064
14.2.2
DMA Destination Address Registers 03 (DAR0DAR3)
Bit:
31
30
29
28
27
26
25
24
Initial value:
--
--
--
--
--
--
--
--
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
23
0
Initial value:
--
--
R/W:
R/W
R/W
DMA destination address registers 03 (DAR0DAR3) are 32-bit readable/writable registers that
specify the destination address of a DMA transfer. These registers have a counter feedback
function, and during a DMA transfer they indicate the next destination address. In single address
mode, the DAR value is ignored when a device with DACK has been specified as the transfer
destination.
Specify a 16-bit, 32-bit, 64-bit, or 32-byte boundary address when performing a 16-bit, 32-bit, 64-
bit, or 32-byte data transfer, respectively. If a different address is specified, an address error will
be detected and the DMAC will halt.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Notes: 1. When a 16-bit, 32-bit, 64-bit, or 32-byte boundary address is specified, take care with
the setting of bit 0, bits 10, bits 20, or bits 40, respectively. If an address
specification that ignores boundary considerations is made, the DMAC will detect an
address error and halt operation on all channels (DMAOR: address error flag AE = 1).
The DMAC will also detect an address error and halt if an area 7 address is specified in
an external data bus transfer, or if the address of a nonexistent on-chip peripheral
module is specified.
2. External addresses are 29 bits in length. SAR[31:29] and DAR[31:29] are not used in
DMA transfer, and it is recommended that they both be set to 000.
Rev. 3.0, 04/02, page 472 of 1064
14.2.3
DMA Transfer Count Registers 03 (DMATCR0DMATCR3)
Bit:
31
30
29
28
27
26
25
24
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
23
22
21
20
19
18
17
16
Initial value:
--
--
--
--
--
--
--
--
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
Initial value:
--
--
--
--
--
--
--
--
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
--
--
--
--
--
--
--
--
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA transfer count registers 03 (DMATCR0DMATCR3) are 32-bit readable/writable registers
that specify the transfer count for the corresponding channel (byte count, word count, longword
count, quadword count, or 32-byte count). Specifying H'000001 gives a transfer count of 1, while
H'000000 gives the maximum setting, 16,777,216 (16M) transfers. During DMAC operation, the
remaining number of transfers is shown.
Bits 3124 of these registers are reserved; they are always read as 0, and should only be written
with 0.
The initial value of these registers after a power-on or manual reset is undefined. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Rev. 3.0, 04/02, page 473 of 1064
14.2.4
DMA Channel Control Registers 03 (CHCR0CHCR3)
Bit:
31
30
29
28
27
26
25
24
SSA2
SSA1
SSA0
STC
DSA2
DSA1
DSA0
DTC
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
23
22
21
20
19
18
17
16
--
--
--
--
DS
RL
AM
AL
Initial value:
0
0
0
0
--
--
--
--
R/W:
R
R
R
R
R/W
(R/W)
R/W
(R/W)
Bit:
15
14
13
12
11
10
9
8
DM1
DM0
SM1
SM0
RS3
RS2
RS1
RS0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
TM
TS2
TS1
TS0
--
IE
TE
DE
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R
R/W
R/(W)
R/W
Notes: The TE bit can only be written with 0 after being read as 1, to clear the flag.
The RL, AM, AL, and DS bits may be absent, depending on the channel.
DMA channel control registers 03 (CHCR0CHCR3) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 3128 and 2724 indicate
the source address and destination address, respectively; these settings are only valid when the
transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA
interface space. In other cases, these bits should be cleared to 0. For details of the PCMCIA
interface, see section 13.3.7, PCMCIA Interface.
Bits 18 and 16 are not present in CHCR2 and CHCR3. In CHCR2 and CHCR3, these bits cannot
be modified (for write, a write value of 0 should always be used) and are always read as 0.
These registers are initialized to H'00000000 by a power-on or manual reset. They retain their
values in standby mode, sleep mode, and deep sleep mode.
Rev. 3.0, 04/02, page 474 of 1064
Bits 31 to 29--Source Address Space Attribute Specification (SSA2SSA0): These bits specify
the space attribute for PCMCIA interface area access.
Bit 31: SSA2
Bit 30: SSA1
Bit 29: SSA0
Description
0
0
0
Reserved in PCMCIA access
(Initial value)
1
Dynamic bus sizing I/O space
1
0
8-bit I/O space
1
16-bit I/O space
1
0
0
8-bit common memory space
1
16-bit common memory space
1
0
8-bit attribute memory space
1
16-bit attribute memory space
Bit 28--Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control
for PCMCIA interface area access.
Bit 28: STC
Description
0
CS5 space wait cycle selection
(Initial value)
Settings of bits A5W2A5W0 in wait control register 2 (WCR2), and bits
A5PCW1A5PCW0, A5TED2A5TED0, and A5TEH2A5TEH0 in the
PCMCIA control register (PCR), are selected
1
CS6 space wait cycle selection
Settings of bits A6W2A6W0 in wait control register 2 (WCR2), and bits
A6PCW1A6PCW0, A6TED2A6TED0, and A6TEH2A6TEH0 in the
PCMCIA control register (PCR), are selected
Note: For details, see section 13.3.7, PCMCIA Interface.
Rev. 3.0, 04/02, page 475 of 1064
Bits 27 to 25--Destination Address Space Attribute Specification (DSA2DSA0): These bits
specify the space attribute for PCMCIA interface area access.
Bit 27: DSA2
Bit 26: DSA1
Bit 25: DSA0
Description
0
0
0
Reserved in PCMCIA access
(Initial value)
1
Dynamic bus sizing I/O space
1
0
8-bit I/O space
1
16-bit I/O space
1
0
0
8-bit common memory space
1
16-bit common memory space
1
0
8-bit attribute memory space
1
16-bit attribute memory space
Bit 24--Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait
cycle control for PCMCIA interface area access. This bit selects the wait control register in the
BSC that performs area 5 and 6 wait cycle control.
Bit 24: DTC
Description
0
CS5 space wait cycle selection
(Initial value)
Settings of bits A5W2A5W0 in wait control register 2 (WCR2), and bits
A5PCW1A5PCW0, A5TED2A5TED0, and A5TEH2A5TEH0 in the
PCMCIA control register (PCR), are selected
1
CS6 space wait cycle selection
Settings of bits A6W2A6W0 in wait control register 2 (WCR2), and bits
A6PCW1A6PCW0, A6TED2A6TED0, and A6TEH2A6TEH0 in the
PCMCIA control register (PCR), are selected
Note: For details, see section 13.3.7, PCMCIA Interface.
Bits 23 to 20--Reserved: These bits are always read as 0, and should only be written with 0.
Rev. 3.0, 04/02, page 476 of 1064
Bit 19--
#
#"
" Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the
'5(4 pin used in external request mode.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0CHCR3.
Bit 19: DS
Description
0
Low level detection
(Initial value)
1
Falling edge detection
Notes: Level detection burst mode when TM = 1 and DS = 0
Edge detection burst mode when TM = 1 and DS = 1
Bit 18--Request Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of
'5(4) is an active-high or active-low output.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode.
Bit 18: RL
Description
0
DRAK is an active-high output
(Initial value)
1
DRAK is an active-low output
Bit 17--Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR1CHCR3. (DDT mode: TDACK)
Bit 17: AM
Description
0
DACK is output in read cycle
(Initial value)
1
DACK is output in write cycle
Bit 16--Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. It is invalid in DDT mode.
Bit 16: AL
Description
0
Active-high output
(Initial value)
1
Active-low output
Rev. 3.0, 04/02, page 477 of 1064
Bits 15 and 14--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from external memory to an external device in single
address mode.
Bit 15: DM1
Bit 14: DM0
Description
0
0
Destination address fixed
(Initial value)
1
Destination address incremented (+1 in 8-bit transfer, +2 in 16-
bit transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-
byte burst transfer)
1
0
Destination address decremented (1 in 8-bit transfer, 2 in 16-
bit transfer, 4 in 32-bit transfer, 8 in 64-bit transfer, 32 in 32-
byte burst transfer)
1
Setting prohibited
Bits 13 and 12--Source Address Mode 1 and 0 (SM1, SM0): These bits specify
incrementing/decrementing of the DMA transfer source address. The specification of these bits is
ignored when data is transferred from an external device to external memory in single address
mode.
Bit 13: SM1
Bit 12: SM0
Description
0
0
Source address fixed
(Initial value)
1
Source address incremented (+1 in 8-bit transfer, +2 in 16-bit
transfer, +4 in 32-bit transfer, +8 in 64-bit transfer, +32 in 32-
byte burst transfer)
1
0
Source address decremented (1 in 8-bit transfer, 2 in 16-bit
transfer, 4 in 32-bit transfer, 8 in 64-bit transfer, 32 in 32-
byte burst transfer)
1
Setting prohibited
Rev. 3.0, 04/02, page 478 of 1064
Bits 11 to 8--Resource Select 3 to 0 (RS3RS0): These bits specify the transfer request source.
Bit 11:
RS3
Bit 10:
RS2
Bit 9:
RS1
Bit 8:
RS0
Description
0
0
0
0
External request, dual address mode*
1
*
3
(external address
space
external address space)
(Initial value)
1
Setting prohibited
1
0
External request, single address mode
External address space
external device*
1,
*
3
1
External request, single address mode
External device
external address space*
1,
*
3
1
0
0
Auto-request (external address space
external address
space)*
2
1
Auto-request (external address space
on-chip peripheral
module)*
2
1
0
Auto-request (on-chip peripheral module
external address
space)*
2
1
Setting prohibited
1
0
0
0
SCI transmit-data-empty interrupt transfer request
(external address space
SCTDR1)*
2
1
SCI receive-data-full interrupt transfer request
(SCRDR1
external address space)*
2
1
0
SCIF transmit-data-empty interrupt transfer request
(external address space
SCFTDR2)*
2
1
SCIF receive-data-full interrupt transfer request
(SCFRDR2
external address space)*
2
1
0
0
TMU channel 2 (input capture interrupt, external address space
external address space)*
2
1
TMU channel 2 (input capture interrupt)
(external address space
on-chip peripheral module)*
2
1
0
TMU channel 2 (input capture interrupt)
(on-chip peripheral module
external address space)*
2
1
Setting prohibited
Notes: *1 External request specifications are valid only for channels 0 and 1. Requests are not
accepted for channels 2 and 3 in normal DMA mode.
*2 Dual address mode
*3 In DDT mode, an external request specification is possible for channels 0, 1, 2, and 3.
Rev. 3.0, 04/02, page 479 of 1064
Bit 7--Transmit Mode (TM): Specifies the bus mode for transfer.
Bit 7: TM
Description
0
Cycle steal mode
(Initial value)
1
Burst mode
Bits 6 to 4--Transmit Size 2 to 0 (TS2TS0): These bits specify the transfer data size. In access
to external memory, the specification is treated as an access size as described in section 13.3,
Operation. In access to a register, the specification is treated as a register access size.
Bit 6: TS2
Bit 5: TS1
Bit 4: TS0
Description
0
0
0
Quadword size (64-bit) specification(Initial value)
1
Byte size (8-bit) specification
1
0
Word size (16-bit) specification
1
Longword size (32-bit) specification
1
0
0
32-byte block transfer specification
Bit 3--Reserved: This bit is always read as 0, and should only be written with 0.
Bit 2--Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated
after the number of data transfers specified in DMATCR (when TE = 1).
Bit 2: IE
Description
0
Interrupt request not generated after number of transfers specified in
DMATCR
(Initial value)
1
Interrupt request generated after number of transfers specified in DMATCR
Rev. 3.0, 04/02, page 480 of 1064
Bit 1--Transfer End (TE): This bit is set to 1 after the number of transfers specified in
DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or
clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1,
the transfer enabled state is not entered even if the DE bit is set to 1.
Bit 1: TE
Description
0
Number of transfers specified in DMATCR not completed
(Initial value)
[Clearing conditions]
When 0 is written to TE after reading TE = 1
In a power-on or manual reset, and in standby mode
1
Number of transfers specified in DMATCR completed
Bit 0--DMAC Enable (DE): Enables operation of the corresponding channel.
Bit 0: DE
Description
0
Operation of corresponding channel is disabled
(Initial value)
1
Operation of corresponding channel is enabled
When auto-request is specified (with RS3RS0), transfer is begun when this bit is set to 1. In the
case of an external request or on-chip peripheral module request, transfer is begun when a transfer
request is issued after this bit is set to 1. Transfer can be suspended midway by clearing this bit to
0.
Even if the DE bit has been set, transfer is not enabled when TE is 1, when DME in DMAOR is 0,
or when the NMIF or AE bit in DMAOR is 1.
Rev. 3.0, 04/02, page 481 of 1064
14.2.5
DMA Operation Register (DMAOR)
Bit:
31
30
29
28
27
26
25
24
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
23
22
21
20
19
18
17
16
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
8
DDT
--
--
--
--
--
PR1
PR0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R
R
R
R
R
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
--
--
--
--
--
AE
NMIF
DME
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/(W)
R/(W)
R/W
Note: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags.
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15--On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode.
Bit 15: DDT
Description
0
Normal DMA mode
(Initial value)
1
On-demand data transfer mode
Note:
%$9/
(DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1,
the
%$9/
pin function is enabled and this pin becomes an active-low output.
Rev. 3.0, 04/02, page 482 of 1064
Bits 14 to 10--Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8--Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
Bit 9: PR1
Bit 8: PR0
Description
0
0
CH0 > CH1 > CH2 > CH3
(Initial value)
1
CH0 > CH2 > CH3 > CH1
1
0
CH2 > CH0 > CH1 > CH3
1
Round robin mode
Bits 7 to 3--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2--Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be
cleared by writing 0 after reading 1.
Bit 2: AE
Description
0
No address error, DMA transfer enabled
(Initial value)
[Clearing condition]
When 0 is written to AE after reading AE = 1
1
Address error, DMA transfer disabled
[Setting condition]
When an address error is caused by the DMAC
Bit 1--NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of
whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all
channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing
0 after reading 1.
Bit 1: NMIF
Description
0
No NMI input, DMA transfer enabled
(Initial value)
[Clearing condition]
When 0 is written to NMIF after reading NMIF = 1
1
NMI input, DMA transfer disabled
[Setting condition]
When an NMI interrupt is generated
Rev. 3.0, 04/02, page 483 of 1064
Bit 0--DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME
bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is
enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are
suspended.
Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or
when the NMI or AE bit in DMAOR is 1.
Bit 0: DME
Description
0
Operation disabled on all channels
(Initial value)
1
Operation enabled on all channels
14.3
Operation
When a DMA transfer request is issued, the DMAC starts the transfer according to the
predetermined channel priority order. It ends the transfer when the transfer end conditions are
satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip
peripheral module request. There are two modes for DMA transfer: single address mode and dual
address mode. Either burst mode or cycle steal mode can be selected as the bus mode.
14.3.1
DMA Transfer Procedure
After the desired transfer conditions have been set in the DMA source address register (SAR),
DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA
channel control register (CHCR), and DMA operation register (DMAOR), the DMAC transfers
data according to the following procedure:
1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE =
0).
2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one
transfer unit of data (determined by the setting of TS2TS0). In auto-request mode, the transfer
begins automatically when the DE bit and DME bit are set to 1. The DMATCR value is
decremented by 1 for each transfer. The actual transfer flow depends on the address mode and
bus mode.
3. When the specified number of transfers have been completed (when the DMATCR value
reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DMTE
interrupt request is sent to the CPU.
4. If a DMAC address error or NMI interrupt occurs, the transfer is suspended. Transfer is also
suspended when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In the event
of an address error, a DMAE interrupt request is forcibly sent to the CPU.
Figure 14.2 shows a flowchart of this procedure.
Rev. 3.0, 04/02, page 484 of 1064
Note:
If a transfer request is issued while transfer is disabled, the transfer enable wait state
(transfer suspended state) is entered. Transfer is started when subsequently enabled (by
setting DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0).
Rev. 3.0, 04/02, page 485 of 1064
Start
Initial settings
(SAR, DAR, DMATCR,
CHCR, DMAOR)
Illegal address check
(reflected in AE bit)
DE, DME = 1?
NMIF, AE, TE = 0?
Transfer
request issued?
*1
Transfer (1 transfer unit)
DMATCR - 1
DMATCR
Update SAR, DAR
DMTE interrupt request
(when IE = 1)
DMATCR = 0?
NMIF or
AE = 1 or DE = 0 or
DME = 0?
End of transfer
Normal end
NMIF or
AE = 1 or DE = 0 or
DME = 0?
Bus mode,
transfer request mode,
detection
method
Transfer suspended
*4
*2
*3
No
No
Yes
Yes
Yes
No
No
No
Yes
Yes
No
Yes
Notes: *1 In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE
and DME bits are set to 1.
*2 level detection (external request) in burst mode, or cycle steal mode
*3 edge detection (external request) in burst mode, or auto-request mode in burst mode
*4
An illegal address is detected by comparing bits TS2TS0 in CHCRn with SARn and DARn
Figure 14.2 DMAC Transfer Flowchart
Rev. 3.0, 04/02, page 486 of 1064
14.3.2
DMA Transfer Requests
DMA transfer requests are basically generated at either the data transfer source or destination, but
they can also be issued by external devices or on-chip peripheral modules that are neither the
source nor the destination.
Transfers can be requested in three modes: auto-request, external request, and on-chip peripheral
module request. The transfer request mode is selected by means of bits RS3RS0 in DMA channel
control registers 03 (CHCR0CHCR3).
Auto Request Mode: When there is no transfer request signal from an external source, as in a
memory-to-memory transfer or a transfer between memory and an on-chip peripheral module
unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a
transfer request signal internally. When the DE bit in CHCR0CHCR3 and the DME bit in the
DMA operation register (DMAOR) are set to 1, the transfer begins (so long as the TE bit in
CHCR0CHCR3 and the NMIF and AE bits in DMAOR are all 0).
External Request Mode: In this mode a transfer is performed in response to a transfer request
signal (
'5(4) from an external device. One of the modes shown in table 14.4 should be chosen
according to the application system. If DMA transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF
= 0, AE = 0), transfer starts when
'5(4 is input. The DS bit in CHCR0/CHCR1 is used to select
either falling edge detection or low level detection for the
'5(4 signal (level detection when DS
= 0, edge detection when DS = 1).
'5(4 is accepted after a power-on reset if TE = 0, NMIF = 0, and AE = 0, but transfer is not
executed if DMA transfer is not enabled (DE = 0 or DME = 0).
In this case, DMA transfer is started when enabled (by setting DE = 1 and DME = 1).
The source of the transfer request does not have to be the data transfer source or destination.
Rev. 3.0, 04/02, page 487 of 1064
Table 14.4
Selecting External Request Mode with RS Bits
RS3
RS2
RS1
RS0
Address Mode
Transfer Source
Transfer Destination
0
0
0
0
Dual address
mode
External memory,
memory-mapped
external device, or
external device with
DACK
External memory,
memory-mapped
external device, or
external device with
DACK
1
0
Single address
mode
External memory
or memory-mapped
external device
External device
with DACK
1
Single address
mode
External device with
DACK
External memory
or memory-mapped
external device
External Request Acceptance Conditions
1. When at least one of DMAOR.DME and CHCR.DE is 0, and DMAOR.NMIF,
DMAOR.AE, and CHCR.TE are all 0, if an external request (
'5(4: edge-detected) is
input it will be held inside the DMAC until DMA transfer is either executed or canceled.
Since DMA transfer is not enabled in this case (DME = 0 or DE = 0), DMA transfer is not
initiated. DMA transfer is started after it is enabled (DME = 1, DE = 1, DMAOR.NMIF =
0, DMAOR.AE = 0, CHCR.TE = 0).
2. When DMA transfer is enabled (DME = 1, DE = 1, DMAOR.NMIF = 0, DMAOR.AE = 0,
CHCR.TE = 0), if an external request (
'5(4) is input, DMA transfer is started.
3. An external request (
'5(4) will be ignored if input when CHCR.TE = 1, DMAOR.NMIF
= 1, DMAOR.AE = 1, during a power-on reset or manual reset, in deep sleep mode,
standby mode, or while the DMAC is in the module standby state.
4. A previously input external request will be canceled by the occurrence of an NMI interrupt
(DMAOR.NMIF = 1) or address error (DMAOR.AE = 1), or by a power-on reset or
manual reset.
Usage Notes
1. An external request (
'5(4) is detected by a low level or falling edge. Ensure that the
external request (
'5(4) signal is held high when there is no DMA transfer request from
an external device after a power-on reset or manual reset.
When DMA transfer is restarted, check whether a DMA transfer request is being held.
2. With
'5(4 edge detection, an accepted external request can be canceled by first negating
'5(4, enabling a change of setting from CHCR.DS = 1 to CHCR.DS = 0, and then
asserting
'5(4 after setting CHCR.DS to 1 again.
Rev. 3.0, 04/02, page 488 of 1064
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed in response to
a transfer request signal (interrupt request signal) from an on-chip peripheral module. As shown in
table 14.5, there are seven transfer request signals: input capture interrupts from the timer unit
(TMU), and receive-data-full interrupts (RXI) and transmit-data-empty interrupts (TXI) from the
two serial communication interfaces (SCI, SCIF). If DMA transfer is enabled (DE = 1, DME = 1,
TE = 0, NMIF = 0, AE = 0), transfer starts when a transfer request signal is input.
The source of the transfer request does not have to be the data transfer source or destination.
However, when the transfer request is set to RXI (transfer request by SCI/SCIF receive-data-full
interrupt), the transfer source must be the SCI/SCIF's receive data register (SCRDR1/SCFRDR2).
When the transfer request is set to TXI (transfer request by SCI/SCIF transmit-data-empty
interrupt), the transfer destination must be the SCI/SCIF's transmit data register
(SCTDR1/SCFTDR2).
Rev. 3.0, 04/02, page 489 of 1064
Table 14.5
Selecting On-Chip Peripheral Module Request Mode with RS Bits
RS3 RS2 RS1 RS0
DMAC Transfer
Request Source
DMAC Transfer
Request Signal
Transfer
Source
Transfer
Destination Bus Mode
1
0
0
0
SCI transmitter
SCTDR1 (SCI
transmit-data-
empty transfer
request)
External*
SCTDR1
Cycle steal
mode
1
SCI receiver
SCRDR1 (SCI
receive-data-full
transfer request)
SCRDR1
External*
Cycle steal
mode
1
0
SCIF transmitter
SCFTDR2 (SCIF
transmit-data-
empty transfer
request)
External*
SCFTDR2
Cycle steal
mode
1
SCIF receiver
SCFRDR2 (SCIF
receive-data-full
transfer request)
SCFRDR2 External*
Cycle steal
mode
1
0
0
TMU channel 2
Input capture
occurrence
External*
External*
Burst/cycle
steal mode
1
TMU channel 2
Input capture
occurrence
External*
On-chip
peripheral
Burst/cycle
steal mode
1
0
TMU channel 2
Input capture
occurrence
On-chip
peripheral
External*
Burst/cycle
steal mode
TMU: Timer unit
SCI:
Serial communication interface
SCIF: Serial communication interface with FIFO
Notes: *
External memory or memory-mapped external device
1. SCI/SCIF burst transfer setting is prohibited.
2. If input capture interrupt acceptance is set for multiple channels and DE =1 for each
channel, processing will be executed on the highest-priority channel in response to a
single input capture interrupt.
3. A DMA transfer request by means of an input capture interrupt can be canceled by
setting TCR2.ICPE1 = 0 and TCR2.ICPE0 = 0 in the TMU.
To output a transfer request from an on-chip peripheral module, set the DMA transfer request
enable bit for that module and output a transfer request signal.
For details, see sections 12, Timer Unit (TMU), 15, Serial Communication Interface (SCI), and
16, Serial Communication Interface with FIFO (SCIF).
When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral
module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs
every transfer in cycle steal mode, and in the last transfer in burst mode.
Rev. 3.0, 04/02, page 490 of 1064
14.3.3
Channel Priorities
If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel
according to a predetermined priority system, either in a fixed mode or round robin mode. The
mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR).
Fixed Mode: In this mode, the relative channel priorities remain fixed. The following priority
orders are available in fixed mode:
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
The priority order is selected with bits PR1 and PR0 in DMAOR.
Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word,
longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest
priority level. This is illustrated in figure 14.3. The order of priority in round robin mode
immediately after a reset is CH0 > CH1 > CH2 > CH3.
Note:
In round robin mode, if no transfer request is accepted for any channel during DMA
transfer, the priority order becomes CH0 > CH1 > CH2 > CH3.
Rev. 3.0, 04/02, page 491 of 1064
CH0 > CH1 > CH2 > CH3
CH1 > CH2 > CH3 > CH0
CH0 > CH1 > CH2 > CH3
Transfer on channel 0
Priority order after transfer
Initial priority order
Channel 0 is given the lowest
priority.
Transfer on channel 1
Priority order after transfer
Initial priority order
Transfer on channel 2
Priority order after transfer
Initial priority order
Priority after transfer due to
issuance of a transfer request
for channel 1 only.
When channel 2 is given the
lowest priority, the priorities of
channels 0 and 1, which were
higher than channel 2, are
also shifted simultaneously. If
there is a transfer request for
channel 1 only immediately
afterward, channel 1 is given
the lowest priority and the
priorities of channels 3 and 0
are simultaneously shifted
down.
Transfer on channel 3
Initial priority order
Priority order after transfer
No change in priority order
CH0 > CH1 > CH2 > CH3
CH3 > CH0 > CH1 > CH2
CH2 > CH3 > CH0 > CH1
CH0 > CH1 > CH2 > CH3
CH0 > CH1 > CH2 > CH3
CH2 > CH3 > CH0 > CH1
When channel 1 is given the
lowest priority, the priority of
channel 0, which was higher
than channel 1, is also
shifted simultaneously.
Figure 14.3 Round Robin Mode
Figure 14.4 shows the changes in priority levels when transfer requests are issued simultaneously
for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. The
operation of the DMAC in this case is as follows.
Rev. 3.0, 04/02, page 492 of 1064
1. Transfer requests are issued simultaneously for channels 0 and 3.
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed
first (channel 3 is on transfer standby).
3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on
transfer standby).
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is
started (channel 3 is on transfer standby).
6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level.
7. The channel 3 transfer is started.
8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered,
giving channel 3 the lowest priority.
3
1, 3
3
Transfer request
Channel
waiting
DMAC operation
Channel priority
order
1. Issued for channels 0
and 3
3. Issued for channel 1
2. Start of channel 0
transfer
0 > 1 > 2 > 3
1 > 2 > 3 > 0
2 > 3 > 0 > 1
0 > 1 > 2 > 3
4. End of channel 0
transfer
5. Start of channel 1
transfer
6. End of channel 1
transfer
7. Start of channel 3
transfer
8. End of channel 3
transfer
Change of
priority order
Change of
priority order
Change of
priority order
None
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode
Rev. 3.0, 04/02, page 493 of 1064
14.3.4
Types of DMA Transfer
The DMAC supports the transfers shown in table 14.6. It can operate in single address mode, in
which either the transfer source or the transfer destination is accessed using the acknowledge
signal, or in dual address mode, in which both the transfer source and transfer destination
addresses are output. The actual transfer operation timing depends on the bus mode, which can be
either burst mode or cycle steal mode.
Table 14.6
Supported DMA Transfers
Transfer Destination
Transfer Source
External Device
with DACK
External
Memory
Memory-Mapped
External Device
On-Chip
Peripheral Module
External device
with DACK
Not available
Single address
mode
Single address
mode
Not available
External memory
Single address
mode
Dual address
mode
Dual address mode Dual address mode
Memory-mapped
external device
Single address
mode
Dual address
mode
Dual address mode Dual address mode
On-chip peripheral
module
Not available
Dual address
mode
Dual address mode Not available
Rev. 3.0, 04/02, page 494 of 1064
Address Modes
Single Address Mode: In single address mode, both the transfer source and the transfer
destination are external; one is accessed by the DACK signal and the other by an address. In this
mode, the DMAC performs a DMA transfer in one bus cycle by simultaneously outputting the
external device strobe signal (DACK) to either the transfer source or transfer destination external
device to access it, while outputting an address to the other side of the transfer. Figure 14.5 shows
an example of a transfer between external memory and an external device with DACK in which
the external device outputs data to the data bus and that data is written to external memory in the
same bus cycle.
DMAC
DACK
External
memory
External device
with DACK
SH7751 Series
External
address
bus
: Data flow
External
data bus
Figure 14.5 Data Flow in Single Address Mode
Two types of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and external memory. Only the external request signal (
'5(4) is used in both these
cases.
Figure 14.6 shows the transfer timing for single address mode.
The access timing depends on the type of external memory. For details, see the descriptions of the
memory interfaces in section 13, Bus State Controller (BSC).
Rev. 3.0, 04/02, page 495 of 1064
Address output to external memory
space
Data output from external device
with DACK
DACK signal to external
device with DACK
WE
signal to external memory space
Address output to external memory
space
Data output from external memory
space
RD
signal to external memory space
DACK signal to external
device with DACK
(a) From external device with DACK to external memory space
(b) From external memory space to external device with DACK
CKIO
A28A0
CSn
D63D0
DACK
WE
CKIO
A28A0
CSn
D63D0
RD
DACK
Figure 14.6 DMA Transfer Timing in Single Address Mode
Rev. 3.0, 04/02, page 496 of 1064
Dual Address Mode: Dual address mode is used to access both the transfer source and the
transfer destination by address. The transfer source and destination can be accessed by either on-
chip peripheral module or external address.
In dual address mode, data is read from the transfer source in the data read cycle, and written to
the transfer destination in the data write cycle, so that the transfer is executed in two bus cycles.
The transfer data is temporarily stored in the data buffer in the bus state controller (BSC).
In a transfer between external memories such as that shown in figure 14.7, data is read from
external memory into the BSC's data buffer in the read cycle, then written to the other external
memory in the write cycle. Figure 14.8 shows the timing for this operation.
Data buffer
Address b
u
s
Data b
u
s
Address b
u
s
Data b
u
s
Memory
Transfer source
module
Transfer destination
module
Memory
Transfer source
module
Transfer destination
module
SAR
DAR
Data buffer
SAR
DAR
Taking the SAR value as the address, data is read from the transfer source module
and stored temporarily in the data buffer in the bus state controller (BSC).
1st bus cycle
2nd bus cycle
Taking the DAR value as the address, the data stored in the BSC's data buffer is
written to the transfer destination module.
DMAC
BSC
BSC
DMAC
Figure 14.7 Operation in Dual Address Mode
Rev. 3.0, 04/02, page 497 of 1064
CKIO
A28A0
D63D0
DACK
Transfer from external memory space to external memory space
Transfer source
address
Transfer destination
address
Data read cycle
(1st cycle)
Data write cycle
(2nd cycle)
Figure 14.8 Example of Transfer Timing in Dual Address Mode
Bus Modes
There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0
CHCR3.
Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus to the CPU at the end of each
transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is
issued, the DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer.
At the end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end
condition is satisfied.
Cycle steal mode can be used with all categories of transfer request source, transfer source, and
transfer destination.
Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer
conditions in this example are dual address mode and
'5(4 level detection.
Rev. 3.0, 04/02, page 498 of 1064
CPU
CPU
DMAC
DMAC
CPU
DMAC
DMAC
CPU
CPU
CPU
Bus cycle
Bus returned to CPU
Read
Write
Read
Write
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode
Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers
data continuously until the transfer end condition is satisfied. Bus release by means of
%5(4 and
refresh requests conform to the DMAC burst mode transfer priority specification in bus control
register 1 (BCRL.DMABST). With
'5(4 low level detection in external request mode, however,
when
'5(4 is driven high the bus passes to another bus master after the end of the DMAC
transfer request that has already been accepted, even if the transfer end condition has not been
satisfied.
Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in
this example are single address mode and
'5(4 level detection (CHCRn.DS = 0, CHCRn.TM =
1).
CPU
DMAC
DMAC
DMAC
DMAC
DMAC
DMAC
CPU
CPU
CPU
Bus cycle
Figure 14.10 Example of DMA Transfer in Burst Mode
Note:
Burst mode can be set regardless of the transfer size. A 32-byte block transfer burst mode
setting can also be made.
Rev. 3.0, 04/02, page 499 of 1064
Relationship between DMA Transfer Type, Request Mode, and Bus Mode
Table 14.7 shows the relationship between the type of DMA transfer, the request mode, and the
bus mode.
Table 14.7
Relationship between DMA Transfer Type, Request Mode, and Bus Mode
Address
Mode
Type of Transfer
Request
Mode
Bus
Mode
Transfer Size
(Bits)
Usable
Channels
Single
External device with DACK
and external memory
External
B/C
8/16/32/64/32B 0, 1 (2, 3)*
6
External device with DACK
and memory-mapped external
device
External
B/C
8/16/32/64/32B 0, 1 (2, 3)*
6
Dual
External memory and external
memory
Internal*
1
,
external*
7
B/C
8/16/32/64/32B 0, 1, 2, 3*
5,
*
6
External memory and memory-
mapped external device
Internal*
1
,
external*
7
B/C
8/16/32/64/32B 0, 1, 2, 3*
5,
*
6
Memory-mapped external
device and memory-mapped
external device
Internal*
1
,
external*
7
B/C
8/16/32/64/32B 0, 1, 2, 3*
5,
*
6
External memory and
on-chip peripheral module
Internal*
2
B/C*
3
8/16/32/64*
4
0, 1, 2, 3*
5,
*
6
Memory-mapped external
device and on-chip
peripheral module
Internal*
2
B/C*
3
8/16/32/64*
4
0, 1, 2, 3*
5,
*
6
32B:
32-byte burst transfer
B:
Burst
C:
Cycle steal
External:
External request
Internal:
Auto request, on-chip peripheral module request
Notes: *1 External request, auto-request, or on-chip peripheral module request (TMU input
capture interrupt request) possible. In the case of an on-chip peripheral module request,
it is not possible to specify external memory data transfer with the SCI (SCIF) as the
transfer request source.
*2 Auto-request, or on-chip peripheral module request possible. If the transfer request
source is the SCI (SCIF), either the transfer source must be SCRDR1 (SCFRDR2) or
the transfer destination must be SCTDR1 (SCFTDR2).
*3 When the transfer request source is the SCI (SCIF), only cycle steal mode can be used.
*4 Access size permitted for the on-chip peripheral module register that is the transfer
source or transfer destination.
*5 When the transfer request is an external request, only channels 0 and 1 can be used.
*6 In DDT mode, transfer requests can be accepted for all channels from external devices
capable of DTR format output.
Rev. 3.0, 04/02, page 500 of 1064
*7 See tables 14.8 and 14.9 for the transfer sources and transfer destinations in DMA
transfer by means of an external request.
(a) Normal DMA Mode
Table 14.8 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by the SH7751 Series in
normal DMA mode.
Table 14.8
External Request Transfer Sources and Destinations in Normal Mode
Transfer Direction (Settable Memory Interface)
Transfer Source
Transfer Destination
Address
Mode
Usable
DMAC
Channels
1
Synchronous DRAM
External device with DACK
Single
0, 1
2
External device with DACK
Synchronous DRAM
Single
0, 1
3
SRAM-type, DRAM
External device with DACK
Single
0, 1
4
External device with DACK
SRAM-type, DRAM
Single
0, 1
5
Synchronous DRAM
SRAM-type, MPX, PCMCIA
*
Dual
0, 1
6
SRAM-type, MPX, PCMCIA
*
Synchronous DRAM
Dual
0, 1
7
SRAM-type, DRAM, PCMCIA,
MPX
SRAM-type, MPX, PCMCIA
*
Dual
0, 1
8
SRAM-type, MPX, PCMCIA
*
SRAM-type, DRAM, PCMCIA,
MPX
Dual
0, 1
*: DACK output setting in dual address mode transfer
"SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
Notes: 1. Memory interfaces on which transfer is possible in single address mode are SRAM,
byte control SRAM, burst ROM, DRAM, and synchronous DRAM.
2. When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
Rev. 3.0, 04/02, page 501 of 1064
(b) DDT Mode
Table 14.9 shows the memory interfaces that can be specified for the transfer source and transfer
destination in DMA transfer initiated by an external request supported by the SH7751 Series in
DDT mode.
Table 14.9
External Request Transfer Sources and Destinations in DDT Mode
Transfer Direction (Settable Memory Interface)
Transfer Source
Transfer Destination
Address
Mode
Usable
DMAC
Channels
1
Synchronous DRAM
External device with DACK
Single
0, 1, 2, 3
2
External device with DACK
Synchronous DRAM
Single
0, 1, 2, 3
3
Synchronous DRAM
SRAM-type, MPX, PCMCIA
*
Dual
0, 1, 2, 3
4
SRAM-type, MPX, PCMCIA
*
Synchronous DRAM
Dual
0, 1, 2, 3
5
SRAM-type, DRAM, PCMCIA,
MPX
SRAM-type, MPX, PCMCIA
*
Dual
0, 1, 2, 3
6
SRAM-type, MPX, PCMCIA
*
SRAM-type, DRAM, PCMCIA,
MPX
Dual
0, 1, 2, 3
*: DACK output setting in dual address mode transfer
"SRAM-type" in the table indicates an SRAM, byte control SRAM, or burst ROM setting.
Notes: 1. The only memory interface on which single address mode transfer is possible in DDT
mode is synchronous DRAM.
2. When performing dual address mode transfer, make the DACK output setting for the
SRAM, byte control SRAM, burst ROM, PCMCIA, or MPX interface.
Bus Mode and Channel Priority Order
When, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to
channel 0, which has a higher priority, the channel 0 transfer is started immediately.
If fixed mode has been set for the priority levels (CH0 > CH1), transfer on channel 1 is continued
after transfer on channel 0 is completely finished, whether cycle steal mode or burst mode is set
for channel 0.
If round robin mode has been set for the priority levels, transfer on channel 1 is restarted after one
transfer unit of data is transferred on channel 0, whether cycle steal mode or burst mode is set for
channel 0. Channel execution alternates in the order: channel 1
channel 0
channel 1
channel 0.
An example of round robin mode operation is shown in figure 14.11.
Rev. 3.0, 04/02, page 502 of 1064
Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or
round robin mode is set for the priority order, the bus is not released to the CPU until channel 1
transfer ends.
CPU
DMAC CH1
DMAC CH1
DMAC CH0
DMAC CH1
DMAC CH0
DMAC CH1
DMAC CH1
CPU
Priority system: Round robin mode
Channel 0:
Cycle steal mode
Channel 1:
Burst mode (edge-sensing)
CH0
CH1
CH0
CPU
CPU
DMAC channel 1
burst mode
DMAC channel 0 and
channel 1 round robin
mode
DMAC channel 1
burst mode
Figure 14.11 Bus Handling with Two DMAC Channels Operating
Note:
When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the
bus is passed to the CPU during a break in requests.
14.3.5
Number of Bus Cycle States and
##"
" Pin Sampling Timing
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. See section 13, Bus State Controller (BSC), for details.
DREQ Pin Sampling Timing: In external request mode, the
'5(4 pin is sampled at the rising
edge of CKIO clock pulses. When
'5(4 input is detected, a DMAC bus cycle is generated and
DMA transfer executed after four CKIO cycles at the earliest.
With
'5(4 falling edge detection, as the signal passes via an asynchronous circuit the DMAC
recognizes
'5(4 two cycles (CKIO) later (one cycle (CKIO) later in the case of low level
detection).
The second and subsequent
'5(4 sampling operations are performed one cycle after the start of
the first DMAC transfer bus cycle (in the case of single address mode).
DRAK is output for one cycle only, once each time
'5(4 is detected, regardless of the transfer
mode or
'5(4 detection method. In the case of burst mode edge detection, '5(4 is sampled in
the first cycle only, and so DRAK is output in the first cycle only .
Operation: Figures 14.12 to 14.22 show the timing in each mode.
Rev. 3.0, 04/02, page 503 of 1064
1. Cycle Steal Mode
In cycle steal mode, The
'5(4 sampling timing differs for dual address mode and single
address mode, and for level detection and edge detection of
'5(4.
For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC
transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second
sampling operation is performed one cycle after the start of the first DMAC transfer write
cycle. If
'5(4 is not detected at this time, sampling is executed in every subsequent cycle.
In figure 14.13 (cycle steal mode, dual address mode, edge detection), DMAC transfer begins,
at the earliest, five CKIO cycles after the first sampling operation. The second sampling
operation begins from the cycle in which the first DMAC transfer read cycle ends. If
'5(4 is
not detected at this time, sampling is executed in every subsequent cycle.
For details of the timing for various memory accesses, see section 13, Bus State Controller
(BSC).
Figure 14.18 shows the case of cycle steal mode, single address mode, and level detection. In
this case, too, transfer is started, at the earliest, four CKIO cycles after the first
'5(4
sampling operation. The second sampling operation is performed one cycle after the start of
the first DMAC transfer bus cycle.
Figure 14.19 shows the case of cycle steal mode, single address mode, and edge detection. In
this case, transfer is started, at the earliest, five CKIO cycles after the first
'5(4 sampling
operation. The second sampling begins one cycle after the first assertion of DRAK.
In single address mode, the DACK signal is output every DMAC transfer cycle.
2. Burst Mode, Dual Address Mode, Level Detection
'5(4 sampling timing in burst mode using dual address mode and level detection is virtually
the same as for cycle steal mode.
For example, in figure 14.14, DMAC transfer begins, at the earliest, four CKIO cycles after the
first sampling operation. The second sampling operation is performed one cycle after the start
of the first DMAC transfer write cycle.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
3. Burst Mode, Single Address Mode, Level Detection
'5(4 sampling timing in burst mode using single address mode and level detection is shown
in figure 14.20.
In the example shown in figure 14.20, DMAC transfer begins, at the earliest, four CKIO cycles
after the first sampling operation, and the second sampling operation begins one cycle after the
start of the first DMAC transfer bus cycle.
In single address mode, the DACK signal is output every DMAC transfer cycle.
Rev. 3.0, 04/02, page 504 of 1064
In figure 14.22, with a 32-byte data size, 32-bit bus width, and SDRAM: row hit write, DMAC
transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second
sampling operation begins one cycle after DACK is asserted for the first DMAC transfer.
4. Burst Mode, Dual Address Mode, Edge Detection
In burst mode using dual address mode and edge detection,
'5(4 sampling is performed in
the first cycle only.
For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five
CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of
the number of data transfers set in DMATCR.
'5(4 is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
5. Burst Mode, Single Address Mode, Edge Detection
In burst mode using single address mode and edge detection,
'5(4 sampling is performed
only in the first cycle.
For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five
cycles after the first sampling operation. DMAC transfer then continues until the end of the
number of data transfers set in DMATCR.
'5(4 is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In single address mode, the DACK signal is output every DMAC transfer cycle.
Suspension of DMA Transfer in Case of
##"
" Level Detection
With
'5(4 level detection in burst mode or cycle steal mode, and in dual address mode or single
address mode, the external device for which DMA transfer is being executed can judge from the
rising edge of CKIO that DRAK has been asserted, and can suspend DMA transfer by negating
'5(4. In this case, the next DRAK signal is not output.
Rev. 3.0, 04/02, page 505 of 1064
Source address
Read
Write
Read
1st
acceptance
2nd
acceptance
Write
Bus locked
Source address
Destination address
Bus locked
Destination address
CPU
CPU
DMAC
CPU
DMAC
DRAK0
DREQ1
DREQ0
(level
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
: DREQ sampling and determination of channel priority
Figure 14.12 Dual Address Mode/Cycle Steal Mode
External Bus
External Bus/
##"
" (Level Detection), DACK (Read Cycle)
Rev. 3.0, 04/02, page 506 of 1064
Source address
Read
Write
Read
Read
3rd
acceptance
4th
accep-
tance
1st
acceptance
2nd
acceptance
Write
Bus locked
Source address
Source address
Destination address
Bus locked
Destination address
CPU
DMAC
CPU
DMAC
CPU
DMAC
DRAK0
DREQ1
DREQ0
(edge
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
: DREQ sampling and determination of channel priority
Figure 14.13 Dual Address Mode/Cycle Steal Mode
External Bus
External Bus/
##"
" (Edge Detection), DACK (Read Cycle)
Rev. 3.0, 04/02, page 507 of 1064
Source address
Read
Write
Read
1st
acceptance
2nd
acceptance
Write
Bus locked
Source address
Destination address
Bus locked
Destination address
CPU
DMAC-2
CPU
DMAC-1
DRAK0
DREQ1
DREQ0
(level
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
: DREQ sampling and determination of channel priority
Figure 14.14 Dual Address Mode/Burst Mode
External Bus
External Bus/
##"
" (Level Detection), DACK (Read Cycle)
Rev. 3.0, 04/02, page 508 of 1064
Source address
Read
Write
Read
1st
acceptance
Write
Bus locked
Source address
Destination address
Bus locked
Destination address
CPU
DMAC-2
CPU
DMAC-1
TE bit: transfer end
DRAK0
DREQ1
DREQ0
(edge
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
: DREQ sampling and determination of channel priority
Figure 14.15 Dual Address Mode/Burst Mode
External Bus
External Bus/
##"
" (Edge Detection), DACK (Read Cycle)
Rev. 3.0, 04/02, page 509 of 1064
Bus cycle
(When Bcyc : Pcyc = 1 : 1)
On-chip
peripheral
address bus
CKIO
Source address
On-chip
peripheral
data bus
Read
Read
Read
D[31:0]
Write
Write
Write
Source address
Source address
A[25:0]
Destination address
Destination address
Destination address
CPU
CPU
DMAC
CPU
DMAC
CPU
DMAC
Figure 14.16 Dual Address Mode/Cycle Steal Mode
On-Chip SCI (Level Detection)
External Bus
Rev. 3.0, 04/02, page 510 of 1064
Bus cycle
(When Bcyc : Pcyc = 1 : 1)
CKIO
Source address
Read
Read
Read
D[31:0]
Write
Write
Write
Source address
Source address
A[25:0]
Destination address
Destination address
Destination address
CPU
DMAC
CPU
DMAC
CPU
DMAC
T1
T2
T1
T2
T1
T2
On-chip
peripheral
address bus
On-chip
peripheral
data bus
Figure 14.17 Dual Address Mode/Cycle Steal Mode
External Bus
On-Chip SCI (Level Detection)
Rev. 3.0, 04/02, page 511 of 1064
Read
Read
Read
Read
1st
acceptance
CPU
CPU
CPU
DMAC
CPU
DMAC
DMAC
CPU
DMAC
Source address
2nd
acceptance
Source address
3rd
acceptance
Source address
4th
acceptance
Source address
DRAK0
DREQ1
DREQ0
(level
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
: DREQ sampling and determination of channel priority
Figure 14.18 Single Address Mode/Cycle Steal Mode
External Bus
External Bus/
##"
" (Level Detection)
Rev. 3.0, 04/02, page 512 of 1064
Source address
Read
Read
Read
3rd
acceptance
1st
acceptance
2nd
acceptance
Source address
Source address
CPU
CPU
DMAC
CPU
DMAC
CPU
DMAC
DRAK0
DREQ1
DREQ0
(edge
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
: DREQ sampling and determination of channel priority
Figure 14.19 Single Address Mode/Cycle Steal Mode
External Bus
External Bus/
##"
" (Edge Detection)
Rev. 3.0, 04/02, page 513 of 1064
Source address
Read
Read
Read
Read
4th
acceptance
3rd
acceptance
1st
acceptance
2nd
acceptance
Source address
Source address
Source address
CPU
DMAC-4
DMAC-2
DMAC-3
CPU
DMAC-1
: DREQ sampling and determination of channel priority
DRAK0
DREQ1
DREQ0
(level
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
Figure 14.20 Single Address Mode/Burst Mode
External Bus
External Bus/
##"
" (Level Detection)
Rev. 3.0, 04/02, page 514 of 1064
Source address
Read
Read
TE bit: transfer end
Read
Read
1st
acceptance
Source address
Source address
Source address
CPU
DMAC-2
DMAC-4
DMAC-3
CPU
DMAC-1
DRAK0
DREQ0
(edge
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
: DREQ sampling and determination of channel priority
Figure 14.21 Single Address Mode/Burst Mode
External Bus
External Bus/
##"
" (Edge Detection)
Rev. 3.0, 04/02, page 515 of 1064
DRAK0
: DREQ sampling and determination of channel priority
DREQ1
DREQ0
(level
detection)
DACK0
Bus cycle
A[25:0]
CKIO
D[31:0]
1st
acceptance
CPU
CPU
D1
D6
D8
Asserted 2 cycles before
start of bus cycle
Asserted 2 cycles before
start of bus cycle
Asserted 2 cycles before
start of bus cycle
2nd
acceptance
3rd
acceptance
DMAC-1
DMAC-2
DMAC-3
Destination
address
Destination
address
Destination
address
D1
D6
D8
D1
D6
D7
D8
D7
D7
Figure 14.22 Single Address Mode/Burst Mode
External Bus
External Bus/
##"
" (Level Detection)/32-Byte Block Transfer
(Bus Width: 32 Bits, SDRAM: Row Hit Write)
Rev. 3.0, 04/02, page 516 of 1064
14.3.6
Ending DMA Transfer
The conditions for ending DMA transfer are different for ending on individual channels and for
ending on all channels together. Except for the case where transfer ends when the value in the
DMA transfer count register (DMATCR) reaches 0, the following conditions apply to ending
transfer.
1. Cycle Steal Mode (External Request, On-Chip Peripheral Module Request, Auto-Request)
When a transfer end condition is satisfied, acceptance of DMAC transfer requests is
suspended. The DMAC completes transfer for the transfer requests accepted up to the point at
which the transfer end condition was satisfied, then stops.
In cycle steal mode, the operation is the same for both edge and level transfer request
detection.
2. Burst Mode, Edge Detection (External Request, On-Chip Peripheral Module Request, Auto-
Request)
The delay between the point at which a transfer end condition is satisfied and the point at
which the DMAC actually stops is the same as in cycle steal mode. In burst mode with edge
detection, only the first transfer request activates the DMAC, but the timing of stop request
(DE = 0 in CHCR, DME = 0 in DMAOR) sampling is the same as the transfer request
sampling timing shown in 4 and 5 under Operation in section 14.3.5. Therefore, a transfer
request is regarded as having been issued until a stop request is detected, and the
corresponding processing is executed before the DMAC stops.
3. Burst Mode, Level Detection (External Request)
The delay between the point at which a transfer end condition is satisfied and the point at
which the DMAC actually stops is the same as in cycle steal mode. As in the case of burst
mode with edge detection, the timing of stop request (DE = 0 in CHCR, DME = 0 in DMAOR)
sampling is the same as the transfer request sampling timing shown in 2 and 3 under Operation
in section 14.3.5. Therefore, a transfer request is regarded as having been issued until a stop
request is detected, and the corresponding processing is executed before the DMAC stops.
4. Transfer Suspension Bus Timing
Transfer suspension is executed on completion of processing for one transfer unit. In dual
address mode transfer, write cycle processing is executed even if a transfer end condition is
satisfied during the read cycle, and the transfers covered in 1, 2, and 3 above are also executed
before operation is suspended.
Rev. 3.0, 04/02, page 517 of 1064
Conditions for Ending Transfer on Individual Channels: Transfer ends on the corresponding
channel when either of the following conditions is satisfied:
The value in the DMA transfer count register (DMATCR) reaches 0.
The DE bit in the DMA channel control register (CHCR) is cleared to 0.
1. End of transfer when DMATCR = 0
When the DMATCR value reaches 0, DMA transfer ends on the corresponding channel and
the transfer end flag (TE) in CHCR is set. If the interrupt enable bit (IE) is set at this time, an
interrupt (DMTE) request is sent to the CPU.
Transfer ending when DMATCR = 0 does not follow the procedures described in 1, 2, 3, and 4
in section 14.3.6.
2. End of transfer when DE = 0 in CHCR
When the DMA enable bit (DE) in CHCR is cleared, DMA transfer is suspended on the
corresponding channel. The TE bit is not set in this case. Transfer ending in this case follows
the procedures described in 1, 2, 3, and 4 in section 14.3.6.
Conditions for Ending Transfer Simultaneously on All Channels: Transfer ends on all
channels simultaneously when either of the following conditions is satisfied:
The address error bit (AE) or NMI flag (NMIF) in the DMA operation register (DMAOR) is
set.
The DMA master enable bit (DME) in DMAOR is cleared to 0.
1. End of transfer when AE = 1 in DMAOR
If the AE bit in DMAOR is set to 1 due to an address error, DMA transfer is suspended on all
channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is
passed to the CPU. Therefore, when AE is set to 1, the values in the DMA source address
register (SAR), DMA destination address register (DAR), and DMA transfer count register
(DMATCR) indicate the addresses for the DMA transfer to be performed next and the
remaining number of transfers. The TE bit is not set in this case. Before resuming transfer, it is
necessary to make a new setting for the channel that caused the address error, then write 0 to
the AE bit after first reading 1 from it. Acceptance of external requests is suspended while AE
is set to 1, so a DMA transfer request must be reissued when resuming transfer. Acceptance of
internal requests is also suspended, so when resuming transfer, the DMA transfer request
enable bit for the relevant on-chip peripheral module must be cleared to 0 before the new
setting is made.
Rev. 3.0, 04/02, page 518 of 1064
2. End of transfer when NMIF = 1 in DMAOR
If the NMIF bit in DMAOR is set to 1 due to an NMI interrupt, DMA transfer is suspended on
all channels in accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is
passed to the CPU. Therefore, when NMIF is set to 1, the values in the DMA source address
register (SAR), DMA destination address register (DAR), and DMA transfer count register
(DMATCR) indicate the addresses for the DMA transfer to be performed next and the
remaining number of transfers. The TE bit is not set in this case. Before resuming transfer after
NMI interrupt handling is completed, 0 must be written to the NMIF bit after first reading 1
from it. As in the case of AE being set to 1, acceptance of external requests is suspended while
NMIF is set to 1, so a DMA transfer request must be reissued when resuming transfer.
Acceptance of internal requests is also suspended, so when resuming transfer, the DMA
transfer request enable bit for the relevant on-chip peripheral module must be cleared to 0
before the new setting is made.
3. End of transfer when DME = 0 in DMAOR
If the DME bit in DMAOR is cleared to 0, DMA transfer is suspended on all channels in
accordance with the conditions in 1, 2, 3, and 4 in section 14.3.6, and the bus is passed to the
CPU. The TE bit is not set in this case. When DME is cleared to 0, the values in the DMA
source address register (SAR), DMA destination address register (DAR), and DMA transfer
count register (DMATCR) indicate the addresses for the DMA transfer to be performed next
and the remaining number of transfers. When resuming transfer, DME must be set to 1.
Operation will then be resumed from the next transfer.
Rev. 3.0, 04/02, page 519 of 1064
14.4
Examples of Use
14.4.1
Examples of Transfer between External Memory and an External Device with
DACK
Examples of transfer of data in external memory to an external device with DACK using DMAC
channel 1 are considered here.
Table 14.10 shows the transfer conditions and the corresponding register settings.
Table 14.10 Conditions for Transfer between External Memory and an External Device
with DACK, and Corresponding Register Settings
Transfer Conditions
Register
Set Value
Transfer source: external memory
SAR1
H'0C000000
Transfer source: external device with DACK
DAR1
(Accessed by DACK)
Number of transfers: 32
DMATCR1
H'00000020
Transfer source address: decremented
CHCR1
H'000022A5
Transfer destination address: (setting invalid)
Transfer request source: external pin (
'5(4
)
edge detection
Bus mode: burst
Transfer unit: word
No interrupt request at end of transfer
Channel priority order: 2 > 0 > 1 > 3
DMAOR
H'00000201
Rev. 3.0, 04/02, page 520 of 1064
14.5
On-Demand Data Transfer Mode (DDT Mode)
14.5.1
Operation
Setting the DDT bit to 1 in DMAOR causes a transition to on-demand data transfer mode (DDT
mode). In DDT mode, it is possible to transfer to channel 0 to 3 via the data bus and DDT module,
and simultaneously issue a transfer request, using the
'%5(4, %$9/, 75, 7'$&., ID [1:0],
DTR.ID, and DTR.MD signals between an external device and the DMAC. Figure 14.23 shows a
block diagram of the DMAC, DDT, BSC, and an external device (with
'%5(4, %$9/, 75,
7'$&., ID [1:0], DTR.ID, and DTR.MD pins).
DMAC
DDT
Memory
External
device (with
,
,
,
,
and ID [1:0])
DTR
BSC
SAR0
DAR0
DMATCR0
CHCR0
DREQ03
Data buffer
bavl
ID[1:0]
ddtmode
Data
buffer
Address bus
ddtmode tdack id[1:0]
Data bus
Request
controller
FIFO or
memory
Figure 14.23 On-Demand Transfer Mode Block Diagram
After first making the normal DMA transfer settings for DMAC channels 0 to 3 using the CPU, a
transfer request is output from an external device using the
'%5(4, %$9/, 75, 7'$&.,
DTR.ID [1:0], and DTR.MD [1:0] signals (handshake protocol using the data bus). A transfer
request can also be issued simply by asserting
75, without using the external bus (handshake
protocol without use of the data bus). For channel 2, after making the DMA transfer settings in the
normal way, a transfer request can be issued directly from an external device (with
'%5(4,
%$9/, 75, 7'$&., DTR.ID [1:0], and DTR.MD [1:0] pins) by asserting '%5(4 and 75
simultaneously .
In DDT mode, there is a choice of five modes for performing DMA transfer.
Rev. 3.0, 04/02, page 521 of 1064
1. Normal data transfer mode (channel 0)
%$9/ (the data bus available signal) is asserted in response to '%5(4 (the data bus request
signal) from an external device. Two CKIO-synchronous cycles after
%$9/ is asserted, the
external data bus drives the data transfer setting command (DTR command) in synchronization
with
75 (the transfer request signal). The initial settings are then made in the DMAC channel
0 control register, and the DMA transfer is processed.
2. Normal data transfer mode (except channel 1 to channel 3)
In this mode, the data transfer settings are made in the DMAC from the CPU, and DMA
transfer requests only are performed from the external device.
As in 1 above,
'%5(4 is asserted from the external device and the external bus is secured,
then the DTR command is driven.
The transfer request channel can be specified by means of the two ID bits in the DTR
command.
3. Handshake protocol using the data bus (valid for channel 0 only)
This mode is only valid for channel 0.
After the initial settings have been made in the DMAC channel 0 control register, the DDT
module asserts a data transfer request for the DMAC by setting the DTR command ID = 00,
MD = 00, and SZ
101, 110 and driving the DTR command.
4. Handshake protocol without use of the data bus
The DDT module includes a function for recording the previously asserted request channel. By
using this function, it is possible to assert a transfer request for the channel for which a request
was asserted immediately before, by asserting
75 only from an external device after a transfer
request has once been made to the channel for which an initial setting has been made in the
DMAC control register (DTR command and data transfer setting by the CPU in the DMAC).
5. Direct data transfer mode (valid for channel 2 only)
A data transfer request can be asserted for channel 2 by asserting
'%5(4 and 75
simultaneously from an external device after the initial settings have been made in the DMAC
channel 2 control register.
Rev. 3.0, 04/02, page 522 of 1064
14.5.2
Pins in DDT Mode
Figure 14.24 shows the system configuration in DDT mode.
Synchronous
DRAM
/
/DRAK0
/
/DACK0
ID1, ID0/DRAK1, DACK1
CLK
D31D0 = DTR
External device
SH7751 Series
A25A0, RAS, CAS, WE, DQMn, CKE
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
#"
#": Data bus release request signal for transmitting the data transfer request format (DTR
format) or a DMA request from an external device to the DMAC
If there is a wait for release of the data bus, an external device can have the data bus released
by asserting
'%5(4. When '%5(4 is accepted, the BSC asserts %$9/.
%$9/
%$9/: Data bus D31D0 release signal
Assertion of
%$9/ means that the data bus will be released two cycles later.
75
75: Transfer request signal
Assertion of
75 has the following different meanings.
In normal data transfer mode (except channel 0),
75 is asserted, and at the same time the
DTR format is output, two cycles after
%$9/ is asserted.
In the case of the handshake protocol without use of the data bus, asserting
75 enables a
transfer request to be issued for the channel for which a transfer request was made
immediately before. This function can be used only when
%$9/ is not asserted two cycles
earlier.
In the case of direct data transfer mode (valid only for channel 2), a direct transfer request
can be made to channel 2 by asserting
'%5(4 and 75 simultaneously.
Rev. 3.0, 04/02, page 523 of 1064
7'$&.
7'$&.: Reply strobe signal for external device from DMAC
The assertion timing is the same as the DACKn assertion timing for each memory interface.
However, note that
7'$&. is an active-low signal.
ID1, ID0: Channel number notification signals
00: Channel 0
01: Channel 1
10: Channel 2
11: Channel 3
Data Transfer Request Format (DTR)
SZ
ID
MD
(Reserved)
31
28 27
25
23
0
(Reserved)
Figure 14.25 Data Transfer Request Format
The data transfer request format (DTR format) consists of 32 bits. In the case of normal data
transfer mode (channel 0, except channel 0) and the handshake protocol using the data bus,
channel number and transfer request mode are specified. Connection is made to D31 through D0.
Bits 31 to 29: Transmit Size (SZ2SZ0)
000: Handshake protocol (data bus used)
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Request queue clear specification
111: Transfer end specification
Bit 28: Reserved
Bits 27 and 26: Channel Number (ID1, ID0)
00: Channel 0
01: Channel 1
10: Channel 2
11: Channel 3
Rev. 3.0, 04/02, page 524 of 1064
Bits 25 and 24: Transfer Request Mode (MD1, MD0)
00: Handshake protocol (data bus used)
01: Setting prohibited
10: Request queue clear specification
11: Setting prohibited
Bits 23 to 0: Reserved
Notes: 1. In channels 1 to 3, only the ID field is valid.
2. In channel 0, the MD field is valid. Set MD = 00. If 01, 10, or 11 is set, the DMAC
will halt with an address error.
3. In edge-sense burst mode, DMA transfer is executed continuously. In level-sense burst
mode and cycle steal mode, a handshake protocol is used to transfer each unit of data.
4. When specifying data transfer requests using a handshake protocol for channel 0, set
ID = 00, MD = 00, and SZ
101, 110 for the DTR format. Use the MOV instruction
to make settings in the DMAC's SAR0, DAR0, CHCR0, and DMATCR0 registers.
Either single address mode or dual address mode can be used as the transfer mode.
Select one of the following settings: CHCR0.RS3--RS0 = 0000, 0010, 0011.
Operation is not guaranteed if the DTR format data settings are DTR.ID = 00,
DTR.MD = 00, and DTR.SZ
101, 110.
Usable SZ, ID, and MD Combination in DDT Mode
Table 14.11 shows the usable combination of SZ, ID, and MD in DDT mode of the SH7751.
Table 14.11 Usable SZ, ID, and MD Combination in DDT Mode
SZ [2:0]
ID [1:0]
MD [1:0]
Function
000
00
00
Request for transfer to
channel 0
110
00
10
Request queue clear
111
00
00
Transfer end
X
01
X
Request for transfer to
channel 1
X
10
X
Request for transfer to
channel 2
X
11
X
Request for transfer to
channel 3
Notes: Don't set values other than those shown in the above table.
X: Don't care
Rev. 3.0, 04/02, page 525 of 1064
14.5.3
Transfer Request Acceptance on Each Channel
On channel 0, a DMA data transfer request can be made by means of the DTR format. No further
transfer requests are accepted between DTR format acceptance and the end of the data transfer.
On channels 1 to 3, output a transfer request from an external device by means of the DTR format
(ID = 01, 10, or 11) after making DMAC control register settings in the same way as in normal
DMA mode. Each of channels 1 to 3 has a request queue that can accept up to four transfer
requests. When a request queue is full, the fifth and subsequent transfer requests will be ignored,
and so transfer requests must not be output. When CHCR.TE = 1 when a transfer request remains
in the request queue and a transfer is completed, the request queue retains it. When another
transfer request is sent at that time, the transfer request is added to the request queue if the request
queue is vacant.
Rev. 3.0, 04/02, page 526 of 1064
Tb
Tc
Td
Te
Tf
Th
Ta
Tg
Tk
Tj
Ti
Tm
Tn
To
Tp
Tq
Ts
Tl
Tr
Tv
Tu
Tt
Tw
tRWD
tDBQS
CKIO
BANK
Precharge-sel
Addr
DQMn
ID1-ID0
D31-D0 (READ)
RD/
tAD
tCSD
tAD
tCSD
Row
Row
Row
tAD
c1
H/L
tRASD
tDQMD
tCASD2
tCASD2
tRDS
tBSD
tBSD
c1
c2
c4
c3
tDQMD
tRDH
DMAC Channel
tIDD
tTDAD
tTDAD
tIDD
tTRS
tTRH
tBAVD
[2CKIO cycles - tDTRS] (= 18ns: 100MHz)
DTR= 1CKIO cycle (= 10ns: 100MHz)
tDTRS
tDTRH
tDBQH
tBAVD
tRASD
Figure 14.26 Single Address Mode/Synchronous DRAM
External Device Longword
Transfer SDRAM Auto-Precharge Read Bus Cycle, Burst (RCD=1, CAS latency=3, TPC=3)
Rev. 3.0, 04/02, page 527 of 1064
Tb
Tc
Td
Te
Tf
Th
Ta
Tg
Tk
Tj
Ti
Tm
Tn
To
Tp
Tq
Ts
Tl
Tr
Tv
Tu
Tt
Tw
CKIO
BANK
Precharge-sel
Addr
DQMn
ID1-ID0
D31-D0 (READ)
RD/
tAD
tCSD
tDQMD
c1
tBSD
tWDD
[2CKIO cycles - tDTRS] (= 18ns: 100MHz)
DTR= 1CKIO cycle (= 10ns: 100MHz)
tBSD
tWDD
tRWD
tCSD
Row
Row
tRASD
Row
tAD
H/L
c1
tAD
tRASD
tCASD2
tCASD2
tRWD
tDQMD
c4
c3
c2
tDTRS
tDTRH
tDBQS
tDBQH
tBAVD
tBAVD
tTRS
tTRH
tTDAD
DMAC Channel
tIDD
tIDD
tTDAD
Figure 14.27 Single Address Mode/External Device
Synchronous DRAM Longword
Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst (RCD=1, TRWL=2, TPC=1)
Rev. 3.0, 04/02, page 528 of 1064
Tb
Tc
Td
Te
Tf
Th
Ta
Tg
Tk
Tj
Ti
Tm
Tn
To
Tp
Tq
Ts
Tl
Tr
Tt
tRWD
tDBQS
CKIO
BANK
Precharge-sel
Addr
DQMn
ID1-ID0
D31-D0 (READ)
RD/
tAD
tCSD
tAD
tCSD
Row
Row
Row
tAD
c1
H/L
tRASD
tDQMD
tCASD2
tCASD2
tRDS
tBSD
tBSD
c1
c2
c4
c3
tDQMD
tRDH
DMAC Channel
tTDAD
tTRS
tTRH
tBAVD
[2CKIO cycles - tDTRS] (= 18ns: 100MHz)
DTR= 1CKIO cycle (= 10ns: 100MHz)
tDTRS
tDTRH
tDBQH
tBAVD
tRASD
tTDAD
DMAC Channel
Figure 14.28 Dual Address Mode/Synchronous DRAM
SRAM Longword Transfer
Rev. 3.0, 04/02, page 529 of 1064
CKIO
ID1, ID0
TDACK
RAS,
CAS, WE
D31D0
A25A0
TR
BAVL
DBREQ
RA
CA
D0
D1
D2
D3
RD
BA
DTR
00
Figure 14.29 Single Address Mode/Burst Mode/External Bus
External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer
RA
CA
WT
BA
D0
D1
D2
D3
D4
D5
DTR
CKIO
ID1, ID0
TDACK
RAS,
CAS, WE
D31D0
A25A0
TR
BAVL
DBREQ
Figure 14.30 Single Address Mode/Burst Mode/External Device
External Bus 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer
Rev. 3.0, 04/02, page 530 of 1064
RA
CA
CA
CA
D1
D0
DTR
BA
RD
RD
RD
00
00
CKIO
ID1, ID0
TDACK
RAS,
CAS, WE
D31D0
A25A0
TR
BAVL
DBREQ
DQMn
Figure 14.31 Single Address Mode/Burst Mode/External Bus
External Device 32-Bit
Transfer/Channel 0 On-Demand Data Transfer
Rev. 3.0, 04/02, page 531 of 1064
RA
CA
CA
D1
D0
DTR
BA
WT
WT
CKIO
ID1, ID0
TDACK
RAS,
CAS, WE
D31D0
A25A0
TR
BAVL
DBREQ
DQMn
Figure 14.32 Single Address Mode/Burst Mode/External Device
External Bus 32-Bit
Transfer/Channel 0 On-Demand Data Transfer
Rev. 3.0, 04/02, page 532 of 1064
CA
CA
D0
D1
DTR
MD = 00
D0
D1
D2
D3
WT
WT
DTR
MD = 00
Start of data transfer
Next transfer request
CKIO
ID1, ID0
TDACK
D31D0
A25A0
TR
BAVL
DBREQ
CMD
Figure 14.33 Handshake Protocol Using Data Bus
(Channel 0 On-Demand Data Transfer)
Rev. 3.0, 04/02, page 533 of 1064
CA
CA
D0
D1
D2
D3
D0
D1
D2
D3
WT
WT
MD = 00
Start of data transfer
Next transfer request
CKIO
ID1, ID0
TDACK
DTR
D31D0
A25A0
TR
BAVL
DBREQ
CMD
Figure 14.34 Handshake Protocol without Use of Data Bus
(Channel 0 On-Demand Data Transfer)
Rev. 3.0, 04/02, page 534 of 1064
CKIO
DBREQ
BAVL
TR
A25A0
D31D0
RAS, CAS,
WE
D0
RA
CA
D1
D2
D3
BA
RD
Figure 14.35 Read from Synchronous DRAM Precharge Bank
CKIO
DBREQ
BAVL
TR
A25A0
D31D0
RAS, CAS,
WE
RA
CA
D0
D1
D2
D3
PCH
BA
RD
Transfer requests can be accepted
Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss)
Rev. 3.0, 04/02, page 535 of 1064
CKIO
DBREQ
BAVL
TR
A25A0
D31D0
RAS, CAS,
WE
CA
RD
D0
D1
D2
D3
Figure 14.37 Read from Synchronous DRAM (Row Hit)
CKIO
DBREQ
BAVL
TR
A25A0
D31D0
RAS, CAS,
WE
RA
CA
BA
WT
D0
D1
D2
D3
Figure 14.38 Write to Synchronous DRAM Precharge Bank
Rev. 3.0, 04/02, page 536 of 1064
CKIO
DBREQ
BAVL
TR
A25A0
D31D0
RAS, CAS,
WE
RA
CA
D0
D1
D2
D3
PCH
BA
WT
Transfer requests can be accepted
Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss)
CKIO
DBREQ
BAVL
TR
A25A0
D31D0
RAS, CAS,
WE
D0
CA
D1
D2
D3
WT
Figure 14.40 Write to Synchronous DRAM (Row Hit)
Rev. 3.0, 04/02, page 537 of 1064
00
D0
D1
D2
RA
CA
RD
BA
DTR
CKIO
ID1, ID0
TDACK
RAS,
CAS, WE
D31D0
A25A0
TR
BAVL
DBREQ
Figure 14.41 Single Address Mode/Burst Mode/External Bus
External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer
Rev. 3.0, 04/02, page 538 of 1064
DMA Operation Register (DMAOR)
31
15
9
8
2
1 0
DDT
PR[1:0]
AE
NMIF
DME
DDT: 0: Normal DMA mode
1: On-demand data transfer mode
Figure 14.42 DDT Mode Setting
DTR
CA
CA
D0
D1
D2
D3
D0
D1
D2
D3 D1
D2
D3
WT
WT
CKIO
ID1, ID0
TDACK
CMD
D31D0
A25A0
TR
BAVL
DBREQ
Start of data transfer
No DMA request sampling
Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/
External Device
External Bus Data Transfer
Rev. 3.0, 04/02, page 539 of 1064
CA
CA
D0
D1
D2 D3
D0 D1
D2
D3
DTR
RD
RD
Start of data transfer
Wait for next DMA request
CKIO
ID1, ID0
TDACK
CMD
D31D0
A25A0
TR
BAVL
DBREQ
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/
External Bus
External Device Data Transfer
CA
CA
CA
RD
RD
RD
DTR
D0
D3
D2
CKIO
ID1, ID0
TDACK
DQMn
D31D0
A25A0
TR
BAVL
DBREQ
CMD
Idle cycle
Idle cycle
Idle cycle
Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Bus
External Device Data Transfer
Rev. 3.0, 04/02, page 540 of 1064
CA
CA
CA
WT
DTR
D0
D3
D1
CKIO
ID1, ID0
TDACK
DQMn
D31D0
A25A0
TR
BAVL
DBREQ
CMD
Idle cycle
Idle cycle
Idle cycle
WT
WT
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device
External Bus Data Transfer
Rev. 3.0, 04/02, page 541 of 1064
DTR
ID = 1, 2, or 3
RA
CA
BA
RD
D0
D1
D2
D3
CKIO
ID1, ID0
TDACK
RAS,
CAS, WE
D31D0
A25A0
TR
BAVL
DBREQ
01 or 10 or 11
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Request to Channels 13 Using Data Bus
Rev. 3.0, 04/02, page 542 of 1064
RA
CA
BA
RD
10
D0
D1
D2
D3
CKIO
ID1, ID0
TDACK
RAS,
CAS, WE
D31D0
A25A0
TR
BAVL
DBREQ
No DTR cycle, so requests can be made at any time
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/
External Bus
External Device Data Transfer/
Direct Data Transfer Request to Channel 2 without Using Data Bus
Rev. 3.0, 04/02, page 543 of 1064
CKIO
CA
CA
RA
BA
RD
RD
RD
RD
ID1, ID0
D31 D0
A25 A0
CA
CA
D0
D1
D2
D3
RAS, CAS,
WE
D0
D1
D2
D3
D0
D1
D2
3rd
4th
1st 2nd
5th
Four requests can be queued
Handshaking is necessary
to send additional requests
No more requests
Must be ignored
(no request transmitted)
Figure 14.49 Single Address Mode/Burst Mode/External Bus
External Device Data
Transfer/Direct Data Transfer Request to Channel 2
Rev. 3.0, 04/02, page 544 of 1064
CKIO
CA
CA
RA
BA
WT
WT
WT
ID1, ID0
D31D0
A25A0
CA
CA
D0
D1
D2
D3
RAS, CAS,
WE
D0
D1
D2
D3
3rd
4th
5th
Handshaking is necessary
to send additional requests
Must be ignored
(no request transmitted)
D0
D1
D2
D3
WT
Four requests can be queued
1st 2nd
Figure 14.50 Single Address Mode/Burst Mode/External Device
External Bus Data
Transfer/Direct Data Transfer Request to Channel 2
Rev. 3.0, 04/02, page 545 of 1064
CKIO
CA
CA
CA
CA
RD
RD
RD
RD
ID1, ID0
D31D0
A25A0
RAS, CAS,
WE
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
3rd
4th
5th
Handshaking is necessary
to send additional requests
Must be ignored
(no request transmitted)
Four requests can be queued
1st 2nd
Figure 14.51 Single Address Mode/Burst Mode/External Bus
External Device Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2
Rev. 3.0, 04/02, page 546 of 1064
CA
CA
WT
WT
WT
ID1, ID0
D31D0
A25A0
CA
CA
D0
D1
D2
D3
RAS, CAS,
WE
D0
D1
D2
D3
3rd
4th
5th
Handshaking is necessary
to send additional requests
Must be ignored
(no request transmitted)
D0
D1
D2
D3
WT
Four requests can be queued
1st 2nd
Figure 14.52 Single Address Mode/Burst Mode/External Device
External Bus Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2
Rev. 3.0, 04/02, page 547 of 1064
14.5.4
Notes on Use of DDT Module
1. Normal data transfer mode (channel 0)
Set DTR.ID = 00 and DTR.MD = 00. If a setting of MD = 01, 10, or 11 is made, the DMAC
will halt with an address error. In this case, the error can be cleared by reading DMAOR.AE =
1, then writing AE = 0.
2. Normal data transfer mode (except channel 1 to channel 3)
If a setting of DTR.ID = 01, 10, or 11 is made, DTR.MD will be ignored.
3. Handshake protocol using the data bus (valid on channel 0 only)
a. The handshake protocol using the data bus can be executed only on channel 0. (The DTR
format must be set to DTR.ID = 00, DTR.MD = 00, and DTR.SZ
101, 110. Operation is
not guaranteed if the DTR format data settings are DTR.ID = 00, DTR. MD = 00, and
DTR.SZ
101, 110.)
b. If, during execution of the handshake protocol using the data bus for channel 0, a request is
input for one of channels 1 to 3, and after that DMA transfer is executed settings of
DTR.ID = 00, DTR.MD = 00, and DTR.SZ
101, 110 are input in the handshake protocol
using the data bus, a transfer request will be asserted for channel 0.
c. If
75 only is asserted by means of the handshake protocol without use of the data bus and a
DMA transfer request is input when channel 0 DMA transfer has ended and CHCR0.TE =
1, the DMAC will freeze. Before issuing a DMA transfer request, the TE flag must be
cleared by writing CHCR0.TE = 0 after reading CHCR0.TE = 1.
4. Handshake protocol without use of the data bus
a. With the handshake protocol without use of the data bus, a DMA transfer request can be
input to the DMAC again for the channel for which transfer was requested immediately
before by asserting
75 only.
b. When using the handshake protocol without use of the data bus, first make the necessary
settings in the DMAC control registers.
c. When not using the handshake protocol without use of the data bus, if
75 only is asserted
without outputting DTR, a request will be issued for the channel for which DMA transfer
was requested immediately before. Also, if the first DMA transfer request after a power-on
reset is input by asserting
75 only, it will be ignored and the DMAC will not operate.
5. Direct data transfer mode (valid on channel 2 only)
a. If a DMA transfer request for channel 2 is input by simultaneous assertion of
'%5(4 and
75 during DMA transfer execution with the handshake protocol without use of the data
bus, it will be accepted if there is space in the DDT channel 2 request queue.
b. In direct data transfer mode (with
'%5(4 and 75 asserted simultaneously), '%5(4 is not
interpreted as a bus arbitration signal, and therefore the
%$9/ signal is never asserted.
6. Request queue transfer request acceptance
a. The DDT has four request queues for each of channels 1 to 3. When these request queues
are full, a DMA transfer request from an external device will be ignored.
Rev. 3.0, 04/02, page 548 of 1064
b. If a DMA transfer request for channel 0 is input during execution of a channel 0 DMA bus
cycle, the DDT will ignore that request. Confirm that channel 0 DMA transfer has finished
(burst mode) or that a DMA bus cycle is not in progress (cycle steal mode).
7. DTR format
a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows.
When DTR.ID= 00
MD = 00, SZ
101, 110: Handshake protocol using the data bus
MD
00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request)
MD = 10, SZ = 110: DDT request queue clear
When DTR.ID
00
Transfer request to channels 1--3 (items other than ID ignored)
8. Data transfer end request
a. A data transfer end request (DTR.ID = 00, MD
00, SZ = 111) cannot be accepted during
channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0,
transfer cannot be ended midway.
b. When a transfer end request (DTR.ID = 00, MD
00, SZ = 111) is accepted, the values set
in CHCR0.SAR0, DAR0, and DMATCR0 are retained. In this case, execution cannot be
restarted from an external device. To restart execution, set CHCR0.DE = 1 with an MOV
instruction.
9. Request queue clearance
a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in
normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are
all cleared. All external requests held on the DMAC side are also cleared.
b. In case 3-c, the DMAC freeze state can be cleared.
c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are
accepted by the DDT in case 11, the DMAC freeze state can be cleared.
10.
'%5(4 assertion
a. After
'%5(4 is asserted, do not assert '%5(4 again until %$9/ is asserted, as this will
result in a discrepancy between the number of
'%5(4 and %$9/ assertions.
b. The
%$9/ assertion period due to '%5(4 assertion is one cycle.
If a row address miss occurs in a read or write in the non-precharged bank during
synchronous DRAM access,
%$9/ is asserted for a number of cycles in accordance with
the RAS precharge interval set in BSC.MCR.TCP.
c. It takes one cycle for
'%5(4 to be accepted by the DMAC after being asserted by an
external device. If a row address miss occurs at this time in a read or write in the non-
precharged bank during synchronous DRAM access, and
%$9/ is asserted, the '%5(4
signal asserted by the external device is ignored. Therefore,
%$9/ is not asserted again
due to this signal.
Rev. 3.0, 04/02, page 549 of 1064
11. Clearing DDT mode
Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT
bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode,
the DMAC will freeze.
This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT
mode.
12. Confirming DMA transfer requests and number of transfers executed
The channel associated with a DMA bus cycle being executed in response to a DMA transfer
request can be confirmed by determining the level of external pins ID1 and ID0 at the rising
edge of the CKIO clock while
7'$&. is asserted.
(ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3)
Rev. 3.0, 04/02, page 550 of 1064
14.6
Configuration of the DMAC (SH7751R)
14.6.1
Block Diagram of the DMAC
Figure 14.53 is a block diagram of the DMAC in the SH7751R.
dreq07
Request
8
dmaqueclr0-7
queclr07
SAR0, DAR0, DMATCR0,
CHCR0 only
DDTMODE
BAVL
48 bits
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Request controller
DTR command buffer
DDT module
DDTD
External bus
tdack
id[2:0]
ID[1:0]
D[31:0]
DBREQ
/
SAR07
DAR07
DMATCR07
CHCR07
DMAOR
Bus
interface
P
e
r
ipher
al b
u
s
Inter
nal b
u
s
DMAC module
Count control
Registr control
Activation
control
Request
priority
control
32B data
buffer
Bus state
controller
On-chip
peripheral
module
Exter
nal address/on-chip
per
ipher
al module address
TMU
SCI, SCIF
DACK0, DACK1
DRAK0, DRAK1
,
DMAOR:
SAR:
DAR:
DMATCR:
CHCR:
DMAC operation register
DMAC source address register
DMAC destination address register
DMAC transfer count register
DMAC channel control register
Figure 14.53 Block Diagram of the DMAC
Rev. 3.0, 04/02, page 551 of 1064
14.6.2
Pin Configuration (SH7751R)
Tables 14.12 and 14.13 show the pin configuration of the DMAC.
Table 14.12 DMAC Pins
Channel
Pin Name
Abbreviation
I/O
Function
0
DMA transfer
request
#"
Input
DMA transfer request input from
external device to channel 0
DREQ acceptance
confirmation
DRAK0
Output
Acceptance of request for DMA
transfer from channel 0 to external
device
Notification to external device of start
of execution
DMA transfer end
notification
DACK0
Output
Strobe output to external device of
DMA transfer request from channel 0
to external device
1
DMA transfer
request
#"
Input
DMA transfer request input from
external device to channel 1
DREQ acceptance
confirmation
DRAK1
Output
Acceptance of request for DMA
transfer from channel 1 to external
device
Notification to external device of start
of execution
DMA transfer end
notification
DACK1
Output
Strobe output to external device of
DMA transfer request from channel 1
to external device
Rev. 3.0, 04/02, page 552 of 1064
Table 14.13 DMAC Pins in DDT Mode
Pin Name
Abbreviation
I/O
Function
Data bus request
#"
(
#"
)
Input
Data bus release request from external
device for DTR format input
Data bus available
%$9/
/
,'
(DRAK0)
Output
Data bus release notification
Data bus can be used 2 cycles after
%$9/
is asserted
Notification of channel number to
external device at same time as
7'$&.
output
Transfer request signal
75
(
'5(4
)
Input
If asserted 2 cycles after
%$9/
assertion, DTR format is sent
Only
75
asserted: DMA request
'%5(4
and
75
asserted
simultaneously: Direct request to
channel 2
DMAC strobe
7'$&.
(DACK0)
Output
Reply strobe signal for external device
from DMAC
Channel number
notification
ID[1:0]
(DRAK1, DACK1)
Output
Notification of channel number to
external device at same time as
7'$&.
output
(ID [1] = DRAK1, ID [0] = DACK1)
Requests for DMA transfer from external devices are normally accepted only on channel 0
(
'5(4) and channel 1 ('5(4). In DDT mode, the %$9/ pin functions as both the data-bus-
available pin and channel-number-notification (
,') pin.
14.6.3
Register Configuration (SH7751R)
Table 14.14 shows the configuration of the DMAC's registers. The DMAC of the SH7751R has a
total of 33 registers: four registers are assigned to each channel, and there is a control register for
the overall control of the DMAC.
Rev. 3.0, 04/02, page 553 of 1064
Table 14.14 Register Configuration
Chan-
nel
Name
Abbre-
viation
Read/
Write
Initial Value P4 Address
Area 7
Address
Access
Size
DMA source
address register 0
SAR0
R/W
Undefined
H'FFA00000 H'1FA00000 32
DMA destination
address register 0
DAR0
R/W
Undefined
H'FFA00004 H'1FA00004 32
DMA transfer
count register 0
DMATCR0 R/W
Undefined
H'FFA00008 H'1FA00008 32
0
DMA channel
control register 0
CHCR0
R/W*
H'00000000 H'FFA0000C H'1FA0000C 32
DMA source
address register 1
SAR1
R/W
Undefined
H'FFA00010 H'1FA00010 32
DMA destination
address register 1
DAR1
R/W
Undefined
H'FFA00014 H'1FA00014 32
DMA transfer
count register 1
DMATCR1 R/W
Undefined
H'FFA00018 H'1FA00018 32
1
DMA channel
control register 1
CHCR1
R/W*
H'00000000 H'FFA0001C H'1FA0001C 32
DMA source
address register 2
SAR2
R/W
Undefined
H'FFA00020 H'1FA00020 32
DMA destination
address register 2
DAR2
R/W
Undefined
H'FFA00024 H'1FA00024 32
DMA transfer
count register 2
DMATCR2 R/W
Undefined
H'FFA00028 H'1FA00028 32
2
DMA channel
control register 2
CHCR2
R/W*
H'00000000 H'FFA0002C H'1FA0002C 32
DMA source
address register 3
SAR3
R/W
Undefined
H'FFA00030 H'1FA00030 32
DMA destination
address register 3
DAR3
R/W
Undefined
H'FFA00034 H'1FA00034 32
DMA transfer
count register 3
DMATCR3 R/W
Undefined
H'FFA00038 H'1FA00038 32
3
DMA channel
control register 3
CHCR3
R/W*
H'00000000 H'FFA0003C H'1FA0003C 32
Com-
mon
DMA operation
register
DMAOR
R/W*
H'00000000 H'FFA00040 H'1FA00040 32
Rev. 3.0, 04/02, page 554 of 1064
Table 14.14 Register Configuration (cont)
Chan-
nel
Name
Abbre-
viation
Read/
Write
Initial Value P4 Address
Area 7
Address
Access
Size
DMA source
address register 4
SAR4
R/W
Undefined
H'FFA00050 H'1FA00050 32
DMA destination
address register 4
DAR4
R/W
Undefined
H'FFA00054 H'1FA00054 32
DMA transfer
count register 4
DMATCR4 R/W
Undefined
H'FFA00058 H'1FA00058 32
4
DMA channel
control register 4
CHCR4
R/W*
H'00000000 H'FFA0005C H'1FA0005C 32
DMA source
address register 5
SAR5
R/W
Undefined
H'FFA00060 H'1FA00060 32
DMA destination
address register 5
DAR5
R/W
Undefined
H'FFA00064 H'1FA00064 32
DMA transfer
count register 5
DMATCR5 R/W
Undefined
H'FFA00068 H'1FA00068 32
5
DMA channel
control register 5
CHCR5
R/W*
H'00000000 H'FFA0006C H'1FA0006C 32
DMA source
address register 6
SAR6
R/W
Undefined
H'FFA00070 H'1FA00070 32
DMA destination
address register 6
DAR6
R/W
Undefined
H'FFA00074 H'1FA00074 32
DMA transfer
count register 6
DMATCR6 R/W
Undefined
H'FFA00078 H'1FA00078 32
6
DMA channel
control register 6
CHCR6
R/W*
H'00000000 H'FFA0007C H'1FA0007C 32
DMA source
address register 7
SAR7
R/W
Undefined
H'FFA00080 H'1FA00080 32
DMA destination
address register 7
DAR7
R/W
Undefined
H'FFA00084 H'1FA00084 32
DMA transfer
count register 7
DMATCR7 R/W
Undefined
H'FFA00088 H'1FA00088 32
7
DMA channel
control register 7
CHCR7
R/W*
H'00000000 H'FFA0008C H'1FA0008C 32
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
* Bit 1 of CHCR0CHCR3 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
Rev. 3.0, 04/02, page 555 of 1064
14.7
Register Descriptions (SH7751R)
14.7.1
DMA Source Address Registers 07 (SAR0SAR7)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value:
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA source address registers 07 (SAR0SAR7) are 32-bit readable/writable registers that
specify the source address for a DMA transfer. The functions of these registers are the same as on
the SH7751. For more information, see section 14.2.1, DMA Source Address Registers 03
(SAR0SAR3).
14.7.2
DMA Destination Address Registers 07 (DAR0DAR7)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value:
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA destination address registers 07 (DAR0DAR7) are 32-bit readable/writable registers that
specify the destination address for a DMA transfer. The functions of these registers are the same
as on the SH7751. For more information, see section 14.2.2, DMA Destination Address Registers
03 (DAR0DAR3).
Rev. 3.0, 04/02, page 556 of 1064
14.7.3
DMA Transfer Count Registers 07 (DMATCR0DMATCR7)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value:
0
0
0
0
0
0
0
0
--
--
--
--
--
--
--
--
R/W:
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA transfer count registers 07 (DMATCR0DMATCR7) are 32-bit readable/writable registers
that specify the number of transfers in transfer operations for the corresponding channel
(bytecount, word count, longword count, quadword count, or 32-byte count). Functions of these
registers are the same as the transfer-count registers of the SH7751. For more information, see
section 14.2.3, DMA Transfer Count Registers 03 (DMATCR0DMATCR3).
14.7.4
DMA Channel Control Registers 07 (CHCR0CHCR7)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SSA2 SSA1 SSA0 STC DSA2 DSA1 DSA0 DTC
--
--
--
--
DS
RL
AM
AL
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
R
R
R
R
R/W (R/W) R/W (R/W)
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
TM
TS2
TS1
TS0 QCL
IE
TE
DE
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (R/W) R/W (R/W) R/W
DMA channel control registers 07(CHCR0CHCR7) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 3128 and 2724
correspond to the source address and destination address, respectively; these settings are only
valid when the transfer involves the CS5 or CS6 space and the relevant space has been specified as
a PCMCIA-interface space. In other cases, these bits should be cleared to 0. For more information
about the PCMCIA interface, see section 13.3.7, PCMCIA Interface.
No function is assigned to bits 18 and 16 of the CHCR2CHCR7 registers. Writing to these bits of
the CHCR2CHCR7 registers is invalid. If, however, a value is written to these bits, it should
always be 0. These bits are always read as 0.
Rev. 3.0, 04/02, page 557 of 1064
These registers are initialized to H'00000000 by a power-on or manual reset. Their values are
retained in standby, sleep, and deep-sleep modes.
Bits 31 to 29--Source Address Space Attribute Specification (SSA2SSA0): These bits specify
the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to
PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the SSA2-
SSA0 bits in section 14.2.4, DMA Channel Control Registers 03 (CHCR0CHCR3).
Bit 28--Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control
for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and
6 wait cycle control.
For details of the settings, see the description of the STC bit in section 14.2.4,
DMA Channel Control Registers 03 (CHCR0CHCR3).
Bits 27 to 25--Destination Address Space Attribute Specification (DSA2DSA0): These bits
specify the space attribute for PCMCIA access. These bits are only valid in the case of page
mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of
the DSA2DSA0 bits in section 14.2.4, DMA Channel Control Registers 03 (CHCR0CHCR3).
Bit 24--Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait
cycle control for PCMCIA access. This bit selects the wait control register in the BSC that
performs area 5 and 6 wait cycle control. For details of the settings, see the description of the DTC
bit in section 14.2.4, DMA Channel Control Registers 03 (CHCR0CHCR3).
Bits 23 to 20--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 19--
#
#"
" Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the
'5(4 pin used in external request mode.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0CHCR7. For details of the settings, see the description of the DS bit in section 14.2.4,
DMA Channel Control Registers 03 (CHCR0CHCR3).
Bit 18--Request Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of
'5(4) is an active-high or active-low output.
This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For
details of the settings, see the description of the RL bit in section 14.2.4, DMA Channel Control
Registers 03 (CHCR0CHCR3).
Bit 17--Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
Rev. 3.0, 04/02, page 558 of 1064
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR1CHCR7. (DDT mode:
7'$&.) For details of the settings, see the description of the AM
bit in section 14.2.4, DMA Channel Control Registers 03 (CHCR0CHCR3).
Bit 16--Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For
details of the settings, see the description of the AL bit in section 14.2.4, DMA Channel Control
Registers 03 (CHCR0CHCR3).
Bits 15 and 14--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from external memory to an external device in single
address mode. For details of the settings, see the description of the DM1 and DM0 bits in section
14.2.4, DMA Channel Control Registers 03 (CHCR0CHCR3).
Bits 13 and 12--Source Address Mode 1 and 0 (SM1, SM0): These bits specify
incrementing/decrementing of the DMA transfer source address. The specification of these bits is
ignored when data is transferred from an external device to external memory in single address
mode. For details of the settings, see the description of the SM1 and SM0 bits in section 14.2.4,
DMA Channel Control Registers 03 (CHCR0CHCR3).
Bits 11 to 8--Resource Select 3 to 0 (RS3RS0): These bits specify the transfer request source.
For details of the settings, see the description of the RS3RS0 bits in section 14.2.4, DMA
Channel Control Registers 03 (CHCR0CHCR3).
Bit 7--Transmit Mode (TM): Specifies the bus mode for transfer. For details of the settings, see
the description of the TM bit in section 14.2.4, DMA Channel Control Registers 03 (CHCR0
CHCR3).
Bits 6 to 4--Transmit Size 2 to 0 (TS2TS0): These bits specify the transfer data size. For
details of the settings, see the description of the TS2TS0 bits in section 14.2.4, DMA Channel
Control Registers 03 (CHCR0CHCR3).
Bit 3
Request Queue Clear (QCL): Writing a 1 to this bit clears the request queues of the
corresponding channel as well as any external requests that have already been accepted. This bit is
only functional when DMAOR.DDT = 1 and DMAOR.DBL = 1.
Rev. 3.0, 04/02, page 559 of 1064
CHCR Bit 3
QCL
Description
0
This bit is always read as 0.
(Initial value)
Writing a 0 to this bit is invalid.
1
When DMAOR.DBL = 1, writing a 1 to this bit clears the request queues on the
DDT side and any external requests stored in the DMAC. The written value is
not retained.
Bit 2--Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated
after the number of data transfers specified in DMATCR (when TE = 1). For details of the
settings, see the description of the IE bit in section 14.2.4, DMA Channel Control Registers 03
(CHCR0CHCR3).
Bit 1--Transfer End (TE): This bit is set to 1 after the number of transfers specified in
DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or
clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1,
the transfer enabled state is not entered even if the DE bit is set to 1. For details of the settings, see
the description of the TE bit in section 14.2.4, DMA Channel Control Registers 03 (CHCR0
CHCR3).
Bit 0--DMAC Enable (DE): Enables operation of the corresponding channel. For details of the
settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 03
(CHCR0CHCR3).
14.7.5
DMA Operation Register (DMAOR)
Bit:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDT DBL
--
--
--
--
PR1 PR0
--
--
--
--
--
AE
NMIF DME
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W
R
R
R
R
R/W R/W
R
R
R
R
R
R/(W) R/(W) R/W
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
Rev. 3.0, 04/02, page 560 of 1064
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15--On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode. For
details of the settings, see the description of the DDT bit in section 14.2.5, DMA Operation
Register (DMAOR)
Bit 14
Number of DDT-Mode Channels (DBL): Selects the number of channels that are able
to accept external requests in DDT mode.
Bit 14: DBL
Description
0
Four DDT-mode channels
(Initial value)
1
Eight DDT-mode channels
Note: When DMAOR.DBL = 0, channels 4 to 7 do not accept external requests.
When DMAOR.DBL = 1, one channel can be selected from among channels 07 by the
combination of DTR.SZ and DTR.ID in the DTR format (see figure 14.54). Table 14.15 shows the
channel selection by DTR format in the DDT mode.
Table 14.15 Channel Selection by DTR Format (DMAOR.DBL = 1)
DTR.ID[1:0]
DTR.SZ[2:0]
101
DTR.SZ[2:0] = 101
00
CH0
CH4
01
CH1
CH5
10
CH2
CH6
11
CH3
CH7
SZ
ID
MD
COUNT*
Reserved
(Reserved)
31
29 28 27 26 25 24 23
16
0
Note: * These bits are valid when request queue clear is specified (with no transfer count function).
Figure 14.54 DTR Format (Transfer Request Format) (SH7751R)
Rev. 3.0, 04/02, page 561 of 1064
Bits 13 to 10--Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8--Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
DMAOR
Bit 9
DMAOR
Bit 8
PR1
PR0
Description
0
0
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
(Initial value)
0
1
CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1
1
0
CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7
1
1
Round robin mode
Bits 7 to 3--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2--Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be
cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in
section 14.2.5, DMA Operation Register (DMAOR)
Bit 1--NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of
whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all
channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing
0 after reading 1. For details of the settings, see the description of the NMIF bit in section 14.2.5,
DMA Operation Register (DMAOR)
Bit 0--DMAC Master Enable (DME): Enables activation of the entire DMAC. When the DME
bit and the DE bit of the CHCR register for the corresponding channel are set to 1, that channel is
enabled for transfer. If this bit is cleared during data transfer, transfers on all channels are
suspended.
Even if the DME bit has been set, transfer is not enabled when TE is 1 or DE is 0 in CHCR, or
when the NMI or AE bit in DMAOR is 1. For details of the settings, see the description of the
DME bit in section 14.2.5, DMA Operation Register (DMAOR)
Rev. 3.0, 04/02, page 562 of 1064
14.8
Operation (SH7751R)
Operation specific to the SH7751R is described here. For details of operation, see section 14.3,
Operation.
14.8.1
Channel Specification for a Normal DMA Transfer
In normal DMA transfer mode, the DMAC always operates with eight channels, and external
requests are only accepted on channel 0 (
'5(4) and channel 1 ('5(4).
After setting the registers of the channels in use, including CHCR, SAR, DAR, and DMATCR,
DMA transfer is started on receiving a DMA transfer request in the transfer-enabled state (DE = 1,
DME = 1, TE = 0, NMIF = 0, AE = 0), in the order of predetermined priority. The transfer ends
when the transfer-end condition is satisfied. There are three modes for transfer requests: auto-
request, external request, and on-chip peripheral module request. The addressing modes for DMA
transfer are the single-address mode and the dual-address mode. Bus mode is selectable between
burst mode and cycle steal mode.
14.8.2
Channel Specification for DDT-Mode DMA Transfer
For DMA transfer in DDT mode, the DMAOR.DBL setting selects either four or eight channels.
External requests are accepted on channels 03 when DMAOR.DBL = 0, and on channels 07
when DMAOR.DBL = 1. For further information on these settings, see the entry on the DBL bit in
section 14.7.5, DMA Operation Register (DMAOR).
14.8.3
Transfer Channel Notification in DDT Mode
When the DMAC is set up for four-channel external request acceptance in DDT mode
(DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel
that is to be used. For more details, see section 14.5, On-Demand Transfer Mode (DDT Mode).
When the DMAC is set up for eight-channel external request acceptance in DDT mode
(DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of
7'$&. assertion)
assertion of
,' from the %$9/ (bus-release notification) pin are used to notify the external
device of the DMAC channel that is to be used (see table 14.16, Notification of Transfer Channel
in Eight-Channel DDT Mode).
When the DMAC is set up for eight-channel external request acceptance in DDT mode
(DMAOR.DBL = 1), it is important to note that the
%$9/ pin has the two functions as shown in
table 14.17.
Rev. 3.0, 04/02, page 563 of 1064
Table 14.16 Notification of Transfer Channel in Eight-Channel DDT Mode
%$9/
%$9/
/
,'
,'
ID[1:0]
Transfer Channel
00
CH0
01
CH1
10
CH2
1
11
CH3
00
CH4
01
CH5
10
CH6
0
11
CH7
Table 14.17 Function of
%$9/
%$9/
Function of
%$9/
%$9/
7'$&.
= High
Bus available (data-bus enabled)
7'$&.
= Low
Notification of channel number (
,'
)
14.8.4
Clearing Request Queues by DTR Format
In DDT mode, the request queues of any channel can be cleared by using DTR.ID, DTR.MD,
DTR.SZ, and DTR.COUNT [7:4] in a DTR format. This function is only available when
DMAOR.DBL = 1. Table 14.18 shows the DTR format settings for clearing request queues.
Rev. 3.0, 04/02, page 564 of 1064
Table 14.18 DTR Format for Clearing Request Queues
DMAOR.DBL DTR.ID
DTR.MD
DTR.SZ
DTR.COUNT[7:4]
Description
10
Clear the request queues of all channels
(1
7).
Clear the CH0 request-accepted flag
0
00
11
110
*
Setting prohibited
10
*
Clear the request queues of all channels
(1
7).
Clear the CH0 request-accepted flag.
0001
Clear the CH0 request-accepted flag
0010
Clear the CH1 request queues.
0011
Clear the CH2 request queues.
0100
Clear the CH3 request queues.
0101
Clear the CH4 request queues.
0110
Clear the CH5 request queues.
0111
Clear the CH6 request queues.
1
00
11
110
1000
Clear the CH7 request queues.
Note: (SH7751R) DTR.SZ = DTR[31:29], DTR.ID = DTR[27:26], DTR.MD = DTR[25:24],
DTR.COUNT[7:4] = DTR[23:20]
14.8.5
Interrupt-Request Codes
When the number of transfers specified in DMATCR has been finished and the interrupt request is
enabled (CHCR.IE = 1), a transfer-end interrupt request can be sent to the CPU from each
channel. Table 14.19 lists the interrupt-request codes that are associated with these transfer-end
interrupts.
Rev. 3.0, 04/02, page 565 of 1064
CKIO
RA
DTR
CA
D1
D2
RD
BA
00
ID1, ID0
RAS,
CAS, WE
D63D0
A25A0
/
D0
Figure 14.55 Single Address Mode/Burst Mode/External Bus
External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer
Table 14.19 DMAC Interrupt-Request Codes
Source of the Interrupt
Description
INTEVT Code
Priority
DMTE0
CH0 transfer-end interrupt
H'640
High
DMTE1
CH1 transfer-end interrupt
H'660
DMTE2
CH2 transfer-end interrupt
H'680
DMTE3
CH3 transfer-end interrupt
H'6A0
DMTE4
CH4 transfer-end interrupt
H'780
DMTE5
CH5 transfer-end interrupt
H'7A0
DMTE6
CH6 transfer-end interrupt
H'7C0
DMTE7
CH7 transfer-end interrupt
H'7E0
DMAE
Address error interrupt
H'6C0
Low
DMTE4DMTE7: These codes are not used in the SH7751.
Rev. 3.0, 04/02, page 566 of 1064
CKIO
RA
DTR
CA
D1
D2
RD
BA
00
ID1, ID0
RAS,
CAS, WE
D63D0
A25A0
/
D0
Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus
External Device/32-Byte Block Transfer/On-Demand Data Transfer on Channel 4
Rev. 3.0, 04/02, page 567 of 1064
14.9
Usage Notes
1. When modifying SAR0SAR3, DAR0DAR3, DMATCR0DMATCR3, and CHCR0
CHCR3 in the SH7751 or when modifying SAR0SAR7, DAR0DAR7, DMATCR0
DMATCR7, and CHCR0CHCR7 in the SH7751R, first clear the DE bit for the relevant
channel to 0.
2. The NMIF bit in DMAOR is set when an NMI interrupt is input even if the DMAC is not
operating.
Confirmation method when DMA transfer is not executed correctly:
With the SH7751, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in
CHCR0CHCR3, and DMATCR0DMATCR3.
With the SH7751R, read the NMIF, AE, and DME bits in DMAOR, the DE and TE bits in
CHCR0CHCR7, and DMATCR0DMATCR7. If NMIF was set before the transfer, the
DMATCR transfer count will remain at the set value. If NMIF was set during the transfer,
when the DE bit is 1 and the TE bit is 0 in CHCR0CHCR3 in the SH7751 or CHCR0
CHCR7 in the SH7751R, the DMATCR value will indicate the remaining number of transfers.
Also, the next addresses to be accessed can be found by reading SAR0SAR3 and DAR0
DAR3 in the SH7751 or SAR0SAR7 and DAR0DAR7 in the SH7751R. If the AE bit has
been set, an address error has occurred. Check the set values in CHCR, SAR, and DAR.
3. Check that DMA transfer is not in progress before making a transition to the module standby
state, standby mode, or deep sleep mode.
Either check that TE = 1 in the SH7751's CHCR0CHCR3 or in the SH7751R's CHCR0
CHCR7, or clear DME to 0 in DMAOR to terminate DMA transfer. When DME is cleared to 0
in DMAOR, transfer halts at the end of the currently executing DMA bus cycle. Note,
therefore, that transfer may not end immediately, depending on the transfer data size. DMA
operation is not guaranteed if the module standby state, standby mode, or deep sleep mode is
entered without confirming that DMA transfer has ended.
4. Do not specify a DMAC, CCN, BSC, UBC, or PCIC control register as the DMAC transfer
source or destination.
5. When activating the DMAC, make the SAR, DAR, and DMATCR register settings for the
relevant channel before setting DE to 1 in CHCR, or make the register settings with DE
cleared to 0 in CHCR, then set DE to 1. It does not matter whether setting of the DME bit to 1
in DMAOR is carried out first or last. To operate the relevant channel, DME and DE must both
be set to 1. The DMAC may not operate normally if the SAR, DAR, and DMATCR settings
are not made (with the exception of the unused register in single address mode).
6. After the DMATCR count reaches 0 and DMA transfer ends normally, always write 0 to
DMATCR even when executing the maximum number of transfers on the same channel.
7. When falling edge detection is used for external requests, keep the external request pin high
when making DMAC settings.
8. When using the DMAC in single address mode, set an external address as the address. All
channels will halt due to an address error if an on-chip peripheral module address is set.
Rev. 3.0, 04/02, page 568 of 1064
Rev. 3.0, 04/02, page 569 of 1064
Section 15 Serial Communication Interface (SCI)
15.1
Overview
The SH7751 Series is equipped with a single-channel serial communication interface (SCI) and a
single-channel serial communication interface with built-in FIFO registers (SCI with FIFO: SCIF).
The SCI can handle both asynchronous and synchronous serial communication.
The SCI supports a smart card interface conforming to ISO/IEC 7816-3 (Identification Card) as a
serial communication interface function for IC card interface use. For details, see section 17,
Smart Card Interface.
The SCIF is a dedicated asynchronous communication serial interface with built-in 16-stage FIFO
registers for both transmission and reception. For details, see section 16, Serial Communication
Interface with FIFO (SCIF).
15.1.1
Features
SCI features are listed below.
Choice of synchronous or asynchronous serial communication mode
Asynchronous mode
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be
carried out with standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface
Adapter (ACIA). A multiprocessor communication function is also provided that enables
serial data communication with a number of processors.
There is a choice of 12 serial data transfer formats.
Data length:
7 or 8 bits
Stop bit length:
1 or 2 bits
Parity:
Even/odd/none
Multiprocessor bit:
1 or 0
Receive error detection:
Parity, overrun, and framing errors
Break detection:
A break can be detected by reading the RxD pin level directly
from the serial port register (SCSPTR1) when a framing error
occurs.
Synchronous mode
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other chips that have a synchronous communication function.
Rev. 3.0, 04/02, page 570 of 1064
There is a single serial data transfer format.
Data length:
8 bits
Receive error detection:
Overrun errors
Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
On-chip baud rate generator allows any bit rate to be selected.
Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
Four interrupt sources
There are four interrupt sources--transmit-data-empty, transmit-end, receive-data-full, and
receive-error--that can issue requests independently. The transmit-data-empty interrupt and
receive-data-full interrupt can activate the DMA controller (DMAC) to execute a data transfer.
When not in use, the SCI can be stopped by halting its clock supply to reduce power
consumption.
Rev. 3.0, 04/02, page 571 of 1064
15.1.2
Block Diagram
Figure 15.1 shows a block diagram of the SCI.
Module data bus
SCRDR1
SCRSR1
RxD
TxD
SCK
SCTDR1
SCTSR1
SCSSR1
SCSCR1
SCSMR1
SCBRR1
Parity generation
Parity check
Transmission/
reception
control
Baud rate
generator
Clock
External clock
P
P
/4
P
/16
P
/64
TEI
TXI
RXI
ERI
SCI
Bus interface
Internal
data bus
SCSPTR1
SCRSR1:
Receive shift register
SCRDR1:
Receive data register
SCTSR1:
Transmit shift register
SCTDR1:
Transmit data register
SCSMR1:
Serial mode register
SCSCR1:
Serial control register
SCSSR1:
Serial status register
SCBRR1:
Bit rate register
SCSPTR1: Serial port register
Figure 15.1 Block Diagram of SCI
Rev. 3.0, 04/02, page 572 of 1064
15.1.3
Pin Configuration
Table 15.1 shows the SCI pin configuration.
Table 15.1
SCI Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
SCK
I/O
Clock input/output
Receive data pin
RxD
Input
Receive data input
Transmit data pin
TxD
Output
Transmit data output
Note:
They are made to function as serial pins by performing SCI operation settings with the TE,
RE, CKEI, and CKE0 bits in SCSCR1 and the C/
bit in SCSMR1. Break state
transmission and detection, can be set in the SCI's SCSPTR1 register.
15.1.4
Register Configuration
The SCI has the internal registers shown in table 15.2. These registers are used to specify
asynchronous mode or synchronous mode, the data format, and the bit rate, and to perform
transmitter/receiver control.
With the exception of the serial port register, the SCI registers are initialized in standby mode and
in the module standby state as well as after a power-on reset or manual reset. When recovering
from standby mode or the module standby state, the registers must be set again.
Table 15.2
SCI Registers
Name
Abbreviation
R/W
Initial
Value
P4 Address
Area 7
Address
Access
Size
Serial mode register
SCSMR1
R/W
H'00
H'FFE00000
H'1FE00000
8
Bit rate register
SCBRR1
R/W
H'FF
H'FFE00004
H'1FE00004
8
Serial control register
SCSCR1
R/W
H'00
H'FFE00008
H'1FE00008
8
Transmit data register
SCTDR1
R/W
H'FF
H'FFE0000C
H'1FE0000C
8
Serial status register
SCSSR1
R/(W)*
1
H'84
H'FFE00010
H'1FE00010
8
Receive data register
SCRDR1
R
H'00
H'FFE00014
H'1FE00014
8
Serial port register
SCSPTR1
R/W
H'00*
2
H'FFE0001C
H'1FE0001C
8
Notes: *1 Only 0 can be written, to clear flags.
*2 The value of bits 2 and 0 is undefined
Rev. 3.0, 04/02, page 573 of 1064
15.2
Register Descriptions
15.2.1
Receive Shift Register (SCRSR1)
Bit:
7
6
5
4
3
2
1
0
R/W:
--
--
--
--
--
--
--
--
SCRSR1 is the register used to receive serial data.
The SCI sets serial data input from the RxD pin in SCRSR1 in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to SCRDR1 automatically.
SCRSR1 cannot be directly read or written to by the CPU.
15.2.2
Receive Data Register (SCRDR1)
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
SCRDR1 is the register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received data from SCRSR1 to
SCRDR1 where it is stored, and completes the receive operation. SCRSR1 is then enabled for
reception.
Since SCRSR1 and SCRDR1 function as a double buffer in this way, it is possible to receive data
continuously.
SCRDR1 is a read-only register, and cannot be written to by the CPU.
SCRDR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Rev. 3.0, 04/02, page 574 of 1064
15.2.3
Transmit Shift Register (SCTSR1)
Bit:
7
6
5
4
3
2
1
0
R/W:
--
--
--
--
--
--
--
--
SCTSR1 is the register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from SCTDR1 to
SCTSR1, then sends the data to the TxD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from SCTDR1
to SCTSR1, and transmission started, automatically. However, data transfer from SCTDR1 to
SCTSR1 is not performed if the TDRE flag in the serial status register (SCSSR1) is set to 1.
SCTSR1 cannot be directly read or written to by the CPU.
15.2.4
Transmit Data Register (SCTDR1)
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCTDR1 is an 8-bit register that stores data for serial transmission.
When the SCI detects that SCTSR1 is empty, it transfers the transmit data written in SCTDR1 to
SCTSR1 and starts serial transmission. Continuous serial transmission can be carried out by
writing the next transmit data to SCTDR1 during serial transmission of the data in SCTSR1.
SCTDR1 can be read or written to by the CPU at all times.
SCTDR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Rev. 3.0, 04/02, page 575 of 1064
15.2.5
Serial Mode Register (SCSMR1)
Bit:
7
6
5
4
3
2
1
0
C/
CHR
PE
O/
STOP
MP
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCSMR1 is an 8-bit register used to set the SCI's serial transfer format and select the baud rate
generator clock source.
SCSMR1 can be read or written to by the CPU at all times.
SCSMR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit 7--Communication Mode (C/
): Selects asynchronous mode or synchronous mode as the
SCI operating mode.
Bit 7: C/
Description
0
Asynchronous mode
(Initial value)
1
Synchronous mode
Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting,
Bit 6: CHR
Description
0
8-bit data
(Initial value)
1
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of SCTDR1 is not transmitted.
Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, parity bit
addition and checking is not performed, regardless of the PE bit setting.
Bit 5: PE
Description
0
Parity bit addition and checking disabled
(Initial value)
1
Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/
bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/
bit.
Rev. 3.0, 04/02, page 576 of 1064
Bit 4--Parity Mode (O/
): Selects either even or odd parity for use in parity addition and
checking. The O/
bit setting is only valid when the PE bit is set to 1, enabling parity bit addition
and checking, in asynchronous mode. The O/
bit setting is invalid in synchronous mode, and
when parity addition and checking is disabled in asynchronous mode.
Bit 4: O/
Description
0
Even parity*
1
(Initial value)
1
Odd parity*
2
Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
*2 When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set, the STOP
bit setting is invalid since stop bits are not added.
Bit 3: STOP
Description
0
1 stop bit*
1
(Initial value)
1
2 stop bits*
2
Notes: *1 In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
before it is sent.
*2 In transmission, two 1-bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Rev. 3.0, 04/02, page 577 of 1064
Bit 2--Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor
format is selected, the PE bit and O/
bit parity settings are invalid. The MP bit setting is only
valid in asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor
Communication Function.
Bit 2: MP
Description
0
Multiprocessor function disabled
(Initial value)
1
Multiprocessor format selected
Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on-
chip baud rate generator. The clock source can be selected from P
, P
/4, P
/16, and P
/64,
according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.9, Bit Rate Register (SCBRR1).
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
P
clock
(Initial value)
1
P
/4 clock
1
0
P
/16 clock
1
P
/64 clock
Note: P
: Peripheral clock
15.2.6
Serial Control Register (SCSCR1)
Bit:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The SCSCR1 register performs enabling or disabling of SCI transfer operations, serial clock
output in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCSCR1 can be read or written to by the CPU at all times.
SCSCR1 is initialized to H'00 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Rev. 3.0, 04/02, page 578 of 1064
Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from SCTDR1 to SCTSR1 and
the TDRE flag in SCSSR1 is set to 1.
Bit 7: TIE
Description
0
Transmit-data-empty interrupt (TXI) request disabled*
(Initial value)
1
Transmit-data-empty interrupt (TXI) request enabled
Note: * TXI interrupt requests can be cleared by reading 1 from the TDRE flag, then clearing it to 0,
or by clearing the TIE bit to 0.
Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from SCRSR1 to SCRDR1 and the RDRF flag in SCSSR1 is set to 1.
Bit 6: RIE
Description
0
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request disabled*
(Initial value)
1
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI)
request enabled
Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0.
Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5: TE
Description
0
Transmission disabled*
1
(Initial value)
1
Transmission enabled*
2
Notes: *1 The TDRE flag in SCSSR1 is fixed at 1.
*2 In this state, serial transmission is started when transmit data is written to SCTDR1 and
the TDRE flag in SCSSR1 is cleared to 0.
SCSMR1 setting must be performed to decide the transmit format before setting the TE
bit to 1.
Rev. 3.0, 04/02, page 579 of 1064
Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4: RE
Description
0
Reception disabled*
1
(Initial value)
1
Reception enabled*
2
Notes: *1 Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
*2 Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode.
SCSMR1 setting must be performed to decide the receive format before setting the RE
bit to 1.
Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when the MP bit in SCSMR1 is set to 1.
The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed) (Initial value)
[Clearing conditions]
When the MPIE bit is cleared to 0
When data with MPB = 1 is received
1
Multiprocessor interrupts enabled*
Note: * When receive data including MPB = 1 is received, the MPIE bit is cleared to 0 automatically,
and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCSCR1 are set to
1) and FER and ORER flag setting is enabled.
Bit 2--Transmit-End interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request generation when there is no valid transmit data in SCTDR1 at the time for MSB data
transmission.
Bit 2: TEIE
Description
0
Transmit-end interrupt (TEI) request disabled*
(Initial value)
1
Transmit-end interrupt (TEI) request enabled*
Note: * TEI interrupt requests can be cleared by reading 1 from the TDRE flag in SCSSR1, then
clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0.
Rev. 3.0, 04/02, page 580 of 1064
Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial
clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of
external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining
the SCI's operating mode with SCSMR1.
For details of clock source selection, see table 15.9 in section 15.3, Operation.
Bit 1: CKE1
Bit 0: CKE0
Description
0
0
Asynchronous mode
Internal clock/SCK pin functions as
input pin (input signal ignored)*
1
Synchronous mode
Internal clock/SCK pin functions as
serial clock output*
1
1
Asynchronous mode
Internal clock/SCK pin functions as
clock output*
2
Synchronous mode
Internal clock/SCK pin functions as
serial clock output
1
0
Asynchronous mode
External clock/SCK pin functions as
clock input*
3
Synchronous mode
External clock/SCK pin functions as
serial clock input
1
Asynchronous mode
External clock/SCK pin functions as
clock input*
3
Synchronous mode
External clock/SCK pin functions as
serial clock input
Notes: *1 Initial value
*2 Outputs a clock of the same frequency as the bit rate.
*3 Inputs a clock with a frequency 16 times the bit rate.
Rev. 3.0, 04/02, page 581 of 1064
15.2.7
Serial Status Register (SCSSR1)
Bit:
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
Initial value:
1
0
0
0
0
1
--
0
R/W:
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Note: * Only 0 can be written, to clear the flag.
SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI,
and multiprocessor bits.
SCSSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SCSSR1 is initialized to H'84 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1.
Bit 7: TDRE
Description
0
Valid transmit data has been written to SCTDR1
[Clearing conditions]
When 0 is written to TDRE after reading TDRE = 1
When data is written to SCTDR1 by the DMAC
1
There is no valid transmit data in SCTDR1
(Initial value)
[Setting conditions]
Power-on reset, manual reset, standby mode, or module standby
When the TE bit in SCSCR1 is 0
When data is transferred from SCTDR1 to SCTSR1 and data can be
written to SCTDR1
Rev. 3.0, 04/02, page 582 of 1064
Bit 6--Receive Data Register Full (RDRF): Indicates that the received data has been stored in
SCRDR1.
Bit 6: RDRF
Description
0
There is no valid receive data in SCRDR1
(Initial value)
[Clearing conditions]
Power-on reset, manual reset, standby mode, or module standby
When 0 is written to RDRF after reading RDRF = 1
When data in SCRDR1 is read by the DMAC
1
There is valid receive data in SCRDR1
[Setting condition]
When serial reception ends normally and receive data is transferred from
SCRSR1 to SCRDR1
Note: SCRDR1 and the RDRF flag are not affected and retain their previous values when an error
is detected during reception or when the RE bit in SCSCR1 is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5: ORER
Description
0
Reception in progress, or reception has ended normally*
1
(Initial value)
[Clearing conditions]
Power-on reset, manual reset, standby mode, or module standby
When 0 is written to ORER after reading ORER = 1
1
An overrun error occurred during reception*
2
[Setting condition]
When the next serial reception is completed while RDRF = 1
Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in
SCSCR1 is cleared to 0.
*2 The receive data prior to the overrun error is retained in SCRDR1, and the data
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1. In synchronous mode, serial transmission cannot be continued either.
Rev. 3.0, 04/02, page 583 of 1064
Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4: FER
Description
0
Reception in progress, or reception has ended normally*
1
(Initial value)
[Clearing conditions]
Power-on reset, manual reset, standby mode, or module standby
When 0 is written to FER after reading FER = 1
1
A framing error occurred during reception
[Setting condition]
When the SCI checks whether the stop bit at the end of the receive data is 1
when reception ends, and the stop bit is 0*
2
Notes: *1 The FER flag is not affected and retains its previous state when the RE bit in SCSCR1
is cleared to 0.
*2 In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit
is not checked. If a framing error occurs, the receive data is transferred to SCRDR1 but
the RDRF flag is not set. Serial reception cannot be continued while the FER flag is set
to 1.
Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception with parity
addition in asynchronous mode, causing abnormal termination.
Bit 3: PER
Description
0
Reception in progress, or reception has ended normally*
1
(Initial value)
[Clearing conditions]
Power-on reset, manual reset, standby mode, or module standby
When 0 is written to PER after reading PER = 1
1
A parity error occurred during reception*
2
[Setting condition]
When, in reception, the number of 1-bits in the receive data plus the parity
bit does not match the parity setting (even or odd) specified by the O/
bit in
SCSMR1
Notes: *1 The PER flag is not affected and retains its previous state when the RE bit in SCSCR1
is cleared to 0.
*2 If a parity error occurs, the receive data is transferred to SCRDR1 but the RDRF flag is
not set. Serial reception cannot be continued while the PER flag is set to 1.
Rev. 3.0, 04/02, page 584 of 1064
Bit 2--Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit
of the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2: TEND
Description
0
Transmission is in progress
[Clearing conditions]
When 0 is written to TDRE after reading TDRE = 1
When data is written to SCTDR1 by the DMAC
1
Transmission has been ended
(Initial value)
[Setting conditions]
Power-on reset, manual reset, standby mode, or module standby
When the TE bit in SCSCR1 is 0
When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit
character
Bit 1--Multiprocessor Bit (MPB): This bit is read-only and cannot be written to. The read value
is undefined.
Note:
This bit is prepared for storing a multi-processor bit in the received data when the receipt
is carried out with a multi-processor format in asynchronous mode, however, this does not
function correctly in this LSI. Do not use the read value from this bit.
Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used,
and when the operation is not transmission.
Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether
transmission has been completed before changing its value.
Bit 0: MPBT
Description
0
Data with a 0 multiprocessor bit is transmitted
(Initial value)
1
Data with a 1 multiprocessor bit is transmitted
Rev. 3.0, 04/02, page 585 of 1064
15.2.8
Serial Port Register (SCSPTR1)
Bit:
7
6
5
4
3
2
1
0
EIO
--
--
--
SPB1IO SPB1DT SPB0IO SPB0DT
Initial value:
0
0
0
0
0
--
0
--
R/W:
R/W
--
--
--
R/W
R/W
R/W
R/W
SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins
multiplexed with the serial communication interface (SCI) pins. Input data can be read from the
RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception
controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be
performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt.
SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0
are initialized to 0 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined.
SCSPTR1 is not initialized in the module standby state or standby mode.
Bit 7--Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent
to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only
ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another
peripheral module. This bit specifies enabling or disabling of the RXI interrupt.
Bit 7: EIO
Description
0
When the RIE bit is 1, RXI and ERI interrupts are sent to INTC(Initial value)
1
When the RIE bit is 1, only ERI interrupts are sent to INTC
Bits 6 to 4--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3--Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When
the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the
C/
bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0.
Bit 3: SPB1IO
Description
0
SPB1DT bit value is not output to the SCK pin
(Initial value)
1
SPB1DT bit value is output to the SCK pin
Rev. 3.0, 04/02, page 586 of 1064
Bit 2--Serial Port Clock Port Data (SPB1DT): Specifies the serial port SCK pin input/output
data. Input or output is specified by the SPB1IO bit (see the description of bit 3, SPB1IO, for
details). When output is specified, the value of the SPB1DT bit is output to the SCK pin. The SCK
pin value is read from the SPB1DT bit regardless of the value of the SPB1IO bit. The initial value
of this bit after a power-on or manual reset is undefined.
Bit 2: SPB1DT
Description
0
Input/output data is low-level
1
Input/output data is high-level
Bit 1--Serial Port Break I/O (SPB0IO): Specifies the serial port TxD pin output condition.
When the TxD pin is actually set as a port output pin and outputs the value set by the SPB0DT bit,
the TE bit in SCSCR1 should be cleared to 0.
Bit 1: SPB0IO
Description
0
SPB0DT bit value is not output to the TxD pin
(Initial value)
1
SPB0DT bit value is output to the TxD pin
Bit 0--Serial Port Break Data (SPB0DT): Specifies the serial port RxD pin input data and TxD
pin output data. The TxD pin output condition is specified by the SPB0IO bit (see the description
of bit 1, SPB0IO, for details). When the TxD pin is designated as an output, the value of the
SPB0DT bit is output to the TxD pin. The RxD pin value is read from the SPB0DT bit regardless
of the value of the SPB0IO bit. The initial value of this bit after a power-on or manual reset is
undefined.
Bit 0: SPB0DT
Description
0
Input/output data is low-level
1
Input/output data is high-level
Rev. 3.0, 04/02, page 587 of 1064
SCI I/O port block diagrams are shown in figures 15.2 to 15.4.
Reset
Reset
Internal data bus
SPTRW
SPTRW
SCI
R
Q
D
SPB1IO
C
R
Q
D
SPB1DT
C
SPTRR
Clock output enable signal
Serial clock output signal
Serial clock input signal
Clock input enable signal
*
SCK
SPTRW: Write to SPTR
SPTRR: Read SPTR
Note: * Signals that set the SCK pin function as internal clock output or external clock input according to
the CKE0 and CKE1 bits in SCSCR1 and the C/ bit in SCSMR1.
Figure 15.2 SCK Pin
Rev. 3.0, 04/02, page 588 of 1064
Reset
Internal data bus
SPTRW
SCI
R
Q
D
SPB0IO
C
Reset
SPTRW
R
Q
D
SPB0DT
C
TxD
Transmit enable signal
Serial transmit data
SPTRW: Write to SPTR
Figure 15.3 TxD Pin
Internal data bus
SCI
RxD
SPTRR
Serial receive data
SPTRR: Read SPTR
Figure 15.4 RxD Pin
Rev. 3.0, 04/02, page 589 of 1064
15.2.9
Bit Rate Register (SCBRR1)
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCBRR1 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SCSMR1.
SCBRR1 can be read or written to by the CPU at all times.
SCBRR1 is initialized to H'FF by a power-on reset or manual reset, in standby mode, and in the
module standby state.
The SCBRR1 setting is found from the following equations.
Asynchronous mode:
N =
10
6
1
64
2
2n1
B
P
Synchronous mode:
N =
10
6
1
8
2
2n1
B
P
Where B:
Bit rate (bits/s)
N:
SCBRR1 setting for baud rate generator (0
N
255)
P
: Peripheral module operating frequency (MHz)
n:
Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SCSMR1 Setting
n
Clock
CKS1
CKS0
0
P
0
0
1
P
/4
0
1
2
P
/16
1
0
3
P
/64
1
1
Rev. 3.0, 04/02, page 590 of 1064
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
100
P
10
6
(N + 1)
B
64
2
2n1
1
Table 15.3 shows sample SCBRR1 settings in asynchronous mode, and table 15.4 shows sample
SCBRR1 settings in synchronous mode.
Rev. 3.0, 04/02, page 591 of 1064
Table 15.3
Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode
P
(MHz)
2
2.097152
2.4576
3
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
0.04
1
174
0.26
1
212
0.03
150
1
103
0.16
1
108
0.21
1
127
0.00
1
155
0.16
300
0
207
0.16
0
217
0.21
0
255
0.00
1
77
0.16
600
0
103
0.16
0
108
0.21
0
127
0.00
0
155
0.16
1200
0
51
0.16
0
54
0.70
0
63
0.00
0
77
0.16
2400
0
25
0.16
0
26
1.14
0
31
0.00
0
38
0.16
4800
0
12
0.16
0
13
2.48
0
15
0.00
0
19
2.34
9600
0
6
6.99
0
6
2.48
0
7
0.00
0
9
2.34
19200
0
2
8.51
0
2
13.78
0
3
0.00
0
4
2.34
31250
0
1
0.00
0
1
4.86
0
1
22.88
0
2
0.00
38400
0
1
18.62 0
1
14.67 0
1
0.00
P
(MHz)
3.6864
4
4.9152
5
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
0.25
150
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
300
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
600
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
1200
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
0
6
6.99
0
7
0.00
0
7
1.73
31250
--
--
--
0
3
0.00
0
4
1.70
0
4
0.00
38400
0
2
0.00
0
2
8.51
0
3
0.00
0
3
1.73
Legend
Blank: No setting is available.
--:
A setting is available but error occurs.
Rev. 3.0, 04/02, page 592 of 1064
Table 15.3
Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont)
P
(MHz)
6
6.144
7.37288
8
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
106
0.44
2
108
0.08
2
130
0.07
2
141
0.03
150
2
77
0.16
2
79
0.00
2
95
0.00
2
103
0.16
300
1
155
0.16
1
159
0.00
1
191
0.00
1
207
0.16
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
155
0.16
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
2.34
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
2.34
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
0
6
5.33
0
7
0.00
38400
0
4
2.34
0
4
0.00
0
5
0.00
0
6
6.99
P
(MHz)
9.8304
10
12
12.288
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
174
0.26
2
177
0.25
2
212
0.03
2
217
0.08
150
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
0.16
0
19
0.00
31250
0
9
1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
2.34
0
9
0.00
Rev. 3.0, 04/02, page 593 of 1064
Table 15.3
Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode (cont)
P
(MHz)
14.7456
16
19.6608
20
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
64
0.70
3
70
0.03
3
86
0.31
3
88
0.25
150
2
191
0.00
2
207
0.16
2
255
0.00
3
64
0.16
300
2
95
0.00
2
103
0.16
2
127
0.00
2
129
0.16
600
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
1200
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
2400
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
4800
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
9600
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
19200
0
23
0.00
0
25
0.16
0
31
0.00
0
32
1.36
31250
0
14
1.70
0
15
0.00
0
19
1.70
0
19
0.00
38400
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
P
(MHz)
24
24.576
28.7
30
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
106
0.44
3
108
0.08
3
126
0.31
3
132
0.13
150
3
77
0.16
3
79
0.00
3
92
0.46
3
97
0.35
300
2
155
0.16
2
159
0.00
2
186
0.08
2
194
0.16
600
2
77
0.16
2
79
0.00
2
92
0.46
2
97
0.35
1200
1
155
0.16
1
159
0.00
1
186
0.08
1
194
0.16
2400
1
77
0.16
1
79
0.00
1
92
0.46
1
97
0.35
4800
0
155
0.16
0
159
0.00
0
186
0.08
0
194
1.36
9600
0
77
0.16
0
79
0.00
0
92
0.46
0
97
0.35
19200
0
38
0.16
0
39
0.00
0
46
0.61
0
48
0.35
31250
0
23
0.00
0
24
1.70
0
28
1.03
0
29
0.00
38400
0
19
2.34
0
19
0.00
0
22
1.55
0
23
1.73
Rev. 3.0, 04/02, page 594 of 1064
Table 15.4
Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode
P
(MHz)
4
8
16
28.7
30
Bit Rate (bits/s)
n
N
n
N
n
N
n
N
n
N
10
--
--
--
--
--
--
--
--
--
--
250
2
249
3
124
3
249
--
--
--
--
500
2
124
2
249
3
124
3
223
3
233
1k
1
249
2
124
2
249
3
111
3
116
2.5k
1
99
1
199
2
99
2
178
2
187
5k
0
199
1
99
1
199
2
89
2
93
10k
0
99
0
199
1
99
1
178
1
187
25k
0
39
0
79
0
159
1
71
1
74
50k
0
19
0
39
0
79
0
143
0
149
100k
0
9
0
19
0
39
0
71
0
74
250k
0
3
0
7
0
15
--
--
0
29
500k
0
1
0
3
0
7
--
--
0
14
1M
0
0*
0
1
0
3
--
--
--
--
2M
0
0*
0
1
--
--
--
--
Note: As far as possible, the setting should be made so that the error is within 1%.
Blank: No setting is available.
--:
A setting is available but error occurs.
*:
Continuous transmission/reception is not possible.
Rev. 3.0, 04/02, page 595 of 1064
Table 15.5 shows the maximum bit rate for various frequencies in asynchronous mode. Tables
15.6 and 15.7 show the maximum bit rates with external clock input.
Table 15.5
Maximum Bit Rate for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)
Settings
P
(MHz)
Maximum Bit Rate (bits/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
8
250000
0
0
9.8304
307200
0
0
12
375000
0
0
14.7456
460800
0
0
16
500000
0
0
19.6608
614400
0
0
20
625000
0
0
24
750000
0
0
24.576
768000
0
0
28.7
896875
0
0
30
937500
0
0
Rev. 3.0, 04/02, page 596 of 1064
Table 15.6
Maximum Bit Rate with External Clock Input (Asynchronous Mode)
P
(MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
8
2.0000
125000
9.8304
2.4576
153600
12
3.0000
187500
14.7456
3.6864
230400
16
4.0000
250000
19.6608
4.9152
307200
20
5.0000
312500
24
6.0000
375000
24.576
6.1440
384000
28.7
7.1750
448436
30
7.5000
468750
Table 15.7
Maximum Bit Rate with External Clock Input (Synchronous Mode)
P
(MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
8
1.3333
1333333.3
16
2.6667
2666666.7
24
4.0000
4000000.0
28.7
4.7833
4783333.3
30
5.0000
5000000.0
Rev. 3.0, 04/02, page 597 of 1064
15.3
Operation
15.3.1
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses.
Selection of asynchronous or synchronous mode and the transmission format is made using
SCSMR1 as shown in table 15.8. The SCI clock source is determined by a combination of the C/
bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1, as shown in table 15.9.
Asynchronous mode
Data length: Choice of 7 or 8 bits
Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the
combination of these parameters determines the transfer format and character length)
Detection of framing, parity, and overrun errors, and breaks, during reception
Choice of internal or external clock as SCI clock source
When internal clock is selected: The SCI operates on the baud rate generator clock and a
clock with the same frequency as the bit rate can be output.
When external clock is selected: A clock with a frequency of 16 times the bit rate must be
input (the on-chip baud rate generator is not used).
Synchronous mode
Transfer format: Fixed 8-bit data
Detection of overrun errors during reception
Choice of internal or external clock as SCI clock source
When internal clock is selected: The SCI operates on the baud rate generator clock and a
serial clock is output off-chip.
When external clock is selected: The on-chip baud rate generator is not used, and the SCI
operates on the input serial clock.
Rev. 3.0, 04/02, page 598 of 1064
Table 15.8
SCSMR1 Settings for Serial Transfer Format Selection
SCSMR1 Settings
SCI Transfer Format
Bit 7:
C/
Bit 6:
CHR
Bit 2:
MP
Bit 5:
PE
Bit 3:
STOP Mode
Data
Length
Multi-
processor
Bit
Parity
Bit
Stop Bit
Length
0
1 bit
0
1
No
2 bits
0
1 bit
0
1
1
8-bit data
Yes
2 bits
0
1 bit
0
1
No
2 bits
0
1 bit
1
0
1
1
Asynchronous
mode
7-bit data
No
Yes
2 bits
0
1 bit
0
1
8-bit data
2 bits
0
1 bit
0
1
1
*
1
Asynchronous
mode
(multiprocessor
format)
7-bit data
Yes
2 bits
1
*
*
*
*
Synchronous
mode
8-bit data
No
No
None
Note: An asterisk in the table means "Don't care."
Table 15.9
SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection
SCSMR1
SCSCR1 Setting
SCI Transmit/Receive Clock
Bit 7:
C/
Bit 1:
CKE1
Bit 0:
CKE0
Mode
Clock
Source
SCK Pin Function
0
0
0
Internal
SCI does not use SCK pin
1
Outputs clock with same
frequency as bit rate
1
0
External
Inputs clock with frequency of
16 times the bit rate
1
Asynchronous
mode
1
0
0
Internal
Outputs serial clock
1
1
0
External
Inputs serial clock
1
Synchronous
mode
Rev. 3.0, 04/02, page 599 of 1064
15.3.2
Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-by-
character basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 15.5 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSB-
first order), a parity bit (high or low level), and finally one or two stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the eighth pulse of a clock with a frequency of 16 times
the length of one bit, so that the transfer data is latched at the center of each bit.
Serial
data
(LSB)
7 or 8 bits
One unit of transfer data (character or frame)
Parity
bit
1 bit,
or none
1 or
2 bits
Stop
bit(s)
1
1
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
Idle state (mark state)
Start
bit
1 bit
(MSB)
Transmit/receive data
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)
Data Transfer Format
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SCSMR1 setting.
Rev. 3.0, 04/02, page 600 of 1064
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
SCSMR1 Settings
Serial Transfer Format and Frame Length
CHR PE
MP
STOP
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P
STOP
0
1
0
1
S
8-bit data
P
STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
*
1
0
S
8-bit data
MPB STOP
0
*
1
1
S
8-bit data
MPB STOP STOP
1
*
1
0
S
7-bit data
MPB STOP
1
*
1
1
S
7-bit data
MPB STOP STOP
Note: An asterisk in the table means "Don't care."
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB:
Multiprocessor bit
Rev. 3.0, 04/02, page 601 of 1064
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/
bit in
SCSMR1 and the CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see
table 15.9.
When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate
used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.6.
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
One frame
0
Figure 15.6 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Data Transfer Operations
SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, it is necessary
to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change
the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation will be unreliable in this case.
Figure 15.7 shows a sample SCI initialization flowchart.
Rev. 3.0, 04/02, page 602 of 1064
Initialization
Clear TE and RE bits
in SCSCR1 to 0
Set CKE1 and CKE0 bits
in SCSCR1 (leaving TE and
RE bits cleared to 0)
Set data transfer format
in SCSMR1
Set value in SCBRR1
1-bit interval elapsed?
Set TE and RE bits in SCSCR1
to 1, and set RIE, TIE, TEIE,
and MPIE bits
End
Yes
Wait
No
1. Set the clock selection in SCSCR1.
Be sure to clear bits RIE, TIE, TEIE,
and MPIE, and bits TE and RE, to 0.
When clock output is selected in
asynchronous mode, it is output
immediately after SCSCR1 settings
are made.
2. Set the data transfer format in
SCSMR1.
3. Write a value corresponding to the
bit rate into SCBRR1. (Not
necessary if an external clock is
used.)
4. Wait at least one bit interval, then set
the TE bit or RE bit in SCSCR1 to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
When transmitting, the SCI will go to
the mark state; when receiving, it will
go to the idle state, waiting for a start
bit.
Figure 15.7 Sample SCI Initialization Flowchart
Serial Data Transmission (Asynchronous Mode): Figure 15.8 shows a sample flowchart for
serial transmission.
Use the following procedure for serial data transmission after enabling the SCI for transmission.
Rev. 3.0, 04/02, page 603 of 1064
Start of transmission
Read TDRE flag in SCSSR1
TDRE = 1?
All data transmitted?
TEND = 1?
Break output?
Clear TE bit in SCSCR1 to 0
End of transmission
Yes
No
Yes
No
Yes
No
Yes
No
Write transmit data to SCTDR1
and clear TDRE flag
in SCSSR1 to 0
Read TEND flag in SCSSR1
Clear SPB0DT to 0 and
set SPB0IO to 1
1. SCI status check and transmit data
write: Read SCSSR1 and check that
the TDRE flag is set to 1, then write
transmit data to SCTDR1 and clear
the TDRE flag to 0.
2. Serial transmission continuation
procedure: To continue serial
transmission, read 1 from the TDRE
flag to confirm that writing is possible,
then write data to SCTDR1, and then
clear the TDRE flag to 0. (Checking
and clearing of the TDRE flag is
automatic when the direct memory
access controller (DMAC) is activated
by a transmit-data-empty interrupt
(TXI) request, and data is written to
SCTDR1.)
3. Break output at the end of serial
transmission: To output a break in
serial transmission, clear the SPB0DT
bit to 0 and set the SPB0IO bit to 1 in
SCSPTR, then clear the TE bit in
SCSCR1 to 0.
Figure 15.8 Sample Serial Transmission Flowchart
Rev. 3.0, 04/02, page 604 of 1064
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes
that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is
generated.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit: One 0-bit is output.
b. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
c. Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor
bit is output. (A format in which neither a parity bit nor a multiprocessor bit is output can
also be selected.)
d. Stop bit(s): One or two 1-bits (stop bits) are output.
e. Mark state: 1 is output continuously until the start bit that starts the next transmission is
sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is
cleared to 0, data is transferred from SCTDR1 to SCTSR1, the stop bit is sent, and then serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then
the line goes to the mark state in which 1 is output continuously. If the TEIE bit in SCSCR1 is
set to 1 at this time, a TEI interrupt request is generated.
Figure 15.9 shows an example of the operation for transmission in asynchronous mode.
Rev. 3.0, 04/02, page 605 of 1064
1
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
1
TDRE
TEND
Serial
data
Start
bit
Data
Parity
bit
Stop
bit
Start
bit
Idle state
(mark state)
Data
Parity
bit
Stop
bit
TXI interrupt
request
Data written to SCTDR1
and TDRE flag cleared to
0 by TXI interrupt handler
One frame
TEI interrupt
request
TXI interrupt
request
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial
reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
Rev. 3.0, 04/02, page 606 of 1064
Start of reception
Read ORER, PER, and FER flags
in SCSSR1
Read RDRF flag in SCSSR1
PER or FER
or ORER = 1?
RDRF = 1?
All data received?
Clear RE bit in SCSCR1 to 0
End of reception
Error handling
Yes
No
Yes
No
Yes
No
Read receive data in SCRDR1,
and clear RDRF flag
in SCSSR1 to 0
1. Receive error handling and
break detection: If a receive
error occurs, read the ORER,
PER, and FER flags in
SCSSR1 to identify the error.
After performing the
appropriate error handling,
ensure that the ORER, PER,
and FER flags are all cleared to
0. Reception cannot be
resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value
of the RxD pin.
2. SCI status check and receive
data read : Read SCSSR1 and
check that RDRF = 1, then read
the receive data in SCRDR1
and clear the RDRF flag to 0.
3. Serial reception continuation
procedure: To continue serial
reception, complete zero-
clearing of the RDRF flag
before the stop bit for the
current frame is received. (The
RDRF flag is cleared
automatically when the direct
memory access controller
(DMAC) is activated by an RXI
interrupt and the SCRDR1
value is read.)
Figure 15.10 Sample Serial Reception Flowchart (1)
Rev. 3.0, 04/02, page 607 of 1064
Error handling
ORER = 1?
FER = 1?
Break?
PER = 1?
End
Yes
Yes
No
Yes
No
No
No
Yes
Clear ORER, PER, and FER flags
in SCSSR1 to 0
Parity error handling
Framing error handling
Clear RE bit in SCSCR1 to 0
Overrun error handling
Figure 15.10 Sample Serial Reception Flowchart (2)
Rev. 3.0, 04/02, page 608 of 1064
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR1 in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
a. Parity check: The SCI checks whether the number of 1-bits in the receive data agrees with
the parity (even or odd) set in the O/E bit in SCSMR1.
b. Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the
first is checked.
c. Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data
can be transferred from SCRSR1 to SCRDR1.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
SCRDR1.
If a receive error is detected in the error check, the operation is as shown in table 15.11.
Note: No further receive operations can be performed when a receive error has occurred. Also
note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared
to 0.
4. If the EIO bit in SCSPTR1 is cleared to 0 and the RIE bit in SCSCR1 is set to 1 when the
RDRF flag changes to 1, a receive-data-full interrupt (RXI) request is generated.
If the RIE bit in SCSCR1 is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated. A receive-data-full request is always output
to the DMAC when the RDRF flag changes to 1.
Table 15.11 Receive Error Conditions
Receive Error
Abbreviation
Condition
Data Transfer
Overrun error
ORER
Reception of next data is
completed while RDRF flag
in SCSSR1 is set to 1
Receive data is not transferred
from SCRSR1 to SCRDR1
Framing error
FER
Stop bit is 0
Receive data is transferred
from SCRSR1 to SCRDR1
Parity error
PER
Received data parity differs
from that (even or odd) set
in SCSMR1
Receive data is transferred
from SCRSR1 to SCRDR1
Figure 15.11 shows an example of the operation for reception in asynchronous mode.
Rev. 3.0, 04/02, page 609 of 1064
1
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
0/1
0
RDRF
FER
Serial
data
Start
bit
Data
Parity
bit
Stop
bit
Start
bit
Data
Parity
bit
Stop
bit
RXI interrupt
request
One frame
SCRDR1 data read and
RDRF flag cleared to 0
by RXI interrupt handler
ERI interrupt request
generated by framing
error
Figure 15.11 Example of SCI Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
15.3.3
Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using a
multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharing a serial transmission line.
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two cycles: an ID transmission cycle which specifies
the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate
between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving station skips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Figure 15.12 shows an example of inter-processor communication using a multiprocessor format.
Rev. 3.0, 04/02, page 610 of 1064
Note:
Even when this LSI has received data with a 0 multiprocessor bit that was meant to be sent
to another station, the RDRF flag in SCSSR1 is set to 1. When the RDRF flag in SCSSR1
is set to 1, the exception handling routine reads the MPIE bit in SCSCR1, and skips the
receive data if the MPIE bit is 1. Skipping of unnecessary data is achieved by
collaborative operation with the exception handling routine.
Transmitting
station
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial transmission line
(MPB = 1)
(MPB = 0)
H'01
H'AA
MPB: Multiprocessor bit
Serial
data
ID transmission cycle:
Receiving station
specification
Data transmission cycle:
Data transmission to
receiving station specified
by ID
Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Rev. 3.0, 04/02, page 611 of 1064
Data Transfer Formats
There are four data transfer formats. When the multiprocessor format is specified, the parity bit
specification is invalid. For details, see table 15.10.
Clock
See the description under Clock in section 15.3.2.
Data Transfer Operations
Multiprocessor Serial Data Transmission: Figure 15.13 shows a sample flowchart for
multiprocessor serial data transmission.
Use the following procedure for multiprocessor serial data transmission after enabling the SCI for
transmission.
Rev. 3.0, 04/02, page 612 of 1064
Start of transmission
Read TEND flag in SCSSR1
TEND = 1?
Clear TDRE flag to 0
Read TEND flag in SCSSR1
TEND = 1?
Clear MPBT bit in SCSSR1 to 0
Write data to SCTDR1
Clear TDRE flag to 0
Read TDRE flag in SCSSR1
End of transmission
No
Yes
No
Yes
All data transmitted?
TDRE = 1?
Yes
Yes
No
No
Set MPBT bit in SCSSR1 to 1 and
write ID data to SCTDR1
1. SCI status check and ID data write:
Read SCSSR1 and check that the
TEND flag is set to 1, then set the
MPBT bit in SCSSR1 to 1 and write
ID data to SCTDR1. Finally, clear the
TDRE flag to 0.
2. Preparation for data transfer: Read
SCSSR1 and check that the TEND
flag is set to 1, then set the MPBT bit
in SCSSR1 to 1.
3. Serial data transmission: Write the
first transmit data to SCTDR1, then
clear the TDRE flag to 0.
To continue data transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to SCTDR1, and then clear
the TDRE flag to 0. (Checking and
clearing of the TDRE flag is
automatic when the direct memory
access controller (DMAC) is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to SCTDR1.)
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart
Rev. 3.0, 04/02, page 613 of 1064
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes
that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts
transmission.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit: One 0-bit is output.
b. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
c. Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
d. Stop bit(s): One or two 1-bits (stop bits) are output.
e. Mark state: 1 is output continuously until the start bit that starts the next transmission is
sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is set to
1, the TEND flag in SCSSR1 is set to 1, the stop bit is sent, and then the line goes to the mark
state in which 1 is output. If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end
interrupt (TEI) request is generated.
4. The SCI monitors the TDRE flag. When TDRE is cleared to 0, the SCI recognizes that data
has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
5. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts
transmitting. If the transmit-data-empty interrupt enable bit (TIE bit) in SCSCR1 is set to 1 at
this time, a transmit-data-empty interrupt (TXI) request is generated.
The order of transmission is the same as in step 2.
Figure 15.14 shows an example of SCI operation for transmission using a multiprocessor format.
Rev. 3.0, 04/02, page 614 of 1064
Serial
data
MPBT bit cleared to 0, data
written to SCTDR1, and
TDRE flag cleared to 0 by
TEI interrupt handler
Data written to SCTDR1
and TDRE flag cleared
to 0 by TXI interrupt
handler
TXI interrupt
request
TEI interrupt
request
1
1
0
D0 D1
D7
0
0
0
D0 D1
D7
0
D0 D1
D7
1
1
1
Multi-
proces-
sor bit
Multi-
proces-
sor bit
Multi-
proces-
sor bit
Stop
bit
Start
bit
Stop
bit
Stop
bit
Start
bit
Data
Data
Data
Start
bit
TDRE
TEND
One frame
Idle state
(mark state)
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for
multiprocessor serial reception.
Use the following procedure for multiprocessor serial data reception after enabling the SCI for
reception.
Rev. 3.0, 04/02, page 615 of 1064
Start of reception
Set MPIE bit in SCSCR1 to 1
Read ORER and FER flags
in SCSSR1
FER = 1? or ORER = 1?
Read RDRF flag in SCSSR1
Read MPIE bit in SCSCR1
RDRF = 1
and MPIE = 0?
Read receive data in SCRDR1
This station's ID?
FER = 1? or ORER = 1?
Read RDRF flag in SCSSR1
RDRF = 1?
Read receive data in SCRDR1
All data received?
End of reception
Error handling
Yes
No
Yes
No
Yes
No
Yes
No
No
No
Yes
Yes
Read ORER and FER flags
in SCSSR1
1. ID reception cycle: Set the MPIE
bit in SCSCR1 to 1.
2. SCI status check, ID reception
and comparison: Read SCSSR1
and SCSCR1, and check that the
RDRF flag is set to 1 and the
MPIE bit is set to 0, then read the
receive data in SCRDR1 and
compare it with this station's ID.
If the data is not this station's ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0. If the
data is this station's ID, clear the
RDRF flag to 0.
3. SCI status check and data
reception: Read SCSSR1 and
check that the RDRF flag is set to
1, then read the data in SCRDR1.
4. Receive error handling and break
detection: If a receive error
occurs, read the ORER and FER
flags in SCSSR1 to identify the
error. After performing the
appropriate error handling,
ensure that the ORER and FER
flags are all cleared to 0.
Reception cannot be resumed if
either of these flags is set to 1. In
the case of a framing error, a
break can be detected by reading
the RxD pin value.
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 3.0, 04/02, page 616 of 1064
ORER = 1?
FER = 1?
Error handling
Overrun error handling
Break?
Framing error handling
Clear RE bit in SCSCR1 to 0
Clear ORER and FER flags
in SCSSR1 to 0
End
Yes
No
No
Yes
Yes
No
Figure 15.15 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 3.0, 04/02, page 617 of 1064
Figure 15.16 shows an example of SCI operation for multiprocessor format reception.
1
0
D0
D1
D7
1
1
0
D0
D1
D7
0
1
1
MPB
MPIE
RDRF
ID1
ID2
Data2
1
0
D0
D1
D7
1
1
0
D0
D1
D7
0
1
1
MPB
MPB
MPIE
RDRF
SCRDR1
value
ID1
Serial
data
Start
bit
Data (ID1)
Stop
bit
Start
bit
Idle state
(mark state)
Data
(Data1)
Stop
bit
(b) Data matches station's ID
RXI interrupt request
(multiprocessor
interrupt)
MPIE = 0
SCRDR1 data read
and RDRF flag
cleared to 0 by RXI
interrupt handler
As data is not
this station's ID,
MPIE bit is set
to 1 again
RXI interrupt
request
MPB
Serial
data
Start
bit
Data (ID2)
Stop
bit
Start
bit
Data
(Data2)
Stop
bit
Idle state
(mark state)
(a) Data does not match station's ID
SCRDR1
value
RXI interrupt request
(multiprocessor interrupt)
MPIE = 0
SCRDR1 data read
and RDRF flag
cleared to 0 by RXI
interrupt handler
As data matches this
station's ID, reception
continues and data is
received by RXI
interrupt handler
MPIE bit set
to 1 again
The RDRF flag
is cleared to 0
by is the RXI
interrupt handler
Figure 15.16 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor
Bit, One Stop Bit)
Rev. 3.0, 04/02, page 618 of 1064
In multiprocessor mode serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR1 in LSB-to-MSB order.
3. If the MPIE bit is 1, MPIE is cleared to 0 when a 1 is received in the multiprocessor bit
position. If the multiprocessor bit is 0, the MPIE bit is not changed.
4. If the MPIE bit is 0, RDRF is checked at the stop bit position, and if RDRF is 1 the overrun
error bit is set. If the stop bit is not 0, the framing error bit is set. If RDRF is 0, the value in
SCRSR1 is transferred to SCRDR1, and if the stop bit is 0, RDRF is set to 1.
15.3.4
Operation in Synchronous Mode
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making
it suitable for high-speed serial communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 15.17 shows the general format for synchronous serial communication.
One unit of transfer data (character or frame)
Note: * High except in continuous transfer
Serial clock
Serial data
LSB
Bit 0
MSB
*
*
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 Don't care
Don't care
Figure 15.17 Data Format in Synchronous Communication
Rev. 3.0, 04/02, page 619 of 1064
In synchronous serial communication, data on the transmission line is output from one falling edge
of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial
clock.
In serial communication, one character consists of data output starting with the LSB and ending
with the MSB. After the MSB is output, the transmission line holds the MSB state.
In synchronous mode, the SCI receives data in synchronization with the falling edge of the serial
clock.
Data Transfer Format
A fixed 8-bit data format is used. No parity or multiprocessor bits are added.
Clock
Either an internal clock generated by the on-chip baud rate generator or an external serial clock
input at the SCK pin can be selected, according to the setting of the C/
bit in SCSMR1 and the
CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. In reception only, if an on-chip clock source is selected, clock
pulses are output while RE = 1. When the last data is received, RE should be cleared to 0 before
the end of bit 7.
Data Transfer Operations
SCI Initialization (Synchronous Mode): Before transmitting and receiving data, it is necessary
to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change
the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1.
Figure 15.18 shows a sample SCI initialization flowchart.
Rev. 3.0, 04/02, page 620 of 1064
Set data transfer format
in SCSMR1
1-bit interval elapsed?
End
No
Wait
Yes
Set TE and RE bits in SCSCR1
to 1, and set RIE, TIE, TEIE,
and MPIE bits
Set value in SCBRR1
Set RIE, TIE, TEIE, MPIE, CKE1
and CKE0 bits in SCSCR1
(leaving TE and RE bits
cleared to 0)
Clear TE and RE bits
in SCSCR1 to 0
Initialization
1. Set the clock selection in SCSCR1.
Be sure to clear bits RIE, TIE, TEIE,
and MPIE, TE and RE, to 0.
2. Set the data transfer format in
SCSMR1.
3. Write a value corresponding to the bit
rate into SCBRR1. (Not necessary if
an external clock is used.)
4. Wait at least one bit interval, then set
the TE bit or RE bit in SCSCR1 to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits. Setting the TE and RE bits
enables the TxD and RxD pins to be
used.
Figure 15.18 Sample SCI Initialization Flowchart
Rev. 3.0, 04/02, page 621 of 1064
Serial Data Transmission (Synchronous Mode): Figure 15.19 shows a sample flowchart for
serial transmission.
Use the following procedure for serial data transmission after enabling the SCI for transmission.
Start of transmission
Read TDRE flag in SCSSR1
TDRE = 1?
All data transmitted?
Read TEND flag in SCSSR1
Clear TE bit in SCSCR1 to 0
End
TEND = 1?
No
Yes
No
Yes
Yes
No
Write transmit data to SCTDR1
and clear TDRE flag
in SCSSR1 to 0
1. SCI status check and transmit
data write: Read SCSSR1 and
check that the TDRE flag is set to
1, then write transmit data to
SCTDR1 and clear the TDRE flag
to 0.
2. To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to
SCTDR1, and then clear the
TDRE flag to 0. (Checking and
clearing of the TDRE flag is
automatic when the direct
memory access controller
(DMAC) is activated by a
transmit-data-empty interrupt
(TXI) request, and data is written
to SCTDR1.)
Figure 15.19 Sample Serial Transmission Flowchart
Rev. 3.0, 04/02, page 622 of 1064
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes
that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.
2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI)
request is generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with
the MSB (bit 7).
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, and serial
transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the MSB (bit 7) is sent, and
the TxD pin maintains its state.
If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is
generated.
4. After completion of serial transmission, the SCK pin is fixed high.
Figure 15.20 shows an example of SCI operation in transmission.
LSB
MSB
TDRE
TEND
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
Serial clock
Serial data
Transfer
direction
TXI interrupt
request
Data written to SCTDR1
and TDRE flag cleared to
0 in TXI interrupt handler
TEI interrupt
request
One frame
TXI interrupt
request
Figure 15.20 Example of SCI Transmit Operation
Rev. 3.0, 04/02, page 623 of 1064
Serial Data Reception (Synchronous Mode): Figure 15.21 shows a sample flowchart for serial
reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
When changing the operating mode from asynchronous to synchronous, be sure to check that the
ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER
flag is set to 1, and neither transmit nor receive operations will be possible.
Start of reception
Read ORER flag in SCSSR1
ORER = 1?
Read RDRF flag in SCSSR1
RDRF = 1?
Read receive data in SCRDR1,
and clear RDRF flag
in SCSSR1 to 0
All data received?
Clear RE bit in SCSCR1 to 0
End of reception
Yes
No
Yes
Yes
No
No
Error handling
1. Receive error handling: If a
receive error occurs, read the
ORER flag in SCSSR1 , and
after performing the appropriate
error handling, clear the ORER
flag to 0. Transfer cannot be
resumed if the ORER flag is set
to 1.
2. SCI status check and receive
data read: Read SCSSR1 and
check that the RDRF flag is set
to 1, then read the receive data
in SCRDR1 and clear the RDRF
flag to 0. Transition of the RDRF
flag from 0 to 1 can also be
identified by an RXI interrupt.
3. Serial reception continuation
procedure: To continue serial
reception, finish reading the
RDRF flag, reading SCRDR1,
and clearing the RDRF flag to 0,
before the MSB (bit 7) of the
current frame is received. (The
RDRF flag is cleared
automatically when the direct
memory access controller
(DMAC) is activated by a
receive-data-full interrupt (RXI)
request and the SCRDR1 value
is read.)
Figure 15.21 Sample Serial Reception Flowchart (1)
Rev. 3.0, 04/02, page 624 of 1064
Error handling
Overrun error handling
Clear ORER flag in SCSSR1 to 0
ORER = 1?
End
Yes
No
Figure 15.21 Sample Serial Reception Flowchart (2)
In serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with serial clock input or output.
2. The received data is stored in SCRSR1 in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0, indicating that the receive data
can be transferred from SCRSR1 to SCRDR1.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If
a receive error is detected in the error check, the operation is as shown in table 15.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
Also, as the RDRF flag is not set to 1 when receiving, the flag must be cleared to 0.
3. If the RIE bit in SCRSR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full
interrupt (RXI) request is generated. If the RIE bit in SCRSR1 is set to 1 when the ORER flag
changes to 1, a receive-error interrupt (ERI) request is generated.
Figure 15.22 shows an example of SCI operation in reception.
Rev. 3.0, 04/02, page 625 of 1064
RDRF
ORER
Transfer
direction
Serial clock
Serial data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RXI interrupt
request
Data read from
SCRDR1 and RDRF
flag cleared to 0 in RXI
interrupt handler
One frame
RXI interrupt
request
ERI interrupt
request due to
overrun error
Figure 15.22 Example of SCI Receive Operation
Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.23
shows a sample flowchart for simultaneous serial transmit and receive operations.
Use the following procedure for simultaneous serial data transmit and receive operations after
enabling the SCI for transmission and reception.
Rev. 3.0, 04/02, page 626 of 1064
Read TDRE flag in SCSSR1
TDRE = 1?
Write transmit data
to SCTDR1 and clear TDRE flag
in SCSSR1 to 0
Read ORER flag in SCSSR1
ORER = 1?
Error handling
Read RDRF flag in SCSSR1
RDRF = 1?
Read receive data in SCRDR1,
and clear RDRF flag
in SCSSR1 to 0
All data transferred?
Clear TE and RE bits
in SCRSR1 to 0
End of transmission/reception
Start of transmission/reception
No
Yes
Yes
No
No
Yes
Yes
No
1. SCI status check and transmit data
write:
Read SCSSR1 and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR1 and clear
the TDRE flag to 0. Transition of the
TDRE flag from 0 to 1 can also be
identified by a TXI interrupt.
2. Receive error handling:
If a receive error occurs, read the
ORER flag in SCSSR1 , and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
3. SCI status check and receive data
read:
Read SCSSR1 and check that the
RDRF flag is set to 1, then read the
receive data in SCRDR1 and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
4. Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, finish reading the RDRF
flag, reading SCRDR1, and clearing
the RDRF flag to 0, before the MSB
(bit 7) of the current frame is received.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR1 and clear the TDRE flag to
0.
(Checking and clearing of the TDRE
flag is automatic when the DMAC is
activated by a transmit-data-empty
interrupt (TXI) request, and data is
written to SCTDR1. Similarly, the
RDRF flag is cleared automatically
when the DMAC is activated by a
receive-data-full interrupt (RXI)
request and the SCRDR1 value is
read.)
Note: When switching from transmit or receive operation to simultaneous transmit and receive
operations, first clear the TE bit and RE bit to 0, then set both these bits to 1.
Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception
Rev. 3.0, 04/02, page 627 of 1064
15.4
SCI Interrupt Sources and DMAC
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request.
Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources
can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in
SCSPTR1. Each kind of interrupt request is sent to the interrupt controller independently.
When the TDRE flag in the serial status register (SCSSR1) is set to 1, a TDR-empty request is
generated separately from the interrupt request. A TDR-empty request can activate the direct
memory access controller (DMAC) to perform data transfer. The TDRE flag is cleared to 0
automatically when a write to the transmit data register (SCTDR1) is performed by the DMAC.
When the RDRF flag in SCSSR1 is set to 1, an RDR-full request is generated separately from the
interrupt request. An RDR-full request can activate the DMAC to perform data transfer.
The RDRF flag is cleared to 0 automatically when a receive data register (SCRDR1) read is
performed by the DMAC.
When the ORER, FER, or PER flag in SCSSR1 is set to 1, an ERI interrupt request is generated.
The DMAC cannot be activated by an ERI interrupt request. When receive data processing is to be
carried out by the DMAC and receive error handling is to be performed by means of an interrupt
to the CPU, set the RIE bit to 1 and also set the EIO bit in SCSPTR1 to 1 so that an interrupt error
occurs only for a receive error. If the EIO bit is cleared to 0, interrupts to the CPU will be
generated even during normal data reception.
When the TEND flag in SCSSR1 is set to 1, a TEI interrupt request is generated. The DMAC
cannot be activated by a TEI interrupt request.
A TXI interrupt indicates that transmit data can be written, and a TEI interrupt indicates that the
transmit operation has ended.
Table 15.12 SCI Interrupt Sources
Interrupt
Source
Description
DMAC
Activation
Priority on
Reset Release
ERI
Receive error (ORER, FER, or PER)
Not possible High
RXI
Receive data register full (RDRF)
Possible
TXI
Transmit data register empty (TDRE)
Possible
TEI
Transmit end (TEND)
Not possible Low
See section 5, Exceptions, for the priority order and relation to non-SCI interrupts.
Rev. 3.0, 04/02, page 628 of 1064
15.5
Usage Notes
The following points should be noted when using the SCI.
SCTDR1 Writing and the TDRE Flag: The TDRE flag in SCSSR1 is a status flag that indicates
that transmit data has been transferred from SCTDR1 to SCTSR1. When the SCI transfers data
from SCTDR1 to SCTSR1, the TDRE flag is set to 1.
Data can be written to SCTDR1 regardless of the state of the TDRE flag. However, if new data is
written to SCTDR1 when the TDRE flag is cleared to 0, the data stored in SCTDR1 will be lost
since it has not yet been transferred to SCTSR1. It is therefore essential to check that the TDRE
flag is set to 1 before writing transmit data to SCTDR1.
Simultaneous Multiple Receive Errors: If a number of receive errors occur at the same time, the
state of the status flags in SCSSR1 is as shown in table 15.13. If there is an overrun error, data is
not transferred from SCRSR1 to SCRDR1, and the receive data is lost.
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data
SCSSR1 Status Flags
Receive Errors
RDRF
ORER
FER
PER
Receive Data
Transfer
SCRSR1
SCRDR1
Overrun error
1
1
0
0
X
Framing error
0
0
1
0
O
Parity error
0
0
0
1
O
Overrun error + framing error
1
1
1
0
X
Overrun error + parity error
1
1
0
1
X
Framing error + parity error
0
0
1
1
O
Overrun error + framing error +
parity error
1
1
1
1
X
O: Receive data is transferred from SCRSR1 to SCRDR1.
X: Receive data is not transferred from SCRSR1 to SCRDR1.
Break Detection and Processing: Break signals can be detected by reading the RxD pin directly
when a framing error (FER) is detected. In the break state the input from the RxD pin consists of
all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that the SCI
receiver continues to operate in the break state, so if the FER flag is cleared to 0 it will be set to 1
again.
Rev. 3.0, 04/02, page 629 of 1064
Sending a Break Signal: The input/output condition and level of the TxD pin are determined by
bits SPB0IO and SPB0DT in the serial port register (SCSPTR1). This feature can be used to send
a break signal.
After the serial transmitter is initialized, the TxD pin function is not selected and the value of the
SPB0DT bit substitutes for the mark state until the TE bit is set to 1 (i.e. transmission is enabled).
The SPB0IO and SPB0DT bits should therefore be set to 1 (designating output and high level)
beforehand.
To send a break signal during serial transmission, clear the SPB0DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of its current state, and the TxD pin becomes an output port
outputting the value 0.
Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission
cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE
flag is set to 1. Be sure to clear the receive error flags to 0 before starting transmission.
Note also that the receive error flags are not cleared to 0 by clearing the RE bit to 0.
Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: The SCI
operates on a base clock with a frequency of 16 times the bit rate. In reception, the SCI
synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive
data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure
15.24.
Rev. 3.0, 04/02, page 630 of 1064
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
D0
D1
16 clocks
8 clocks
Base clock
Receive data
(RxD)
Start bit
7.5 clocks
+7.5 clocks
Synchronization
sampling timing
Data sampling
timing
Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 ) (L 0.5) F (1 + F)
100%
1
2N
| D 0.5 |
N
................ (1)
M: Receive margin (%)
N:
Ratio of clock frequency to bit rate (N = 16)
D:
Clock duty cycle (D = 0 to 1.0)
L:
Frame length (L = 9 to 12)
F:
Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 1/(2
16))
100% = 46.875% .......................................... (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 3.0, 04/02, page 631 of 1064
When Using the DMAC: When an external clock source is used as the serial clock, the transmit
clock should not be input until at least 5 peripheral operating clock cycles after SCTDR1 is
updated by the DMAC. Incorrect operation may result if the transmit clock is input within 4 cycles
after SCTDR1 is updated. (See figure 15.25)
SCK
TDRE
TxD
D0
D1
D2
D3
D4
D5
D6
D7
t
Note: When operating on an external clock, set t > 4.
Figure 15.25 Example of Synchronous Transmission by DMAC
When SCRDR1 is read by the DMAC, be sure to set the SCI receive-data-full interrupt (RXI) as
the activation source with bits RS3 to RS0 in CHCR.
When Using Synchronous External Clock Mode:
Do not set TE or RE to 1 until at least 4 peripheral operating clock cycles after external clock
SCK has changed from 0 to 1.
Only set both TE and RE to 1 when external clock SCK is 1.
In reception, note that if RE is cleared to 0 from 2.5 to 3.5 peripheral operating clock cycles
after the rising edge of the RxD D7 bit SCK input, RDRF will be set to 1 but copying to
SCRDR1 will not be possible.
When Using Synchronous Internal Clock Mode: In reception, note that if RE is cleared to zero
1.5 peripheral operating clock cycles after the rising edge of the RxD D7 bit SCK output, RDRF
will be set to 1 but copying to SCRDR1 will not be possible.
When Using DMAC: When using the DMAC for transmission/reception, make a setting to
suppress output of RXI and TXI interrupt requests to the interrupt controller. Even if a setting is
made to output interrupt requests, interrupt requests to the interrupt controller will be cleared by
the DMAC independently of the interrupt handling program.
Rev. 3.0, 04/02, page 632 of 1064
Rev. 3.0, 04/02, page 633 of 1064
Section 16 Serial Communication Interface with FIFO
(SCIF)
16.1
Overview
The SH7751 Series is equipped with a single-channel serial communication interface with built-in
FIFO buffers (Serial Communication Interface with FIFO: SCIF). The SCIF can perform
asynchronous serial communication.
Sixteen-stage FIFO registers are provided for both transmission and reception, enabling fast,
efficient, and continuous communication.
16.1.1
Features
SCIF features are listed below.
Asynchronous serial communication
Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character. Serial data communication can be carried
out with standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
There is a choice of 8 serial data transfer formats.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even/odd/none
Receive error detection: Parity, framing, and overrun errors
Break detection: If the receive data following that in which a framing error occurred is also
at the space "0" level, and there is a frame error, a break is detected. When a framing error
occurs, a break can also be detected by reading the RxD2 pin level directly from the serial
port register (SCSPTR2).
Full-duplex communication capability
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
On-chip baud rate generator allows any bit rate to be selected.
Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK2 pin
Rev. 3.0, 04/02, page 634 of 1064
Four interrupt sources
There are four interrupt sources--transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-error--that can issue requests independently.
The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
When not in use, the SCIF can be stopped by halting its clock supply to reduce power
consumption.
Modem control functions (
#%$ and %$) are provided.
The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
the receive data in the receive FIFO register, can be ascertained.
A timeout error (DR) can be detected during reception.
Rev. 3.0, 04/02, page 635 of 1064
16.1.2
Block Diagram
Figure 16.1 shows a block diagram of the SCIF.
Module data bus
SCFRDR2
(16-stage)
SCRSR2
RxD2
TxD2
SCK2
SCFTDR2
(16-stage)
SCTSR2
SCSMR2
SCLSR2
SCFDR2
SCFCR2
SCFSR2
SCBRR2
Parity generation
Parity check
Transmission/
reception
control
Baud rate
generator
Clock
External clock
P
P
/4
P
/16
P
/64
TXI
RXI
ERI
BRI
SCIF
Bus interface
Internal
data bus
SCSCR2
SCSPTR2
SCRSR2:
Receive shift register
SCFRDR2: Receive FIFO data register
SCTSR2:
Transmit shift register
SCFTDR2: Transmit FIFO data register
SCSMR2:
Serial mode register
SCSCR2:
Serial control register
SCFSR2:
Serial status register
SCBRR2:
Bit rate register
SCSPTR2: Serial port register
SCFCR2:
FIFO control register
SCFDR2:
FIFO data count register
SCLSR2:
Line status register
Figure 16.1 Block Diagram of SCIF
Rev. 3.0, 04/02, page 636 of 1064
16.1.3
Pin Configuration
Table 16.1 shows the SCIF pin configuration.
Table 16.1
SCIF Pins
Pin Name
Abbreviation
I/O
Function
Serial clock pin
MD0/SCK2
I/O
Clock input/output
Receive data pin
MD2/RxD2
Input
Receive data input
Transmit data pin
MD1/TxD2
Output
Transmit data output
Modem control pin
MD7/
%$
I/O
Transmission enabled
Modem control pin
MD8/
#%$
I/O
Transmission request
Note: These pins function as the MD0, MD1, MD2, MD7, and MD8 mode input pins after a power-
on reset. These pins are made to function as serial pins by performing SCIF operation
settings with the TE, RE, CKE1, and CKE0 bits in SCSCR2 and the MCE bit in SCFCR2.
Break state transmission and detection can be set in the SCIF's SCSPTR2 register.
16.1.4
Register Configuration
The SCIF has the internal registers shown in table 16.2. These registers are used to specify the
data format and bit rate, and to perform transmitter/receiver control.
Table 16.2
SCIF Registers
Name
Abbrevia-
tion
R/W
Initial
Value
P4
Address
Area 7
Address
Access
Size
Serial mode register
SCSMR2
R/W
H'0000
H'FFE80000 H'IFE80000 16
Bit rate register
SCBRR2
R/W
H'FF
H'FFE80004 H'IFE80004 8
Serial control register
SCSCR2
R/W
H'0000
H'FFE80008 H'IFE80008 16
Transmit FIFO data register SCFTDR2
W
Undefined H'FFE8000C H'IFE8000C 8
Serial status register
SCFSR2
R/(W)*
1
H'0060
H'FFE80010 H'IFE80010 16
Receive FIFO data register SCFRDR2 R
Undefined H'FFE80014 H'IFE80014 8
FIFO control register
SCFCR2
R/W
H'0000
H'FFE80018 H'IFE80018 16
FIFO data count register
SCFDR2
R
H'0000
H'FFE8001C H'IFE8001C 16
Serial port register
SCSPTR2
R/W
H'0000*
2
H'FFE80020 H'IFE80020 16
Line status register
SCLSR2
R/(W)*
3
H'0000
H'FFE80024 H'IFE80024 16
Notes: *1 Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot be
modified.
*2 The value of bits 6, 4, 2, and 0 is undefined.
*3 Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified.
Rev. 3.0, 04/02, page 637 of 1064
16.2
Register Descriptions
16.2.1
Receive Shift Register (SCRSR2)
Bit:
7
6
5
4
3
2
1
0
R/W:
--
--
--
--
--
--
--
--
SCRSR2 is the register used to receive serial data.
The SCIF sets serial data input from the RxD2 pin in SCRSR2 in the order received, starting with
the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to the receive FIFO register, SCFRDR2, automatically.
SCRSR2 cannot be directly read or written to by the CPU.
16.2.2
Receive FIFO Data Register (SCFRDR2)
Bit:
7
6
5
4
3
2
1
0
R/W:
R
R
R
R
R
R
R
R
SCFRDR2 is a 16-stage FIFO register that stores received serial data.
When the SCIF has received one byte of serial data, it transfers the received data from SCRSR2 to
SCFRDR2 where it is stored, and completes the receive operation. SCRSR2 is then enabled for
reception, and consecutive receive operations can be performed until the receive FIFO register is
full (16 data bytes).
SCFRDR2 is a read-only register, and cannot be written to by the CPU.
If a read is performed when there is no receive data in the receive FIFO register, an undefined
value will be returned. When the receive FIFO register is full of receive data, subsequent serial
data is lost.
The contents of SCFRDR2 are undefined after a power-on reset or manual reset.
Rev. 3.0, 04/02, page 638 of 1064
16.2.3
Transmit Shift Register (SCTSR2)
Bit:
7
6
5
4
3
2
1
0
R/W:
--
--
--
--
--
--
--
--
SCTSR2 is the register used to transmit serial data.
To perform serial data transmission, the SCIF first transfers transmit data from SCFTDR2 to
SCTSR2, then sends the data to the TxD2 pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from SCFTDR2
to SCTSR2, and transmission started, automatically.
SCTSR2 cannot be directly read or written to by the CPU.
16.2.4
Transmit FIFO Data Register (SCFTDR2)
Bit:
7
6
5
4
3
2
1
0
R/W:
W
W
W
W
W
W
W
W
SCFTDR2 is a 16-stage FIFO register that stores data for serial transmission.
If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the
transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission.
SCFTDR2 is a write-only register, and cannot be read by the CPU.
The next data cannot be written when SCFTDR2 is filled with 16 bytes of transmit data. Data
written in this case is ignored.
The contents of SCFTDR2 are undefined after a power-on reset or manual reset.
Rev. 3.0, 04/02, page 639 of 1064
16.2.5
Serial Mode Register (SCSMR2)
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
--
CHR
PE
O/
STOP
--
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R/W
R
R/W
R/W
SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate
generator clock source.
SCSMR2 can be read or written to by the CPU at all times.
SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 7--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 6--Character Length (CHR): Selects 7 or 8 bits as the asynchronous mode data length.
Bit 6: CHR
Description
0
8-bit data
(Initial value)
1
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of SCFTDR2 is not transmitted.
Bit 5--Parity Enable (PE): Selects whether or not parity bit addition is performed in
transmission, and parity bit checking in reception.
Bit 5: PE
Description
0
Parity bit addition and checking disabled
(Initial value)
1
Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/
bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity (even
or odd) specified by the O/
bit.
Bit 4--Parity Mode (O/
): Selects either even or odd parity for use in parity addition and
checking. The O/
bit setting is only valid when the PE bit is set to 1, enabling parity bit addition
and checking. The O/
bit setting is invalid when parity addition and checking is disabled.
Rev. 3.0, 04/02, page 640 of 1064
Bit 4: O/
Description
0
Even parity*
1
(Initial value)
1
Odd parity*
2
Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
*2 When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length.
Bit 3: STOP
Description
0
1 stop bit*
1
(Initial value)
1
2 stop bits*
2
Notes: *1 In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
before it is sent.
*2 In transmission, two 1-bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2--Reserved: This bit is always read as 0, and should only be written with 0.
Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on-
chip baud rate generator. The clock source can be selected from P
, P
/4, P
/16, and P
/64,
according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 16.2.8, Bit Rate Register (SCBRR2).
Bit 1: CKS1
Bit 0: CKS0
Description
0
0
P
clock
(Initial value)
1
P
/4 clock
1
0
P
/16 clock
1
P
/64 clock
Note: P
: Peripheral clock
Rev. 3.0, 04/02, page 641 of 1064
16.2.6
Serial Control Register (SCSCR2)
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
REIE
--
CKE1
CKE0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
The SCSCR2 register performs enabling or disabling of SCIF transfer operations, serial clock
output, and interrupt requests, and selection of the serial clock source.
SCSCR2 can be read or written to by the CPU at all times.
SCSCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 8, and 2--Reserved: These bits are always read as 0, and should only be written with
0.
Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty
interrupt (TXI) request generation when serial transmit data is transferred from SCFTDR2 to
SCTSR2, the number of data bytes in the transmit FIFO register falls to or below the transmit
trigger set number, and the TDFE flag in the serial status register (SCFSR2) is set to 1.
Bit 7: TIE
Description
0
Transmit-FIFO-data-empty interrupt (TXI) request disabled*
(Initial value)
1
Transmit-FIFO-data-empty interrupt (TXI) request enabled
Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit trigger
set number to SCFTDR2 after reading 1 from the TDFE flag, then clearing it to 0, or by
clearing the TIE bit to 0.
Bit 6--Receive Interrupt Enable (RIE): Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag in SCFSR2 is set to 1, a receive-error
interrupt (ERI) request when the ER flag in SCFSR2 is set to 1, and a break interrupt (BRI)
request when the BRK flag in SCFSR2 or the ORER flag in SCLSR2 is set to 1.
Rev. 3.0, 04/02, page 642 of 1064
Bit 6: RIE
Description
0
Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request disabled*
(Initial value)
1
Receive-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request enabled
Note: * An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag, then
clearing the flag to 0, or by clearing the RIE bit to 0. ERI and BRI interrupt requests can be
cleared by reading 1 from the ER, BRK, or ORER flag, then clearing the flag to 0, or by
clearing the RIE and REIE bits to 0.
Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF.
Bit 5: TE
Description
0
Transmission disabled
(Initial value)
1
Transmission enabled*
Note: * Serial transmission is started when transmit data is written to SCFTDR2 in this state.
Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be
made, the transmission format decided, and the transmit FIFO reset, before the TE bit is set
to 1.
Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCIF.
Bit 4: RE
Description
0
Reception disabled*
1
(Initial value)
1
Reception enabled*
2
Notes: *1 Clearing the RE bit to 0 does not affect the DR, ER, BRK, RDF, FER, PER, and ORER
flags, which retain their states.
*2 Serial transmission is started when a start bit is detected in this state.
Serial mode register (SCSMR2) and FIFO control register (SCFCR2) settings must be
made, the reception format decided, and the receive FIFO reset, before the RE bit is set
to 1.
Rev. 3.0, 04/02, page 643 of 1064
Bit 3--Receive Error Interrupt Enable (REIE): Enables or disables generation of receive-error
interrupt (ERI) and break interrupt (BRI) requests. The REIE bit setting is valid only when the
RIE bit is 0.
Bit 3: REIE
Description
0
Receive-error interrupt (ERI) and break interrupt (BRI) requests disabled*
(Initial value)
1
Receive-error interrupt (ERI) and break interrupt (BRI) requests enabled
Note: * Receive-error interrupt (ERI) and break interrupt (BRI) requests can be cleared by reading 1
from the ER, BRK, or ORER flag, then clearing the flag to 0, or by clearing the RIE and
REIE bits to 0. When REIE is set to 1, ERI and BRI interrupt requests will be generated
even if RIE is cleared to 0. In DMAC transfer, this setting is made if the interrupt controller is
to be notified of ERI and BRI interrupt requests.
Bits 1 and 0: Clock Enable 1 and 0 (CKE1 and CKE0): These bits select the SCIF clock source
and enable/disable clock output from the SCK2 pin. The combination of CKE1 and CKE0
determine whether the SCK2 pin functions as serial clock output pin or the serial clock input pin.
Note, however, that the setting of the CKE0 bit is valid only when CKE1 = 0 (internal clock
operation). When CKE1 = 1 (external clock), CKE0 is ignored. Also, be sure to set CKE1 and
CKE0 prior to determining the SCIF operating mode with SCSMR2.
Bit 1: CKE1
Bit 0: CKE0
Description
0
0
Internal clock/SCK pin functions as port (Initial value)
1
Internal clock/SCK2 pin functions as clock output*
1
1
0
External clock/SCK2 pin functions as clock input*
2
1
External clock/SCK2 pin functions as clock input*
2
Notes: *1 Outputs a clock with a frequency 16 times the bit rate.
*2 Inputs a clock with a frequency 16 times the bit rate.
Rev. 3.0, 04/02, page 644 of 1064
16.2.7
Serial Status Register (SCFSR2)
Bit:
15
14
13
12
11
10
9
8
PER3
PER2
PER1
PER0
FER3
FER2
FER1
FER0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
ER
TEND
TDFE
BRK
FER
PER
RDF
DR
Initial value:
0
1
1
0
0
0
0
0
R/W:
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/(W)*
R/(W)*
Note: * Only 0 can be written, to clear the flag.
SCFSR2 is a 16-bit register. The lower 8 bits consist of status flags that indicate the operating
status of the SCIF, and the upper 8 bits indicate the number of receive errors in the data in the
receive FIFO register.
SCFSR2 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
ER, TEND, TDFE, BRK, RDF, and DR. Also note that in order to clear these flags they must be
read as 1 beforehand. The FER flag and PER flag are read-only flags and cannot be modified.
SCFSR2 is initialized to H'0060 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 12--Number of Parity Errors (PER3PER0): These bits indicate the number of data
bytes in which a parity error occurred in the receive data stored in SCFRDR2.
After the ER bit in SCFSR2 is set, the value indicated by bits 15 to 12 is the number of data bytes
in which a parity error occurred.
If all 16 bytes of receive data in SCFRDR2 have parity errors, the value indicated by bits PER3 to
PER0 will be 0.
Bits 11 to 8--Number of Framing Errors (FER3FER0): These bits indicate the number of
data bytes in which a framing error occurred in the receive data stored in SCFRDR2.
After the ER bit in SCFSR2 is set, the value indicated by bits 11 to 8 is the number of data bytes in
which a framing error occurred.
If all 16 bytes of receive data in SCFRDR2 have framing errors, the value indicated by bits FER3
to FER0 will be 0.
Rev. 3.0, 04/02, page 645 of 1064
Bit 7--Receive Error (ER): Indicates that a framing error or parity error occurred during
reception.*
Note: * The ER flag is not affected and retains its previous state when the RE bit in SCSCR2 is
cleared to 0. When a receive error occurs, the receive data is still transferred to SCFRDR2,
and reception continues.
The FER and PER bits in SCFSR2 can be used to determine whether there is a receive
error in the data read from SCFRDR2.
Bit 7: ER
Description
0
No framing error or parity error occurred during reception
(Initial value)
[Clearing conditions]
Power-on reset or manual reset
When 0 is written to ER after reading ER = 1
1
A framing error or parity error occurred during reception
[Setting conditions]
When the SCIF checks whether the stop bit at the end of the receive
data is 1 when reception ends, and the stop bit is 0*
When, in reception, the number of 1-bits in the receive data plus the
parity bit does not match the parity setting (even or odd) specified by the
O/
bit in SCSMR2
Note: * In 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is
not checked.
Rev. 3.0, 04/02, page 646 of 1064
Bit 6--Transmit End (TEND): Indicates that there is no valid data in SCFTDR2 when the last
bit of the transmit character is sent, and transmission has been ended.
Bit 6: TEND
Description
0
Transmission is in progress
[Clearing conditions]
When transmit data is written to SCFTDR2, and 0 is written to TEND
after reading TEND = 1
When data is written to SCFTDR2 by the DMAC
1
Transmission has been ended
(Initial value)
[Setting conditions]
Power-on reset or manual reset
When the TE bit in SCSCR2 is 0
When there is no transmit data in SCFTDR2 on transmission of the last
bit of a 1-byte serial transmit character
Rev. 3.0, 04/02, page 647 of 1064
Bit 5--Transmit FIFO Data Empty (TDFE): Indicates that data has been transferred from
SCFTDR2 to SCTSR2, the number of data bytes in SCFTDR2 has fallen to or below the transmit
trigger data number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR2), and
new transmit data can be written to SCFTDR2.
Bit 5: TDFE
Description
0
A number of transmit data bytes exceeding the transmit trigger set number
have been written to SCFTDR2
[Clearing conditions]
When transmit data exceeding the transmit trigger set number is written
to SCFTDR2 after reading TDFE = 1, and 0 is written to TDFE
When transmit data exceeding the transmit trigger set number is written
to SCFTDR2 by the DMAC
1
The number of transmit data bytes in SCFTDR2 does not exceed the
transmit trigger set number
(Initial value)
[Setting conditions]
Power-on reset or manual reset
When the number of SCFTDR2 transmit data bytes falls to or below the
transmit trigger set number as the result of a transmit operation*
Note: * As SCFTDR2 is a 16-byte FIFO register, the maximum number of bytes that can be written
when TDFE = 1 is 16 - (transmit trigger set number). Data written in excess of this will be
ignored.
The number of data bytes in SCFTDR2 is indicated by the upper bits of SCFDR2.
Bit 4--Break Detect (BRK): Indicates that a receive data break signal has been detected.
Bit 4: BRK
Description
0
A break signal has not been received
(Initial value)
[Clearing conditions]
Power-on reset or manual reset
When 0 is written to BRK after reading BRK = 1
1
A break signal has been received*
[Setting condition]
When data with a framing error is received, followed by the space "0" level
(low level ) for at least one frame length
Note: * When a break is detected, the receive data (H'00) following detection is not transferred to
SCFRDR2. When the break ends and the receive signal returns to mark "1", receive data
transfer is resumed.
Rev. 3.0, 04/02, page 648 of 1064
Bit 3--Framing Error (FER): Indicates whether or not a framing error has been found in the
data that is to be read from the receive FIFO data register (SCFRDR2).
Bit 3: FER
Description
0
There is no framing error in the receive data that is to be read from
SCFRDR2
(Initial value)
[Clearing conditions]
Power-on reset or manual reset
When there is no framing error in the data that is to be read next from
SCFRDR2
1
There is a framing error in the receive data that is to be read from
SCFRDR2
[Setting condition]
When there is a framing error in the data that is to be read next from
SCFRDR2
Bit 2--Parity Error (PER): Indicates whether or not a parity error has been found in the data that
is to be read from the receive FIFO data register (SCFRDR2).
Bit 2: PER
Description
0
There is no parity error in the receive data that is to be read from SCFRDR2
(Initial value)
[Clearing conditions]
Power-on reset or manual reset
When there is no parity error in the data that is to be read next from
SCFRDR2
1
There is a parity error in the receive data that is to be read from SCFRDR2
[Setting condition]
When there is a parity error in the data that is to be read next from
SCFRDR2
Rev. 3.0, 04/02, page 649 of 1064
Bit 1--Receive FIFO Data Full (RDF): Indicates that the received data has been transferred
from SCRSR2 to SCFRDR2, and the number of receive data bytes in SCFRDR2 is equal to or
greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO control
register (SCFCR2).
Bit 1: RDF
Description
0
The number of receive data bytes in SCFRDR2 is less than the receive
trigger set number
(Initial value)
[Clearing conditions]
Power-on reset or manual reset
When SCFRDR2 is read until the number of receive data bytes in
SCFRDR2 falls below the receive trigger set number after reading RDF
= 1, and 0 is written to RDF
When SCFRDR2 is read by the DMAC until the number of receive data
bytes in SCFRDR2 falls below the receive trigger set number
1
The number of receive data bytes in SCFRDR2 is equal to or greater than
the receive trigger set number
[Setting condition]
When SCFRDR2 contains at least the receive trigger set number of receive
data bytes*
Note: * SCFRDR2 is a 16-byte FIFO register. When RDF = 1, at least the receive trigger set
number of data bytes can be read. If all the data in SCFRDR2 is read and another read is
performed, the data value will be undefined. The number of receive data bytes in SCFRDR2
is indicated by the lower bits of SCFDR2.
Rev. 3.0, 04/02, page 650 of 1064
Bit 0--Receive Data Ready (DR): Indicates that there are fewer than the receive trigger set
number of data bytes in SCFRDR2, and no further data has arrived for at least 15 etu after the stop
bit of the last data received.
Bit 0: DR
Description
0
Reception is in progress or has ended normally and there is no receive data
left in SCFRDR2
(Initial value)
[Clearing conditions]
Power-on reset or manual reset
When all the receive data in SCFRDR2 has been read after reading DR
= 1, and 0 is written to DR
When all the receive data in SCFRDR2 has been read by the DMAC
1
No further receive data has arrived
[Setting condition]
When SCFRDR2 contains fewer than the receive trigger set number of
receive data bytes, and no further data has arrived for at least 15 etu after
the stop bit of the last data received*
Note: * Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.
etu: Elementary time unit (time for transfer of 1 bit)
16.2.8
Bit Rate Register (SCBRR2)
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SCSMR2.
SCBRR2 can be read or written to by the CPU at all times.
SCBRR2 is initialized to H'FF by a power-on reset or manual reset. It is not initialized in standby
mode or in the module standby state.
Rev. 3.0, 04/02, page 651 of 1064
The SCBRR2 setting is found from the following equation.
Asynchronous mode:
N =
10
6
1
64
2
2n1
B
P
Where B:
Bit rate (bits/s)
N:
SCBRR2 setting for baud rate generator (0
N
255)
P
: Peripheral module operating frequency (MHz)
n:
Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SCSMR2 Setting
n
Clock
CKS1
CKS0
0
P
0
0
1
P
/4
0
1
2
P
/16
1
0
3
P
/64
1
1
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
1
100
P
10
6
(N + 1)
B
64
2
2n1
16.2.9
FIFO Control Register (SCFCR2)
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
RSTRG2 RSTRG1 RSTRG0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
RTRG1
RTRG0
TTRG1
TTRG0
MCE
TFRST
RFRST
LOOP
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR2 can be read or written to by the CPU at all times.
Rev. 3.0, 04/02, page 652 of 1064
SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 11--Reserved: These bits are always read as 0, and should only be written with 0.
Bits 10, 9 and 8--
#
#%$
%$ Output Active Trigger (RSTRG2, RSTG1, and RSTG0): These bits
output the high level to the
#%$ signal when the number of received data stored in the receive
FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the table below.
Bit 10: RSTRG2
Bit 9: RSTRG1
Bit 8: RSTRG0
#%$
#%$
Output Active Trigger
0
0
0
15
(Initial value)
1
1
1
0
4
1
6
1
0
0
8
1
10
1
0
12
1
14
Bits 7 and 6--Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to
set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status
register (SCFSR2).
The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than
the trigger set number shown in the following table.
Bit 7: RTRG1
Bit 6: RTRG0
Receive Trigger Number
0
0
1
(Initial value)
1
4
1
0
8
1
14
Rev. 3.0, 04/02, page 653 of 1064
Bits 5 and 4--Transmit FIFO Data Number Trigger (TTRG1, TTRG0): These bits are used
to set the number of remaining transmit data bytes that sets the transmit FIFO data register empty
(TDFE) flag in the serial status register (SCFSR2). The TDFE flag is set when the number of
transmit data bytes in SCFTDR2 is equal to or less than the trigger set number shown in the
following table.
Bit 5: TTRG1
Bit 4: TTRG0
Transmit Trigger Number
0
0
8 (8)
(Initial value)
1
4 (12)
1
0
2 (14)
1
1 (15)
Note: Figures in parentheses are the number of empty bytes in SCFTDR2 when the flag is set.
Bit 3--Modem Control Enable (MCE): Enables the
%$ and #%$ modem control signals.
Bit 3: MCE
Description
0
Modem signals disabled*
(Initial value)
1
Modem signals enabled
Note: *
%$
is fixed at active-0 regardless of the input value, and
#%$
output is also fixed at 0.
Bit 2--Transmit FIFO Data Register Reset (TFRST): Invalidates the transmit data in the
transmit FIFO data register and resets it to the empty state.
Bit 2: TFRST
Description
0
Reset operation disabled*
(Initial value)
1
Reset operation enabled
Note: * A reset operation is performed in the event of a power-on reset or manual reset.
Bit 1--Receive FIFO Data Register Reset (RFRST): Invalidates the receive data in the receive
FIFO data register and resets it to the empty state.
Bit 1: RFRST
Description
0
Reset operation disabled*
(Initial value)
1
Reset operation enabled
Note: * A reset operation is performed in the event of a power-on reset or manual reset.
Rev. 3.0, 04/02, page 654 of 1064
Bit 0--Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive
input pin (RxD2), and the
#%$ pin and %$ pin, enabling loopback testing.
Bit 0: LOOP
Description
0
Loopback test disabled
(Initial value)
1
Loopback test enabled
16.2.10
FIFO Data Count Register (SCFDR2)
SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and
SCFRDR2.
The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show
the number of receive data bytes in SCFRDR2.
SCFDR2 can be read by the CPU at all times.
Bit:
15
14
13
12
11
10
9
8
--
--
--
T4
T3
T2
T1
T0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates
that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data.
Bit:
7
6
5
4
3
2
1
0
--
--
--
R4
R3
R2
R1
R0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that
there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data.
Rev. 3.0, 04/02, page 655 of 1064
16.2.11
Serial Port Register (SCSPTR2)
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
RTSIO
RTSDT
CTSIO
CTSDT
SCKIO
SCKDT
SPB2IO SPB2DT
Initial value:
0
--
0
--
0
--
0
--
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCSPTR2 is a 16-bit readable/writable register that controls input/output and data for the port pins
multiplexed with the serial communication interface with FIFO (SCIF) pins. Input data can be
read from the RxD2 pin, output data written to the TxD2 pin, and breaks in serial
transmission/reception controlled, by means of bits 1 and 0. Data can be read from, and output
data written to, the SCK2 pin by means of bits 3 and 2. Data can be read from, and output data
written to, the
%$ pin by means of bits 5 and 4. Data can be read from, and output data written
to, the
#%$ pin by means of bits 6 and 7.
SCSPTR2 can be read or written to by the CPU at all times. All SCSPTR2 bits except bits 6, 4, 2,
and 0 are initialized to 0 by a power-on reset or manual reset; the value of bits 6, 4, 2, and 0 is
undefined. SCSPTR2 is not initialized in standby mode or in the module standby state.
Bits 15 to 8--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 7--Serial Port RTS Port I/O (RTSIO): Specifies the serial port
#%$ pin input/output
condition. When the
#%$ pin is actually set as a port output pin and outputs the value set by the
RTSDT bit, the MCE bit in SCFCR2 should be cleared to 0.
Bit 7: RTSIO
Description
0
RTSDT bit value is not output to
#%$
pin
(Initial value)
1
RTSDT bit value is output to
#%$
pin
Bit 6--Serial Port RTS Port Data (RTSDT): Specifies the serial port
#%$ pin input/output
data. Input or output is specified by the RTSIO bit (see the description of bit 7, RTSIO, for
details). In output mode, the RTSDT bit value is output to the
#%$ pin. The #%$ pin value is
read from the RTSDT bit regardless of the value of the RTSIO bit. The initial value of this bit
after a power-on reset or manual reset is undefined.
Rev. 3.0, 04/02, page 656 of 1064
Bit 6: RTSDT
Description
0
Input/output data is low-level
1
Input/output data is high-level
Bit 5--Serial Port CTS Port I/O (CTSIO): Specifies the serial port
%$ pin input/output
condition. When the
%$ pin is actually set as a port output pin and outputs the value set by the
CTSDT bit, the MCE bit in SCFCR2 should be cleared to 0.
Bit 5: CTSIO
Description
0
CTSDT bit value is not output to
%$
pin
(Initial value)
1
CTSDT bit value is output to
%$
pin
Bit 4--Serial Port CTS Port Data (CTSDT): Specifies the serial port
%$ pin input/output
data. Input or output is specified by the CTSIO bit (see the description of bit 5, CTSIO, for
details). In output mode, the CTSDT bit value is output to the
%$ pin. The %$ pin value is
read from the CTSDT bit regardless of the value of the CTSIO bit. The initial value of this bit
after a power-on reset or manual reset is undefined.
Bit 4: CTSDT
Description
0
Input/output data is low-level
1
Input/output data is high-level
Bit 3--Serial Port Clock Port I/O (SCKIO): Sets the I/O for the SCK2 pin serial port. To
actually set the SCK2 pin as the port output pin and output the value set in the SCKDT bit, set the
CKE1 and CKE0 bits of the SCSCR2 register to 0.
Bit 3: SCKIO
Description
0
Shows that the value of the SCKDT bit is not output to the SCK2 pin
(Initial value)
1
Shows that the value of the SCKDT bit is output to the SCK2 pin.
Bit 2--Serial Port Clock Port Data (SCKDT): Specifies the I/O data for the SCK2 pin serial
port. The SCKIO bit specified input or output. (See bit 3: SCKIO, for details.) When set for
output, the value of the SCKDT bit is output to the SCK2 pin. Regardless of the value of the
SCKIO bit, the value of the SCK2 pin is fetched from the SCKDT bit. The initial value after a
power-on reset or manual reset is undefined.
Rev. 3.0, 04/02, page 657 of 1064
Bit 2: SCKDT
Description
0
Shows I/O data level is LOW
1
Shows I/O data level is HIGH
Bit 1--Serial Port Break I/O (SPB2IO): Specifies the serial port TxD2 pin output condition.
When the TxD2 pin is actually set as a port output pin and outputs the value set by the SPB2DT
bit, the TE bit in SCSCR2 should be cleared to 0.
Bit 1: SPB2IO
Description
0
SPB2DT bit value is not output to the TxD2 pin
(Initial value)
1
SPB2DT bit value is output to the TxD2 pin
Bit 0--Serial Port Break Data (SPB2DT): Specifies the serial port RxD2 pin input data and
TxD2 pin output data. The TxD2 pin output condition is specified by the SPB2IO bit (see the
description of bit 1, SPB2IO, for details). When the TxD2 pin is designated as an output, the value
of the SPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bit
regardless of the value of the SPB2IO bit. The initial value of this bit after a power-on reset or
manual reset is undefined.
Bit 0: SPB2DT
Description
0
Input/output data is low-level
1
Input/output data is high-level
Rev. 3.0, 04/02, page 658 of 1064
SCIF I/O port block diagrams are shown in figures 16.2 to 16.6.
Reset
Internal data bus
SPTRW
D7
D6
SCIF
R
Q
D
RTSIO
C
Reset
Mode setting
register
SPTRR
SPTRW
R
Q
D
RTSDT
C
MD8/RTS2
SPTRW: Write to SPTR
SPTRR: Read SPTR
Note: * The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2.
Modem control
enable signal*
RTS2 signal
Figure 16.2 MD8/RTS2 Pin
Rev. 3.0, 04/02, page 659 of 1064
Reset
Internal data bus
SPTRW
D5
D4
SCIF
R
Q
D
CTSIO
C
Reset
SPTRR
Mode setting register
SPTRW
R
Q
D
CTSDT
C
MD7/CTS2
SPTRW: Write to SPTR
SPTRR: Read SPTR
Note: * The CTS2 pin function is designated as modem control by the MCE bit in SCFCR2.
Modem control enable signal*
CTS2 signal
Figure 16.3 MD7/CTS2 Pin
Rev. 3.0, 04/02, page 660 of 1064
Reset
Internal data bus
SPTRW
Mode setting
register
SCIF
R
Q
D
D1
D0
SPB2IO
C
Reset
SPTRW
R
Q
D
SPB2DT
C
MD1/TxD2
SPTRW: Write to SPTR
Transmit enable
signal
Serial transmit data
Figure 16.4 MD1/TxD2 Pin
Internal data bus
Mode setting
register
SCIF
MD2/RxD2
SPTRR
D0
Serial receive
data
SPTRR: Read SPTR
Figure 16.5 MD2/RxD2 Pin
Rev. 3.0, 04/02, page 661 of 1064
Reset
Reset
Internal data bus
SPTRW
SPTRW
SCIF
R
Q
D
SCKIO
C
R
Q
D
SCKDT
C
SPTRR
Clock output enable signal
Serial clock output signal
Serial clock input signal
Clock input enable signal
*
MD0/SCK2
Mode setting
register
SPTRW: Write to SPTR
SPTRR: Read SPTR
Note: * Signals that set the SCK2 pin function as internal clock output or external clock input according to
the CKE0 and CKE1 bits in SCSCR2.
Figure 16.6 MD0/SCK2 Pin
Rev. 3.0, 04/02, page 662 of 1064
16.2.12
Line Status Register (SCLSR2)
Bit:
15
14
13
12
11
10
9
8
--
--
--
--
--
--
--
--
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
ORER
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
(R/W)*
Note: * Only 0 can be written, to clear the flag.
Bits 15 to 1--Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0--Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 0: ORER
Description
0
Reception in progress, or reception has ended normally*
1
(Initial value)
[Clearing conditions]
Power-on reset or manual reset
When 0 is written to ORER after reading ORER = 1
1
An overrun error occurred during reception*
2
[Setting condition]
When the next serial reception is completed while the receive FIFO is full
Notes: *1 The ORER flag is not affected and retains its previous state when the RE bit in
SCSCR2 is cleared to 0.
*2 The receive data prior to the overrun error is retained in SCFRDR2, and the data
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1.
Rev. 3.0, 04/02, page 663 of 1064
16.3
Operation
16.3.1
Overview
The SCIF can carry out serial communication in asynchronous mode, in which synchronization is
achieved character by character. See section 15.3.2, Operation in Asynchronous Mode, for details.
Sixteen-stage FIFO buffers are provided for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed.
#%$ and %$ signals
are also provided as modem control signals.
The transmission format is selected using the serial mode register (SCSMR2), as shown in table
16.3. The SCIF clock source is determined by the CKE1 bit in the serial control register
(SCSCR2), as shown in table 16.4.
Data length: Choice of 7 or 8 bits
Choice of parity addition and addition of 1 or 2 stop bits (the combination of these parameters
determines the transfer format and character length)
Detection of framing errors, parity errors, receive-FIFO-data-full state, overrun errors, receive-
data-ready state, and breaks, during reception
Indication of the number of data bytes stored in the transmit and receive FIFO registers
Choice of internal or external clock as SCIF clock source
When internal clock is selected: The SCIF operates on the baud rate generator clock, and a
clock with a frequency of 16 times the bit rate must be output
When external clock is selected: A clock with a frequency of 16 times the bit rate must be
input (the on-chip baud rate generator is not used).
Table 16.3
SCSMR2 Settings for Serial Transfer Format Selection
SCSMR2 Settings
SCIF Transfer Format
Bit 6:
CHR
Bit 5:
PE
Bit 3:
STOP
Mode
Data
Length
Multiprocessor
Bit
Parity
Bit
Stop Bit
Length
0
1 bit
0
1
No
2 bits
0
1 bit
0
1
1
8-bit data
Yes
2 bits
0
1 bit
0
1
No
2 bits
0
1 bit
1
1
1
Asynchronous mode
7-bit data
No
Yes
2 bits
Rev. 3.0, 04/02, page 664 of 1064
Table 16.4
SCSCR2 Settings for SCIF Clock Source Selection
SCSCR2 Setting
SCIF Transmit/Receive Clock
Bit 1: CKE1
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