Document Outline
- Cover
- Preface
- Revisions and Additions in this Edition
- Contents
- Section 1 Overview
- 1.1 Overview
- 1.2 Internal Block Diagram
- 1.3 Pin Arrangement and Functions
- 1.3.1 Pin Arrangement
- 1.3.2 Pin Functions in Each Operating Mode
- 1.3.3 Pin Functions
- Section 2 CPU
- 2.1 Overview
- 2.1.1 Features
- 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU
- 2.1.3 Differences from H8/300 CPU
- 2.1.4 Differences from H8/300H CPU
- 2.2 CPU Operating Modes
- 2.3 Address Space
- 2.4 Register Configuration
- 2.4.1 Overview
- 2.4.2 General Registers
- 2.4.3 Control Registers
- 2.4.4 Initial Register Values
- 2.5 Data Formats
- 2.5.1 General Register Data Formats
- 2.5.2 Memory Data Formats
- 2.6 Instruction Set
- 2.6.1 Overview
- 2.6.2 Instructions and Addressing Modes
- 2.6.3 Table of Instructions Classified by Function
- 2.6.4 Basic Instruction Formats
- 2.6.5 Notes on Use of Bit-Manipulation Instructions
- 2.7 Addressing Modes and Effective Address Calculation
- 2.7.1 Addressing Mode
- 2.7.2 Effective Address Calculation
- 2.8 Processing States
- 2.8.1 Overview
- 2.8.2 Reset State
- 2.8.3 Exception-Handling State
- 2.8.4 Program Execution State
- 2.8.5 Bus-Released State
- 2.8.6 Power-Down State
- 2.9 Basic Timing
- 2.9.1 Overview
- 2.9.2 On-Chip Memory (ROM, RAM)
- 2.9.3 On-Chip Supporting Module Access Timing
- 2.9.4 External Address Space Access Timing
- 2.10 Usage Notes
- 2.10.1 TAS Instruction
- 2.10.2 STM/LDM Instruction
- Section 3 MCU Operating Modes
- 3.1 Overview
- 3.1.1 Operating Mode Selection
- 3.1.2 Register Configuration
- 3.2 Register Descriptions
- 3.2.1 Mode Control Register (MDCR)
- 3.2.2 System Control Register (SYSCR)
- 3.2.3 Bus Control Register (BCR)
- 3.2.4 Serial/Timer Control Register (STCR)
- 3.3 Operating Mode Descriptions
- 3.3.1 Mode 1
- 3.3.2 Mode 2
- 3.3.3 Mode 3
- 3.4 Pin Functions in Each Operating Mode
- 3.5 Memory Map in Each Operating Mode
- Section 4 Exception Handling
- 4.1 Overview
- 4.1.1 Exception Handling Types and Priority
- 4.1.2 Exception Handling Operation
- 4.1.3 Exception Sources and Vector Table
- 4.2 Reset
- 4.2.1 Overview
- 4.2.2 Reset Sequence
- 4.2.3 Interrupts after Reset
- 4.3 Interrupts
- 4.4 Trap Instruction
- 4.5 Stack Status after Exception Handling
- 4.6 Notes on Use of the Stack
- Section 5 Interrupt Controller
- 5.1 Overview
- 5.1.1 Features
- 5.1.2 Block Diagram
- 5.1.3 Pin Configuration
- 5.1.4 Register Configuration
- 5.2 Register Descriptions
- 5.2.1 System Control Register (SYSCR)
- 5.2.2 Interrupt Control Registers A to C (ICRA to ICRC)
- 5.2.3 IRQ Enable Register (IER)
- 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
- 5.2.5 IRQ Status Register (ISR)
- 5.2.6 Address Break Control Register (ABRKCR)
- 5.2.7 Break Address Registers A, B, C (BARA, BARB, BARC)
- 5.3 Interrupt Sources
- 5.3.1 External Interrupts
- 5.3.2 Internal Interrupts
- 5.3.3 Interrupt Exception Vector Table
- 5.4 Address Breaks
- 5.4.1 Features
- 5.4.2 Block Diagram
- 5.4.3 Operation
- 5.4.4 Usage Notes
- 5.5 Interrupt Operation
- 5.5.1 Interrupt Control Modes and Interrupt Operation
- 5.5.2 Interrupt Control Mode 0
- 5.5.3 Interrupt Control Mode 1
- 5.5.4 Interrupt Exception Handling Sequence
- 5.5.5 Interrupt Response Times
- 5.6 Usage Notes
- 5.6.1 Contention between Interrupt Generation and Disabling
- 5.6.2 Instructions that Disable Interrupts
- 5.6.3 Interrupts during Execution of EEPMOV Instruction
- 5.7 DTC Activation by Interrupt
- 5.7.1 Overview
- 5.7.2 Block Diagram
- 5.7.3 Operation
- Section 6 Bus Controller
- 6.1 Overview
- 6.1.1 Features
- 6.1.2 Block Diagram
- 6.1.3 Pin Configuration
- 6.1.4 Register Configuration
- 6.2 Register Descriptions
- 6.2.1 Bus Control Register (BCR)
- 6.2.2 Wait State Control Register (WSCR)
- 6.3 Overview of Bus Control
- 6.4 Basic Bus Interface
- 6.3.1 Bus Specifications
- 6.3.2 Advanced Mode
- 6.3.3 Normal Mode
- 6.3.4 I/O Select Signal
- 6.4.1 Overview
- 6.4.2 Data Size and Data Alignment
- 6.4.3 Valid Strobes
- 6.4.4 Basic Timing
- 6.4.5 Wait Control
- 6.5 Burst ROM Interface
- 6.5.1 Overview
- 6.5.2 Basic Timing
- 6.5.3 Wait Control
- 6.6 Idle Cycle
- 6.6.1 Operation
- 6.6.2 Pin States in Idle Cycle
- 6.7 Bus Arbitration
- 6.7.1 Overview
- 6.7.2 Operation
- 6.7.3 Bus Transfer Timing
- Section 7 Data Transfer Controller [H8S/2128 Series]
- 7.1 Overview
- 7.1.1 Features
- 7.1.2 Block Diagram
- 7.1.3 Register Configuration
- 7.2 Register Descriptions
- 7.2.1 DTC Mode Register A (MRA)
- 7.2.2 DTC Mode Register B (MRB)
- 7.2.3 DTC Source Address Register (SAR)
- 7.2.4 DTC Destination Address Register (DAR)
- 7.2.5 DTC Transfer Count Register A (CRA)
- 7.2.6 DTC Transfer Count Register B (CRB)
- 7.2.7 DTC Enable Registers (DTCER)
- 7.2.8 DTC Vector Register (DTVECR)
- 7.2.9 Module Stop Control Register (MSTPCR)
- 7.3 Operation
- 7.3.1 Overview
- 7.3.2 Activation Sources
- 7.3.3 DTC Vector Table
- 7.3.4 Location of Register Information in Address Space
- 7.3.5 Normal Mode
- 7.3.6 Repeat Mode
- 7.3.7 Block Transfer Mode
- 7.3.8 Chain Transfer
- 7.3.9 Operation Timing
- 7.3.10 Number of DTC Execution States
- 7.3.11 Procedures for Using the DTC
- 7.3.12 Examples of Use of the DTC
- 7.4 Interrupts
- 7.5 Usage Notes
- Section 8 I/O Ports
- 8.1 Overview
- 8.2 Port 1
- 8.2.1 Overview
- 8.2.2 Register Configuration
- 8.2.3 Pin Functions in Each Mode
- 8.2.4 MOS Input Pull-Up Function
- 8.3 Port 2
- 8.3.1 Overview
- 8.3.2 Register Configuration
- 8.3.3 Pin Functions in Each Mode
- 8.3.4 MOS Input Pull-Up Function
- 8.4 Port 3
- 8.4.1 Overview
- 8.4.2 Register Configuration
- 8.4.3 Pin Functions in Each Mode
- 8.4.4 MOS Input Pull-Up Function
- 8.5 Port 4
- 8.5.1 Overview
- 8.5.2 Register Configuration
- 8.5.3 Pin Functions
- 8.6 Port 5
- 8.6.1 Overview
- 8.6.2 Register Configuration
- 8.6.3 Pin Functions
- 8.7 Port 6
- 8.7.1 Overview
- 8.7.2 Register Configuration
- 8.7.3 Pin Functions
- 8.8 Port 7
- 8.8.1 Overview
- 8.8.2 Register Configuration
- 8.8.3 Pin Functions
- Section 9 8-Bit PWM Timers [H8S/2128 Series]
- 9.1 Overview
- 9.1.1 Features
- 9.1.2 Block Diagram
- 9.1.3 Pin Configuration
- 9.1.4 Register Configuration
- 9.2 Register Descriptions
- 9.2.1 PWM Register Select (PWSL)
- 9.2.2 PWM Data Registers (PWDR0 to PWDR15)
- 9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)
- 9.2.5 Peripheral Clock Select Register (PCSR)
- 9.2.6 Port 1 Data Direction Register (P1DDR)
- 9.2.7 Port 2 Data Direction Register (P2DDR)
- 9.2.8 Port 1 Data Register (P1DR)
- 9.2.9 Port 2 Data Register (P2DR)
- 9.2.10 Module Stop Control Register (MSTPCR)
- 9.3 Operation
- 9.3.1 Correspondence between PWM Data Register Contents and Output Waveform
- Section 10 14-Bit PWM D/A
- 10.1 Overview
- 10.1.1 Features
- 10.1.2 Block Diagram
- 10.1.3 Pin Configuration
- 10.1.4 Register Configuration
- 10.2 Register Descriptions
- 10.2.1 PWM D/A Counter (DACNT)
- 10.2.2 D/A Data Registers A and B (DADRA and DADRB)
- 10.2.3 PWM D/A Control Register (DACR)
- 10.2.4 Module Stop Control Register (MSTPCR)
- 10.3 Bus Master Interface
- 10.4 Operation
- Section 11 16-Bit Free-Running Timer
- 11.1 Overview
- 11.1.1 Features
- 11.1.2 Block Diagram
- 11.1.3 Input and Output Pins
- 11.1.4 Register Configuration
- 11.2 Register Descriptions
- 11.2.1 Free-Running Counter (FRC)
- 11.2.2 Output Compare Registers A and B (OCRA, OCRB)
- 11.2.3 Input Capture Registers A to D (ICRA to ICRD)
- 11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF)
- 11.2.5 Output Compare Register DM (OCRDM)
- 11.2.6 Timer Interrupt Enable Register (TIER)
- 11.2.7 Timer Control/Status Register (TCSR)
- 11.2.8 Timer Control Register (TCR)
- 11.2.9 Timer Output Compare Control Register (TOCR)
- 11.2.10 Module Stop Control Register (MSTPCR)
- 11.3 Operation
- 11.3.1 FRC Increment Timing
- 11.3.2 Output Compare Output Timing
- 11.3.3 FRC Clear Timing
- 11.3.4 Input Capture Input Timing
- 11.3.5 Timing of Input Capture Flag (ICF) Setting
- 11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)
- 11.3.7 Setting of FRC Overflow Flag (OVF)
- 11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF
- 11.3.9 ICRD and OCRDM Mask Signal Generation
- 11.4 Interrupts
- 11.5 Sample Application
- 11.6 Usage Notes
- Section 12 8-Bit Timers
- 12.1 Overview
- 12.1.1 Features
- 12.1.2 Block Diagram
- 12.1.3 Pin Configuration
- 12.1.4 Register Configuration
- 12.2 Register Descriptions
- 12.2.1 Timer Counter (TCNT)
- 12.2.2 Time Constant Register A (TCORA)
- 12.2.3 Time Constant Register B (TCORB)
- 12.2.4 Timer Control Register (TCR)
- 12.2.5 Timer Control/Status Register (TCSR)
- 12.2.6 Serial/Timer Control Register (STCR)
- 12.2.7 System Control Register (SYSCR)
- 12.2.8 Timer Connection Register S (TCONRS)
- 12.2.9 Input Capture Register (TICR) [TMRX Additional Function]
- 12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]
- 12.2.11 Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions]
- 12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]
- 12.2.13 Module Stop Control Register (MSTPCR)
- 12.3 Operation
- 12.3.1 TCNT Incrementation Timing
- 12.3.2 Compare-Match Timing
- 12.3.3 TCNT External Reset Timing
- 12.3.4 Timing of Overflow Flag (OVF) Setting
- 12.3.5 Operation with Cascaded Connection
- 12.3.6 Input Capture Operation
- 12.4 Interrupt Sources
- 12.5 8-Bit Timer Application Example
- 12.6 Usage Notes
- 12.6.1 Contention between TCNT Write and Clear
- 12.6.2 Contention between TCNT Write and Increment
- 12.6.3 Contention between TCOR Write and Compare-Match
- 12.6.4 Contention between Compare-Matches A and B
- 12.6.5 Switching of Internal Clocks and TCNT Operation
- Section 13 Timer Connection [H8S/2128 Series]
- 13.1 Overview
- 13.1.1 Features
- 13.1.2 Block Diagram
- 13.1.3 Input and Output Pins
- 13.1.4 Register Configuration
- 13.2 Register Descriptions
- 13.2.1 Timer Connection Register I (TCONRI)
- 13.2.2 Timer Connection Register O (TCONRO)
- 13.2.3 Timer Connection Register S (TCONRS)
- 13.2.4 Edge Sense Register (SEDGR)
- 13.2.5 Module Stop Control Register (MSTPCR)
- 13.3 Operation
- 13.3.1 PWM Decoding (PDC Signal Generation)
- 13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)
- 13.3.3 Measurement of 8-Bit Timer Divided Waveform Period
- 13.3.4 IHI Signal and 2fH Modification
- 13.3.5 IVI Signal Fall Modification and IHI Synchronization
- 13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)
- 13.3.7 HSYNCO Output
- 13.3.8 VSYNCO Output
- Section 14 Watchdog Timer (WDT)
- 14.1 Overview
- 14.1.1 Features
- 14.1.2 Block Diagram
- 14.1.3 Pin Configuration
- 14.1.4 Register Configuration
- 14.2 Register Descriptions
- 14.2.1 Timer Counter (TCNT)
- 14.2.2 Timer Control/Status Register (TCSR)
- 14.2.3 System Control Register (SYSCR)
- 14.2.4 Notes on Register Access
- 14.3 Operation
- 14.3.1 Watchdog Timer Operation
- 14.3.2 Interval Timer Operation
- 14.3.3 Timing of Setting of Overflow Flag (OVF)
- 14.4 Interrupts
- 14.5 Usage Notes
- 14.5.1 Contention between Timer Counter (TCNT) Write and Increment
- 14.5.2 Changing Value of CKS2 to CKS0
- 14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode
- 14.5.4 Counter Value in Transitions between High-Speed Mode, Subactive Mode, and
Watch Mode
- Section 15 Serial Communication Interface (SCI)
- 15.1 Overview
- 15.1.1 Features
- 15.1.2 Block Diagram
- 15.1.3 Pin Configuration
- 15.1.4 Register Configuration
- 15.2 Register Descriptions
- 15.2.1 Receive Shift Register (RSR)
- 15.2.2 Receive Data Register (RDR)
- 15.2.3 Transmit Shift Register (TSR)
- 15.2.4 Transmit Data Register (TDR)
- 15.2.5 Serial Mode Register (SMR)
- 15.2.6 Serial Control Register (SCR)
- 15.2.7 Serial Status Register (SSR)
- 15.2.8 Bit Rate Register (BRR)
- 15.2.9 Serial Interface Mode Register (SCMR)
- 15.2.10 Module Stop Control Register (MSTPCR)
- 15.3 Operation
- 15.3.1 Overview
- 15.3.2 Operation in Asynchronous Mode
- 15.3.3 Multiprocessor Communication Function
- 15.3.4 Operation in Synchronous Mode
- 15.4 SCI Interrupts
- 15.5 Usage Notes
- Section 16 I
2
C Bus Interface (IIC) [H 8S /2128 S eries O ption]
- 16.1 Overview
- 16.1.1 Features
- 16.1.2 Block Diagram
- 16.1.3 Input/Output Pins
- 16.1.4 Register Configuration
- 16.2 Register Descriptions
- 16.2.1 I 2 C Bus Data Register (ICDR)
- 16.2.2 Slave Address Register (SAR)
- 16.2.3 Second Slave Address Register (SARX)
- 16.2.4 I 2 C Bus Mode Register (ICMR)
- 16.2.5 I 2 C Bus Control Register (ICCR)
- 16.2.6 I 2 C Bus Status Register (ICSR)
- 16.2.7 Serial/Timer Control Register (STCR)
- 16.2.8 DDC Switch Register (DDCSWR)
- 16.2.9 Module Stop Control Register (MSTPCR)
- 16.3 Operation
- 16.3.1 I 2 C Bus Data Format
- 16.3.2 Master Transmit Operation
- 16.3.3 Master Receive Operation
- 16.3.4 Slave Receive Operation
- 16.3.5 Slave Transmit Operation
- 16.3.6 IRIC Setting Timing and SCL Control
- 16.3.7 Automatic Switching from Formatless Mode to I 2 C Bus Format
- 16.3.8 Operation Using the DTC
- 16.3.9 Noise Canceler
- 16.4 Usage Notes
- Section 17 A/D Converter
- 17.1 Overview
- 17.1.1 Features
- 17.1.2 Block Diagram
- 17.1.3 Pin Configuration
- 17.1.4 Register Configuration
- 17.2 Register Descriptions
- 17.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
- 17.2.2 A/D Control/Status Register (ADCSR)
- 17.2.3 A/D Control Register (ADCR)
- 17.2.4 Keyboard Comparator Control Register (KBCOMP)
- 17.2.5 Module Stop Control Register (MSTPCR)
- 17.3 Interface to Bus Master
- 17.4 Operation
- 17.4.1 Single Mode (SCAN = 0)
- 17.4.2 Scan Mode (SCAN = 1)
- 17.4.3 Input Sampling and A/D Conversion Time
- 17.4.4 External Trigger Input Timing
- 17.5 Interrupts
- 17.6 Usage Notes
- Section 18 RAM
- 18.1 Overview
- 18.1.1 Block Diagram
- 18.1.2 Register Configuration
- 18.2 System Control Register (SYSCR)
- 18.3 Operation
- 18.3.1 Expanded Mode (Modes 1, 2, and 3 (EXPE = 1))
- 18.3.2 Single-Chip Mode (Modes 2 and 3 (EXPE = 0))
- Section 19 ROM
- 19.1 Overview
- 19.1.1 Block Diagram
- 19.1.2 Register Configuration
- 19.2 Register Descriptions
- 19.2.1 Mode Control Register (MDCR)
- 19.3 Operation
- 19.4 Overview of Flash Memory
- 19.4.1 Features
- 19.4.2 Block Diagram
- 19.4.3 Flash Memory Operating Modes
- 19.4.4 Pin Configuration
- 19.4.5 Register Configuration
- 19.5 Register Descriptions
- 19.5.1 Flash Memory Control Register 1 (FLMCR1)
- 19.5.2 Flash Memory Control Register 2 (FLMCR2)
- 19.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
- 19.5.4 Serial/Timer Control Register (STCR)
- 19.6 On-Board Programming Modes
- 19.6.1 Boot Mode
- 19.6.2 User Program Mode
- 19.7 Programming/Erasing Flash Memory
- 19.7.1 Program Mode
- 19.7.2 Program-Verify Mode
- 19.7.3 Erase Mode
- 19.7.4 Erase-Verify Mode
- 19.8 Flash Memory Protection
- 19.8.1 Hardware Protection
- 19.8.2 Software Protection
- 19.8.3 Error Protection
- 19.9 Interrupt Handling when Programming/Erasing Flash Memory
- 19.10 Flash Memory Programmer Mode
- 19.10.1 Programmer Mode Setting
- 19.10.2 Socket Adapters and Memory Map
- 19.10.3 Programmer Mode Operation
- 19.10.4 Memory Read Mode
- 19.10.5 Auto-Program Mode
- 19.10.6 Auto-Erase Mode
- 19.10.7 Status Read Mode
- 19.10.8 Status Polling
- 19.10.9 Programmer Mode Transition Time
- 19.10.10 Notes On Memory Programming
- 19.11 Flash Memory Programming and Erasing Precautions
- 19.12 Note on Switching from F-ZTAT Version to Mask ROM Version
- Section 20 Clock Pulse Generator
- 20.1 Overview
- 20.1.1 Block Diagram
- 20.1.2 Register Configuration
- 20.2 Register Descriptions
- 20.2.1 Standby Control Register (SBYCR)
- 20.2.2 Low-Power Control Register (LPWRCR)
- 20.3 Oscillator
- 20.3.1 Connecting a Crystal Resonator
- 20.3.2 External Clock Input
- 20.4 Duty Adjustment Circuit
- 20.5 Medium-Speed Clock Divider
- 20.6 Bus Master Clock Selection Circuit
- 20.7 Subclock Input Circuit
- 20.8 Subclock Waveform Shaping Circuit
- 20.9 Clock Selection Circuit
- Section 21 Power-Down State
- 21.1 Overview
- 21.1.1 Register Configuration
- 21.2 Register Descriptions
- 21.2.1 Standby Control Register (SBYCR)
- 21.2.2 Low-Power Control Register (LPWRCR)
- 21.2.3 Timer Control/Status Register (TCSR)
- 21.2.4 Module Stop Control Register (MSTPCR)
- 21.3 Medium-Speed Mode
- 21.4 Sleep Mode
- 21.4.1 Sleep Mode
- 21.4.2 Clearing Sleep Mode
- 21.5 Module Stop Mode
- 21.5.1 Module Stop Mode
- 21.5.2 Usage Note
- 21.6 Software Standby Mode
- 21.6.1 Software Standby Mode
- 21.6.2 Clearing Software Standby Mode
- 21.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode
- 21.6.4 Software Standby Mode Application Example
- 21.6.5 Usage Note
- 21.7 Hardware Standby Mode
- 21.7.1 Hardware Standby Mode
- 21.7.2 Hardware Standby Mode Timing
- 21.8 Watch Mode
- 21.8.1 Watch Mode
- 21.8.2 Clearing Watch Mode
- 21.9 Subsleep Mode
- 21.9.1 Subsleep Mode
- 21.9.2 Clearing Subsleep Mode
- 21.10 Subactive Mode
- 21.10.1 Subactive Mode
- 21.10.2 Clearing Subactive Mode
- 21.11 Direct Transition
- 21.11.1 Overview of Direct Transition
- Section 22 Electrical Characteristics
[H8S/2128 Series, H8S/2128 F-ZTAT]
- 22.1 Absolute Maximum Ratings
- 22.2 DC Characteristics
- 22.3 AC Characteristics
- 22.3.1 Clock Timing
- 22.3.2 Control Signal Timing
- 22.3.3 Bus Timing
- 22.3.4 Timing of On-Chip Supporting Modules
- 22.4 A/D Conversion Characteristics
- 22.5 Flash Memory Characteristics
- 22.6 Usage Note
- Section 23 Electrical Characteristics [H8S/2124 Series]
- 23.1 Absolute Maximum Ratings
- 23.2 DC Characteristics
- 23.3 AC Characteristics
- 23.3.1 Clock Timing
- 23.3.2 Control Signal Timing
- 23.3.3 Bus Timing
- 23.3.4 Timing of On-Chip Supporting Modules
- 23.4 A/D Conversion Characteristics
- 23.5 Usage Note
- Appendix A Instruction Set
- A.1 Instruction
- 2. Arithmetic Instructions
- 3. Logic Instructions
- 4. Shift Instructions
- 5. Bit Manipulation Instructions
- 6. Branch Instructions
- 7. System Control Instructions
- 8. Block Transfer Instructions
- A.2 Instruction Codes
- A.3 Operation Code Map
- A.4 Number of States Required for Execution
- A.5 Bus States During Instruction Execution
- Appendix B Internal I/O Registers
- B.1 Addresses
- B.2 Register Selection Conditions
- B.3 Functions
- Appendix C I/O Port Block Diagrams
- C.1 Port 1 Block Diagram
- C.2 Port 2 Block Diagrams
- C.3 Port 3 Block Diagram
- C.4 Port 4 Block Diagrams
- C.5 Port 5 Block Diagrams
- C.6 Port 6 Block Diagrams
- C.7 Port 7 Block Diagrams
- Appendix D Pin States
- D.1 Port States in Each Processing State
- Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
- E.1 Timing of Transition to Hardware Standby Mode
- E.2 Timing of Recovery from Hardware Standby Mode
- Appendix F Product Code Lineup
- Appendix G Package Dimensions
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
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Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
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Remember to give due consideration to safety when making your circuit designs, with appropriate
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Hitachi Single-Chip Microcomputer
H8S/2128 Series
H8S/2127
HD6432127RW, HD6432127R
H8S/2126
HD6432126RW, HD6432126R
H8S/2124 Series
H8S/2122
HD6432122
H8S/2120
HD6432120
H8S/2128 F-ZTAT
TM
HD64F2128
Hardware Manual
ADE-602-114B
Rev. 3.0
03/26/01
Hitachi, Ltd.
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Preface
The H8S/2128 Series and H8S/2124 Series comprise high-performance microcomputers with a
32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system
configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen
internal 16-bit general registers with a 32-bit configuration, and a concise and optimized
instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
Programs based on the high-level language C can also be run efficiently.
Single-power-supply flash memory (F-ZTATTM*) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip peripheral functions include a 16-bit free-running timer module (FRT), 8-bit timer
module (TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX), a serial
communication interface (SCI), A/D converter (ADC), and I/O ports. An I
2
C bus interface (IIC)
can also be incorporated as an option.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
The H8S/2128 Series has all the above on-chip supporting functions, and can also be provided
with an IIC module as an options. The H8S/2124 Series comprises reduced-function versions, with
fewer TMR, and no PWM, IIC, or DTC modules.
Use of the H8S/2128 or H8S/2124 Series enables compact, high-performance systems to be
implemented easily. The various timer functions and their interconnectability (timer connection),
plus the interlinked operation of the I
2
C bus interface and data transfer controller (DTC), in
particular, make these devices ideal for use in PC monitors. In addition, the combination of F-
ZTAT
TM
and reduced-function versions is ideal for system applications in which on-chip program
memory is essential to meet performance requirements, product start-up times are short, and
program modifications may be necessary after end-product assembly.
This manual describes the hardware of the H8S/2128 Series and H8S/2124 Series. Refer to the
H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the
instruction set.
Note: * F-ZTAT
TM
(Flexible-ZTAT) is a trademark of Hitachi, Ltd.